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WO1997050111A1 - Puce de semiconducteur et reticule de production de semiconducteur - Google Patents

Puce de semiconducteur et reticule de production de semiconducteur Download PDF

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Publication number
WO1997050111A1
WO1997050111A1 PCT/JP1997/002196 JP9702196W WO9750111A1 WO 1997050111 A1 WO1997050111 A1 WO 1997050111A1 JP 9702196 W JP9702196 W JP 9702196W WO 9750111 A1 WO9750111 A1 WO 9750111A1
Authority
WO
WIPO (PCT)
Prior art keywords
pattern
chip
semiconductor
semiconductor chip
region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP1997/002196
Other languages
English (en)
Japanese (ja)
Inventor
Yuji Takagi
Yukio Matsuyama
Takashi Hiroi
Masahiro Watanabe
Maki Tanaka
Seiji Ishikawa
Aritoshi Sugimoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Publication of WO1997050111A1 publication Critical patent/WO1997050111A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F9/00—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
    • G03F9/70—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically for microlithography
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54413—Marks applied to semiconductor devices or parts comprising digital information, e.g. bar codes, data matrix
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54433—Marks applied to semiconductor devices or parts containing identification or tracking information
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54453—Marks applied to semiconductor devices or parts for use prior to dicing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the present invention relates to a semiconductor chip and a reticle for manufacturing a semiconductor, and more particularly to a reticle for manufacturing a semiconductor chip and a semiconductor chip whose design coordinate position can be easily specified by a pattern provided on the semiconductor chip.
  • the location of the final functional defect of a semiconductor chip detected by fail bit inspection is specified by CAD data, and when visually checking the cause of the defect for observation and analysis, the semiconductor chip to be observed is Alternatively, load the semiconductor wafer on which the semiconductor chip is built into a stage equipped with a microscope, such as a review station, and locate it at the location specified by the CAD data. To this end, alignment techniques used for other applications such as steppers were used.
  • the alignment force used for other uses such as steppers does not exactly match the design coordinate system based on the virtually existing scribe center, and this alignment marker is used.
  • this alignment marker is used.
  • it When it is positioned by positioning it, it will be out of order of tens of micrometers.
  • a review station or the like described in the prior art even if the stage is moved to the indicated coordinate values, several to ten cells are required from the target location. It is located some distance away, and it takes a lot of man-hours to look around the area visually.
  • design coordinate system on actual chip It is necessary to reduce the man-hours required for the observation by taking measures to make the observation possible. Disclosure of the invention
  • the problem described above is to utilize the peripheral area of the chip formed on the semiconductor wafer, and to set the position in the chip to the uppermost layer part during visual observation or to the layer that can be detected at the time of observation by design coordinates in this area.
  • a pattern obtained by encoding the position on each coordinate axis of the design coordinate system is provided in a specific area in the outer peripheral part on the chip in a horizontal and vertical direction, so that the pattern is read by a computer at the time of observation and encoded. This is achieved by reading the position information on each coordinate axis by decoding from and positioning the chip.
  • FIG. 1 is a plan view showing an arrangement of semiconductor chips on a semiconductor wafer
  • FIG. 2 is a view showing a variation of an XY coordinate system on the semiconductor chip.
  • FIG. 3 is a plan view showing a schematic configuration of a semiconductor chip.
  • FIG. 4 is an enlarged plan view showing a part of the corner of the gardening portion when the present invention selects the gardening portion of the semiconductor chip as a predetermined region.
  • FIGS. 5 and 6 are plan views showing a method of encoding a pattern in a girder drilling part when a girder part of a semiconductor chip is selected as a predetermined region according to the present invention.
  • the figure is a diagram for explaining a correspondence table between an encoding pattern and a decoded value according to the present invention.
  • FIG. 8 is a plan view showing a method of coding a pattern in the guarding portion when the present invention selects a guarding portion of a semiconductor chip as a predetermined region.
  • FIG. 9 shows that the present invention is applied to a semiconductor chip gardening as a predetermined region.
  • FIG. 6 is an enlarged plan view showing a corner portion of the semiconductor chip when the outside of the portion is selected.
  • FIG. 10 is a plan view showing a method of encoding a pattern in a scribe area when the present invention selects a scribe area as a predetermined area.
  • FIG. 11 and FIG. FIG. 7 is a plan view showing another example of a method of encoding a pattern in a scribe area.
  • FIG. 13 is an enlarged plan view showing a part of a corner of a semiconductor chip when the present invention is selected between a bonding portion and a circuit pattern forming region region as a predetermined region. is there.
  • FIG. 1 is an enlarged view of one of the semiconductor chips built on a semiconductor substrate.
  • the rectangular area around the diagonal line shown by 1 is one semiconductor chip, and the diagonal area around 8 is the semiconductor chip built on the semiconductor wafer adjacent to the 1 semiconductor chip. Is shown.
  • the dashed-dotted line indicated by 2 is called a scribe center, and serves as a guideline when dicing the semiconductor chip 1 and surrounding chips to separate them and finally cut them into individual semiconductor chips.
  • Fig. 1 two vertically running scribe centers and two horizontally running scribe centers are indicated by alternate long and short dash lines.
  • the position in the semiconductor chip 1 shown at the center is defined by the XY coordinate system defined by the X and Y coordinates shown in FIG. , 4, 5, and 6 are rectangular areas.
  • the origin indicated by 3 is called the design origin.
  • semiconductor chip 1 The design origin of the upper adjacent semiconductor chip is 4, and the same coordinate system and area are defined recursively. Depending on the design data, the design origin may be 4, 5, or 6, instead of 3. Also, as shown in FIG. 2, there are eight possible ways to define the XY coordinate system, including the method shown in FIG. Hereinafter, the description will be made using the design origin position shown in FIG. 1 and the design coordinate system defined by the XY coordinate system.
  • FIG. 3 is an enlarged view of the semiconductor chip 1 shown in FIG.
  • Reference numeral 7 denotes a region sandwiched between the rectangular regions 3, 4, 5, and 6 and the semiconductor chip 1, and is called a scribe region.
  • Reference numeral 8 denotes a region provided on the outer peripheral portion of the semiconductor chip 1 and is called a bonding portion.
  • the guard ring is provided to prevent moisture and sodium from entering the chip from the side, and is made of aluminum or silicon oxide with a width of about tens of microphones. Is formed by the material used in the above.
  • Reference numeral 10 denotes a circuit pattern forming area of the chip body in which a wiring circuit pattern that actually functions is formed.
  • Reference numeral 9 denotes an area between the normal gardening portion 8 and the circuit pattern formation area 10, which is usually a blank area of 100 to 200 microphones D-torl.
  • the area for forming a pattern that encodes the position on each coordinate axis of the design coordinate system so that the position in the circuit pattern formation area 10 can be identified by the design coordinate value includes the scribe area 7, the guard-ring section 8, and the blank area. 9 It may be used.
  • FIG. 4 is an enlarged view of the lower left corner of the semiconductor chip shown in FIG.
  • the design coordinate system is represented by the X and Y axes defined by the design coordinate origin 3 and the scribe center.
  • 8 is a girdering part
  • 10 is a circuit pattern formation area.
  • a rectangular wave pattern is cut around the outer periphery of the guiding portion 8 shown in FIG.
  • the coordinate value on the X axis or the coordinate value on the Y axis is encoded using the cut position of the rectangular wave in the directions corresponding to the X axis and the Y axis, the size of the rectangular wave, and the distance between the rectangular waves.
  • FIG. 5 shows a first specific example of encoding using a gardening unit.
  • the interval U represents one unit of the encoded pattern.
  • Section D is a delimiter that indicates a break in the pattern unit.
  • Section B is a bit pattern. If there is a rectangular cut pattern as shown in part of section B, the value is set to binary code 1; otherwise, it is set to 0.
  • the cut width of the rectangle is set to one half of the bit area section B. This width may be an arbitrary fixed distance.
  • the delimiter and the bit pattern are distinguished by the difference of each pattern width s1 and S2.
  • the code coded by the pattern unit is read as follows. First, a delimiter of pattern width S1 is detected, and the bit pattern following it is read. In FIG. 5, the width is written in 9 bits, but this bit width may be changed as necessary.
  • the bit pattern in FIG. 5 is 101 1 110 1, which represents a decimal number of 370.
  • 0 to 5 1 1 can be represented. Therefore, as shown in FIG. 5, when considered in the X direction, the size XS in the X direction of the circuit pattern formation area 10 shown in FIG. Is defined as X unit, and the starting position of the pattern unit is determined in advance as X start as shown in Fig. 4, so that the pattern unit shown in Fig. 5 Start position X n
  • the encoded pattern in the X and Y directions of the gardening section 8 is formed.
  • the positions of X and Y are determined, and the position indicated by any design coordinates in the circuit pattern formation region 10 can be determined.
  • the distance of the pattern unit section U may be shortened and the bit width may be increased.
  • the Y direction may be shortened and the bit width may be increased.
  • FIG. 6 shows a second embodiment using a girder ring.
  • Section U represents one unit of the encoded pattern.
  • the section D is a delimiter indicating a break between the patterns Pl, P2, and P3 encoded by the length.
  • the pattern lengths indicated by Pl, P2, and P3 are quantized in 10 steps. That is, if the minimum unit distance is d, the pattern length P n is
  • the combination of the following three pattern lengths starting from any delimiter must be unique, that is, it corresponds to one axis direction of X or Y in one chip.
  • the condition is that there is no overlap in the combination of three consecutive pattern lengths, which are in the drawing 8. This is hereinafter referred to as a non-duplication condition.
  • the pattern length In determining the pattern length, the following must be considered. First, the pattern length must be determined cyclically. That is, if P1, P2, and P3 are determined, the first two of the next pattern are P2 and P3, and P2, P3 It is necessary to determine the next pattern P4 following. Second, the distance U including the three pattern lengths needs to be averaged as a whole.
  • the encoding of the gardening section 8 in the X and Y directions is performed.
  • the positions of X and Y are determined from the obtained pattern, and the position indicated by arbitrary design coordinates in the chip 10 can be determined.
  • the pattern combination is 3 and the pattern length is 10 steps.
  • the number of combinations of patterns and the number of steps of the pattern length may be different values.
  • FIG. 8 shows a third embodiment using a guiding part.
  • This method is a modification of the first embodiment using the gardening unit shown in FIG. 5, and a section U represents one unit of the encoded pattern.
  • Section D is a pattern This is a delineation showing the end of the unit.
  • Section B is a bit pattern. If there is a rectangular cut pattern as shown in part of section B, it is set to binary code 1; otherwise, it is set to 0.
  • the cut width of the rectangle is set to one half of the bit area section B, but this width may be an arbitrary constant distance.
  • the delimiter and the 'bit pattern are identified by the difference between the pattern widths S1 and S2.
  • the first embodiment using the guarding part is that one bit has a depth d. d is quantized in six steps. That is, assuming that the minimum unit distance is w, the path length P n is
  • the bit pattern encoding method such as NRZ-I, MFM, and MDM used in magnetic recording devices and the like is used. Etc. can also be applied.
  • the pattern provided to the girdering portion may be outside or inside the girdering.
  • the pattern to be formed is described as a rectangle, any other shape may be used as long as it can be detected, for example, a sawtooth shape, a triangle, a semicircle, or the like.
  • FIG. 9 is an enlarged view of the lower left corner of the semiconductor chip shown in FIG.
  • the design coordinate system is represented by the design coordinate origin 3 and the X and Y axes defined by the scribe center.
  • 8 is Gardrin And 10, a circuit pattern forming area.
  • the oblique hatched rectangular area 11 shown in FIG. 9 is a pattern formed for the same purpose as the pattern formed on the edge of the gardening portion in the above-described embodiment using the gardening portion.
  • the coordinate value on the X axis or the coordinate value on the Y axis is encoded using the position of the rectangular pattern in the direction corresponding to the X axis and the Y axis, the size of the rectangular pattern, and the distance between the rectangular patterns.
  • FIG. 10 shows a first specific example of encoding using a scribe area.
  • Section U represents one unit of the encoded pattern.
  • Section D is a delimiter that indicates a break in the unit in the palace.
  • Section B is a bit pattern. If there is a sheep-shaped notch pattern as shown in part of section B, set it to binary code 1; otherwise, set it to 0.
  • the width of the rectangular pattern is set to one half of the bit area section B, but the width may be any constant distance.
  • the delimiter and bit pattern are identified by the difference between each pattern width S 1 and S 2.
  • the code coded by the pattern unit is read as follows. First, a delimiter with a pattern width of S1 is detected, and the subsequent bit pattern is read. In Fig. 10, it is written in 9-bit width, but this bit width may be changed as needed.
  • the bit pattern in FIG. 10 is 101 1 110 0 10 and represents a decimal number of 3700.
  • 0 to 5 1 1 can be represented.Thus, considering in the X direction as shown in Fig. 10, the X direction size XS of chip 10 shown in Fig. 3 is 5 12 or less. If the appropriate divided distance is defined as X unit and the starting position of the pattern unit is determined in advance as X start as shown in Fig. 9, the starting position of the pattern unit shown in Fig. 10 X n
  • the X and Y encoded patterns in the X and Y directions of the scribe area 7 can be obtained. Is determined, and a position indicated by arbitrary design coordinates in the circuit pattern formation region 10 can be determined.
  • Section U represents one unit of the encoded pattern.
  • Section D is a delimiter indicating a break between patterns P1, P2, and P3 encoded by the length.
  • the pattern lengths indicated by Pl, P2, and P3 are quantized in 10 steps. That is, if the minimum unit distance is d, the pattern length P n is
  • the position of the delimiter can be specified by measuring the first three pattern lengths P1, P2, and P3 from one delimiter.
  • the combination of the following three pattern lengths starting from an arbitrary delimiter must be unique, that is, a scribe area corresponding to one X or Y axis direction in one chip.
  • the condition is that there is no overlap in the combination of three consecutive pattern lengths. This is hereinafter referred to as a non-overlapping condition.
  • the pattern length must be determined cyclically. That is, if P 1, P 2, and P 3 are determined, the first two of the following patterns are P 2 and P 3, and under these conditions, P 2 It is necessary to determine the next pattern P4 following P3.
  • P 1, P 2, and P 3 determined under the above conditions complicates the correspondence with the actual coordinate values. Therefore, as shown in FIG. 7, P 1, P 2, and P 3 The combination is used as an index, and table data is stored in advance so that the coordinate value X can be obtained.
  • the scribe area 7 can be encoded in the X and Y directions.
  • the positions of X and Y are determined from the obtained pattern, and the position indicated by arbitrary design coordinates in the circuit pattern formation region 10 can be determined.
  • FIG. 8 shows a third embodiment using a scribe area. This method is a modification of the first embodiment using the scribe area shown in FIG. 10, and a section U represents one unit of the encoded pattern. Section D is a delimiter indicating a break in the unit of the pattern. Section B is a bit pattern. If a rectangular cut pattern as shown in the figure exists in a part of section B, the binary code is set to 1. Otherwise, it is set to 0.
  • the cut width of the rectangle is set to one half of the bit area section B, but this width may be an arbitrary constant distance.
  • the delimiter and the bit pattern are identified by the difference between the pattern widths S 1 and S 2.
  • the first embodiment using the gardening part is that one bit has a depth d.
  • d is quantized in six stages. That is, if the minimum unit distance is w, the pattern length P n is
  • the value of 6 to the fourth power that is, a value from 0 to 1295, and the length of one unit can be expressed by the first It can be expressed in about half as compared with the embodiment.
  • the correspondence with the coordinate values is the same as in the first embodiment using the scribe area.
  • bit pattern coding methods such as NRZ-I, MFM, and M used in magnetic recording devices and the like. Etc. are also applicable.
  • the pattern to be formed has been described as a rectangle, but any other shape, such as a sawtooth shape, a triangle, or a semicircle, may be used as long as it can be detected.
  • FIG. 13 is a further enlarged view of the lower left corner of the semiconductor chip shown in FIG.
  • the design coordinate system is represented by the design coordinate origin 3 and the X and Y axes defined by the scribe center.
  • Reference numeral 8 denotes a guard portion
  • 10 denotes a circuit pattern forming region
  • 9 denotes a blank region between the guard portion 8 and the circuit pattern forming region.
  • a hatched rectangular area 12 shown in FIG. 13 corresponds to c X-axis and Y-axis, which are patterns formed for the same purpose as the pattern described in the above embodiment using the scribe area. Using the position of the rectangular pattern in the direction, the size of the rectangular pattern, and the distance between the rectangular patterns, the coordinate value on the X axis or the coordinate value on the Y axis is encoded.
  • X start in FIG. 13 corresponds to X start in the first embodiment using the scribe area disclosed in the scribe area 7.
  • the encoded pattern only needs to be formed on the uppermost layer or a layer that can be observed by a method using an optical or an electron beam and a method using an ultrasonic wave during visual observation. .
  • a pattern that encodes the position on each coordinate axis of the design coordinate system is provided on the chip so that the position in the chip can be identified by the design coordinate value. Observing the pattern, extracting the pattern by image processing, decoding the coded pattern information, and reading out the position information on each coordinate axis to obtain the chip position accurately Becomes possible.
  • the semiconductor chip to which the present invention is applied to the production process of a semiconductor device, it becomes possible to observe a defect position that causes a final functional defect of the semiconductor chip in a short time, thereby making it possible to process the semiconductor chip in a short time. It is expected that the feedback for improvement will be faster.

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Preparing Plates And Mask In Photomechanical Process (AREA)

Abstract

On a utilisé de manière classique un marqueur d'alignement destiné à une autre fin, tel que dans un moteur pas-à-pas, pour trouver la position, spécifiée par des données CAD, d'un défaut fonctionnel final d'une puce de semiconducteur détecté par des inspections binaires de défaut. Toutefois, ce marqueur d'alignement ne coïncide pas exactement avec un système de coordonnées de conception, lequel est établi sur la base d'un centre de découpage existant virtuellement et, lorsque la puce de semiconducteur est positionnée à l'aide du marqueur, une erreur de l'ordre de quelques dizaines de micromètres se produit. Par conséquent, lors de l'observation d'un défaut au niveau d'un point désigné par des valeurs de coordonnées de conception, une quantité considérable d'homme-heure a été nécessaire, du fait que le point désigné du défaut à observer s'écarte de la position réelle d'environ quelque cellules à 10 cellules et le voisinage du point doit faire l'objet d'une recherche visuelle pour trouver le défaut. Selon cette invention, on a disposé des motifs selon lesquels la position sur chaque axe de coordonnées de l'axe de coordonnées de conception est codée de sorte que la position se trouvant dans la puce, formée sur une plaquette en semiconducteur, peut être reconnue à partir des valeurs de coordonnées de conception, dans des zones horizontales et verticales spécifiques de la couche supérieure, au moment de l'observation visuelle d'une couche qui est détectable au moment de l'observation, en utilisant la région périphérique de la puce. Les motifs sont entrés dans un ordinateur au moment de l'observation, des informations de position relatives à chaque axe de coordonnées sont extraites par décodage du motif codé, et la puce est positionnée.
PCT/JP1997/002196 1996-06-26 1997-06-25 Puce de semiconducteur et reticule de production de semiconducteur Ceased WO1997050111A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP8/165551 1996-06-26
JP16555196A JPH1012527A (ja) 1996-06-26 1996-06-26 半導体チップおよび半導体製造用レチクル

Publications (1)

Publication Number Publication Date
WO1997050111A1 true WO1997050111A1 (fr) 1997-12-31

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023144548A1 (fr) * 2022-01-31 2023-08-03 Cambridge Enterprise Limited Marqueur lisible par machine et procédé d'identification

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5076407B2 (ja) * 2006-09-05 2012-11-21 ミツミ電機株式会社 半導体装置及びその製造方法
EP2309539B1 (fr) 2009-10-09 2018-12-05 STMicroelectronics Srl Indexation de dispositifs électroniques avec des marqueurs de pondérations différentes
ITMI20101415A1 (it) * 2010-07-29 2012-01-30 St Microelectronics Srl Circuiti integrati tracciabili e relativo metodo di produzione
JP5893287B2 (ja) * 2011-08-10 2016-03-23 ルネサスエレクトロニクス株式会社 半導体装置および基板

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04340214A (ja) * 1990-12-14 1992-11-26 Fujitsu Ltd 半導体装置の製造方法
JPH05313350A (ja) * 1992-04-01 1993-11-26 Nec Corp 半導体装置のフォトマスク
JPH0845800A (ja) * 1994-07-29 1996-02-16 Nec Yamaguchi Ltd 半導体ウエハおよびその識別方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04340214A (ja) * 1990-12-14 1992-11-26 Fujitsu Ltd 半導体装置の製造方法
JPH05313350A (ja) * 1992-04-01 1993-11-26 Nec Corp 半導体装置のフォトマスク
JPH0845800A (ja) * 1994-07-29 1996-02-16 Nec Yamaguchi Ltd 半導体ウエハおよびその識別方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023144548A1 (fr) * 2022-01-31 2023-08-03 Cambridge Enterprise Limited Marqueur lisible par machine et procédé d'identification

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