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TWI267904B - Mask material conversion - Google Patents

Mask material conversion Download PDF

Info

Publication number
TWI267904B
TWI267904B TW094130194A TW94130194A TWI267904B TW I267904 B TWI267904 B TW I267904B TW 094130194 A TW094130194 A TW 094130194A TW 94130194 A TW94130194 A TW 94130194A TW I267904 B TWI267904 B TW I267904B
Authority
TW
Taiwan
Prior art keywords
layer
spacer
pattern
mask
substrate
Prior art date
Application number
TW094130194A
Other languages
English (en)
Other versions
TW200612473A (en
Inventor
Mirzafer K Abatchev
Gurtej Sandhu
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Publication of TW200612473A publication Critical patent/TW200612473A/zh
Application granted granted Critical
Publication of TWI267904B publication Critical patent/TWI267904B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0338—Process specially adapted to improve the resolution of the mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Drying Of Semiconductors (AREA)
  • Semiconductor Memories (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Element Separation (AREA)

Description

1267904 九、發明說明： 【發明所屬之技術領域】 本發明一般相關於積體電路製造，尤其相關於光罩技 術。 【先前技術】
許多因素，包括現代電子設備中對可攜性、計算能力、 口己隐合里及此里效率的需求增加，造成積體電路的尺寸持 續減小。為促進此尺寸減小，組成特徵，如形成積體電路 的電氣裝置及互連線寬度’亦持續地減低。 例如在記憶體電路中，或如動態隨機存取記憶體 (DRAM)、#態隨機存取記憶體（SRAM)、鐵電性㈣記憶 體等裝置中，降低特徵尺寸的趨勢是明顯的。舉例而言， DRAM通㊉包括數百萬個完全相同的電路元件，習知為記 憶體單元。在其最普通形式中，—記憶體單元通常由二電 氣裝置組成：-儲存電容器及—存取場效電晶體。各記憶 體早定址位置’其可儲存一位元（二進位數字）資 枓。一位凡可通過該電晶體而寫至-單元，及藉由自參考 電極側感測該儲存電極上 ……何而讀取。藉由降低組成的 記憶裝置的尺寸可降寸併此等特徵的 裝入記憶裝置中而增加儲存容量。化體早凡 特：尺寸的持續減低對用以形成該等特徵的技 的要求。例如，通常使 定圖崇先心將導線等特徵在-基板上 ”吏用間距的觀念說明此等特徵。間距定義為二 104505.doc 1267904 鄰接特徵中的-完全相同點間的距離。此等特徵通常由田比 鄰特徵間的間隔定義，該間隔通常由一絕緣體或一導體等 材料來填補。結果，間距可視為—特徵的寬及用以分開該 特徵與一鄰接特徵的間隔寬度的和。然而，由於光學及光 或輻射波長等因素，光微影技術各具有一最小間距，低於 該間距，—特定光微影技術無法可靠地形成特徵。因此， 一光微影技術的最小間距可限制特徵尺寸的減小。 ，’間距加倍，，係為使光微影技術的性能延伸以超出其最小 間距而提出的-方法。此-方法在圖1A至1F中說明，且揭 不在頒予L〇wrey等人的美國專利號5,328,81〇中。參照圖 1A ’百先使用光微影在—光阻層中形成—線圖案，用以 覆蓋在一耗材層20及-基板3〇之上。如圖1B所示，接著藉 由#刻步驟（較佳為各向異性）將該圖案轉移到層，用 、v成數個位置支架或心軸4〇。如圖ic所示，可剝除光阻 線10’且各向同性地_心轴伽增加鄰接心軸侧的距 離。如圖1D所示’ 一材料層5〇後續在心轴4〇之上沈積。如 圖1E所不’接著精由在_方向性間隔層钱刻中自該等表面 7〇及叫先餘刻該間隔層材料，在該等心轴的數個側壁 上形成數個間隔ys 60 Μ層60即自另一材料的數個側壁延伸或原 始形成延伸的材料。 — 十如圖1F所示，接著移除其餘的心軸 40 ’僅留下該等間陪 ^層60，其一起作為一蝕刻光罩以使 個下層圖案化。因一 已知間距先前包括一用以界定一 特徵及一間隔的圖幸 ^ ^ 系之處，相同的寬度今包括由該等間隔 層60界疋的二特徵 一 ^ 一間隔。結果，有效降低一光微影技 104505.doc 1267904 術的可能最小特徵尺寸。 應了解，雖然在上述範例中該間距實際上減半，但此間 距減低傳統上稱為間距”加倍”，或更常稱為間距，，倍增，，。 意即，傳統上間距”倍增，，某倍數，實際上涉及減低該間距 該倍數。本文中保留傳統的術語。 一特徵的臨界尺寸係特徵的最小尺寸。就使用間隔層⑼ 形成的特徵而言，該臨界尺寸通常對應至該等間隔層的寬 度。通常該等間隔層的寬度依次依層5〇的一厚度9〇而定 (參看圖1〇及化）。因此，通常形成層50到一對應至期望臨 界尺寸的厚度90。 該等間隔層60的品質及一致性直接影響到數個積體電路 的品質，該等積體電路使用該等間隔層作為一光罩而部分 界定在基板30中。然而，在該等期望間隔層6〇寬度比該等 心軸40及/或用以分開該等間隔層⑼的間隔大的地方，已 觀察到最後形成的賴層6G及該等間隔層6G形成的餘刻光 罩會具有不良—致性°此不良—致性依次會造成基板中形 成不良界定及非一致性的特徵。結果，基板中形成的積體 電路的電氣效能會劣化’或該等積體電路會無法使用。 因此而要形成蝕刻光罩的方法，該等蝕刻光罩具有高 度致及界定完善圖案，尤其是配合間距倍增中形成的間 隔。 【發明内容】 祀據本^明的一概念，揭示一種製造積體電路的方法。 該方法包括提供-基板，其具一覆蓋光罩層。該光罩層包 104505.doc 1267904 括光罩材料，及數個開口，其形成一圖案。將該光罩材料 氧化，及後續將該圖案轉移到該基板。 根據本發明的另一概念，揭示一種形成積體電路的方 法。該方法包括提供一圖案，其包括一光罩層中的數個光 罩線’用以覆蓋-基板。該等光罩線包括—先質材料。藉 由使該先質材料起化學反應以形成一化學化合物，其比該 先夤材料佔用更大體積，使該等光罩線成長到一期望寬 度。 根據本發明的另一概念，揭示一種形成積體電路的方 法。該方法包括提供一圖案化光罩，其覆蓋一基板。該光 罩層包括一先質材料，其起化學反應以形成一蝕刻停止材 料。後續將該光罩層中的圖案轉移到一下層。 根據本發明的又一概念，揭示一種半導體處理的方法。 该方法包括提供一基板。一暫時層覆蓋在該基板上，及一 可光學界定層覆蓋在該暫時層上。使一圖案在該可光學界 疋層中形成且轉移到該暫時層，用以在該暫時層中形成複 數個位置支架。一間隔層材料的覆蓋層在該複數個位置支 架上方沈積。將該間隔層材料可選擇地自數値水平表面移 除。相關於該間隔層材料，將該等位置支架可選擇地移 除。使該間隔層材料擴充到一期望尺寸。 根據本發明的另一概念，揭示一種形成記憶裝置的方 法。该方法包括藉由間距倍增以形成複數個光罩線。由一 開放間隔使鄰接的光罩線互相分開，及使鄰接光罩線間的 開放間隔變窄。 104505.doc 1267904 根據本發明的又一概念，揭示一種半導體處理的方法。 :…去匕括藉由間距倍增以形成複數個光罩線。藉由使形 、〆等光罩線的材料轉換成另—材料，使該材料的體積擴 充到一期望寬度。 ’ 【實施方式】 :發現’-些間隔層圖案的不良品質是由於沈積間隔層 ； 形層及/或蝕刻此材料以形成數個間隔層時遭遇 的困難。因間隔層通常是由數個間隔層材料覆蓋層的數個 垂直延伸部分在一複雜光罩地形的上方形成，該等層的正 形性將影響該等層形成的間隔的一致性，如寬度、高度及 物理放置。應了解，一分層越是正形，其複製的形狀:接 近其沈積表面的形狀。 然而，當臨界尺寸持續降低時，數個心軸間的間隔或開 口的縱橫比持續增加。此結果的部分原因是，想要藉由減 低心軸間的間隔寬度將數個特徵更緊密包裝_起。此外， 在轉移圖案的一般方法中’該等間隔層及一下層兩者皆曝 露至一餘刻劑’其優先地餘刻掉基板材料。然而’钕刻劑 亦以較低速率磨掉該等間隔層。因此，即使當一萨界尺寸 降低々’該等間隔層的垂直高度仍必須保持一位準;。以容許 在該等間隔層完全被蝕刻劑磨掉前完成一圖案轉移。 因此，間隔層材料的高度正形層的沈積越來越困難，邙 分是由於先質氣體擴散到數個心軸間的間隔底部越來越二 限制。當數個側壁填滿間隔層材料時，此擴散在一沈積2 程期間成為越來越受到更多限制’因此尚增加該等:壁間 104505.doc 1267904 的間隔的縱橫比。為此緣故，沈積較薄數層比沈積較厚數 層谷易且可罪。作為數個不良正形較厚沈積層的結果，該 等層形成的間隔層的一致性亦會不良。 此外，如同先質會難以到達高縱橫比間隔的底部，有些 間隔的、縱橫比亦可限制钱刻齊j渗透到該等間隔底部的量。 因此，當蝕刻橫向延伸該間隔層材料層的數個部分以界定 個別間隔層時，有些間隔層材料會不期望地留在此等間隔 的底部，令形成數個間隔層’其具有底表面的寬不同於預 期的寬度。因此，在沈積及姑刻間隔層材料層中遭遇的困 難，令該等間隔層寬度上的精確控制亦困難。 有利地，本發明的數個較佳實施例能在使用一光罩圖案 形成的特徵的寬度及一致性上提供更精確的控制。在該等 較佳實施例中，該光罩圖案由一材料形成，該材料可藉由 一後續製程’如氧化’自行增加到m小或臨^尺 寸。接著該光罩圖案經受擴充製程，使光罩特徵的寬度辦 加到期望寬度。接著該等今已增大的光罩特徵可用以在 -下層中形成一圖案。應了解，本文中使用的 :，在一材料中，如-光罩層中或-基板中，形成且具： 7刀開界線的任何體積或開口。 較佳地’接受增大製程的圖案係一由間 隔層圖案。該等間隔層較佳包括秒，例如…= 矽。亥增大過程可為令該等間隔層擴充的任何過程 曰 =隔層包㈣的地方，擴充製程較佳包括該等間隔= 乳以屯成乳化石夕。此外，使該等間隔層氧化直到其成手 104505.doc 1267904 :卜期望寬度。成長到該期望寬度後，該等間隔層可用以 錢個下層中定出數個特徵的圖案。視需要，可將該等間 隔層在氧化後修整成一期望臨界尺寸。 有利地，藉由在該等間隔層形成後使其成長到一期望寬 ^ ’可沈積-較薄間隔層材料層。藉由沈積比一期望臨界 =需更薄的數層’使該等層的正形較少依沈 制而定。結果，使形成-已知臨界尺寸的間 丨同層的製程窗口加寬。 :外’如上述’一間隔層通常形成到一特殊高度，其 „ ^ 光罩以執订的一特殊半導體製程（例如蝕 : 、換雜、氧化等)及將曝露至該製程的下基板特 殊材料的需求而指定。例如， 、 j如間隔層通常形成到一高度， 〆、考置在後續钱刻一下声湘門— 因間隔層通常在如氧化二：;Γ 。有利地， … 期間疋在橫向及垂直兩方向成長， 的因=可能在將間隔層圖案轉移到一下層時將最終形成 :::間：層'刻掉。而且，因為-間隔層.刻形成的間 ^層的初始面度係依—心 隔層未增大則心軸高度可小於所需古/^稍後㈣間 因此進等心軸間的間隔的縱橫比， =進-步解除間隔層材料沈積的需求且進一步增加製程 π P戶材料氮^及氧化石夕特別適合作為用於光罩形成的 == 由於相對於包括金屬、氧化物及切 I他各種材料的可選㈣刻化學可用性。有利地， 104505.doc -12- 1267904 該矽間隔層II換成—氧化 /」a U备许本發明的敕祛眚 例能輕易插入各種不同製 r 尤其疋間距倍增，大艚 上不茜要改變該製程流。此 ^ ^ ^^ 矽間隔層部分轉換成氧化 石夕的杜仍谷村選擇餘刻化學，其將侵 料，而不會侵钱氧化石夕或殘留的石夕。 人先罩材 :下：參照數個附圖，其中從頭到尾相同數字表 部刀。應了解’圖2至22並非必然按比例繪製。
^了^’雖__佳實施例將在任何情況中發現應 =#成—光罩圖案的數個個別部分形成後想要增 加该專部分的尺寸，尤其在數個有利的實施例中，但該光 罩圖案包括由間距倍增形成的數個間隔層。因此，該等間 距倍增的特徵較伟呈古_ 八有一間距，其低於光微影技術的最小 間距’光微影技術係用以將形成該等間隔層所用的心軸圖 案化。此外’雖然該等較佳實施例可用以形成一積體電 路’但其尤其有利地適用於形成具電氣裝置陣列的裴置， 該等電氣裝置陣列包括邏輯或閘極陣列，及dram、r〇m 或决閃讀體等揮發性及非揮發性記憶裝置。 乡…、至圖2，提供一部分形成的積體電路1 〇〇。一基板 110叹置在各種不同光罩層12〇至15〇的下方。將蝕刻該等 層12〇至150以形成一光罩，使基板11〇圖案化以形成各種 不同特徵，將詳述如下。 π a 了解，忒基板可包括一單一材料層、複數個不同材 料層，層中具有數個不同材料或結構區域的一層或數層 等。此等材料可包括半導體、絕緣體、導體，或其組合。 104505.doc l2679〇4 例如，該基板可包括摻雜的多晶矽、一電氣元件主動區、 石夕化物’或嫣、鋁或銅層等金屬層，或其組合。因此， M下討論的光罩特徵可直接對應至該基板中如互連等傳導 特徵的期望放置。在其他實施例中，該基板可為一絕緣 體，及光罩特徵的位置可對應至絕緣體的期望位置。 覆蓋在基板110上的數個層12〇至15〇的材料，較佳依據 化學考量及本文中討論的多種圖案形成及圖案轉移的製程 籲條件來加以選擇。因一最上層光可限定層120與基板U0間 ❸數層將用以將衍生自光可限^層120的-圖案轉移到基 板110 ’因此較佳選擇光可限定層12〇與基板11〇間的數 層，令其相對於其他曝露材料而可作選擇性餘刻。應了 解’當-材料的_速率比腳材料至少约大5倍，較佳 、’勺大10倍及更佳約大20倍時，要考慮可選擇地或優先地蝕 刻該材料。 在所示實施例中’光可限定層⑵覆蓋在一第一硬式光 罩或蝕刻停止層130上，該蝕刻停止層覆蓋在一暫時層140 Λ暫夺層倀盍在一第二硬式光罩層或蝕刻停止層15〇 上’餘刻停止層150覆蓋在例如將通過第二硬式光罩層150 餘刻以定圖案的基板11 〇上。 光可限定層12 〇較佳由一本 先阻劑形成，包括此藝中習用 的任何光阻劑。例如，兮也_ h 該先阻劑可為與157 nm、193 nm或 248 nm波長系統，193 ，皮長汉潤糸統或電子束系統相容 的任何光阻劑。較佳亦阳如μ ,A , 先阻剑材料的範例包括，氟化氬 (ArF)感光阻劑，即適合盥— 一 ArF光源配合使用的光阻劑， 104505.doc -14- 1267904 “鼠化氪（KrF)感光阻劑，即適合與一尺斤光源配合使用的 ^背丨ArF光阻劑較佳與利用如193 nm等較短波長光的 光微影系統配合使用。KrF光阻劑較佳與如248疆系統等 車乂長波長光微影系統配合使用。
:务硬式光罩層130的材料較佳包括一無機材料，及示 範材料包括氧化矽(Si〇2)、石夕，或-介電抗反射塗層 (DARC)，如一飽含矽的氮氧化矽。在所示實施例中，第 更式光罩層130係一介電抗反射塗層（DARC)。暫時層 140較佳由非晶石炭所形《，其相對於該等較佳硬式光罩材 料提供極高㈣刻選擇性。更佳地，該非晶碳係—非晶碳 形式，其高度透光且在對齊中提供進_步的改善。用以形 成一鬲度透明碳的沈積技術可參看A. Helmbold、D.
MeiSSner的著作，薄固態膜283(1996)，第196至203頁。 因為用以蝕刻光阻劑的較佳化學通常亦蝕刻相當數量的 非晶碳，及因為相對於各式各樣非光阻劑，化學能夠以絕 佳選擇性蝕刻非晶碳，因此選自此類材料的硬式光罩層 130較佳地分開層12〇與14〇。如上述，第一硬式光罩層 幸乂佳包括氧化矽、石夕，或一 DARC，其相對於非晶碳可優 先地加以移除。 此外，使用DARC用於第一硬式光罩層13〇可特別有利於 形成圖案，#具有接近光微影技術的解析度㈣的間距。 該等DARC可藉由將光反射減至最小而增強解析度，光反 射了 IV低光4影用以界定一圖案邊緣的精確度。視需要， 除了第一硬式光罩層130之外，可同樣地使用一底部抗反 104505.doc -15- 1267904 射，塗層（BARC)(未顯示）來控制光反射。 ^ 式光罩層150較佳包括一介電抗反射塗層 (DARC)(例如一氮氧介 乳化矽）、矽，或氧化鋁（A1203)。此外，
可視需要使用一底邻浐G ,^ 展°卩抗反射塗層（baRC)(未顯示）來控制光 反射。：所示實施例中，第二硬式光罩層15。包師3。 曰。丄、擇用於夕種層的適當材料外，選擇層12〇至⑼的 :度較倥依蝕刻化學及本文中所述製程條件的相容性而 疋：例如’當藉由選擇性蝕刻一下層以將一圖案從一上層 下層時，將來自該兩層的材料蝕刻到某些程度。 因此’較上層較佳夠厚，令其未在圖案轉移進程中蝕刻 掉0 在所不貫施例φ 土 _Γ 例肀，先可限定層120的厚度較佳介於約1〇〇 nm與約 300 nm之 ρ弓 ^ ^ ^ 曰’ ’更it厚度在約150 nm與約250 nm之 ^第硬式光罩層130的厚度較佳介於約10 nm與約500 η γπ之間，爭j去戸由
子度在約15 nm與約300 nm之間。暫時層 140的厚度較佳介於約1⑻nm與約300腿之間，更佳厚度 在、力100 nm與約200 nm之間。第二硬式光罩層15〇的厚度 車乂佳；丨於㈣1〇 _與約5〇疆之間，更佳厚度在約1〇麵與 約30 nm之間。 心了解本文中所述各種層可由熟諳此藝者習知的各種 方去來形成。例如，可使用如化學汽相沈積等各種汽相沈 積方法來’成硬式光罩層。可使用旋塗式方法來形成光可 此外可藉由使用一氫碳化合物或此類化合物之 奶口物作為碳先質的化學汽相沈積來形成非晶碳層。示範 104505.doc -16- 1267904 先質包括丙烯、丙炔、丙烷、丁烷、丁烯、丁二烯及乙 炔。开> 成非晶碳層的一合適方法揭示在2003年6月3日頒予 Fairbairn等人的美國專利號6,573,〇3〇 B1中。 在根據數個較佳實施例及參照至圖3至11的方法的第一 方面中，由間距倍增形成一間隔層圖案。 參照至圖3，在光可限定層120中形成一圖案，其包括數 個光可限定材料特徵124所界定的數個間隔或渠溝122。該 等渠溝122例如可由光微影來形成，其中通過一主光罩將 層12 0曝路至輕射，及接著加以顯影。顯影後，殘留的光 可限定材料，即所示實施例中的光阻劑，形成如所示線 124等數個特徵（僅顯示在剖面中）。 最終形成的線124及間隔122的間距等於一線124的寬與 一鄰接間隔122的寬的和。為將使用此線124及間隔122的 圖案所形成的特徵的臨界尺寸減至最小，該間距較佳在或 接近用以使光可限定層120圖案化的光微影技術的極限。 因此，該間距可在光微影技術的最小間距，及以下論及的 間隔層圖案可有利地具有一間距，其低於光微影技術的最 小間距。 如圖4所示’可視需要而藉由钱刻光阻線124以加寬間隔 122，以形成改良式間隔122a及線124a。較佳使用一各向 同性蝕刻，如氧化硫電漿，例如包括s〇2、〇2、沁及^的 電漿，以蝕刻該等光阻線124。較佳選擇該蝕刻的程度， 令間隔122a及線124a的寬度大體上等於稍後形成間隔層間 的期望間隔，如以下由圖8至1〇的討論所了解。有利地， 104505.doc 17 1267904 此蝕刻容許線124a比使用定出光可限定層12〇圖案的光微 影技術可能做到的更窄。此外，該蝕刻可使線124a的邊緣 平滑，因此提高該等線124a的一致性。 在（改良式）光可限定層120中的圖案較佳轉移到暫時層 140，以容許沈積一間隔層材料層17〇(圖7)。因此，較佳由 可耐住間隔層材料沈積製程條件的材料來形成暫時層 140，將詳述如下。在間隔層材料的沈積與光可限定層12〇 相容的其他實施例中，可省略暫時層14〇，及可直接在光 限定特徵124或光可限定層12〇本身的改良式光限定特徵 124a上沈積該間隔層材料。 在所示實加例中，除了具有高於光阻劑的耐熱性之外， 較佳選擇用以形成暫時層140的材料，以相對於間隔層175 的材料（圖8)及下蝕刻停止層15〇，而選擇地移除該材料。 如上述，層140較佳由非晶碳形成。 在光可限定層120中的圖案較佳首先轉移到硬式光罩層 130,如圖5所示。雖然若硬式光罩層13〇是薄的，亦適合 使用一濕式（各向同性）蝕刻，但較佳使用一各向異性蝕刻 完成此轉移。較佳的氟碳電漿蝕刻化學包括CF4、CFH3、 CF2H2及 CF3H。 3 接著將光可限定層120中的圖案轉移到暫時層140，如圖 6所示，較佳使用一含S〇2電漿，例如含§〇2、〇2及斛的一 電漿。有利地，該含S〇2電漿可以比蝕刻硬式光罩層13〇大 2〇倍的速率，更佳是大40倍的速率蝕刻較佳暫時層140的 反 σ適含S〇2電漿揭示在Abatchev等人的美國專利申 104505.doc -18- 1267904 請號1()/931，772中，中請日讓年8月31日，名稱為臨界尺 寸控制。應了解，含S〇2電漿可同時蝕刻暫時層丨扣，且亦 移除光可限定層12〇。最終形成的線⑽構成該等位置支 架或心軸，以該等位置支架或心軸將形成—含數個間隔層 175的圖案（圖8)。
接下來，如® 7所示，較佳在包括硬式光罩層13〇、硬式 光罩150及暫時層14〇的側壁的曝露表面之上正形地沈積一 間隔層材料層170。可視需要在沈積層170前移除硬式光罩 層130。間隔層材料可為任何材料，其可作為將一圖案轉 移到下基板110的-光罩’或其可容許通過將形成的光罩 處^個下層結構。該間隔層材料較佳：1)可以良好步驟 涵盍範圍而沈積；2)可用與暫時層14〇相容的一溫度沈 積；3)可進-步處理以增大其尺寸；及4)在增大後，可相 對於暫時層i40及暫時層14〇下方的任何層而作選擇㈣ ，°較佳材料包括多晶梦及非晶石夕。層m較佳沈積到一 厚度，其在約20 nm與約60 nm之間，更佳在約2〇咖與約 nm之間。較佳地’該步進涵蓋範圍約或更大，及 更佳是約90%或更大。 如圖8所示’接著間隔層17〇受到一各向異性蝕刻，用以 自部分形成的積體電路100的水平表面18〇移除間隔層材 料。可使用HBr/C1電漿執行此一钱刻，其亦習知為一間隔 層钱刻。該钮刻可包括-物理成分，及較佳亦包括一化學 成分，例如一反應式離子蝕刻（RIE)，如—Cl2、HBr蝕刻 等。例如可使用LAM TCP9400執行此一蝕刻，其具有約 104505.doc 1267904 300至 1000 mTorr屢力 W上功率及約50至250 W下功率在約7至 ，流動約0至55 sccm Cl2及約〇至2⑻ HBr。 接下來移除硬式光罩層130(若仍存在）及暫時層140，以 留下數個獨立的間隔層175(圖11}。因為間隔層175可以是 薄的’及因為硬式光罩層13G可由類似間隔層175的材料形 成，因此一間隔填充層155可在間隔層175上方及周圍形 成，以有助於維持間隔層175的結構完整性，及有助於蝕 刻分層㈣及刚，如圖9所示。較佳地，層155包括光阻 劑，其可在一旋塗製程中沈積。例如在間隔層175夠寬及 可使用適當蝕刻化學的其他實施例中，不用沈積層155即 可移除層130及140。 夢照圖10，例如藉由平面化將硬式光罩層13〇與間隔填 充層155的一頂部分一起移除。用以蝕刻層13〇及155的較 佳化學包括一含兩步驟的蝕刻：首先使用cF4/He電漿直到 移除層130(圖9)，及接著使用一 〇2電漿將暫時層14〇與間 隔填充層1 55的其餘部分一起移除。圖丨丨顯示最終形成的 結構。或者’為在該蝕刻的第一部分移除層丨3 〇，可使層 130及155受到化學機械研磨過程。 因此’形成一含數個獨立間隔層175的圖案。用以蝕刻 層140及155的較佳化學包括一氧化硫電漿蝕刻。有利 地’相較於通常用於間隔層的氮化矽或氧化矽等材料，石夕 較易各向同性地或各向異性地蝕刻。在一些實施例中，在 間隔層敍刻後’藉由修整間隔層175以調整間隔層175的臨 104505.doc -20- 1267904 界尺寸。 因此’間距倍增已完成。在所示實施例中，該等間隔層 175的間距大略是光微影原初形成的光阻線124者（圖3)的一 半。有利地，可形成約具1〇〇 nm或更小間距的數個間隔層 175。應了解，因間隔層175在該等特徵或線12仆的側壁上 形成，因此間隔層175通常遵循光可限定層12〇中原初形成 的特徵或線124的圖案輪廓。
接下來，在根據數個較佳實施例的方法的第二方面中， 將間隔層175增大’令其寬度對應至將在基板ιι〇中形成的 特徵的期望臨界尺寸。較佳地’達成此增大係藉由使間隔 層175起反應以形成佔據更多空間的一新化合物或合金。 在所示具有㈣成間隔層的實施例中，增大製程較佳包括 該等間隔層的氧化。應了解，間隔層175基於氧化而增 大:如圖12所示。間隔層咖的尺寸將依間隔層π氧化 "王度而有所不同。因必匕’較佳選擇氧化的期間及程度， :間隔層175達到一期望寬度％。達成間隔層明氧化係 猎由此藝中習知的任^ g ^ 7虱化製权，包括熱氧化、使用氧基 或電漿的氧化等。在i他竇 ,y ^ 隹，、他貫^例中，可藉由此藝中習知的 壬了鼠化製程以氮化間隔声 Π 而使其增大。因此，可形 成一 έ數個間隔層175狂的圖宏 95。 固案’该荨間隔層具有期望寬度 ’可正形地沈積且可使 例如，可使用鈦以形成 形成丁i02或TiN2而使該 應了解，間隔層175可由可 用合適蝕刻化學的任何材料开 間隔層⑺，且藉由氧化或氮 104505.doc 1267904 :1::，：。其他材料範例包括-(其可藉由氧化或氮 化以形成^卜&或氮化纽而擴充）及鶴（其可藉由氧化或氮 /成虱化鎢或氮化鎢而擴充）。 ^擇增A的程度，令間隔層175增大到_寬 二 =上等於該等特徵的期望臨界尺寸，該等特徵如 互吏間隔層:75a形成的圖案在基板u。中定出圖案的 望 4立元線、電晶體列，或波形花紋線間的間隙
如，依該等期望臨界尺寸是否僅稍微或大體上較大 :氧化間隔層175的尺寸而定，可使該等間隔層”5a氧 :到一較大或較小程度。因此，選擇如期間、化學反應、 溫度等製程條件以達成期望的間隔層擴充程度。 應了解’間隔層1 75的成長亦將使用以分開該等間隔層 二5的空間變窄。較佳地，將間隔層175定位成考量到此變 乍此外，藉由如—各向同性钱刻以修整間隔層1 ，可 在擴充後調整間隔層175a的臨界尺寸。 亦應了解，間隔層175a本身可直接作為一硬式光罩使 用，將一下基板110定出圖案。然而，較佳地，將該間隔 層175a圖案轉移到一或多個下層，其對基板ιι〇提供較優 於間隔層175a的蝕刻選擇性。參照至圖13，間隔層175以乍 出的圖案可轉移到第二硬式光罩層150。較佳地，使用一 BCh/Cl2電漿蝕刻以蝕刻第二硬式光罩層15〇。 麥妝至圖14，可視需要在將基板丨丨〇定圖案前移除間隔 層175a。可使用一濕蝕製程將間隔層175a移除。有利地， 藉由移除間隔層175a，使覆蓋在基板110上的光罩的縱橫 104505.doc -22- 1267904 比減低，因此容許蝕刻劑及其他處理化學品較容易達到， 基板，且因此改善垂直側壁的形成，《不然即清楚刻= 輪廓且完成處理。 在其他實施例中，如圖15所示，可利用一額外光罩層 16〇以定出基板110的圖案。此類基板例如可包括多層，^ 需要多個連續蝕刻以定出圖案。由於可用化學以容許非/曰、 奴相對於許多含矽基板材料極可作選擇性移除，因2額外 光罩層160較佳由非晶碳形成。 應了解，可應用上述步驟以形成用以覆蓋額外光罩層 160的數個間隔層175a。參照圖16，形成含數個間隔層 的:圖案。如圖17所示，接著如上述，該等間隔層175例 如藉由氧化而擴充到一期望寬度。接著較佳可使用一 bci3/ci2電漿㈣卜將含數個間隔層175_圖案轉移到第 二硬式光罩層15〇,如圖18所示。接著較佳藉由各向異性 地蝕刻額外光罩層16〇，將該圖案轉移至額外光罩層“Ο， 如圖19所不。較佳地，該各向異性蝕刻包括將額外光罩層 160曝露到一含s〇2電漿。在其他實施例中，應了解可在蝕 刻層150前，或在蝕刻基板11〇前移除該等間隔層175，如 以上參照圖14所述。 接者可通過光罩層160及15〇及間隔層175&處理基板 11〇，以界定多種特徵，例如電晶體、電容器及/或互連。 在基板110包括數個不同材料層的地方，可使用一連串不 同化本過私，較佳是乾餘化學，連續地通過該等不同層而 蝕刻。應了解，可依使用的化學或數個化學而定，蝕刻該 104505.doc -23- Ϊ267904 非 及硬式光罩層】50。然而，額外光罩層】60的 非曰曰灭對傳統钱刻化學有利地提供絕佳阻抗，尤I是用以 钱刻含矽材料者。因此， 八 .額外先罩層〗60可有效地作為一 =用’以通過複數個基板層而银刻，或用以形成高縱 ^比知溝1後可移除額外光罩層⑽以進—步處理基板 ^ 了解’本文中所述任何步驟中，將一圖案從一第一位 t移至-第二位準涉及在該第二位準中形成數個特徵， ::常對應至該第一位準上的數個特徵。例如，在第二位 準中的線路徑通常將遵循第一位準上的線路徑，及第二位 ^上其他特徵的位置將對應到第二位準上類似特徵的位 、°然而’從第-位準到第二位準’特徵的精確形狀及尺 寸可不@。例b ’依蝕刻化學及條件而冑，可相對於第一 位準上的圖案’增大或減小用以形成該轉移圖案的特徵間 的尺寸及相對間隔，但仍很像相同的初始"圖案"。因此， 仍認定轉移圖案是與初始圖案相@的圖案。㈣下，在光 罩特被周圍形成間隔層可改變該圖案。 應了解，根據该等較佳實施例形成接點提供許多優勢。 例如’因較薄層比較厚層易正形地沈積’因此用以形成間 隔層的間隔層材料層可以改良正形沈積。結果，可由且改 良-致性的此等層形成間隔層。此外，此等層的相對薄度 減低佈滿該間隔層材料之毯狀層的渠溝的縱橫比，因此$ 許蝕刻劑較易深入該等渠溝的底部，且因此促進間隔層2 刻0 104505.doc -24- 1267904 亦應了解，所示實施例可有多種修改。例如，間隔層 1 75或1 75a的間距可多於兩倍。達成進一步的間距倍增可 藉由在間隔層175或175a周圍形成額外間隔層，接著移除 間隔層175或175a，接著在先前環繞間隔層175或17化的間 隔層周圍形成數個間隔層等。進一步間距倍增的示範方法 揭示在Lowrey等人的美國專利號5,328,810中。 此外，可重疊或緊鄰間隔層175或175&形成其他多種圖 案，其用以定出不同尺寸的特徵。例如，可形成一額外光 可限定層以覆蓋在間隔層175或175&上，且接著定圖案以
形成該等其他圖案。形成此類圖案的方法揭示在美國專利 申請號10/931，771 ’中請人Tran等人，申請日2〇〇4年8月η 曰’名稱為”增加光學對齊邊緣的方法”。 此外，雖然可使所有間隔層175氧化，使其具有一類似 寬度，但在其他實施例中，僅使該等間隔層175中的一些 者氧化。例如，可藉由沈積及以―保護層圖案及接著: 曝露的間隔層氧化’以保護一些間隔層175免於氧化。 此外’依轉換的材料及轉換過程的程度而定， 續化學轉換過料會„地增加間隔層Μ的尺寸。在此 中’本文中揭示的製程仍然適合將間隔層 =用高度選擇性姓刻的材料。因此，該轉換過程可有 利地將間隔層175轉換成-較佳钱刻停止層，以用於後續 的蝕刻步驟。例如，可將一 用於後，，，只 化"金屬，其可有利地對如下=::氧化或氮 蝕刻選擇性。 “周圍材料提供良好的 104505.doc -25- 1267904
參照圖20至22,其中增大間隔層175，應了解可在間隔 層㈣沈積後及形成該等獨立間隔層175前的任何點，例 如可藉由氧化使間隔層175或層17〇增大。例如，在沈積一 間隔層材料之毯狀層17〇後（圖2〇)，可如圖21所示使整㈣ 狀層170增大，以形成一擴充的毯狀層17〇&。如上述，較 佳選擇該擴充製程，包括製程條件（例如期間、化學反 應、溫度等），令毯狀層170擴充到一期望厚度，其對應到 一期望臨界尺寸，考量到後續間隔層餘刻期間的任何水平 收縮。因此，該擴充製程可留下僅部分地氧化的層Μ。 如圖22所示H隔層則後，接著移除該等心轴 襲’以留下該等獨立的間隔層175卜有利地，因間隔層 .比間隔層175厚，因此可不需要一保護的間隔填充層 155(圖9) ’及使用—各向異性#刻，例如使用—氣碳電 漿，钱刻該等心軸124b。 一在其他實施例中，可在間隔層钱刻後及㈣該等心轴 前，使間隔層Π5擴充（例如，可使圖8中的間隔層175擴 充）。有利地，因容許間隔層175僅在一方向中橫向地成 長，因此此類型擴充在減低一對間隔層175的構成間隔層 間的距離時，容許個別間隔層175配對間的距離維持不 艾然而，如上述，較佳在形成該等間隔層i75作為數個 獨立結構後執行該擴充步驟，以促進層17〇的蝕刻。 同樣地，雖然通過該各種光罩層而，，處理，，較佳涉及蝕刻 一下層，但通過該等光罩層而處理可涉及使該等光罩層下 方的數層、、、工x任何半導體製程。例女口，處王里可涉及通過該 104505.doc -26- 1267904 氮化或沈積數種材 等光罩層及在數個下層上摻雜、氧化 料。 因此，熟諳此藝者應了解， 方法及結構可作出其他多種省 修改及變動意欲涵括在本發明 内0 不背離本發明的範圍，上述 略、添加及修改。所有此類 如後附請求項所界定的範圍 【圖式簡單說明】
由以上較佳實施例的詳細說明及附圖可了解本發明，該 等實施例及附圖係用以說明’並非用以限制本發明，及其 中： 八 圖1A至1F以示意剖面圖說明根據一先前技藝間距倍增 方法而形成的數個光罩線； 圖2根據本發明的數個較佳實施例，以示意剖面圖說明 一部分形成的記憶裝置； 圖3根據本發明的數個較佳實施例，說明圖2中部分形成 的記憶裝置在一可光學界定層中形成數線後的示意剖面 圖； 圖4根據本發明的數個較佳實施例，說明圖3中該部分形 成記憶裝置在加寬數個光阻線間的間隔後的示意剖面圖； 圖5根據本發明的數個較佳實施例，說明圖4中該部分形 成記憶裝置在通過一硬式光罩層蝕刻後的示意剖面圖； 圖6根據本發明的數個較佳實施例，說明圖$中該部分形 成g己憶裝置在將一圖案自該光阻層及數個硬式光罩層轉移 到一暫時層後的示意剖面圖； 104505.doc -27- 1267904 圖7根據本發明的數個較佳實施例，說明圖6中該部分形 成記憶裝置在沈積一間隔層材料覆蓋層後的示意剖面圖； 圖8根據本發明的數個較佳實施例，說明圖7中該部分形 成記憶裝置在一間隔層蝕刻後的示意剖面圖； 圖9根據本發明的數個較佳實施例，說明圖8中該部分形 成記憶裝置在塗佈一可移除材料後的示意剖面圖； 圖1 〇根據本發明的數個較佳實施例，說明圖9中該部分 形成記憶裝置在蝕刻該光阻層及數個硬式光罩層後的示咅 剖面圖； 圖11根據本發明的數個較佳實施例，說明圖1 〇中該部分 形成記憶裝置在移除該光阻層及數個暫時層後的示意剖面 圖； 圖12根據本發明的數個較佳實施例，說明圖丨丨中該部分 形成記憶裝置在該等間隔層增大到一期望寬度後的示意剖 面圖； 圖13根據本發明的數個較佳實施例，說明圖12中該部分 形成記憶裝置在將該間隔層圖案轉移到一下硬式光罩層後 的示意剖面圖； 圖14根據本發明的數個較佳實施例，說明圖13中該部分 形成記憶裝置在移除該等間隔層後的示意剖面圖； 圖1 5根據本發明的數個較佳實施例，以示意剖面圖說明 圖1中的部分形成記憶裝置，其具有一額外遮罩層； 圖16根據本發明的數個較佳實施例，說明圖丨5中該部分 形成記憶裝置在形成數個間隔層後的示意剖面圖； 104505.doc -28- 1267904 圖1 7根據本發明的數個較佳實施例，說明圖16中該部分 形成記憶裝置在使數個間隔層擴充後的示意剖面圖； 圖1 8根據本發明的數個較佳實施例，說明圖17中該部分 形成5己憶裝置在通過一硬式光罩層蝕刻後的示意剖面圖； 圖19根據本發明的數個較佳實施例，說明圖18中該部分 形成記憶裝置在將該間隔層圖案轉移到該額外遮罩層後的 示意剖面圖； 圖20根據本發明的數個較佳實施例，說明圖6中該部分 形成記憶裝置在沈積一間隔層材料覆蓋層後的示意剖面 圖； 圖21根據本發明的數個較佳實施例，說明圖2〇中該部分 形成記憶裝置在該覆蓋層增大到一期望厚度後的示意剖面 圖；及 圖22根據本發明的數個較佳實施例，說明圖2 1中該部分 形成記憶裝置在移除該硬式光罩及數個暫時層後的示意剖 面圖。 【主要元件符號說明】 10 光阻線 20 消耗層 30, 110 基板 40 心車由 50 材料層 60 間隔層 70, 80, 180 水平表面 104505.doc -29- 1267904 90 厚度 95 期望寬度 100 積體電路 120 光可限定層 122, 122a 間隔（渠溝） 124 光可限定材料特徵（線） 124a 改良式光可限定材料特徵（線） 124b 最終形成線 130 第一硬式光罩（蝕刻停止）層 140 暫時層 150 第二硬式光罩（蝕刻停止）層 155 間隔填空層 160 額外光罩層 170 間隔層材料層 175, 175a 間隔層
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1267904 十、申請專利範圍： 1. 一種製造積體電路之方法，包括： 提供一基板，其具有一 九罩層’該光罩層包括光罩 材料及數個開口，該亦罢η A ^罩材料及數個開π形成-圖案； 乳化該光罩材料；及 氧化該光罩材料後，轉移該圖案至該基板。 2. 如請求項1之方法，其中轉移該氧化光罩圖案包括，通 過該光罩層中之該笪 亥4開口以蝕刻該半導體基板。 3. 如請求項1之方法，JL中兮本w庶a T忒光罩層包括多晶矽或非 石夕。 4. 如請求項3之方法，i由姓外土里篇 八中使该先罩層氧化包括形成氧化 石夕。 5.如請求項3之方法，甘士 /士》, ^ 去其中使該光罩層氧化包括，部分地 氧化该光罩層。 6·如：求項1之方法，其中部分地氧化該光罩層包括，增 大./光罩材料至_期望寬度，其對應至該積體電路中之 一特徵之一期望臨界尺寸。 7·如明求項6之方法，其中該期望臨界尺寸係該積體電路 中之數個導電互連之一寬度。 8 'kp 士主戈 • 明〉項1之方法，其中該基板包括複數個不同材料 層。 了 9·如明求項8之方法，其中轉移該圖案至該半導體基板包 括°亥複數層各利用一不同蝕刻化學。 1 0 ·如請|工苔 、之方法’其中該基板係一絕緣體。 104505.doc 1267904 11.12. 如。月求項10之方法，其中轉移該圖案至該半 定一記憶裝置陣列之數個導線。 如請求項1之方法，其中提供-基板包括， 立曰以形成一含數個間隔層之囷案，其中該光 该專間隔層。 導體基板界 藉由間距倍 罩材料包括 禋形成積體電路之方法
二用以覆蓋-基板之一光罩層中提供一圖案，其包括 個光罩線，該等光罩線包括-先質材料；及 =化學地反應該先質材料以成長該等光罩線至—期 寬度，以开》成一化學化合物， 之體積。 ”佔用大於該先質材料 14 ·如請求項13之方法 氧化。 其中成長該等光罩線包括執行一熱 1 5 ·如請求項13之方法 個光罩線。 其中藉由間距倍增以形成該等複數
16·如請求項13之方法， 1 7 ·如請求項13之方法， 板之間。 其中該等光罩線包括矽。 其中-非晶碳位於該光罩層與該基 卻堉承項13之方法，尚包 # ^ ^ . 在成長該等光罩線後，轉 私^圖案至該光罩層與該基 .〇 , ^ 攸间之一硬式光罩層。 19·如铂求項18之方法，其中該硬 20如請求項1Q夕古、i +罩層包括氧化鋁。 . 9之方法，其中轉移該圖案 括，以Βα3/α2電襞峨硬式光罩層。 '先罩層匕 21.如請求項18之方法，尚包括 得移4圖案至一硬式光罩 104505.doc 1267904 層後，、相對於該硬式光罩層而選擇性移除該光罩層。 /长項18之方法，尚包括，轉移該圖案至-硬式光罩 、“麦轉移韻案至該硬式光罩層與該基板間之一額外 光罩層。 23·如請求項22之方法，其中 1 φ丄 八T ”亥額外先罩層包括非晶碳。 24·如請求項13之方法，其 、 Τ^ I冤度對應至將在該基板 中形成之數個導線之一臨界尺寸。 25· 一種形成積體電路之方法，包括·· 提供一圖案化光罩層，苴 L 八復派在一基板上，該光罩層 包括一先質材料； 化學地反應該先質材料以形成—餘刻停止材料·及 後續地轉移該光罩層中之圖案至一下層。 26.如請求項25之方法，ι ψ仆爯絲她从 〃中化學轉換使該先質材料之一體 積增大。 2 7 ·如晴求項2 6之方法，其中化學轉換 τ 予锝換包括執行一熱氧化。 •如请求項25之方法，其中該圖宰化 / α杀化先罩層包括由間距倍 增形成之複數個光罩線。 29·如請求項25之方法，其中該先質材料選自以下各物組成 之群組：矽、鈦、鈕及鎢。 3〇.如請求項29之方法，其中該餘刻停止材料包括一氧化物 或一氮化物。 h•如請求項25之方法’其中—非晶碳位於該光罩層與該基 板之間’及其中後續地轉移包括轉移該圖案至該非晶碳 層0 I04505.doc 1267904 32·如請求項25之方法，其中轉移該圖案至該非晶碳層包括 執行一 S Ο 2電漿餘刻。 33· —種半導體處理之方法，包括： 提供一基板，其中一暫時層覆蓋在該基板上，及一光 可限定層覆蓋在該暫時層上； 在該光可限定層中形成一圖案； 轉移該圖案至該暫時層’用以在該暫時層中形成複數 個位置支架； 在該複數個位置支架之上沈積一間卩5 ^ 间隔層材料之毯狀 層； 將該間隔層材料自數個水平表面選擇地移除； 相對於該間隔層材料，選擇地移除該等位置支架；及 擴充該間隔層材料至一期望尺寸。 34.如請求項33之方法’其中選擇地移除該等位置支架形成 :含數個獨立間隔層之圖案’及其中擴充該間隔層材料 係在選擇地移除該等位置支架後執行。 35_如請求項33之方法，其中擴充該間隔層材料係在自數個 水平表面選擇地移除該間隔層材料前執行。 36.如請求項33之方法，其中擴充該間隔層材料係在自數個 水平表面選擇地移除該間隔層材料後，及在選擇地移除 該等位置支架前執行。 ^ 37·如請求項33之方法， 38·如請求項37之方法， 3 9 ·如請求項3 8之方法， 其中該暫時層包括非晶碳。 其中該光可限定層包括光阻劑。 其中在該光可限定層中形成一圖案 104505.doc 1267904 包括，執行光微影及後續地各向同性地蝕刻該光可限定 層。 40·如請求項38之方法，苴中一石由斗止里识、 ，、甲硬式先罩層分開該暫時層與 該光可限定層。 4 1.如清求項4 〇之方法，苴中辞石承彳也宏 ，、甲Θ硬式先罩層包括一介電抗反 射塗層。 4 2 ·如请求項41之方法，1中續介雷ρ ，、T 〇褒；丨電抗反射塗層包括氮氧化 石夕。 43.如請求項41之方法，其中選擇地移除該等位置支架包 括： 在該間隔層材料之上及周圍沈積一填充材料； 同時蝕刻該填充材料及該硬式光罩層；及 後續地同時蝕刻該填充材料及該暫時層。 44·如請求項43之方法，其中 T ^ 具兄材枓包括沈積光阻 劑。 45.如請求項44之方法，其中沈積光阻劑包括執行一旋塗方 法0 Μ.如請求項43之方法，其中同時兹刻該填充材料及該硬式 光罩層包括執行一 CF4/He電漿蝕刻。 請求項43之方法，其中後續地同時—該填充材料及 該暫時層包括執行一 02電漿蝕刻。 48.如請求項33之方法’其中沈積間隔層材料之—毯狀層包 括，藉由化學汽相沈積以沈積一矽層。 曰 49·如請求項48之方法，其中擴充該間隔層材料包括形成氧 104505.doc 1267904 巧匕秒。 5〇·如請求項48夕士、+ ^ / ，/、中自數個水平表面選擇地移除該 間隔層材料包括各向異性地韻刻該石夕層。HB /二員5〇之方法中各向異性地蝕刻該矽層包括以 HBr/C!2電漿蝕刻該矽層。 52. 一種形成記憶裝置之方法，包括： 精由間隔倍增以形成複數個光罩 使鄰接光罩線彼此分開；及 ^ 使郇接光罩線間之該空隔變窄。 53·如請求項52之 矽。 ，、宁°亥專先罩線包括多晶矽或非晶 54·如請求項52 、2之方法’其中使該空隔變窄包括，使該等光 :ε反應以形成一不同化學化合物或合金。 55. ^ Γ求項54之方法，其中使該等光罩線起反應包括 由氣化而擴充該等光罩線。 冗·如請求項55之方法，1 — /、甲便"亥等光罩線起反應包括 王乳化該等光罩線。 57·如請求項52之方法 案至一下層。 58·如請求項57之方法 59·如請求項58之方法 尚包括轉移該等光罩線形成之 藉 70 圖 其中該下層包括非晶碳。 其中轉移該圖案至該非晶碳層包 括’轉移該圖案至_石承4也 接著將該圖案自該 更式先罩層轉移至該非晶碳層。 6〇·如π求項59之方法，其中轉移該圖案至一硬式光罩層包 104505.doc 1267904 括，以BCl3/Cl2t漿餘刻該硬式光罩層。 月求項59之方法，其中將該圖案自該硬式光罩層轉移 至孩非0曰奴層包括，曝露該非晶碳層至含電漿。 62· —種半導體處理之方法，包括： 藉由間距倍增以形成複數個光罩線；及 藉由使形成該等光罩線之一材料轉換成另-材料，而 擴充該材料體積至一期望寬度。 63.如請求項62之方法，其中使形成該等光罩線之—材料體 積擴充包肖，在％成複數個光罩線間距倍增期間擴充間 隔層材料之一毯狀層。 64·如請求項63之方法，其中包括： 形成複數個心軸； - 沈積該間隔層材料之毯狀層； 擴充該間隔層材料；及· 擴充該間隔層材料後，蝕刻數個水平表面，用以自兮 鲁間隔層之毯狀層形成數個間隔層，其中該等間隔層形成 該等光罩線。 ^ 65.如請求項63之方法，其中形成複數個光罩線包括·· 形成複數個心軸； 沈積該間隔層材料之毯狀層； 蝕刻數個水平表面以自該間隔層材料之毯狀層形成數 個間隔層，其中該等間隔層形成該等光罩線； 钱刻數個水平表面後，擴充該間隔層材料，·及 後續地相對於該擴充後之間隔層材料，優先地移除該 104505.doc 1267904 專心車由。 月农項62之方法，其中使形成該等光罩線之一材料體 、η充i括，使間距倍增後之一含數個間隔層之圖案擴 充。 八 6 7.如請求項62 貝62之方法，其中將該材料轉換成另一材科包 使形成該等光罩線之該材料氧化。 68.如請求項62 、 法，其中將該材料轉換成另一材料包 使形成該等光罩線之該材料氮化。 ★明求項62之方法，尚包括，通過該等光罩線間之數個 汗口而曝露一下層至數個反應體。 求項69之方法，其中該等反應體係數個蝕刻劑。 72如二t員7°之方法’其中曝露-下層包括蝕刻非晶碳。 板。 八甲曝路一下層包括蝕刻一導電基 73.^凊未項62之方法，尚包括，使形成該等光罩線之 料體積擴充後，修整該等光罩線。 、材 74·如睛求項62之方法， 矽。 千”亥荨先罩線包括多晶矽或非晶 75·如請求項62之方 ^ ^ 八中该期望寬度係一積體電路中數 個導電互連線之一臨界尺寸。 甲數 104505.doc
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EP1794777B1 (en) 2016-03-30
KR20070067119A (ko) 2007-06-27
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US20060046200A1 (en) 2006-03-02
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