RU2580099C2 - Apparatus for determining values ??of characteristics of readiness for use product - Google Patents

Abstract

FIELD: computer engineering.

SUBSTANCE: invention relates to computer engineering, particularly control devices, and can be used in development activities and operating practice where there is need to determine optimum periods of control and maintenance of articles, ensuring required their readiness for use. Device comprises a memory unit, twelve gates, a multivibrator, five adders, an OR circuit, three flip-flops, four nonlinearity units, two adder accumulators, five multipliers, two comparators, two subtractors, two integrators, five delay elements, a memory element, a divider unit and polarised relay.

EFFECT: technical result consists in improvement of accuracy of device.

1 cl, 2 dwg

Description

The invention relates to computer technology, in particular to control devices. It can be used in scientific research and operational practice to determine the optimal timing of maintenance of products of periodic use and the corresponding values of indicators of readiness of products for intended use.

Known devices [3, 4, 5, 6], allowing to determine the periods of service, providing extreme values of the criterion functions. A common disadvantage of these devices is limited functionality. They do not allow to determine the time interval when the operational readiness of the product for use is no less than required.

The device [7] allows you to determine the optimal criterion of readiness for use of the product, the frequency of maintenance and the time interval at which the operational readiness of the product for use will be no less than specified. The scope of this device is limited to products of continuous use.

The closest in technical essence to the claimed invention is a device [8], containing a memory block, thirteen valves, two adders, a multivibrator, an OR circuit, three triggers, two nonlinearity blocks, two accumulating adders, three multiplication blocks, two comparators, two subtractors, two integrators, five delay elements, memory element, divider, polarized relay. Its disadvantage is the low accuracy of determining the values of the output quantities, because does not allow to take into account the change in the rate of expenditure of the reliability potential of the product at the stage of its maintenance.

The aim of the proposed technical solution is to increase the accuracy of determining the values of the output values. The goal is achieved by taking into account the difference in the value of the failure rate of the product according to a change in the mode of its functioning.

Each product continuously expends its reliability potential, and the consumption rate depends on the mode of its use [1]. The change in mode is manifested in a change in the failure rate.

The process of applying many products is cyclical. Each cycle may include the operation of the product in nominal mode, in light mode, as well as in rest mode. The application process diagram is shown in figure 1, which reflects the following values:

τ is the duration of the product application cycle (for example, one day);

t ₁ - the duration of use of the product in nominal mode with a load factor k _n = 1. Moreover, the failure rate has a value of λ ₁ .

On the interval t ₂ = τ-t ₁ various products, depending on the technology of their application and the actual load, can be in one of the following modes:

a) lightweight mode, in connection with a decrease in load;

b) rest after application.

In this regard, in the time interval t ₂ the failure rate λ ₂ will have different values λ ₂ = λ ₁ · k _n in accordance with the change in the coefficient k _{n of the} load. Note that, according to [2], in the case of a lightweight mode of operation of the product k _n <1, and in the rest mode, according to [1], 0 <k _n □ 1.

To maintain the product in working condition, its maintenance is periodically carried out and the time τ _obs . At the same time, in-depth state monitoring is performed during the time τ _k1 , carrying out preventive maintenance and restoring operability in case of failure detection, which takes time τ _Β . At the end of these works, a control check of the condition of the product is carried out for a time τ _k2 .

Note that the control of the technical condition is carried out in the conditions of the nominal operating mode of the product. Therefore, at time intervals τ _k1 and τ _k2 , the failure rate is λ ₁ . For carrying out preventive and repair work, the product is put into rest mode, which corresponds to the failure rate λ ₂ . In this regard, the duration of maintenance is expressed as follows:

or

where P (T), P (τ _k1 + τ _k2 ), P (τ _B ) is the probability of failure-free operation of the product in the corresponding time interval.

циклов применения изделия длительностью τ каждый, т.е.Service Period T includes many $$i=\overline{\mathrm{one,}n}$$

application cycles of a product of duration τ each, i.e.

Where

The duration T _c the product service cycle, taking into account (1), is

The probability of failure-free operation of the product in the time interval Τ is determined by the relation

For many products, the predominance of sudden failures is characteristic and the exponential distribution of the time of their occurrence is applicable. In this case, the following takes place:

The working time of the product in the interval τ of one application cycle is determined by the formula

and on the time interval T its value will be

Comprehensive indicators of product quality are the availability factors K _G and operational readiness K _OG .

The availability factor of the serviced product, taking into account (1), (4), (10), is expressed by the following ratio:

From (11) it can be seen that the availability factor substantially depends on the period T of product service. As studies show, the function K _Г (Т) for some (optimal) value of T * has a global extremum.

In connection with the foregoing, the problem of determining the optimal period of maintenance of the product can be written as follows:

When planning the implementation of particularly important work in a certain time interval ξ <T *, it is important to know that the operational readiness of the product for use will be no less than required (given). This is expressed by the value of the operational readiness coefficient in the following form:

Where

P (ξ) is the probability of failure-free operation of the product, calculated similarly to the value of P (T).

The task of determining the maximum allowable time interval ξ ^extra , when K _OG will be at least given, we write in the following form:

The proposed mathematical model can be implemented using the inventive device, a diagram of which is shown in figure 2.

The device contains: a memory unit 1, valves 2, 4, 6, 27, 28, 30, 32, 41, 45, 46, 47, 48, a multivibrator 5 that is in standby mode, triggers 7, 25, 37, accumulating adders 8 , 11 (the scheme and operation are presented in [3]), adders 3, 9, 10, 39, 42, blocks of nonlinearities 12, 14, 19, 21, OR 13, multiplication blocks 15, 16, 23, 26, 29, polarized relay 17, delay elements 18, 31, 33, 38, 44, subtractors 20, 22, comparators 24, 36, memory element 34, integrators 35, 40, division block 43.

вводятся в блок памяти 1 через его входы с первого по восьмой соответственно.Before starting the operation of the device, the initial data λ ₁ , t ₁ , λ ₂ , τ _K1 , τ _B , τ _K2 , τ, $$K_{\mathrm{ABOUT}R}^{s\mathrm{but}d}$$

are entered into the memory unit 1 through its inputs from the first to the eighth, respectively.

In the operation of the device, two stages are manifested. First, the optimal value of the period T * is determined according to (12), and then the value ξ ^{add is} calculated in accordance with (15).

The device operates as follows. According to the “Start” signal coming from the ninth input of the device, the second 25 and third 37 triggers are set to zero. In this case, the gates 6, 28, 41, 45, 46, 47, 48 are closed, and the gates 27, 30, 32 are opened, the first trigger 7 is transferred to a single state, thereby providing the values of the stored data to the outputs of the memory unit 1. In addition, the “Start” signal, passing through the OR 13 circuit, is fed to the input of the multivibrator 5. By the output (single) signal of the multivibrator 5, the first 2 and second 4 valves are opened. This ensures a single arrival of the value of parameter t ₁ from the second output of the memory unit 1 to the first accumulating adder 8, and the value of the parameter τ from the seventh output of the memory unit 1 to the second accumulating adder 11. A single signal of the multivibrator 5 is also fed to the control inputs of the first 2 and second 11 accumulative adders, ensuring the implementation of the process of accumulation and transmission of the resulting data obtained in accordance with (2) and (3), in the associated elements of the device circuit. At the same time, from the first output of memory block 1, the value of parameter λ ₁ is transmitted to the first inputs of the second 14 and third 19 non-linearity blocks, and from the third output of memory block 1, the value of parameter λ ₂ is transmitted to the first inputs of the first 12 and fourth 21 non-linearity blocks.

Consider the first cycle of the device to determine the optimal value of the period T *, expressed by the relation (12).

The output signal T ₁ = t _{1 of the} first accumulating adder 8 is supplied to the second inputs of the third non-linearity block 19, the first subtractor 20 and the first integrator 35. In the non-linearity block 19, according to (6), the value P ₁ (t ₁ ) is calculated and transmitted to the first the input of the fourth multiplication block 26 is directly, and through the open sixth valve 30, to the first input of the first integrator 35. The value of the parameter T = τ from the output of the second accumulating adder 11 through the normally closed contacts of the relay 17 is fed to the input of the second delay element 31, and directly - to the second input of the fifth adder 42 and to the first input of the first subtractor 20. The differential potential T ₂ = t ₂ from the output of the subtractor 20 is transmitted to the second inputs of the fourth block of nonlinearity 21 and the second integrator 40. In nonlinearity block 21 according to (7), the value P is calculated ₂ (t ₂ ) and is transmitted directly to the second input of the fourth multiplication block 26, and through the open seventh valve 32 to the first input of the second integrator 40. In the first 35 and second 40 integrators, the values of the product’s working state time T _f1 = t _f1 and T _{p2 p2} = t Correspondingly enno. The output signal of the first integrator 35 is transmitted to the first input, and the output signal of the second integrator 40 to the second input of the fourth adder 39. The addition result calculated according to (10) from the output of the adder 39 is transmitted to the first input of the division unit 43.

Simultaneously with the above, the value of τ _obs is calculated in accordance with relation (1). Moreover, from the fourth output of the memory unit 1, the value of τ _k1 is transmitted to the first input of the first adder 3. From the fifth output of memory block 1, the value of τ _{B is} supplied to the first inputs of the first block of nonlinearity 12, second 9, and third 10 adders. From the sixth output of memory unit 1, the values of τ _{k2 are} transmitted to the second inputs of the first 3 and third 10 adders. The output signal (τ _k1 + τ _k2 ) of the first adder 3 is supplied to the second inputs of the second adder 9 and the second non-linearity block 14. In the non-linearity blocks 12 and 14, the values of P (τ _B ) and P (τ _k1 + τ _k2 ) are generated, respectively. The output signals of the blocks of nonlinearities 12 and 14 are transmitted separately to the first and second inputs of the first block of multiplication 15. The result of multiplication P (τ _B ) · P (τ _k1 + τ _k2 ) from block 15 is fed to the second input of the second block of multiplication 16. In the third adder 10, the addition of τ _B and τ _k2 is realized. The result is transmitted to the first input of the second multiplication block 16. The output signal of block 16 is supplied to the first input of the third multiplication block 23, the second input of which from the fourth multiplication block 26 receives a signal corresponding to the value of P (τ). In the third block of multiplication 23, the product of its input quantities (τ _B + τ _k2 ) P (τ) · P (τ _B ) · P (τ _k1 + τ _k2 ) is realized and transmitted to the second input of the second subtractor 22. The output signal of the second adder 9 (τ _k1 + τ _B + τ _k2 ) enters the second subtractor 22 through its first input. In the subtractor 22, a value of τ _obs is generated, displayed by relation (1), and transmitted through the open fourth gate 27 to the third delay element 33 and to the first input of the fifth adder 42. The signal corresponding to the sum (τ + τ _obs ) from the output of the adder 42 transmitted to the dividing unit 43. The result of division of the calculated according to (11) the value K _T availability factor, the output is supplied through the fifth delay element 44 dividing unit 43 to a second input, and directly - the first input of the second comparator 36.

At the initial stage of operation of the device, i.e. for small values of the service period T, the function K _G (T) is monotonically increasing. In this regard, when comparing the current K _G (T _i ) and the delay delayed by the fifth element 44 for one cycle of calculating K _G (T _i-1 ) values, the control signal appears at the first output of the comparator 36 and is fed to the input through the OR 13 circuit multivibrator 5. A single output pulse of the multivibrator 5 will open the first 2 and second 4 gates. As a result of this, the values of the output quantities of the first 8 and second 11 accumulative adders will increase by the values of t ₁ and τ, respectively. Next, the process of calculating all the considered values and comparing the previous value of K _G (T _i-1 ) with the current K _G (T _i ) will be repeated. The number of calculation cycles will increase as long as the inequality K _G (T _i ) ≥K _G (T _i-1 ) persists. In each next cycle, the content of accumulating adders 8 and 11 will increase by t ₁ and τ, respectively, and stored in these adders until the next cycle of calculations. This increase is accompanied by a change in the values of other calculated values.

с выхода пятого элемента задержки 44 через девятый вентиль 45 поступит в элемент памяти 34 и на второй выход устройства. Оптимальное значение периода технического обслуживания T*=T_i-1 с выхода второго элемента задержки 31 через десятый вентиль 46 поступит на третий выход устройства. Реле 17 переключит выход второго накапливающего сумматора 11 на вход первого элемента задержки 18, разорвав связь сумматора 11 с входом второго элемента задержки 31. В то же время, управляющий сигнал со второго выхода второго компаратора 36, пройдя через схему ИЛИ 13, поступит на вход мультивибратора 5 и начнется второй этап работы устройства.As soon as it turns out in comparator 36 that K _Г (T _i ) <K _Г (T _i-1 ), the control signal will appear at its second output. According to this signal, the first 8 and second 11 accumulating adders are reset, the third trigger 37 will switch to a single state. Its output potential will go to the first control input of the memory element 34, to the control input of the relay 17, it will open the third 6, fifth 28, eighth 41, ninth 45 and tenth 46 valves, and the fourth 27, sixth 30 and seventh 32 valves will close. The calculated value τ _obs from the output of the third delay element 33 through the eighth valve 41 will go to the first output of the device. Maximum value $$K_R=K_{R_{i-\mathrm{one}}}$$

from the output of the fifth delay element 44 through the ninth valve 45 will go to the memory element 34 and to the second output of the device. The optimal value of the maintenance period T * = T _i-1 from the output of the second delay element 31 through the tenth valve 46 will go to the third output of the device. Relay 17 will switch the output of the second accumulating adder 11 to the input of the first delay element 18, breaking the connection of the adder 11 with the input of the second delay element 31. At the same time, the control signal from the second output of the second comparator 36, passing through the OR 13 circuit, will be input to the multivibrator 5 and the second stage of the device operation will begin.

. В компараторе 24 осуществляется сравнение вычисленного и заданного значений коэффициента оперативной готовности. В начале второго этапа работы устройства (при корректном задании значения $$K_{ОГ}^{зад}$$

) вычисленное значение $$K_{ОГ}^{выч}$$

будет больше заданного. Поэтому управляющий сигнал первого компаратора 24 с первого его выхода через схему ИЛИ 13 поступит на вход мультивибратора 5. Далее процесс вычисления значения K_ОГ и сравнение его с заданным $$K_{ОГ}^{зад}$$

повторится, но при новом ξ_i>ξ_i-1 значении времени ξ, возрастающем согласно (14). Каждое вычисленное значение $$K_{О{Г}_i}$$

с выхода пятого блока умножения 29 передается в четвертый элемент задержки 38, а значение величины ξ_i с выхода второго накапливающего сумматора 11 через реле 17 поступает в первый элемент задержки 18.Multivibrator 5 generates single pulses and transmits them to the blocks 2, 4, 8, 11 conjugated to it. The combination of blocks 19, 20, 21 and 26 provides the calculation of the value of Ρ (ξ ₁ = τ) similar to how these blocks functioned on the first stage of the device. The output signal Ρ (ξ ₁ ) of the fourth multiplication block 26 through the open fifth gate 28 will be fed to the first input of the fifth multiplication block 29. The value K _G (T *) comes to its second input from the output of the memory element 34. In the multiplication unit 29, the value of the operational readiness coefficient K _OΓ (ξ ₁ ) is calculated in accordance with (13) and transmitted to the first input of the first comparator 24, the second value of which comes from the eighth output of the memory unit 1 through the third gate 6 $$K_{\mathrm{ABOUT}R}^{s\mathrm{but}d}$$

. The comparator 24 compares the calculated and set values of the coefficient of operational readiness. At the beginning of the second stage of the device operation (if the value is set correctly $$K_{\mathrm{ABOUT}R}^{s\mathrm{but}d}$$

) calculated value $$K_{\mathrm{ABOUT}R}^{\mathrm{at}sh}$$

will be more than the given. Therefore, the control signal of the first comparator 24 from its first output through the OR 13 circuit will go to the input of the multivibrator 5. Next, the process of calculating the value of K _OG and comparing it with a given $$K_{\mathrm{ABOUT}R}^{s\mathrm{but}d}$$

will be repeated, but with a new ξ _i > ξ _i-1 time value ξ increasing according to (14). Each calculated value $$K_{\mathrm{ABOUT}{R}_i}$$

from the output of the fifth multiplication block 29 is transmitted to the fourth delay element 38, and the value of ξ _i from the output of the second accumulating adder 11 through the relay 17 enters the first delay element 18.

, управляющий сигнал возникнет на его втором выходе и поступит на второй вход второго триггера 25, переводя его в единичное состояние. Выходной потенциал триггера 25 поступит на разрешающие входы одиннадцатого 47 и двенадцатого 48 вентилей. В связи с этим, вычисленное значение $$K_{ОГ}^{выч}=K_{О{Г}_{i-1}}$$

с выхода четвертого элемента задержки 38 через вентиль 47 поступит на четвертый выход устройства. С выхода первого элемента задержки 18 через вентиль 48 допустимое значение величины ξ^доп=ξ_i-1 поступит на пятый выход устройства.As soon as when comparing in the first comparator 24 it turns out that $$K_{\mathrm{ABOUT}R}^{\mathrm{at}sh}<K_{\mathrm{ABOUT}R}^{s\mathrm{but}d}$$

, the control signal will occur at its second output and will go to the second input of the second trigger 25, translating it into a single state. The output potential of the trigger 25 will go to the enable inputs of the eleventh 47 and twelfth 48 gates. In this regard, the calculated value $$K_{\mathrm{ABOUT}R}^{\mathrm{at}sh}=K_{\mathrm{ABOUT}{R}_{i-\mathrm{one}}}$$

from the output of the fourth delay element 38 through the valve 47 will go to the fourth output of the device. From the output of the first delay element 18 through the valve 48, the permissible value of ξ ^add = ξ _i-1 will go to the fifth output of the device.

The control signal from the second output of the first comparator 24 will also go to the second control inputs of the first trigger 7 and the memory element 34. The trigger 7 will switch to the zero state and its output potential, coming to the ninth input of the memory unit 1, will close all its outputs. Memory element 34 is reset to zero. This completes the operation of the device.

The positive effect that can be obtained from the use of the proposed technical solution is to obtain the calculated values of the optimal service period and the corresponding values of the availability factor, the time required for the maintenance of the product, and the acceptable time interval after the service, in which the operational readiness of the product for application will be no less than specified. The calculated values of the output values allow you to reasonably plan the application and technical operation of the product.

When developing the device diagram, the functional elements described in [9] were used.

Information sources

1. Sedyakin N.M. About one physical principle of the theory of reliability. - Ed. Proceedings of the Academy of Sciences of the USSR, OTN, Technical Cybernetics, 1966, No. 3.

2. Colonel A.M. Fundamentals of reliability theory. - M.: Science, 1964.

3. Grishin V.D., Zinoviev S.V., Sokolov B.V., Maydanovich O.V. Patent RU 2452027, IPC G07C 3/08, 1012.

4. Sokolov B.V., Grishin V.D., Zelentsov V.A., Tsivirko E.G. Patent RU 2476934, IPC G07C 3/08, 2013.

5. Sokolov BV, Starodubov VA, Grishin VD, Tsivirko EG Patent RU 2476935, IPC G07C 3/08, 2013.

6. Sokolov BV, Grishin VD, Zelentsov VA, Maydanovich OV Patent RU 2479041, IPC G07C 3/08, 2013.

7. Sokolov B.V., Grishin V.D., Zinoviev S.V., Maydanovich OV, Zelentsov V.A. Decision on the grant of a patent dated 12/16/2013 by application No. 2012149898, IPC G07C 3/08, G06F 17/00, 2012.

8. Sokolov B.V., Grishin V.D., Zinoviev S.V., Zelentsov V.A., Tsivirko E.G. Decision on the grant of a patent dated December 16, 2013 by application No. 2012149896, IPC G07C 3/08, G06F 17/00, 2012.

9. Tetelbaum I.M., Schreider Yu.R. 400 circuits for ABM. - M .: Energy, 1978.

Claims (1)

A device for determining the values of the characteristics of the readiness of the product for use, containing a third multiplication unit, a memory unit, the first, second, third, seventh, eighth inputs of which are the same inputs of the device, the ninth input of which is connected to the first inputs of the second and third triggers, OR circuit, and the first a trigger, the first output of which is connected to the ninth input of the memory unit, and the second input - to the second output of the first comparator, to the second input of the memory element and to the second input of the second trigger, the output of which is inen with the control inputs of the eleventh gate and the twelfth gate, the output of which is the fifth output of the device, and the information input through the first delay element is connected to the second relay output, the first output of which through the second delay element is connected to the information input of the tenth valve, the output of which is the third output of the device , and the control input is connected to the output of the third trigger, to the first input of the memory element, to the control inputs of the fourth, fifth, sixth, seventh and eighth gates, and to the second relay input and to the control input of the third gate, the information input of which is connected to the eighth output of the memory unit, and the output to the second input of the first comparator, the first output of which is connected to the fourth input of the OR circuit, the third input of which is connected to the second output of the second comparator , with the second input of the third trigger, with the inputs "reset to zero" of the first and second accumulating adders, the second input of the OR circuit is connected to the first output of the second comparator, and the output through the multivibrator is connected to the control the odes of the first and second gates, the first accumulating adder and the second accumulating adder, the information input of which through the second gate is connected to the seventh output of the memory unit, and the output is connected to the first input of the relay, to the second input of the fifth adder and to the first input of the first subtractor, the second input of which together with the second inputs of the first integrator and the third nonlinearity block, it is connected to the output of the first accumulating adder, the input of which is connected through the first gate to the second output of the memory block, the third the stroke of which is connected to the first input of the fourth non-linearity block, the second input of which is connected to the output of the first subtractor and to the second input of the second integrator, and the output is connected to the information input of the seventh valve, the output of which is connected to the first input of the second integrator, the output of which is connected to the second input of the fourth an adder, the first input of which is connected to the output of the first integrator, the first input of which is connected to the output of the sixth valve, the information input of which is connected through the third non-linearity block the first output of the memory block, and directly to the first input of the fourth multiplication block, the second input of which is connected to the output of the fourth non-linearity block, and the output is connected to the information input of the fifth gate, the output of which is connected to the first input of the fifth multiplication block, the second input of which is connected to the output memory element, and the output is directly connected to the first input of the first comparator and through the fourth delay element to the information input of the eleventh gate, the output of which is the fourth output of the properties, the first output of which through the eighth gate is connected to the output of the third delay element, and the second output of the device is connected to the information input of the memory element and to the output of the ninth valve, the information input of which is connected to the second input of the second comparator and to the output of the fifth delay element, the input of which is connected with the first input of the second comparator and with the output of the division unit, the second input of which is connected to the output of the fifth adder, and the first input to the output of the fourth adder, characterized in that the second, third and third adders, the first and second non-linearity blocks, the first and second multiplication blocks, the fourth, fifth and sixth inputs of the device being the same inputs of the memory block, the first output of which is connected to the first input of the second non-linearity block, the second input of which is connected to the second the input of the second adder and the output of the first adder, the first input of which is connected to the fourth output of the memory block, the fifth output of which is connected to the first inputs of the second and third adders and to the first input of the first block which has a second input connected to the third output of the device, and the output is connected to the first input of the first multiplication block, the second input of which is connected to the output of the second non-linearity block, and the output is connected to the second input of the second multiplication block, the sixth output of the memory block is connected to the second input of the first the adder and the second input of the third adder, the output of which is connected to the first input of the second multiplication block, the output of which is connected to the first input of the third multiplication block, the second input of which is connected with the output of the fourth block multiplication, and the output is connected to the second input of the second subtractor, the first input of which is connected to the output of the second adder, and the output is connected to the information input of the fourth gate, the output of which is connected to the input of the third delay element and to the first input of the fifth adder.

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