RU2452027C2 - Device for determining values of operational characteristics of article - Google Patents

Abstract

FIELD: information technology.

SUBSTANCE: device for determining values of operational characteristics of an article has a memory unit, five rectifiers, a multivibrator, two flip-flops, an attenuator, two adder accumulators, an OR circuit, a comparator, two nonlinearity units, three subtractors, two delay elements, three memory elements, two integrators, two multipliers, three adders and a divider.

EFFECT: high accuracy of the device by taking into account differences in failure rate values.

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Description

The invention relates to computer technology, in particular to control devices. It can be used in experimental design work and operating practice to determine the optimal frequency of technical maintenance of products and the corresponding quality indicators of their functioning.

There are devices [3, 4, 5, 6] designed to determine the optimal periods of technical maintenance of products. The scope of their application is limited to products that are constantly functioning in operating mode. The use of these devices, in relation to products with a variable operating mode, does not provide the necessary accuracy in determining the values of the output parameters.

The closest in technical essence to the claimed invention is a device [7] containing adders, a multiplication unit, a nonlinearity unit, memory elements, an integrator, timers, a division unit, delay elements, triggers, an OR element, comparators and keys. This device has the same disadvantages as its counterparts [3, 4, 5, 6].

Each product continuously expends its reliability potential, and the consumption rate depends on the mode of its use [1]. The change in mode is manifested in a change in the failure rate. This must be considered when determining the parameters of the product maintenance strategy.

The purpose of the proposed technical solution is to increase accuracy and expand the scope of the device. The goal is achieved by implementing a mathematical model that allows you to take into account the difference in the values of the failure rate according to changes in the mode of operation of the product.

The process of applying many products is cyclical. Each cycle may include the operation of the product in nominal mode, in light mode, as well as a rest mode. The application process diagram has the form

Here τ is the duration of the product application cycle (for example, one day);

t ₁ - the duration of use in nominal mode with a load factor k _n equal to one. Moreover, the failure rate has a value of λ ₁ .

On the interval t ₂ = τ-t ₁ various products, depending on the technology of their application and the actual load, can be in one of the following modes:

a) lightweight mode, in connection with the reduction of the load (for example, means of energy systems of continuous use);

b) rest after use (for example, technical equipment of enterprises working in one or two shifts; means of radio and television studios; on-board equipment of vehicles and much more).

In this regard, in the time interval t ₂ the failure rate λ ₂ will have different values λ ₂ = λ ₁ · k _n in accordance with the change in the coefficient k _{n of the} load. Note that according to [2], in the case of a lightweight mode of operation of the product, k _n <1, and in the rest mode, according to [1], 0 <k _n << 1 (It is confirmed in a number of later publications by authors - followers of the author of [1 ]).

циклов применения длительностью τ каждый, т.е.To maintain the product in working condition, its maintenance is periodically carried out and the time τ _obs . At the same time, in-depth condition monitoring, routine maintenance and restoration of the product’s performance in case of failure is performed. The duration of the service period T includes many

application cycles of duration τ each, i.e.

The total duration of the product in the nominal mode of operation on the time interval T will be

and the duration of the product in another mode (rest or reduced load) is expressed as

Service Duration is

The probability of failure-free operation of the product on the time interval T is determined by the ratio

For many products, the predominance of sudden failures is characteristic and the exponential distribution of the time of their occurrence is applicable. In this regard, the following relationships hold:

At any time interval t, the product can be in one of two states

t = t _f + t _o ,

where t _f - time operational state;

t _o - time spent in denial.

During one cycle of application of the product in nominal mode, the last ratio has the form

Likewise, in the interval of the light mode or rest mode, there will be

The working time of the product in the interval of one application cycle is determined by the formula

and on the time interval T its value will be

Based on the foregoing, the possible time the product is in a state of failure at the same interval T is expressed as

An important quantitative characteristic of product quality is the downtime coefficient, its value is determined by the formula

Where

- product downtime.

The organization of the operation of products provides for the determination of the terms of maintenance, ensuring the required quality of their

коэффициентаvalid value

coefficient

just me. The task of determining the optimal period of product maintenance is written as follows:

The proposed mathematical model can be implemented in hardware using a device, a diagram of which is shown in Figure 1.

The device contains: a memory unit 1; first 2; second 3; third 16; fourth 26 and fifth 33 gates; multivibrator 4, working in standby mode; first 5 and second 11 triggers; attenuator 6; the first 7 and second 8 accumulative adders; circuit OR 9; comparator 10; the first 12 and second 18 blocks of nonlinearities; first 13, second 22 and third 29 subtracters; the first 14, second 24 and third 31 delay elements; the first 15, second 25 and third 32 memory elements; first 17 and second 28 integrators; the first 19 and second 21 blocks of multiplication; first 20, second 27 and third 30 adders; division block 23.

Note the following:

a) two subtractors from the three claimed devices are considered equivalents of two prototype adders;

b) all valves are equivalent to the corresponding keys of the prototype;

c) not involved three memory elements of the prototype, neither separately nor in aggregate, can be considered as equivalent to the memory block 1 of the claimed device, since they do not allow to realize its capabilities.

All noted in the text of the claims.

Figure 2 shows the scheme of the accumulating adder corresponding to the adders 7 and 8 of the device. Each of them contains an adder 1, the first 2 and second 3 memory elements and the element NOT 4. The process of accumulation and output of the results occurs according to the control signals of the multivibrator 4 of the device supplied to the second input of the accumulating adder.

The work of the accumulating adder is as follows. In the initial state, in the absence of a control signal, the first memory element 2 is closed, and the second memory element 3 is opened by the output signal of the element NOT 4. When a control signal is received from the multivibrator 4 of the device, the output of the second memory element 3 is closed, the first memory element 2 is opened, and the first input adder 1 receives the set value of the corresponding time parameter. The output signal of the first memory element 2 is transmitted to the second memory element 3 and to the second input of the adder 1. In the adder 1, the values of its input values are added, the result of addition is transmitted to the first memory element 2. The duration of the output pulse of the multivibrator 4 of the device provides a single update of the contents of the first 2 and second 3 memory elements. On the trailing edge of the output signal of the multivibrator 4 of the device, the output of the first memory element 2 is closed (the updated value of its input signal is stored) and the output of the second memory element 3, which is the output of the accumulating adder, is opened. Upon receipt of each next control signal from the multivibrator 4 of the device, the value of the output signal of the accumulating adder increases by the value of its input signal. Element NOT 4 serves to ensure that memory elements 2 and 3 work in antiphase.

вводятся в блок памяти 1 через его входы с 1 по 5 соответственно. Значение коэффициента нагрузки К_н задается аттенюатором 6 через его первый вход, являющийся шестым входом устройства.Before starting the operation of the device, the initial data λ ₁ , t ₁ , τ, τ _obs ,

are entered into the memory unit 1 through its inputs 1 to 5, respectively. The value of the load factor K _n is set by the attenuator 6 through its first input, which is the sixth input of the device.

The process of determining the optimal solution is iterative in nature. Consistently in each i-th operation cycle of the device, the value of the service period T increases according to (1).

Similarly, according to (2) and (3), the values of T ₁ and T ₂ increase.

. Процесс поиска решения прекращается при К_П(T)>

.Accordingly, the value of the criterion function K _P (T) is calculated and compared with a given value

. The solution search process terminates when K _P (T)>

.

The device operates as follows. According to the "Start" signal coming from the seventh input of the device, the second trigger 11 switches to the zero state and closes the output valves 16, 26, 33 of the device; the first trigger 5 is transferred to a single state, thereby providing the values of the stored data to the outputs of the memory unit 1. In addition, the “Start” signal, passing through the OR 9 circuit, is fed to the input of the multivibrator 4. Multivibrator 4 generates a single pulse, transfers it to the control inputs of the first 2 and second 3 gates and opens them for a time equal to the duration of this pulse. A single signal of the multivibrator 4 is also fed to the control inputs of the first 7 and second 8 accumulating adders and ensures their implementation of the process of accumulation and transmission of results to the associated circuit elements of the device.

From the second output of the memory unit 1 through the first valve 2, the value of t _{1 is} supplied to the first accumulating adder 7, and from the third output of the memory unit 1 through the second gate 3 to the second accumulating adder 8, the value of τ is received. At the same time, from the first output of memory unit 1, the signal corresponding to the value of λ ₁ is transmitted to the second input of the attenuator 6 and to the first input of the first non-linearity block 12.

Consider in detail the first cycle of the device.

The output signal T ₁ = t _{1 of the} first accumulating adder 7 is supplied to the second inputs of the first non-linearity block 12, the first integrator 17 and the first subtractor 13. In the non-linearity block 12, according to (6), the probability value P ₁ (t ₁ ) is calculated and transmitted to the first inputs of the first integrator 17 and the second block of multiplication 21. The output signal of the attenuator 6, corresponding to the value of the failure rate λ ₂ = λ ₁ * K _n , is transmitted to the first input of the second block of nonlinearity 18. The value of the parameter T = τ from the output of the second accumulating adders 8 is transmitted on in d of the first delay element 14, to the first inputs of the first subtracter 13 and the first adder 20 and also to a second input of the third subtracter 29. The difference potential T ₂ = t ₂ from the output of first subtracter 13 is supplied to the second inputs of the second block 18 and the non-linearity of the second integrator 28 In the second block of nonlinearity 18, according to (7), the probability value P ₂ (t ₂ ) is calculated and transmitted to the first input of the second integrator 28 and to the second input of the second multiplication block 21. In the first 17 and second 28 integrators, the operating state time values are generated and items T _f1 = t _f1 and T _f2 = t _f2, respectively. The output signal of the first integrator 17 is transmitted to the first input, and the output signal of the second integrator 28 to the second input of the second adder 27. The addition result, calculated according to (11) with i = l, from the output of the second adder 27 goes to the first input of the third subtractor 29. At the same time, in the second block of multiplication 21, in accordance with (5), the probability of failure-free operation P (τ) is calculated and transmitted to the second input of the first block of multiplication 19. The value of τ _obs s is received at the first inputs of the first multiplication block 19 and the second subtractor 22 the fourth output of the memory unit 1. In the multiplication unit 19, a signal τ _obs P (τ) is generated and transmitted to the second input of the second subtractor 22. The output signal τ _obs- τ _obs P (τ) of the second subtractor 22 is transmitted to the second inputs of the first 20 and third 30 adders . At the first input of the adder 30 from the output of the third subtractor 29, a difference signal is received, expressed by relation (12) as applied to the first cycle of the device, i.e. t ₀ = τ-t _f .

коэффициента простоя.The signal corresponding to the relation (14), from the output of the third adder 30 is fed to the input of the third delay element 31 and to the first input of the division unit 23. In the first adder 20, a signal corresponding to the denominator of the ratio (13) is generated and transmitted to the second input of the division unit 23 The division result corresponding to the calculated value of the downtime coefficient is output from the division block 23 to the input of the second delay element 24 and to the second input of the comparator 10, to the first input of which a predetermined value is supplied from the fifth output of the memory unit 1

idle rate.

с вычисленным

повторится. Число циклов вычислений будет увеличиваться пока будет сохраняться неравенство

. В каждом очередном цикле содержание накапливающих сумматоров 7 и 8 будет увеличиваться на величину t₁ и τ соответственно и сохранятся в этих сумматорах до очередного цикла вычислений. Это увеличение сопровождается изменением значений всех других расчетных величин.For real products, it is true that in the first cycle of the device (τ = T), the calculated value of the downtime coefficient will be less than the specified value. Therefore, as a result of their comparison in the comparator 10, a control signal will appear at its first output, which, passing through the OR 9 circuit, will be fed to the input of the multivibrator 4. A single output pulse of the multivibrator 4 will open the first 2 and second 3 valves. As a result of this, the values of the output values of the first 7 and second 8 accumulative adders will increase by t ₁ and τ, respectively. Further, the process of calculating all quantities and comparing the set value

with calculated

will happen again. The number of computation cycles will increase while inequality persists

. In each next cycle, the content of accumulating adders 7 and 8 will increase by t ₁ and τ, respectively, and will be stored in these adders until the next cycle of calculations. This increase is accompanied by a change in the values of all other calculated values.

The calculated values of the service period T, the idle coefficient K _p (T) and the idle time T _pr delayed by the delay elements 14, 24, 31 for the duration of one calculation cycle are transmitted, respectively, to the first 15, to the second 25 and to the third 32 memory elements . After each next cycle of the device, the data values of these memory elements are updated.

управляющий сигнал появится на его втором выходе и поступит на вторые входы первого 5 и второго 11 триггеров. При этом первый триггер 5 переключится в нулевое состояние и его выходной потенциал, поступив на шестой вход блока памяти 1, закроет все выходы этого блока. Второй триггер 11 переключится в единичное состояние. Выходной потенциал второго триггера 11 откроет вентили 16, 26 и 33, а также поступит на управляющие входы первого 15, второго 25 и третьего 32 элементов памяти. Вычисленное согласно (1) значение периода обслуживания T^*, соответствующее условию (15), с выхода первого элемента памяти 15 через открытый третий вентиль 16 поступит на первый выход устройства. Значение коэффициента простоя K_П(T^*) с выхода второго элемента памяти 25 через открытый четвертый вентиль 26 поступит на второй выход устройства. Вычисленное в соответствии с (14) время простоя Т_пр(Т^*) с выхода третьего элемента памяти 32 через открытый пятый вентиль 33 поступит на третий выход устройства. На этом работа устройства заканчивается.As soon as in comparator 10 it turns out that

the control signal appears on its second output and goes to the second inputs of the first 5 and second 11 triggers. In this case, the first trigger 5 will switch to the zero state and its output potential, having entered the sixth input of the memory block 1, will close all the outputs of this block. The second trigger 11 will switch to a single state. The output potential of the second trigger 11 will open the gates 16, 26 and 33, and will also go to the control inputs of the first 15, second 25 and third 32 memory elements. The value of the service period T ^* calculated according to (1), corresponding to condition (15), from the output of the first memory element 15 through the open third gate 16 will go to the first output of the device. The value of the idle coefficient K _P (T ^* ) from the output of the second memory element 25 through the open fourth valve 26 will go to the second output of the device. The idle time T _pr (T ^* ) calculated in accordance with (14) from the output of the third memory element 32 through the open fifth gate 33 will go to the third output of the device. This completes the operation of the device.

The positive effect that can be obtained from the use of the proposed technical solution is to obtain the calculated values of the service period, downtime coefficient and downtime, calculated taking into account the variable use of the product. The calculated values of the output values allow you to reasonably plan the application and technical operation of the product.

When developing the device diagram, the functional elements described in [8] were used.

Information sources

1. Sedyakin N.M. About one physical principle of the theory of reliability. - Ed. Proceedings of the Academy of Sciences of the USSR, OTN, Technical Cybernetics, 1966, No. 3.

2. Colonel A.M. Fundamentals of reliability theory. - M.: Science, 1964.

3. Grishin V.D., Manuylov Yu.S., Schenev A.N. Patent RU No. 2206123, IPC G07C 3/08, 2003.

4. Grishin V.D., Pavlov A.N., Mikhailov E.P. Patent RU No. 2343544, IPC G07C 3/08, 2009.

5. Grishin V.D., Kudryashov A.N., Timoshenko D.V. Patent RU No. 2347272, IPC G07C 3/08, 2009.

6. Grishin V.D., Myshinsky D.A., Taganov I.Yu. Patent RU No. 2361277, IPC G07C 3/08, 2009.

7. Grishin V.D., Shulgin A.E., Petrov A.A. Patent RU No. 2361276, IPC G07C, 3/08, 2009.

8. Tetelbaum I.M., Schreider Yu.R. 400 schemes for AVM. - M .: Energy, 1978.

Claims (2)

1. A device for determining the values of the operational characteristics of the product, containing the first and second valves, the first trigger, OR circuit, the first subtractor; the first non-linearity unit, the output of which is connected to the first input, and the second input with the second input of the first integrator, the output of which is connected to the first input of the second adder; the first multiplication unit, the output of which is connected to the second input of the second subtractor, the output of which is connected to the second input of the third adder, the output of which through the third delay element is connected to the information input of the third memory element, and directly to the first input of the division unit, the second input of which is connected to the output of the first adder, and the output through the second delay element is connected to the information input of the second memory element and is directly connected to the second input of the comparator, the second output of which is connected nen with the second input of the second trigger, the output of which is connected to the control inputs of the first, second and third memory elements, the third, fourth and fifth gates, the information input of the fifth gate is connected to the output of the third memory element, and the output is the third output of the device, the second output of which is the output of the fourth gate, the information input of which is connected to the output of the second memory element; the first output of the device is the output of the third gate, the information input of which is connected to the output of the first memory element, the information input of which through the first delay element is connected to the first input of the first adder, characterized in that a memory unit, attenuator, multivibrator generating single pulses are inserted into it, two accumulating adders, a second nonlinearity block, a second multiplication block, a second integrator and a third subtractor, and from the first to fifth inputs of the device are the inputs of the same name As for the memory, the sixth input of the device is the first input of the attenuator, and the seventh input is connected to the first inputs of the second trigger, OR circuit, and the first trigger, the second input of which is connected to the second input of the second trigger, and the output is connected to the sixth input of the memory block, the first output of which is connected with the second input of the attenuator and with the first input of the first nonlinearity block, the second input of which, together with the second input of the first subtractor, is connected to the output of the first accumulating adder, and the output is connected to the first input of the second block multiplication, the output of which is connected to the second input of the first block of multiplication, and the second input is connected to the first input of the second integrator and to the output of the second nonlinearity block, the first input of which is connected to the output of the attenuator, and the second input is connected to the output of the first subtractor and the second input of the second integrator whose output is connected to the second input of the second adder, the output of which is connected to the first input of the third subtractor, the output of which is connected to the first input of the third adder, the second input of which is connected to the second the course of the first adder, the first input of which is connected with the first input of the first subtractor, with the second input of the third subtractor and with the output of the second accumulating adder, the first input of which is connected to the output of the second gate, the information input of which is connected to the third output of the memory unit, the second output of which is connected to the information input of the first gate, the output of which is connected to the first input of the first accumulating adder, and the control input together with the control input of the second valve is connected to the output of the multivibra torus, whose input is connected to the output of OR gate, the second input of which is connected to the first output of the comparator, the first input of which is connected to a fifth output of the storage unit, fourth output of which is connected to the first inputs of the first multiplication block and the second subtractor. 2. The device according to claim 1, characterized in that the accumulating adder contains an adder, the first input of which is the information input of the accumulating adder, and the output is connected to the information input of the first memory element, the control input of which is the control input of the accumulating adder and is NOT connected to the control input of the second memory element, the information input of which is connected to the second input of the adder and with the output of the first memory element, and the output is the output of the accumulating adder.

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