RU2411568C2 - Device for information display - Google Patents

Abstract

FIELD: information technologies.

SUBSTANCE: device includes the second and third registers, group of majority elements, number of which is determined by number of digits of information input of device, information inputs of the second and third registers are connected to appropriate information inputs of device, information outputs of the first register are connected to the first inputs of majority documents, information outputs of the second register are connected to the second inputs of majority elements, information outputs of the third register are connected to third inputs of majority elements, outputs of which are connected to inputs of coupling unit, the second output of address decoder is connected to recording input of the second register, the third output of address decoder is connected to recording input of the third register and to input of delay element.

EFFECT: reliability and fault tolerance improvement.

2 cl, 1 dwg

Description

This invention relates to computer technology and automation, can be used in equipment with high reliability, not having access for repair, for example for spacecraft.

A device for outputting information that contains the address decoder, the first and second element AND, the OR element, the delay element, the first and second one-shot and data register (AS No. 1548781, G06F 3/00, G06F 13/00, author B. P. Tkachev).

However, this device has insufficient reliability.

Closest to the proposed technical essence is a device for outputting digital information from a parallel highway, containing a register, an AND element, a delay element, an address decoder, a comparison unit, information inputs of the register are information inputs of the device, and the outputs are connected to the inputs of the interface unit (trunk amplifiers ), the outputs of which are the information outputs of the device, the input of the register entry is connected to the output of the decoder, the inputs of which are the address inputs of the device, p the first group of inputs of the comparison unit is connected to the information inputs of the register, the second group of inputs of the comparison unit is connected to the outputs of the interface unit, and the output is connected to the first input of the element And whose outputs are the control output of the device, the second input of the element And is connected to the output of the delay element, the input of which connected to the output of the decoder (AS No. 1608631, G06F 3/00, author VVVinogradov), which is selected as a prototype.

This device has insufficient robustness and reliability. Namely, if there are failures at the information inputs of the device at the time of writing, the information will be entered into the register, therefore, information will be recorded at the information outputs of the device, and if at the time of comparison the information on the information inputs of the device is restored, then the information recorded in the register and at the information outputs of the device, it will be different, therefore, information at the information outputs of the device will be skipped. In addition, the device does not have a signal about a malfunction, for example, a register due to the action of heavy charged particles (TZZ) of outer space, to which memory elements are especially susceptible.

The aim of the invention is to remedy these disadvantages.

This goal is achieved by the fact that the second and third registers are introduced into the device, a group of majority elements, the number of which is determined by the number of bits of the information input of the device, the information inputs of the second and third registers are connected to the corresponding information inputs of the device, the information outputs of the first register are connected to the first inputs of the majority elements , the information outputs of the second register are connected to the second inputs of the majority elements, the information outputs of the third reg tra third inputs connected to the majority elements, whose outputs are connected to inputs of the conjugation unit, the second output of the address decoder connected to the recording input of the second register, the third output of the address decoder connected to the input of the third register to the input of the recording and the delay element.

In addition, the second AND element and the OR element are led into it, and the comparison unit contains the outputs “more” and “less”, which are connected to the inputs of the OR element, the output of which is connected to the first input of the second element AND, the second input of which is connected to the output of the element delays, the output of the second element And is the signal output of the "malfunction" of the device.

The drawing shows a functional diagram of a device for outputting digital information.

The device for outputting digital information contains address inputs 1 connected to the address decoder 2, information inputs 3 connected to the first group of inputs of the comparison unit 4 and to information inputs of the first, second, third registers 5, 6, 7, delay element 8, OR element 9, two elements And 10 and 11, the outputs of which respectively are the output “Control” 12 of the device and the output “Fault” 13 of the device, a group of major elements 14 by the number of bits of the information input of the device, the outputs of which are connected to the inputs of the unit interface 15, the outputs of which are connected to the second group of inputs of the comparison unit 4 and are information outputs 16 of the device, the first output of the decoder 2 is connected to the recording input of the first register 5, the second output is connected to the recording input of the second register 6, the third output is connected to the recording input of the third register 7 and with the input of the delay element 8, the output of which is connected to the first inputs of the elements And 10 and 11, the second input of the first element And 10 is connected to the output "equal" of the comparison unit 4, and the outputs "more" and "less" are connected to the inputs of the element tent OR 9, the output of which is connected to the second input of the second element And 11, the information outputs of the first register 5 are connected to the first inputs of the majority elements 14, the information outputs of the second register 6 are connected to the second inputs of the majority elements 14, the information outputs of the third register 7 are connected to the third inputs majority elements 14.

The device operates as follows. Information is exchanged between the control device and the output device via address input 1 and information input 3. The required data for output are set to information inputs 3, when the addresses of the first register 5, second register 6 and third register 7 are sequentially fed to address inputs 1 in the corresponding registers 5, 6, 7, the information from which is majorized in the majority elements 14 and through the interface unit 15 is fed to output 16, if the data at input 3 and output 1 coincide 6 of the device at the output “is equal to” of the comparison unit 4, logical 1 is formed. After a time determined by the delay element 8, the output of the first element And 10 displays a signal about the readiness of information at the output of the device 16. If the data at input 3 and the output 16 of the device do not match at the output “more” or “less” of the comparison unit 4, logical 1 is formed, which, through the OR element 9, enters the second input of the second element And 11 and after a time determined by the delay element 8, at the output of the second element And 11 and, therefore, at the output 13 appears A signal about the device malfunction. Delay element 8 provides the completion time of transients in register 7, in majority elements 14, in the interface unit 15 and in the comparison unit 4. The spacing of entries in the registers allows to parry short-term single failures at the information inputs of the device, and the failure of one of the three registers does not entail failure of the device itself.

This device is supposed to be used in spacecraft control equipment. The prototype is made on integrated circuits of the 1526 series, the delay element is made on an RC chain.

Of the sources of information and patent materials known to the author, the totality of features similar to the totality of features of the claimed subject matter is not known.

Claims (2)

1. A device for outputting information containing an address decoder, a comparison unit, a register, a delay element, an AND element, a pairing unit, information inputs of the device are connected to the information inputs of the register and to the first group of inputs of the comparison unit, the second group of inputs of which are connected to the outputs of the interface unit which are the information outputs of the device, the output of the comparison unit is connected to the first input of the And element, the outputs of which are the control output of the device, the address inputs of the decoder are address and device inputs, and the output is connected to the register entry, the output of the delay element is connected to the second input of the And element, characterized in that the second and third registers are introduced into it, a group of major elements, the number of which is determined by the number of bits of the information input of the device, information inputs of the second and the third registers are connected to the corresponding information inputs of the device, the information outputs of the first register are connected to the first inputs of the majority elements, the information outputs of the second the second register are connected to the second inputs of the majority elements, the information outputs of the third register are connected to the third inputs of the majority elements, the outputs of which are connected to the inputs of the interface unit, the second output of the address decoder is connected to the input of the second register, the third output of the address decoder is connected to the input of the third register and with the input of the delay element. 2. The device according to claim 1, characterized in that the second AND element and the OR element are inserted into it, and the comparison unit contains the outputs “more” and “less”, which are connected to the inputs of the OR element, the output of which is connected to the first input of the second element And, the second input of which is connected to the output of the delay element, the output of the second element And is the signal output of the "malfunction" of the device.