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EP0092211A1 - Dispositif de commutation de programme de temps électronique - Google Patents

Dispositif de commutation de programme de temps électronique Download PDF

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Publication number
EP0092211A1
EP0092211A1 EP83103713A EP83103713A EP0092211A1 EP 0092211 A1 EP0092211 A1 EP 0092211A1 EP 83103713 A EP83103713 A EP 83103713A EP 83103713 A EP83103713 A EP 83103713A EP 0092211 A1 EP0092211 A1 EP 0092211A1
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EP
European Patent Office
Prior art keywords
time
memory
button
circuit
switching device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP83103713A
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German (de)
English (en)
Other versions
EP0092211B2 (fr
EP0092211B1 (fr
Inventor
Winfried Brandenberg
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Legrand GmbH
Original Assignee
Westdeutsche Elektrogeraetebau GmbH
Legrand GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
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Application filed by Westdeutsche Elektrogeraetebau GmbH, Legrand GmbH filed Critical Westdeutsche Elektrogeraetebau GmbH
Priority to AT83103713T priority Critical patent/ATE30974T1/de
Publication of EP0092211A1 publication Critical patent/EP0092211A1/fr
Application granted granted Critical
Publication of EP0092211B1 publication Critical patent/EP0092211B1/fr
Publication of EP0092211B2 publication Critical patent/EP0092211B2/fr
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • G—PHYSICS
    • G04—HOROLOGY
    • G04G—ELECTRONIC TIME-PIECES
    • G04G15/00—Time-pieces comprising means to be operated at preselected times or after preselected time intervals
    • G04G15/006—Time-pieces comprising means to be operated at preselected times or after preselected time intervals for operating at a number of different times

Definitions

  • the present invention relates to an electronic time or time program switching device, comprising an electronic clock with a clock generator and several divider stages, a central unit with read / write work memories and / or read-only memories, computer, ie. arithmetic-logic unit for the processing of data, as well as program memory with associated program counter and decoding devices, and a luminous digit on direction, an input unit with controls, such as buttons and switches, an output unit for the excitation or de-excitation of switch devices for consumer circuits, and finally control and power supply modules, as well as a housing in the front wall of control and setting fields and at least one luminous digit device is arranged, with further special features according to the preamble of claim 1.
  • time switches with electromechanical drive and mechanical switching devices, such as radially displaceable switching segments, plug-in switching fingers, or the like, have recently become increasingly high. So now and in the future it will probably be required even more that at least several time switch programs, ie. with differences in different days of the week and also for several switching channels with partially different time switching programs should be as easy and error-free to set.
  • the switching data record cannot be completely entered, but only a partial section thereof, for example. with a single day of the week, either an ON switching time or an OFF switching time; Combinations e.g. of several days of the week with the same ON and OFF switching times are neither possible in the display nor can they be checked at the same time.
  • a pattern for a programming sheet is therefore included in the operating instructions.
  • the invention is therefore based on the object of improving a time or time program switching device and its modules according to the preamble of claim 1, ie. the display device for the ON and OFF switching times with any number of days of the week and possibly different switching channels - optionally adjustable in any change of the sections of the complete data set - combined with the operating elements and intermediate memories so that they can be controlled and designed so that the individual switching times and secondary data can be configured can be entered in any order and the entry of inadmissible switching time data is excluded from the outset, incorrect or no longer required input data for switching times in individual sections can be corrected as desired and complete data sets with ON and OFF switching times, weekday (s) and secondary data, e.g. selected switching channels or choice between ON or OFF switching time, can be clearly read and adjusted or corrected during the entire setting process.
  • Fig.la the top view - from the front as a front view - is shown on the timer with closed housing 1, from which one can see the division of the front panel 2 into the control panel 3 and the display panel 4.
  • the control panel 3 itself is also divided into subfields 5 to 8 in accordance with the outline of the control elements, the bottom 5 being the function selection main switch 9 "STEL / AUT” and the group of switching channel selector switches 1o to 13 ("Sl to S4"), the upper strip 14 of the keypad 6 "SET” the function selection keys 15 (CLOCK), 16 (ON switching time) and 17 (OFF switching time), the middle strip 18 and the lower strip 19 the setting keys "h” 2o (hours ), "m” 21 (minutes), “s” 22 (seconds), “d1-7” 23 (weekdays), "Sl-4" 24 (switching channels) and "Q” 25 (acknowledgment); the last one
  • the key mentioned belongs to the variant of the single-digit input that is possible in the two cases "dl-7
  • the associated data is shifted by one digit, ie the previously entered value is deleted and the character concerned is only added to the associated buffer memory to the data that may already be stored there by actuating the "Q" key.
  • Display field 4 shows the ⁇ complete data record for a switching time pair - in the case of a query - or part of it when it is first entered after complete deletion - with the switching time image in an upper half 3o for the ON switching time with the symbol "I” 31 and a lower half 32, mirrored from top to bottom, is divided with the symbol "0" 33 and each half except for the times "h", “m” and “s” with a colon between the data for "h “and” m “below and above the same bar marks 35, 36 in seven adjacent positions corresponding to the days of the week and in the right part 37 of the display field 4 arrows one above the other. 38 for the display of the selected switching channels.
  • the special division of the operating (3) and display fields (4) gives the user a particularly easy and fail-safe setting of the timer data.
  • the routine selected with the function selector key "CLOCK” he can set the built-in electronic clock by pressing the setting keys 2o to 22 "h”, “m” and “s”, as well as for the valid weekday "dl-7” - Press as often or as long (for automatic pulse train) until the relevant section value matches the current time, after which he presses the function selection key 29 "AUT" to transfer the set half data record to the buffer for the current time and release the continuation the automatic operation of the electronic timer and thus the ongoing automatic adjustment of the built-in electronic clock.
  • the user For the purpose of setting the ON and OFF switching times, the user has only one of the function selection buttons "I” 16 and “O” 17 and then again in succession - in any order - the setting buttons 2o to 25 for the associated switching times, days of the week and Actuate switching channels, also as long or as often until the desired values are displayed in the individual sections; if this is the case, he in turn only has to press the function selection key 29 "AUT” or "PROGR”, whereupon the complete data record shown in the display field 4 as associated digits, identifiers and symbols is transferred to the working memory or the associated register and also "AUT" operation is restored.
  • the geometric arrangement of the setting keys 2o to 25 and the function selection keys 15 to 17 and 29 in accordance with the order also makes operation easier, because the function selection keys 15 to 17 and 29 are in a common line 39, the group of keys 26 to 28 for the interrogation, correction and deletion in sections, which also includes the total reset by means of the pushbutton 41 "Reset", in a line 4o perpendicular thereto and the actual setting keys are accommodated in the subfield lying between them.
  • FIGURE 1b a partial section in the longitudinal direction, the arrangement of the circuit board 51, double-sided self-aligning manner by clamping attachment between ribs 52 which are of the housing top part is integrally formed on the side wall 53, and the end surfaces of the side wall 54 of the housing lower section supported.
  • the function selection and the setting buttons 55 to 58 are each from a neck, for example. 53, of rectangular cross-section and a head plate 6o composed of a rubber-like material with additives made conductive and in its entirety by an elastic support surface 61 and connected to it integrally and integrally.
  • the contact surface 61 is pressed onto the circuit board below the neck in question and the ends of conductor tracks applied at this point are thus conductively connected, ie.
  • the necks 55 to 59 are formed by the webs integrally formed below the front plate 2, for example. 62, 63, and the support surface 61 through the intermediate webs also integrally formed there, for example. 64 held at a precisely uniform distance from the front plate 2 self-adjusting.
  • the semiconductor compact brick 67 with the display device and associated electronic assemblies is installed directly under the window 68 in the front panel 2 in the display panel 66 and is electrically connected to the circuit board 51 of the circuit board 51 by the associated connecting lugs.
  • On the inside of the printed circuit board 51 are printed circuit boards 69, 7o at right angles to it, as indicated, for mechanical stiffening and for mounting larger components, such as capacitors of the power supply part, a battery for the power reserve, and the relays appropriate.
  • Fig.lc is the top view of the bare upper housing part 1 with holes 81, 82 for screwing it to the lower housing part, with openings for the window 83 belonging to the display device, for function selection and setting keys, for example.
  • FIG. 2a shows in the bottom view of the upper housing part 101 the integrally molded frame lo2 of the window lo3 for the display device (not shown) and the holding frame lo4 for this, as well as the openings, for example. 1 0 5, for the necks not shown here, 106 for example. of the finger lo7 belonging to an actuating key (in FIG. 2c) and the guide ribs combined to form a lattice work lo8, namely integrally molded on the underside of the front plate lo9, for example. llo to 113, on all four sides of the rectangular openings, e.g. 1 0 5, and with each other and with these integrally molded stiffening ribs, eg. 114, 115.
  • Fig.2e shows the top view of the completely unpopulated front panel lo9 with the openings, for example. lo5 for a key neck, e.g. lo6) un for a channel switch 121, as well as for the function selection main switch 122 ("STEL / AUT).
  • FIG. 3 shows a longitudinal section AB through the housing upper part, which is supplemented by a longitudinal section through the lower housing part 151 and a phantom longitudinal view of the cover housing 152, and which is provided with a compact semiconductor module 153 for the display device and a group 154 of setting buttons.
  • relays 159 to 162 electrolytic capacitors 163, 164 and the other parts are arranged on the inside of the circuit boards 158, 159 which are attached at right angles to the underside of the circuit board on the longitudinal edges of the circuit board 155 of the power supply part 165.
  • the phantom view also shows how the pot-shaped cover housing 152 is fastened with the aid of clamping claws in the grooves with internal teeth 166 being put over the housing lower part.
  • FIG. 4 a shows a variant of the front view with a different housing shape, in which the display 181 and control panels 182 are arranged one above the other with longitudinal edges abutting one another (to be understood only conceptually).
  • the comments on Fig.la apply with regard to the ease of operation due to the geometrical assignment of display area areas and switches or buttons according to their ranking, especially the increase in the displayed values per button or with a long press of a sequence, and for the days of the week and the channels of the ongoing switchover after pressing the button and the transfer to the programming memory only after Actuation of the acknowledgment button in the same way, so that further explanations are unnecessary.
  • the electronic equipment and consequently the equipment of the front panel - apart from the local arrangement - corresponds to that of Fig.la.
  • FIG.4b The front view for an embodiment electronically disassembled with respect to Fig.la or Fig.4a is shown in Fig.4b.
  • the digits of the display 184, 185 of the ON switching time and corresponding to the OFF switching time indicate the hours or minutes, while the colons 186 arranged between them indicate the seconds or other sections of the minutes.
  • the saved switching times are queried with the "Check” button (194), the queried switching times are deleted with the "Clear” button (195), and the (complete) data record is saved in accordance with the switching time image in the "Program” (196) button Display in memory; the button ("clock picture") (197) is used to set the continuously running time in the background, the button “I / O” (198) to choose between "ON” and “OFF” switching times, and to start the Operation of the timer for setting and automatic operation, switches 199 and 2oo of the operating or channel circuit can be set to "Set / Program” or "Automatic / independent of this".
  • the parts with a dashed line are missing in the single-channel version of the time or time program switching device.
  • the printed circuit board 215 is together with their side circuit boards 216, 217 between the upper housing part 201 and the lower housing part 2o3 with the aid of the ribs, for example. 2o6 and 21o clamped correctly in accordance with distance and shape.
  • One side printed circuit board has a connector plug 219 on the part protruding from the floor.
  • the lower housing part (151 in FIG. 3) is shown with a bottom view, a longitudinal section EF and a top view in FIGS. 6a, b, and c.
  • the height-offset form which on the one hand offers a larger space for power supply in the room part 221, while the elongated room part 222 offers space for connector strips, means for connecting the installation and the lower room part 225 for the larger components , such as electrolytic capacitors, batteries and relays is sufficient, on the other hand, the circuit board with the connector strip extends through the slot 223 in the intermediate floor 224.
  • the grooves 226, 227 with offset toothed inner surfaces 228 and the integrally molded sleeves 229, 23o for screwing to the upper housing part are arranged on the side walls.
  • the spacer bars 231, 232 for the self-adjustment of the distance and the position of the cover housing are also in one piece forms.
  • Fig.7a for a longitudinal section AB
  • Fig.7c a cross section IK
  • Fig.7d for a cross section GH
  • Fig.7e for a longitudinal section CD through the lower housing part
  • Fig.7b for a side view in the direction of arrow N
  • Fig.7f for a side view in the direction of arrow O on the lower housing part
  • FIG. 8 and 9 show the cover housing (202 in FIG. 5b) in cross sections JK (FIG. 8a), L-0 (FIG. 8c), in longitudinal section AH (FIG. 8b), in a top view of the interior (FIG .8d), repeatedly shown in bottom view (Fig.9a) and front view (Fig. 9b).
  • the screwing sleeves (214 in Fig. 5b) are designated 241, 242, on the side walls are integrally molded ribs, for example. 243, 244, for supporting the side walls of the lower housing part (FIGS. 6 and 7) on the lugs (233, 234) of the upper edge.
  • Break-out opening areas 247 and 248, 249, 25o are provided in the floor 245 and in the front wall 246 for connecting lines and assembly.
  • Other integral parts are, for example. the fitting parts 251 for the lower housing part.
  • Fig.lo shows a simplified block diagram with the most important electronic components.
  • the buffer 301 for the sections 3o2 to 3o5 of the current time which are connected as consecutive counters with the levels 6 0 (s), 6 0 (m), 24 (h) and 7 (d) and both at non-drawn position of the switch 3o6 from the buffer 3o7 with a data record read in there, set the current time, and the electronic clock (buffer 3 0 1) can be continuously fed from the frequency divider pulse source controlled by an oscillator 3o8, as well as the sections of the buffer 3o7 the programming memory 31o sections invite, its portions g by actuation of the setting keys 311 and with switch to oN or oFF switching times e-set switch 311 by means of clock pulses from the clock generator 309 are set.
  • the buffer memory 3o7 can be connected to the input memory 312 of a display device and to the main memory 313 via the line group 314.
  • a complete data record is shoveled from the main memory into the intermediate memory 3o7, while the current time is displayed by the display device.
  • the latter and one of the two half data records for ON and OFF switching times are located in sections at the inputs of the logic comparator units 314, which, in the case of equality, have a signal at their outputs via the AND logic elements 315 (not shown in detail) for all Sections switch the switching devices together with the signal of the channel selection section 316 to the ON or OFF operating state.
  • FIG. 11 shows a schematic overview of the division of the overall block diagram with logical parallel logic levels and the association of the block diagrams 11a to 11d:
  • the subgroup of Fig.lla with the function selection buttons 321 (CLOCK) for the current time, 322 (ON), 323 (OFF) for the ON and OFF switching times, 324 (AS1 ...) for the query channel Preselection and 325 (AUT) for taking over the automatic operation of the electronic time switch are on one side at the clock pulse source T 1 , T 2 - which still has to be explained - and are on the output side via the AND elements with the complementary outputs Q of the FLIP-FLOP - Links 331 to 335 of the other function selection keys linked.
  • the FLIP-FLOP element eg. 332 controlled by pressing a key (eg. 322) does not have the inputs of all other FLIP-FLOP elements 331, 333, 334 and 335 through its Q output enabled AND gates 326, 328, 329 and 330 blocks.
  • H signals are on the output lines 336 (CLOCK), 337 (AUT), 338 ("I") and 339 ("O") and 34o (AS1, ..) as long as no other function selection key than that of the set FLIP-FLOP element has been actuated.
  • the function selection main switch "AUT / STEL” 341 is located at some point in the circuit, as a result of which the same output effect as with the "AUT" function selection button 325 is achieved - but blocked.
  • the switching channel actuating switches 342 serve to block the control circuit of the switching devices in one of the operating states: remain ON, remain OFF or remain inactive.
  • the set outputs of the monistable FLOP t elements 332 and 333 are linked by OR gates 375, 376 so that they indicate output signals via FLIP-FLOP gates 379, 38o as to whether all of the relevant setting keys are actuated; only then is an H signal given both for the control routine "ON” and for that "OFF” and passed on via the AND gate 377 on line 378 for a positive result of the completeness check.
  • These output signals also control, via an OR gate 381, a time-delayed monostable FLOP gate, the complementary Q output signal 382 of which is on the reset line 383 for the reset inputs.
  • the "ABF” key 356 thus only causes the reloading of a data record stored in the working memory into the input memory of the display device and thus an interruption of the "AUT" routine if the "AS1 " function selection key has been actuated beforehand, ie . a signal is present on line 384 and enables the forwarding of the "ABF” signal to line 386 via AND gate 385.
  • the actual set signals go from the relevant output of one of the AND gates 36o to 364 to the individually assigned sections of the intermediate memory 387 to 391 and set them to the corresponding values of the programming memory depending on the number of clock pulses entered; the buffer sections 387 and 391 are designed as shift memories, so that after each input which is to be stored, these are entered into the actual register by a signal at the output of the AND gate 366 belonging to the acknowledgment actuating key "QUI" 357 387 : or 391 t - possibly in addition to the positions already occupied - must be saved.
  • the data contents of the "switching time” and “switching channel” sections are taken from the outputs 393 and 394 of the programming memory 392.
  • 11c shows the function selection signals "I", “O”, “AS1 ..”, 4 0 1 to 4 0 3, and the control signal "ABF” 404 with the outputs "SZ” (switching times) 4 0 5 and "SK” (switching channels) 4o6 the inputs and outputs for ON switching time - 407, 4o8 and OFF switching time 4 0 9, 41o of the buffer for the complete data set, and switching channel 411, as well as the input of the electronic clock 413 and the input 414, as well as the outputs 415 (ON switching time), 416 (OFF switching time) and 417 (switching channel) of the working memory 418 through a chain 419 of AND gates and the AND gate 430 of the latter together with the completeness signal logically linked on line 421 (378 in Fig. 11b).
  • the data transports in connection with the working memory 418 are controlled by the central unit 422 including decoder in connection with a program memory 423 and possibly with an external additional read / write memory 4
  • Fig.lld are the assemblies of the electronic Clock 441 with the time segment stages 442 (day of the week “d"), 443 (hours “h"), 444 (minutes “m” and 445 (seconds “s") with the clock generator 446, consisting of an oscillator 447 and various divider stages, e.g. for 1 ms, 1/2 s, 1/8 s and 1 s clock output, e.g. T 1 and T 2 , as well as (1 s) for the ongoing advancement of the electronic clock 441
  • the time segment stages 442 to 445 can also be set from the programming memory (392 in Fig.llb) via line 448 and the AND gate 449. The presence of the function signal "CLOCK" on line 45o.
  • FIG. 12 shows an example with logical serial logic stages for the comparison of data record sections using shift registers when processing the time comparison of time and programmed ON or OFF switching time.
  • the associated data and half data sets are in registers 471 and 472 for the days of the week, 473 and 474 for "h", “m” and “s” for the current time and the stored switching time, and registers 475 and 476 for the switching channels of an intermediate memory loaded from the working memory 477 via the lines 479, 48o and 481 chers 478 filed.
  • Shift registers 482 to 485 and 486, 487 are assigned to registers 472, 473 of the switching times on the input side and output side and the registers for the switching channels only on the output side.
  • the shift registers each switch the input and / or the output of the relevant time segment register to the next one.
  • the clock pulses are generated by multiple linking by means of AND gates between clock signal line 488 via a first AND gate 489 with the AND gates controlled by CARRY and STATUS output signals of the comparator stage 49o with a 491 negated on one side and a 492 negated on both sides ' Approved. If, at the next clock pulse, the comparator element 49o determines equality and the CARRY and STATUS outputs are high, the AND element 493 is released and a clock pulse is transmitted to the further shift registers 484, 485 and via the counter 494 and the AND element 495 487 is given so that the comparison for the next section is released.
  • shift registers 5o4 to 5o8 By means of the shift registers 5o4 to 5o8, these constants are sequentially read out from the key switch (or switch contacts) matrix (563 in FIG. 14) and in intermediate storage locations "STELF” 5 0 9, “TASMRK 1 " (51o or " TASMRK 2 "511 stored key codes compared and depending on the result of the logic comparator 512, the CARRY and STATUS signals through AND gates 513, 514 and 515 unchanged, with one and with two negated inputs, linked to the clock signal and, accordingly, the register positions switched from level to level until equality is determined and then the procedure is switched on in a subordinate register, e.g. 5 0 2, 5o3 etc.
  • the output signals then control via further AND gates 516 and another shift register closes the signal circuits for the following circuit groups.
  • FIG. 14 shows the exemplary embodiment with a microprocessor in which the modules arithmetic-logic unit (ALE) 551, buffer group 552, input and output register R 553, output register D 554, working memory 555 including programming memory, Buffer for complete data sets, program memory 556 including program counter, return address memory and table memory, operation part decoder 557 and display device including auxiliary modules and clock 558 are integrated.
  • ALE arithmetic-logic unit
  • Fig. 16 shows that the display, change and deletion of the data of the displayed, set days of the week and switching channels takes place in the same simple way.
  • the days of the week for the ON switching time are there in each case in the upper line and for the OFF switching time in the lower - in accordance with the picture 6 0 5 on the display - shown as a series of bars that may light up next to each other, with "flashing" hatched and “constant", ie. are drawn in solid black.
  • Fig. 16a 1) the sequence of the bar images according to the actuation of the pushbuttons “dl-7", if necessary or in part several times, "Q" acknowledgment and 2) the switching time data record corresponding to the setting of the days of the week. Excerpt reproduced.
  • Fig.l6b is shown how the setting according to 1) by pressing the button "dl-7", again sometimes several times without acknowledgment, and the button "Q" the setting of Tuesday and Wednesday is expanded by the additional days of the week Thursday and Saturday , 3).
  • line 1) indicates an incomplete entry of the switching channels (only n SL 1 "), which is supplemented by pressing the button” Sl-2 “and” Q “to that according to line 2), as the sequence of In the event of an incorrect setting according to line 1 of FIG. 16f 2 to the second switching channel, the button “Sl-2” is used to switch to the first switching channel, the symbol flashing, and then by pressing the button "Q" this correction can be saved.
  • FIG. 17 shows a block diagram for an example of the compatibility check (plausibility) of the individual data of the complete switching time data record found complete by the completeness check in the programming memory 621 with the partial areas for the symbol "I” 622, the weekdays “d” 623 , the switching time of day in hours “h", minutes “m” and seconds “s” 624, of the ON switching time partial data record, and correspondingly the symbol “O” 625, the days of the week “d” 626, the switching time of day 627 of the OFF switching time partial data record with the switching channel or the switching channels "SK" 628 associated entered data for possible contradiction (s).
  • These include, for example. the setting ON switching time equal to OFF switching time for the same weekdays and the same switching channels.
  • SK I is equal to SK O the condition must be met: T p / I less than T P / O T p / I switch-on time T P / O switch-off time all in all Programming memory 621.
  • index "I” means belonging to the switch-on times, index “O” to the switch-off times, index P to the programming memory and index A to the main memory, "T” means switching time of day) must be compared and related to each other put: The following requirements must be met in any case: The following cases must then be excluded from forwarding the set data contained in the programming memory to the working memory: T P / I greater than T A / O ; T p / O greater than T A / I / AZ + 1 independently of this, however, T P / i must also be less than T A / I of the data record just read from the main memory.
  • the requirements regarding the switching channels Kp and K A are determined by the comparator stage 644, for the number of days of the week d A / I b between . d A / I / AZ + 1 (in buffers 645 and 646) and the number of days of the week d p / O or d A / O (buffers 635, 647), as well as dp / I or d A / I in the Comparator stages 648, 649, the data of the symbols O / P and O / A in the partial areas 625, 65o and finally the data of the symbols I / p and I A b z w.
  • the actual plausibility check consists of the further linking steps: First, the selected registers and the intermediate registers are located at the inputs of comparator stage 656 via shift registers 636 and 657 638 or 658 re-stored data of the most significant digits of the ON switching times Tp / I of the programming memory 621 or T A / I of the working memory 418, ie.
  • the buffer memory 63o that is to say the addressed switching time data record;
  • the selected data of the most significant digits of the OFF switching times T P / O of the programming memory 621 and TA / 0 of the buffer memory 63o are located via shift registers 637 and 66o and stored in the intermediate registers 639 and 661, respectively of the working memory 418 - with the same addressing as with the ON switching time of day - on;
  • the comparator stage 662 together with the output signals of the intermediate registers 638 and 663 - the latter via the shift register 664 - the data of the most significant digits of the OFF switching times T p / O of the programming memory 621 or T A / I / AZ + 1 of the next higher address of the working memory 418 for the same days of the week and switching channels.
  • the outputs of the comparison stages 656, 659 and 662 are through the OR gate 665, the AND gate 666 and partly via the AND gate 643a, the output signal of which increases the address counter 629 by one, and finally the AND gate 667 is linked in such a way that that on the output line 668 - if conditions are met - an enable signal for the transfer of the complete switching time data record in the programming memory 621 to the addressed subarea between AZ and AZ + 1 of the main memory 418 occurs via the line 669 and the AND gates 670, 671; the AND gate 671 is also only conductive if the enable signals of the completeness check are applied to its inputs 672, 673 (outputs of the AND gates 375, 376 in FIG. 11b).
  • An enable signal for deleting the data record or its partial areas in the programming memory or — depending on the actuation of the pushbuttons — the working memory is issued via line 674.

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Electric Clocks (AREA)
  • Programmable Controllers (AREA)
  • Electronic Switches (AREA)
  • Control Of Motors That Do Not Use Commutators (AREA)
EP83103713A 1982-04-20 1983-04-17 Dispositif de commutation de programme de temps électronique Expired - Lifetime EP0092211B2 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AT83103713T ATE30974T1 (de) 1982-04-20 1983-04-17 Elektronisches zeitprogramm-schaltgeraet.

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE3214372A DE3214372A1 (de) 1982-04-20 1982-04-20 Elektronisches zeitschaltgeraet
DE3214372 1982-04-20

Publications (3)

Publication Number Publication Date
EP0092211A1 true EP0092211A1 (fr) 1983-10-26
EP0092211B1 EP0092211B1 (fr) 1987-11-19
EP0092211B2 EP0092211B2 (fr) 1991-07-03

Family

ID=6161256

Family Applications (1)

Application Number Title Priority Date Filing Date
EP83103713A Expired - Lifetime EP0092211B2 (fr) 1982-04-20 1983-04-17 Dispositif de commutation de programme de temps électronique

Country Status (8)

Country Link
US (1) US4594007A (fr)
EP (1) EP0092211B2 (fr)
AT (1) ATE30974T1 (fr)
DE (2) DE3214372A1 (fr)
ES (1) ES521646A0 (fr)
GR (1) GR78191B (fr)
IE (1) IE54902B1 (fr)
WO (1) WO1983003688A1 (fr)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1986003308A1 (fr) * 1984-11-27 1986-06-05 Aktieselskabet Laur. Knudsen Nordisk Elektricitets Chronometre programmable
DE3622681A1 (de) * 1986-07-05 1988-01-21 Diehl Gmbh & Co Elektronische uhr mit einer digitalanzeige
EP0316913A3 (fr) * 1987-11-16 1991-02-06 OMRON Corporation Commutateur horaire
EP0503265A1 (fr) * 1991-02-04 1992-09-16 Joh. Vaillant GmbH u. Co. Unité d'entrée de données pour un régulateur de chauffage programmable
EP0447849B1 (fr) * 1990-03-20 1996-01-03 elero Antriebs- und Sonnenschutztechnik Gmbh & Co. KG. Commande électronique pour volet roulant

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JPS61275691A (ja) * 1985-05-31 1986-12-05 Casio Comput Co Ltd アラ−ム時計
DE8816400U1 (de) * 1988-04-25 1989-06-15 Siemens AG, 1000 Berlin und 8000 München Zeitschaltgerät mit einer mikrocomputergesteuerten Programm-Einstellvorrichtung
FR2775865B1 (fr) * 1998-03-04 2000-06-09 Valeo Electronique Tableau de commande a circuit imprime, en particulier pour vehicule automobile
US6060980A (en) * 1999-08-20 2000-05-09 Bedol; Mark A. Appointment timer
US20050083786A1 (en) * 2003-10-15 2005-04-21 Shih-Cheng Tsai Multi-functional timer
US20070273548A1 (en) * 2004-11-10 2007-11-29 Lg Electronics Inc. Remote Monitor in Electric Home Appliances

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FR2296213A1 (fr) * 1974-12-27 1976-07-23 Kienzle Uhrenfabriken Gmbh Horloge electronique fonctionnant numeriquement
US4004085A (en) * 1974-04-19 1977-01-18 Tokyo Shibaura Electric Co., Ltd. Receiving program-presetting system for a television receiver
FR2415915A1 (fr) * 1978-01-26 1979-08-24 Nissan Motor Procede et appareil pour accorder un recepteur de radiodiffusion suivant une sequence programmee
GB1572562A (en) * 1976-07-06 1980-07-30 Citizen Watch Co Ltd Multi-function temepiece
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GB923609A (en) * 1959-07-17 1963-04-18 Pye Ltd Automatic control arrangement
US4004085A (en) * 1974-04-19 1977-01-18 Tokyo Shibaura Electric Co., Ltd. Receiving program-presetting system for a television receiver
FR2296213A1 (fr) * 1974-12-27 1976-07-23 Kienzle Uhrenfabriken Gmbh Horloge electronique fonctionnant numeriquement
GB1572562A (en) * 1976-07-06 1980-07-30 Citizen Watch Co Ltd Multi-function temepiece
GB1580020A (en) * 1977-03-15 1980-11-26 Citizen Watch Co Ltd Portable electronic apparatus equipped with time-keeping means
FR2415915A1 (fr) * 1978-01-26 1979-08-24 Nissan Motor Procede et appareil pour accorder un recepteur de radiodiffusion suivant une sequence programmee
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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1986003308A1 (fr) * 1984-11-27 1986-06-05 Aktieselskabet Laur. Knudsen Nordisk Elektricitets Chronometre programmable
DE3622681A1 (de) * 1986-07-05 1988-01-21 Diehl Gmbh & Co Elektronische uhr mit einer digitalanzeige
EP0316913A3 (fr) * 1987-11-16 1991-02-06 OMRON Corporation Commutateur horaire
US5088071A (en) * 1987-11-16 1992-02-11 Omron Tateisi Electronics Co. Time switch
EP0447849B1 (fr) * 1990-03-20 1996-01-03 elero Antriebs- und Sonnenschutztechnik Gmbh & Co. KG. Commande électronique pour volet roulant
EP0503265A1 (fr) * 1991-02-04 1992-09-16 Joh. Vaillant GmbH u. Co. Unité d'entrée de données pour un régulateur de chauffage programmable

Also Published As

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DE3374613D1 (en) 1987-12-23
EP0092211B2 (fr) 1991-07-03
ATE30974T1 (de) 1987-12-15
EP0092211B1 (fr) 1987-11-19
ES8402083A1 (es) 1984-01-16
GR78191B (fr) 1984-09-26
DE3214372C2 (fr) 1988-07-14
IE54902B1 (en) 1990-03-14
DE3214372A1 (de) 1983-11-03
WO1983003688A1 (fr) 1983-10-27
ES521646A0 (es) 1984-01-16
IE830891L (en) 1983-10-20
US4594007A (en) 1986-06-10

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