| SCNN: An accelerator for compressed-sparse convolutional neural networks A Parashar, M Rhu, A Mukkara, A Puglielli, R Venkatesan, B Khailany, ... ACM SIGARCH computer architecture news 45 (2), 27-40, 2017 | 1720 | 2017 |
| Timeloop: A systematic approach to dnn accelerator evaluation A Parashar, P Raina, YS Shao, YH Chen, VA Ying, A Mukkara, ... 2019 IEEE international symposium on performance analysis of systems and …, 2019 | 635 | 2019 |
| Simba: Scaling deep-learning inference with multi-chip-module-based architecture YS Shao, J Clemons, R Venkatesan, B Zimmer, M Fojtik, N Jiang, B Keller, ... Proceedings of the 52nd annual IEEE/ACM international symposium on …, 2019 | 585 | 2019 |
| MACACO: Modeling and analysis of circuits for approximate computing R Venkatesan, A Agarwal, K Roy, A Raghunathan 2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 667-673, 2011 | 352 | 2011 |
| Spin-transfer torque memories: Devices, circuits, and systems X Fong, Y Kim, R Venkatesan, SH Choday, A Raghunathan, K Roy Proceedings of the IEEE 104 (7), 1449-1488, 2016 | 234 | 2016 |
| TapeCache: A high density, energy efficient cache based on domain wall memory R Venkatesan, V Kozhikkottu, C Augustine, A Raychowdhury, K Roy, ... Proceedings of the 2012 ACM/IEEE international symposium on Low power …, 2012 | 179 | 2012 |
| Magnet: A modular accelerator generator for neural networks R Venkatesan, YS Shao, M Wang, J Clemons, S Dai, M Fojtik, B Keller, ... 2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-8, 2019 | 162 | 2019 |
| Softermax: Hardware/software co-design of an efficient softmax for transformers JR Stevens, R Venkatesan, S Dai, B Khailany, A Raghunathan 2021 58th ACM/IEEE Design Automation Conference (DAC), 469-474, 2021 | 159 | 2021 |
| A 0.32–128 TOPS, scalable multi-chip-module-based deep neural network inference accelerator with ground-referenced signaling in 16 nm B Zimmer, R Venkatesan, YS Shao, J Clemons, M Fojtik, N Jiang, B Keller, ... IEEE Journal of Solid-State Circuits 55 (4), 920-932, 2020 | 139 | 2020 |
| Dwm-tapestri-an energy efficient all-spin cache using domain wall shift based writes R Venkatesan, M Sharad, K Roy, A Raghunathan 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2013 | 119 | 2013 |
| SPINDLE: SPINtronic deep learning engine for large-scale neuromorphic computing SG Ramasubramanian, R Venkatesan, M Sharad, K Roy, A Raghunathan Proceedings of the 2014 international symposium on Low power electronics and …, 2014 | 113 | 2014 |
| Vs-quant: Per-vector scaled quantization for accurate low-precision neural network inference S Dai, R Venkatesan, M Ren, B Zimmer, W Dally, B Khailany Proceedings of Machine Learning and Systems 3, 873-884, 2021 | 110 | 2021 |
| Accelerating chip design with machine learning B Khailany Proceedings of the 2020 ACM/IEEE Workshop on Machine Learning for CAD, 33-33, 2020 | 100 | 2020 |
| Analog/mixed-signal hardware error modeling for deep learning inference AS Rekhi, B Zimmer, N Nedovic, N Liu, R Venkatesan, M Wang, ... Proceedings of the 56th Annual Design Automation Conference 2019, 1-6, 2019 | 96 | 2019 |
| Buffets: An efficient and composable storage idiom for explicit decoupled data orchestration M Pellauer, YS Shao, J Clemons, N Crago, K Hegde, R Venkatesan, ... Proceedings of the Twenty-Fourth International Conference on Architectural …, 2019 | 90 | 2019 |
| A modular digital VLSI flow for high-productivity SoC design B Khailany, E Khmer, R Venkatesan, J Clemons, JS Emer, M Fojtik, ... Proceedings of the 55th Annual Design Automation Conference, 1-6, 2018 | 90 | 2018 |
| Stag: Spintronic-tape architecture for gpgpu cache hierarchies R Venkatesan, SG Ramasubramanian, S Venkataramani, K Roy, ... ACM SIGARCH Computer Architecture News 42 (3), 253-264, 2014 | 86 | 2014 |
| Optimal clipping and magnitude-aware differentiation for improved quantization-aware training C Sakr, S Dai, R Venkatesan, B Zimmer, W Dally, B Khailany International conference on machine learning, 19123-19138, 2022 | 62 | 2022 |
| A 0.11 pj/op, 0.32-128 tops, scalable multi-chip-module-based deep neural network accelerator with ground-reference signaling in 16nm B Zimmer, R Venkatesan, YS Shao, J Clemons, M Fojtik, N Jiang, B Keller, ... 2019 Symposium on VLSI Circuits, C300-C301, 2019 | 62 | 2019 |
| A 95.6-TOPS/W deep learning inference accelerator with per-vector scaled 4-bit quantization in 5 nm B Keller, R Venkatesan, S Dai, SG Tell, B Zimmer, C Sakr, WJ Dally, ... IEEE Journal of Solid-State Circuits 58 (4), 1129-1141, 2023 | 60 | 2023 |
Brucek KhailanySenior Director of VLSI Research, NVIDIAVerified email at cva.stanford.edu
