| Efficient processing of deep neural networks: A tutorial and survey V Sze, YH Chen, TJ Yang, JS Emer Proceedings of the IEEE 105 (12), 2295-2329, 2017 | 5516 | 2017 |
| Eyeriss: An energy-efficient reconfigurable accelerator for deep convolutional neural networks YH Chen, T Krishna, JS Emer, V Sze IEEE journal of solid-state circuits 52 (1), 127-138, 2016 | 4571 | 2016 |
| Eyeriss: A spatial architecture for energy-efficient dataflow for convolutional neural networks YH Chen, J Emer, V Sze ACM SIGARCH computer architecture news 44 (3), 367-379, 2016 | 2247 | 2016 |
| SCNN: An accelerator for compressed-sparse convolutional neural networks A Parashar, M Rhu, A Mukkara, A Puglielli, R Venkatesan, B Khailany, ... ACM SIGARCH computer architecture news 45 (2), 27-40, 2017 | 1720 | 2017 |
| Eyeriss v2: A flexible accelerator for emerging deep neural networks on mobile devices YH Chen, TJ Yang, J Emer, V Sze IEEE Journal on Emerging and Selected Topics in Circuits and Systems 9 (2 …, 2019 | 1359 | 2019 |
| A systematic methodology to compute the architectural vulnerability factors for a high-performance microprocessor SS Mukherjee, C Weaver, J Emer, SK Reinhardt, T Austin Proceedings. 36th Annual IEEE/ACM International Symposium on …, 2003 | 1347 | 2003 |
| Exploiting choice: Instruction fetch and issue on an implementable simultaneous multithreading processor DM Tullsen, SJ Eggers, JS Emer, HM Levy, JL Lo, RL Stamm Proceedings of the 23rd annual international symposium on Computer …, 1996 | 1232 | 1996 |
| High performance cache replacement using re-reference interval prediction (RRIP) A Jaleel, KB Theobald, SC Steely Jr, J Emer ACM SIGARCH computer architecture news 38 (3), 60-71, 2010 | 1085 | 2010 |
| Adaptive insertion policies for high performance caching MK Qureshi, A Jaleel, YN Patt, SC Steely, J Emer ACM SIGARCH Computer Architecture News 35 (2), 381-391, 2007 | 1007 | 2007 |
| Understanding error propagation in deep learning neural network (DNN) accelerators and applications G Li, SKS Hari, M Sullivan, T Tsai, K Pattabiraman, J Emer, SW Keckler Proceedings of the international conference for high performance computing …, 2017 | 767 | 2017 |
| Simultaneous multithreading: A platform for next-generation processors SJ Eggers, JS Emer, HM Levy, JL Lo, RL Stamm, DM Tullsen IEEE micro 17 (5), 12-19, 2002 | 716 | 2002 |
| There’s plenty of room at the Top: What will drive computer performance after Moore’s law? CE Leiserson, NC Thompson, JS Emer, BC Kuszmaul, BW Lampson, ... Science 368 (6495), eaam9744, 2020 | 666 | 2020 |
| The soft error problem: An architectural perspective SS Mukherjee, J Emer, SK Reinhardt 11th International Symposium on High-Performance Computer Architecture, 243-247, 2005 | 641 | 2005 |
| Timeloop: A systematic approach to dnn accelerator evaluation A Parashar, P Raina, YS Shao, YH Chen, VA Ying, A Mukkara, ... 2019 IEEE international symposium on performance analysis of systems and …, 2019 | 635 | 2019 |
| Simba: Scaling deep-learning inference with multi-chip-module-based architecture YS Shao, J Clemons, R Venkatesan, B Zimmer, M Fojtik, N Jiang, B Keller, ... Proceedings of the 52nd annual IEEE/ACM international symposium on …, 2019 | 585 | 2019 |
| Hardware for machine learning: Challenges and opportunities V Sze, YH Chen, J Emer, A Suleiman, Z Zhang 2017 IEEE custom integrated circuits conference (CICC), 1-8, 2017 | 549 | 2017 |
| Memory dependence prediction using store sets GZ Chrysos, JS Emer ACM SIGARCH Computer Architecture News 26 (3), 142-153, 1998 | 495 | 1998 |
| Sparse convolutional neural network accelerator WJ Dally, A Parashar, JS Emer, SW Keckler, LR Dennison US Patent 10,891,538, 2021 | 484 | 2021 |
| Scheduling heterogeneous multi-cores through performance impact estimation (PIE) K Van Craeynest, A Jaleel, L Eeckhout, P Narvaez, J Emer ACM SIGARCH Computer Architecture News 40 (3), 213-224, 2012 | 459 | 2012 |
| DAWG: A defense against cache timing attacks in speculative execution processors V Kiriansky, I Lebedev, S Amarasinghe, S Devadas, J Emer 2018 51st Annual IEEE/ACM International Symposium on Microarchitecture …, 2018 | 452 | 2018 |
Vivienne SzeProfessor, EECS at MITVerified email at mit.edu
