| Modeling the effect of technology trends on the soft error rate of combinational logic P Shivakumar, M Kistler, SW Keckler, D Burger, L Alvisi Proceedings International Conference on Dependable Systems and Networks, 389-398, 2002 | 2040 | 2002 |
| SCNN: An accelerator for compressed-sparse convolutional neural networks A Parashar, M Rhu, A Mukkara, A Puglielli, R Venkatesan, B Khailany, ... ACM SIGARCH computer architecture news 45 (2), 27-40, 2017 | 1720 | 2017 |
| Exascale computing study: Technology challenges in achieving exascale systems P Kogge, K Bergman, S Borkar, D Campbell, W Carson, W Dally, ... | 1515* | 2008 |
| An adaptive, non-uniform cache structure for wire-delay dominated on-chip caches C Kim, D Burger, SW Keckler ACM SIGPLAN Notices 37 (10), 211-222, 2002 | 1083 | 2002 |
| Clock rate versus IPC: The end of the road for conventional microarchitectures V Agarwal, MS Hrishikesh, SW Keckler, D Burger Proceedings of the 27th annual international symposium on Computer …, 2000 | 1029 | 2000 |
| GPUs and the future of parallel computing SW Keckler, WJ Dally, B Khailany, M Garland, D Glasco IEEE micro 31 (5), 7-17, 2011 | 914 | 2011 |
| Exploiting ILP, TLP, and DLP with the polymorphous TRIPS architecture K Sankaralingam, R Nagarajan, H Liu, C Kim, J Huh, D Burger, ... Computer Architecture, 2003. Proceedings. 30th Annual International …, 2003 | 774 | 2003 |
| Understanding error propagation in deep learning neural network (DNN) accelerators and applications G Li, SKS Hari, M Sullivan, T Tsai, K Pattabiraman, J Emer, SW Keckler Proceedings of the international conference for high performance computing …, 2017 | 767 | 2017 |
| Research challenges for on-chip interconnection networks JD Owens, WJ Dally, R Ho, DN Jayasimha, SW Keckler, LS Peh IEEE micro 27 (5), 96-108, 2007 | 661 | 2007 |
| Timeloop: A systematic approach to dnn accelerator evaluation A Parashar, P Raina, YS Shao, YH Chen, VA Ying, A Mukkara, ... 2019 IEEE international symposium on performance analysis of systems and …, 2019 | 635 | 2019 |
| vDNN: Virtualized deep neural networks for scalable, memory-efficient neural network design M Rhu, N Gimelshein, J Clemons, A Zulfiqar, SW Keckler 2016 49th Annual IEEE/ACM International Symposium on Microarchitecture …, 2016 | 605 | 2016 |
| Simba: Scaling deep-learning inference with multi-chip-module-based architecture YS Shao, J Clemons, R Venkatesan, B Zimmer, M Fojtik, N Jiang, B Keller, ... Proceedings of the 52nd annual IEEE/ACM international symposium on …, 2019 | 585 | 2019 |
| Scaling to the end of silicon with EDGE architectures D Burger, SW Keckler, KS McKinley, M Dahlin, LK John, C Lin, CR Moore, ... Computer 37 (7), 44-55, 2004 | 552 | 2004 |
| Regional congestion awareness for load balance in networks-on-chip P Gratz, B Grot, SW Keckler High Performance Computer Architecture, 2008. HPCA 2008. IEEE 14th …, 2008 | 507 | 2008 |
| A NUCA substrate for flexible CMP cache sharing J Huh, C Kim, H Shafi, L Zhang, D Burger, SW Keckler ACM International Conference on Supercomputing 25th Anniversary Volume, 380-389, 2005 | 502 | 2005 |
| Sparse convolutional neural network accelerator WJ Dally, A Parashar, JS Emer, SW Keckler, LR Dennison US Patent 10,891,538, 2021 | 484 | 2021 |
| Sparse convolutional neural network accelerator WJ Dally, A Parashar, JS Emer, SW Keckler, LR Dennison US Patent 10,528,864, 2020 | 369 | 2020 |
| Energy-efficient mechanisms for managing thread context in throughput processors M Gebhart, DR Johnson, D Tarjan, SW Keckler, WJ Dally, E Lindholm, ... Proceedings of the 38th annual international symposium on Computer …, 2011 | 366 | 2011 |
| The optimal logic depth per pipeline stage is 6 to 8 FO4 inverter delays MS Hrishikesh, D Burger, NP Jouppi, SW Keckler, KI Farkas, ... ACM SIGARCH Computer Architecture News 30 (2), 14-24, 2002 | 365 | 2002 |
| Transparent offloading and mapping (TOM) enabling programmer-transparent near-data processing in GPU systems K Hsieh, E Ebrahimi, G Kim, N Chatterjee, M O'Connor, N Vijaykumar, ... ACM SIGARCH Computer Architecture News 44 (3), 204-216, 2016 | 362 | 2016 |
Doug BurgerCorporate VP, Managing Director, Microsoft Research CoreVerified email at microsoft.com
