| Rethinking DRAM design and organization for energy-constrained multi-cores AN Udipi, N Muralimanohar, N Chatterjee, R Balasubramonian, A Davis, ... Proceedings of the 37th annual international symposium on Computer …, 2010 | 374 | 2010 |
| Transparent offloading and mapping (TOM) enabling programmer-transparent near-data processing in GPU systems K Hsieh, E Ebrahimi, G Kim, N Chatterjee, M O'Connor, N Vijaykumar, ... ACM SIGARCH Computer Architecture News 44 (3), 204-216, 2016 | 362 | 2016 |
| Fine-grained DRAM: Energy-efficient DRAM for extreme bandwidth systems M O'Connor, N Chatterjee, D Lee, J Wilson, A Agrawal, SW Keckler, ... Proceedings of the 50th Annual IEEE/ACM International Symposium on …, 2017 | 337 | 2017 |
| Micro-pages: increasing DRAM efficiency with locality-aware data placement K Sudan, N Chatterjee, D Nellans, M Awasthi, R Balasubramonian, ... ACM SIGARCH Computer Architecture News 38 (1), 219-230, 2010 | 315 | 2010 |
| Compressing DMA engine: Leveraging activation sparsity for training deep neural networks M Rhu, M O'Connor, N Chatterjee, J Pool, Y Kwon, SW Keckler 2018 IEEE International Symposium on High Performance Computer Architecture …, 2018 | 262 | 2018 |
| Understanding reduced-voltage operation in modern DRAM devices: Experimental characterization, analysis, and mechanisms KK Chang, AG Yağlıkçı, S Ghose, A Agrawal, N Chatterjee, A Kashyap, ... Proceedings of the ACM on Measurement and Analysis of Computing Systems 1 (1 …, 2017 | 254 | 2017 |
| Usimm: the utah simulated memory module N Chatterjee, R Balasubramonian, M Shevgoor, S Pugsley, A Udipi, ... University of Utah, Tech. Rep, 1-24, 2012 | 231* | 2012 |
| What your DRAM power models are not telling you: Lessons from a detailed experimental study S Ghose, AG Yaglikçi, R Gupta, D Lee, K Kudrolli, WX Liu, H Hassan, ... Proceedings of the ACM on Measurement and Analysis of Computing Systems 2 (3 …, 2018 | 174 | 2018 |
| Architecting an energy-efficient dram system for gpus N Chatterjee, M O’Connor, D Lee, DR Johnson, SW Keckler, M Rhu, ... 2017 IEEE International Symposium on High Performance Computer Architecture …, 2017 | 138 | 2017 |
| Page migration in a 3D stacked hybrid memory NS Jayasena, GH Loh, JM O'Connor, N Chatterjee US Patent 9,535,831, 2017 | 134 | 2017 |
| Managing DRAM latency divergence in irregular GPGPU applications N Chatterjee, M O'Connor, GH Loh, N Jayasena, R Balasubramonia SC'14: Proceedings of the International Conference for High Performance …, 2014 | 130 | 2014 |
| Anatomy of gpu memory system for multi-application execution A Jog, O Kayiran, T Kesten, A Pattnaik, E Bolotin, N Chatterjee, ... Proceedings of the 2015 international symposium on memory systems, 223-234, 2015 | 126 | 2015 |
| Leveraging heterogeneity in DRAM main memories to accelerate critical word access N Chatterjee, M Shevgoor, R Balasubramonian, A Davis, Z Fang, R Illikkal, ... 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture, 13-24, 2012 | 92 | 2012 |
| Staged reads: Mitigating the impact of DRAM writes on DRAM reads N Chatterjee, N Muralimanohar, R Balasubramonian, A Davis, NP Jouppi IEEE International Symposium on High-Performance Comp Architecture, 1-12, 2012 | 86 | 2012 |
| Toward standardized near-data processing with unrestricted data placement for GPUs G Kim, N Chatterjee, M O'Connor, K Hsieh Proceedings of the International Conference for High Performance Computing …, 2017 | 78 | 2017 |
| Need for speed: Experiences building a trustworthy system-level gpu simulator O Villa, D Lustig, Z Yan, E Bolotin, Y Fu, N Chatterjee, N Jiang, D Nellans 2021 IEEE International Symposium on High-Performance Computer Architecture …, 2021 | 69 | 2021 |
| Memory access methods and apparatus N Muralimanohar, AN Udipi, N Chatterjee, R Balasubramonian, AL Davis, ... US Patent 9,361,955, 2016 | 69 | 2016 |
| DeLTA: GPU performance model for deep learning applications with in-depth memory system traffic analysis S Lym, D Lee, M O'Connor, N Chatterjee, M Erez 2019 IEEE international symposium on performance analysis of systems and …, 2019 | 60 | 2019 |
| Quantifying the relationship between the power delivery network and architectural policies in a 3D-stacked memory device M Shevgoor, JS Kim, N Chatterjee, R Balasubramonian, A Davis, ... Proceedings of the 46th Annual IEEE/ACM International Symposium on …, 2013 | 60 | 2013 |
| Reducing data transfer energy by exploiting similarity within a data transaction D Lee, M O'Connor, N Chatterjee 2018 IEEE International Symposium on High Performance Computer Architecture …, 2018 | 40 | 2018 |
Mike O'ConnorNVIDIA ResearchVerified email at nvidia.com
