WO2025239583A1 - Circuit board and semiconductor package - Google Patents

Abstract

This circuit board comprises: a first insulating layer; a second insulating layer which arranged on the first insulating layer and which is made of the same material as the first insulating layer; a third insulating layer which is arranged between the first insulating layer and the second insulating layer and which is made of a material different from that of the first insulating layer; a first via electrode passing through upper and lower surfaces of the first insulating layer; and a second via electrode passing through at least a partial region of the second insulating layer, wherein vertical direction length of the first via electrode is longer than the vertical direction length of the second via electrode.

Description

Circuit boards and semiconductor packages

This embodiment relates to a circuit board and a semiconductor package.

Recently, electronic product technology has been moving toward multifunctionality and high-speed operation, and to respond to this trend, semiconductor chip manufacturing technology is also developing at a rapid pace.

In particular, the thickness of circuit boards applied for miniaturization of finished electronic products is also decreasing, and technologies related to multilayer circuit boards that configure more circuit layers within a circuit board of the same thickness are being actively researched.

A circuit board is a substrate made by printing a circuit line pattern with a conductive material, such as copper, onto an electrically insulating substrate. It is a general term for a board immediately before electronic components are mounted. To densely mount numerous electronic components on a flat surface, the mounting locations of each component are determined, and the circuit patterns connecting the components are printed and secured onto the flat surface.

Circuit boards comprise multiple insulating layers arranged vertically. Recently, a structure has been proposed that utilizes Photo-Imageable Dielectric (PID) layers within each insulating layer to achieve thinner circuit boards. However, PID multilayer structures suffer from warpage due to their low rigidity.

The present embodiment provides a circuit board and semiconductor package capable of minimizing warpage by reinforcing rigidity while reducing thickness in a structure in which multiple insulating layers are arranged.

A circuit board according to the present embodiment includes a first insulating layer; a second insulating layer disposed on the first insulating layer and made of the same material as the first insulating layer; a third insulating layer disposed between the first insulating layer and the second insulating layer and made of a different material from the first insulating layer; a first via electrode penetrating the upper and lower surfaces of the first insulating layer; and a second via electrode penetrating at least a portion of the second insulating layer, wherein a vertical length of the first via electrode is longer than a vertical length of the second via electrode.

The first insulating layer and the second insulating layer may be prepreg (PPG).

The third insulating layer may be a PID (Photo-Imageable Dielectric) or ABF (Ajinomoto Build-up Film).

The third insulating layer may be provided in multiple numbers and placed between the first insulating layer and the second insulating layer.

The third insulating layer may have two or fewer layers.

It may include a pattern electrode arranged on the surface of the second insulating layer; a pattern electrode arranged on the surface of the third insulating layer; and a through electrode vertically connecting the pattern electrode of the second insulating layer and the pattern electrode of the third insulating layer.

The pattern electrode of the second insulating layer, the pattern electrode of the third insulating layer, and the through electrode can form an inductor.

A fourth insulating layer is disposed below the first insulating layer and is made of the same material as the first insulating layer, and the third insulating layer can be disposed between the first insulating layer and the fourth insulating layer.

Based on the first insulating layer, the second insulating layer, the third insulating layer, and the circuit pattern arranged on the upper side may be symmetrical with the fourth insulating layer, the third insulating layer, and the circuit pattern arranged on the lower side.

A semiconductor package according to the present embodiment includes a main substrate; and a circuit board coupled to the main substrate, wherein the circuit board includes a first insulating layer; a second insulating layer disposed on the first insulating layer and made of the same material as the first insulating layer; a third insulating layer disposed between the first insulating layer and the second insulating layer and made of a different material from the first insulating layer; a first via electrode penetrating an upper surface and a lower surface of the first insulating layer; and a second via electrode penetrating at least a portion of the second insulating layer, wherein a vertical length of the first via electrode is longer than a vertical length of the second via electrode.

In this embodiment, in a structure in which multiple insulating layers are stacked in a vertical direction, the vertical height of the circuit board can be reduced due to the material difference between the multiple insulating layers, so there is an advantage in that miniaturization is possible.

In addition, there is an advantage in that the rigidity of the circuit board can be reinforced by placing the first insulating layer, the second insulating layer, and the fourth insulating layer, which are composed of prepregs, between the third insulating layers.

In addition, there is an advantage in that the warpage of the circuit board due to the difference in upper and lower stress can be minimized by arranging and forming the insulating layers and circuit patterns arranged above and below the first insulating layer symmetrically.

Figure 1 is a cross-sectional view of a circuit board according to a first embodiment of the present invention.

Figures 2 to 5 are drawings for explaining various application examples of a circuit board according to the first embodiment of the present invention.

Fig. 6 is a cross-sectional view of a semiconductor package according to an embodiment of the present invention.

Figure 7 is a cross-sectional view of a circuit board according to a second embodiment of the present invention.

Figure 8 is a cross-sectional view of a circuit board according to a third embodiment of the present invention.

Fig. 9 is a cross-sectional view showing the layout structure of a circuit board according to a comparative example.

Fig. 10 is a drawing measuring stress distribution in a circuit board according to a comparative example.

Fig. 11 is a drawing measuring stress distribution in a circuit board according to an embodiment of the present invention.

Hereinafter, a preferred embodiment of the present invention will be described in detail with reference to the attached drawings.

However, the technical idea of the present invention is not limited to some of the embodiments described, but can be implemented in various different forms, and within the scope of the technical idea of the present invention, one or more of the components between the embodiments can be selectively combined or substituted for use.

In addition, terms (including technical and scientific terms) used in the embodiments of the present invention may be interpreted as having a meaning that can be generally understood by a person of ordinary skill in the technical field to which the present invention belongs, unless explicitly and specifically defined and described, and terms that are commonly used, such as terms defined in a dictionary, may be interpreted in consideration of the contextual meaning of the relevant technology.

In addition, the terms used in the embodiments of the present invention are for the purpose of describing the embodiments and are not intended to limit the present invention. In this specification, the singular may also include the plural unless specifically stated in the phrase, and when it is described as "A and/or at least one (or more) of B, C," it may include one or more of all combinations that can be combined with A, B, and C.

Additionally, in describing components of embodiments of the present invention, terms such as first, second, A, B, (a), (b), etc. may be used.

These terms are intended only to distinguish one component from another, and are not intended to limit the nature, order, or sequence of the component.

And, when a component is described as being 'connected', 'coupled' or 'connected' to another component, it may include not only cases where the component is directly connected, coupled or connected to the other component, but also cases where the component is 'connected', 'coupled' or 'connected' by another component between the component and the other component.

Additionally, when it is described as being formed or arranged "above or below" each component, "above" or "below" includes not only cases where the two components are in direct contact with each other, but also cases where one or more other components are formed or arranged between the two components. Also, when it is expressed as "above" or "below", it can include the meaning of the downward direction as well as the upward direction based on one component.

FIG. 1 is a cross-sectional view of a circuit board according to a first embodiment of the present invention, FIGS. 2 to 5 are drawings for explaining various application examples of the circuit board according to the first embodiment of the present invention, and FIG. 6 is a cross-sectional view of a semiconductor package according to an embodiment of the present invention.

Referring to FIG. 1, a circuit board (10) according to an embodiment of the present invention may include a first insulating layer (100), a second insulating layer (110), a third insulating layer, a fourth insulating layer (120), a plurality of pad portions, a plurality of via electrodes, a plurality of pattern electrodes, and a plurality of through electrodes.

Here, the first insulating layer (100), the second insulating layer (110), and the fourth insulating layer (120) may be formed of the same material. For example, the first insulating layer (100), the second insulating layer (110), and the fourth insulating layer (120) may include any insulator such as a photocurable material and/or a thermocurable material. For example, the first insulating layer (100), the second insulating layer (110), and the fourth insulating layer (120) may be formed of a prepreg (PPG) including glass fiber in a resin. The resin of the first insulating layer (100), the second insulating layer (110), and the fourth insulating layer (120) may include at least one of an epoxy resin, a bismaleimide triazine resin (BT resin), and a phenol resin. When the resin of the first insulating layer (100), the second insulating layer (110), and the fourth insulating layer (120) is used as an insulating layer resin, it may include a reinforcing material made of glass fiber or aramid fiber.

The material constituting the third insulating layer may be different from the material constituting any one of the first insulating layer (100), the second insulating layer (110), and the fourth insulating layer (120). For example, the material of the third insulating layer may be any insulator such as photocurable and/or thermosetting. The material of the third insulating layer may be an insulator in which inorganic and/or organic fillers are dispersed in a resin such as Ajinomoto Build-up Film (ABF), a product released by Ajinomoto Co., Ltd., as a PID (Photo-Imageable Dielectric) or thermosetting insulator.

Hereinafter, as illustrated in FIG. 1, a circuit board (10) according to the present embodiment will be described as an example in which a second insulating layer (110) is disposed on a first insulating layer (100), a fourth insulating layer (120) is disposed under the first insulating layer (100), and a third insulating layer is disposed on at least one of between the first insulating layer (100) and the second insulating layer (110), on the upper portion of the second insulating layer (110), between the first insulating layer (100) and the fourth insulating layer (120), and under the lower portion of the fourth insulating layer (120). In other words, the circuit board (10) may be understood as having an upper build-up layer (101) disposed on a first insulating layer (100), a lower build-up layer (102) disposed under the first insulating layer (100), and the upper build-up layer (101) composed of a second insulating layer (110) and a third insulating layer, and the lower build-up layer (102) composed of a fourth insulating layer (120) and a third insulating layer.

The first insulating layer (100) may be disposed between the upper build-up layer (101) and the lower build-up layer (102). The first insulating layer (100) may be a prepreg (PPG) as described above. The first insulating layer (100) may also be called a core layer. The first insulating layer (100) may have a first thickness (H1) in the vertical direction. For example, the thickness of the first insulating layer (100) may be 40 um or more and 100 um or less. When the thickness of the first insulating layer (100) is 40 um or less, the rigidity of the first insulating layer (100) disposed at the center of the circuit board (10) is reduced, and thus the circuit board (10) may be vulnerable to warpage. If the thickness of the first insulating layer (100) is 100 um or more, there is a risk that the thickness of the circuit board (10) may increase excessively.

The circuit board (10) according to the present embodiment may have a structure in which the upper build-up layer (101) and the lower build-up layer (102) are symmetrical with respect to the first insulating layer (100). The circuit pattern in the upper build-up layer (101) and the circuit pattern in the lower build-up layer (102) may also be arranged symmetrically with respect to the first insulating layer (100).

The second insulating layer (110) may be disposed on the first insulating layer (100). The second insulating layer (110) and the first insulating layer (100) may be spaced apart from each other in the vertical direction, and at least one third insulating layer may be disposed therebetween. The second insulating layer (110) may be a prepreg (PPG). The second insulating layer (110) may have a second thickness (H2) in the vertical direction. The second thickness (H2) may be smaller than the first thickness (H1). For example, the second thickness (H2) may be 15 um or more and 30 um or less. When the second thickness (H2) is 15 um or less, the supporting force of the plurality of third insulating layers disposed on the upper and lower sides may decrease, causing warping of the circuit board (10). If the second thickness (H2) is 30 um or more, there is a risk that the thickness of the circuit board (10) may increase excessively.

The fourth insulating layer (120) may be arranged under the first insulating layer (100). The fourth insulating layer (120) and the first insulating layer (100) may be spaced apart from each other in the vertical direction, and at least one third insulating layer may be arranged therebetween. The fourth insulating layer (120) may be a prepreg (PPG). The fourth insulating layer (120) may have a second thickness (H2) in the vertical direction. The thickness of the fourth insulating layer (120) may be the same as the thickness of the second insulating layer (110). The thickness (H2) of the fourth insulating layer (120) may be 15 um or more and 30 um or less. When the fourth thickness (H2) is 15 um or less, the supporting force of the plurality of third insulating layers arranged above and below may decrease, causing warping of the circuit board (10). If the fourth thickness (H2) is 30 um or more, there is a risk that the thickness of the circuit board (10) may increase excessively.

The third insulating layer may be disposed on at least one of the following: between the first insulating layer (100) and the second insulating layer (110), on the upper portion of the second insulating layer (110), between the first insulating layer (100) and the fourth insulating layer (120), and on the lower portion of the fourth insulating layer (120). The third insulating layer may be laminated in multiple layers in the vertical direction. For example, the third insulating layer may be provided in two or fewer layers on at least one of the following: between the first insulating layer (100) and the second insulating layer (110), on the upper portion of the second insulating layer (110), between the first insulating layer (100) and the fourth insulating layer (120), and on the lower portion of the fourth insulating layer (120). Accordingly, cracks due to the fourth insulating layer (120) having relatively weak rigidity can be minimized.

The third insulating layer may include the 3-1 insulating layer to the 3-8 insulating layer (131, 132, 133, 134, 135, 136, 137, 138).

In detail, the third insulating layer includes a 3-1 insulating layer (131) disposed on the 1st insulating layer (100), a 3-2 insulating layer (132) disposed between the 3-1 insulating layer (131) and the 2nd insulating layer (110), a 3-3 insulating layer (133) disposed on the 2nd insulating layer (110), a 3-4 insulating layer (134) disposed on the 3-3 insulating layer (133), a 3-5 insulating layer (135) disposed on the lower surface of the 1st insulating layer (100), a 3-6 insulating layer (136) disposed between the 3-5 insulating layer (135) and the 4th insulating layer (120), a 3-7 insulating layer (137) disposed on the lower surface of the 4th insulating layer (120), and a 3-7 insulating layer (137) disposed on the lower surface of the 3-7 insulating layer (137). It may include a 3-8 insulating layer (138).

The 3-1 to 3-8 insulating layers (131, 132, 133, 134, 135, 136, 137, 138) may be arranged vertically between the first insulating layer (100) and the second insulating layer (110), on the upper side of the second insulating layer (110), between the first insulating layer (100) and the fourth insulating layer (120), and on the lower side of the fourth insulating layer (120), respectively.

The third insulating layer may be a Photo-Imageable Dielectric (PID) or an Ajinomoto Build-up Film (ABF). The third insulating layer may have a third thickness (H3) in the vertical direction. The third thickness (H3) may be smaller than the second thickness (H2). For example, the third thickness (H3) may be 5 μm or more and 30 μm or less. When the third thickness (H3) is 5 μm or less, it may be difficult to form a via electrode and a pad portion penetrating the third insulating layer. When the third thickness (H3) is 30 μm or more, there is a concern that the thickness of the circuit board (10) may be excessively increased.

The plurality of pad parts are a first pad part (141) disposed on the upper surface of the first insulating layer (100), a second pad part (142) disposed on the lower surface of the first insulating layer (100), a third pad part (143) disposed on the upper surface of the 3-1 insulating layer (131), a fourth pad part (144) disposed on the upper surface of the 3-2 insulating layer (132), a fifth pad part (145) disposed on the upper surface of the 2nd insulating layer (110), a sixth pad part (146) disposed on the upper surface of the 3-3 insulating layer (133), a seventh pad part (147) disposed on the upper surface of the 3-4 insulating layer (134), an eighth pad part (148) disposed on the lower surface of the 3-5 insulating layer (135), a ninth pad part (149) disposed on the lower surface of the 3-6 insulating layer (136), and a fourth pad part (120). It may include a 10th pad part (150) arranged on the lower surface, an 11th pad part (151) arranged on the lower surface of the 3rd-7th insulating layer (137), and a 12th pad part (152) arranged on the lower surface of the 3rd-8th insulating layer (138).

The first pad part (141) is embedded in the lower surface of the 3-1 insulating layer (131), the third pad part (143) is embedded in the lower surface of the 3-2 insulating layer (132), the fourth pad part (144) is embedded in the lower surface of the 2nd insulating layer (110), the fifth pad part (145) is embedded in the lower surface of the 3-3 insulating layer (133), the sixth pad part (146) is embedded in the lower surface of the 3-4 insulating layer (134), the second pad part (142) is embedded in the upper surface of the 3-5 insulating layer (135), the eighth pad part is embedded in the upper surface of the 3-6 insulating layer (136), the ninth pad part (149) is embedded in the upper surface of the 4th insulating layer (120), and the tenth pad part (150) is embedded in the upper surface of the It can also be understood that the 11th pad portion (151) is embedded in the upper surface of the 3-7th insulating layer (137), and that the 11th pad portion (151) is embedded in the upper surface of the 3-8th insulating layer (138).

The seventh pad portion (147) and the twelfth pad portion (152) can be respectively placed on the upper and lower surfaces of the circuit board (10).

A plurality of via electrodes are arranged to penetrate the first insulating layer (100) and electrically connect the first pad portion (141) and the second pad portion (142), a first via electrode (153) arranged to penetrate the 3-1 insulating layer (131) and electrically connect the first pad portion (141) and the third pad portion (143), a third via electrode (155) arranged to penetrate the 3-2 insulating layer (132) and electrically connect the third pad portion (143) and the fourth pad portion (144), a fourth via electrode (156) arranged to penetrate the 2nd insulating layer (110) and electrically connect the fourth pad portion (144) and the fifth pad portion (145), and a third via electrode (156) arranged to penetrate the 3-3 insulating layer (133) and electrically connect the fifth pad portion (145) and the sixth pad portion (146). A fifth via electrode (157) electrically connecting, a sixth via electrode (158) positioned to penetrate the third-fourth insulating layer (134) and electrically connecting the sixth pad portion (146) and the seventh pad portion (147), a seventh via electrode (159) penetrating the third-fifth insulating layer (135) and electrically connecting the second pad portion (142) and the eighth pad portion (148), an eighth via electrode (160) penetrating the third-sixth insulating layer (136) and electrically connecting the eighth pad portion (148) and the ninth pad portion (149), a ninth via electrode (161) penetrating the fourth insulating layer (120) and electrically connecting the ninth pad portion (149) and the tenth pad portion (150), and a ninth via electrode (161) penetrating the third-seventh insulating layer (137) and electrically connecting the tenth pad portion (150) and It may include a 10th via electrode (162) that electrically connects the 11th pad portion (151) and an 11th via electrode (163) that penetrates the 3rd-8th insulating layer (138) and electrically connects the 11th pad portion (151) and the 12th pad portion (152).

The first to eleventh via electrodes (153, 154, 155, 156, 157, 158, 159, 160, 161, 162, 163) may be arranged to overlap each other in the vertical direction. The first to sixth via electrodes (153, 154, 155, 156, 157, 158) may have a shape in which the horizontal width decreases as they go downward, and a shape in which the cross-sectional area decreases, respectively. The seventh to eleventh via electrodes (159, 160, 161, 162, 163) may have a shape in which the horizontal width increases as they go downward, and a shape in which the cross-sectional area increases, respectively.

The vertical length of the first via electrode (153) penetrating the first insulating layer (100) may be longer than the vertical length of the fourth via electrode (156) penetrating the second insulating layer (110) or the vertical length of the ninth via electrode (161) penetrating the fourth insulating layer (120). The vertical length of the first via electrode (153) may be formed to be longer than the vertical length of any one of the second to eleventh via electrodes (154, 155, 156, 157, 158, 159, 160, 161, 162, 163). This is due to the difference in vertical thickness between the first insulating layer (100) and other insulating layers and the arrangement structure of each of the plurality of pad portions. By forming the length of the via electrode long in the first insulating layer (100) having relatively high rigidity and forming the length of the via electrode short in the region of the second to fourth insulating layers (110, 120, 130) having relatively low rigidity, the via electrode can be compactly combined within the circuit board.

The circuit board (10) may include a plurality of pattern electrodes and a plurality of through-hole electrodes. Here, the plurality of pattern electrodes may be referred to as a plurality of pad portions, and the plurality of through-hole electrodes may be referred to as a plurality of via electrodes, depending on the functional difference between the plurality of pattern electrodes and the plurality of through-hole electrodes. It goes without saying that the plurality of pattern electrodes may also be referred to as a plurality of pad portions, and the plurality of through-hole electrodes may also be referred to as a plurality of via electrodes.

The plurality of pattern electrodes include a first pattern electrode (171) disposed on the upper surface of the first insulating layer (100), a second pattern electrode (177) disposed on the lower surface of the first insulating layer (100), a third pattern electrode (172) disposed on the upper surface of the 3-1 insulating layer (131), a fourth pattern electrode (173) disposed on the upper surface of the 3-2 insulating layer (132), a fifth pattern electrode (174) disposed on the upper surface of the 2nd insulating layer (110), a sixth pattern electrode (175) disposed on the upper surface of the 3-3 insulating layer (133), a seventh pattern electrode (176) disposed on the upper surface of the 3-4 insulating layer (134), an eighth pattern electrode (178) disposed on the lower surface of the 3-5 insulating layer (135), and a ninth pattern electrode (179) disposed on the lower surface of the 3-6 insulating layer (136). It may include a 10th pattern electrode (180) arranged on the lower surface of the 4th insulating layer (120), an 11th pattern electrode (181) arranged on the lower surface of the 3rd-7th insulating layer (137), and a 12th pattern electrode (182) arranged on the lower surface of the 3rd-8th insulating layer (138).

The horizontal length of any one of the pattern electrodes among the first to sixth pattern electrodes (171, 177, 172, 173, 174, 175) and the eighth to eleventh pattern electrodes (178, 179, 180, 181) may be longer than the horizontal length of any one of the pad portions among the first to twelfth pad portions (141, 142, 143, 144, 145, 146, 147, 148, 149, 150, 151, 152). The horizontal length of any one of the pattern electrodes among the first to sixth pattern electrodes (171, 177, 172, 173, 174, 175) and the eighth to eleventh pattern electrodes (178, 179, 180, 181) may be at least twice the horizontal length of any one of the pad portions among the first to twelfth pad portions (141, 142, 143, 144, 145, 146, 147, 148, 149, 150, 151, 152).

The seventh pattern electrode (176) disposed on the upper surface of the circuit board (10) and the twelfth pattern electrode (182) disposed on the lower surface of the circuit board (10) may each include two or more regions divided horizontally. For example, the seventh pattern electrode (176) includes a 7-1 pattern electrode (176a) and a 7-2 pattern electrode (176b) spaced apart horizontally, and the 7-1 pattern electrode (176a) and the 7-2 pattern electrode (176b) may each be electrically connected to the 6th pattern electrode (175). The 12th pattern electrode (182) includes a 12-1st pattern electrode (182a) and a 12-2nd pattern electrode (182b) that are spaced apart in the horizontal direction, and the 12-1st pattern electrode (182a) and the 12-2nd pattern electrode (182b) can each be electrically connected to the 11th pattern electrode (181).

The first pattern electrode (171) may overlap with the first pad portion (141) in a horizontal direction. The second pattern electrode (177) may overlap with the second pad portion (142) in a horizontal direction. The third pattern electrode (172) may overlap with the third pad portion (143) in a horizontal direction. The fourth pattern electrode (173) may overlap with the fourth pad portion (144) in a horizontal direction. The fifth pattern electrode (174) may overlap with the fifth pad portion (145) in a horizontal direction. The sixth pattern electrode (175) may overlap with the sixth pad portion (146) in a horizontal direction. The seventh pattern electrode (176) may overlap with the seventh pad portion (147) in a horizontal direction. The eighth pattern electrode (178) may overlap with the eighth pad portion (148) in a horizontal direction. The ninth pattern electrode (179) may overlap horizontally with the ninth pad portion (149). The tenth pattern electrode (180) may overlap horizontally with the tenth pad portion (150). The eleventh pattern electrode (181) may overlap horizontally with the eleventh pad portion (151). The twelfth pattern electrode (182) may overlap horizontally with the twelfth pad portion (152).

A plurality of through electrodes are arranged to penetrate the 3-1 insulating layer (131) and electrically connect the first pattern electrode (171) and the third pattern electrode (172), a first through electrode (183) arranged to penetrate the 3-2 insulating layer (132) and electrically connect the third pattern electrode (172) and the fourth pattern electrode (173), a third through electrode (185) arranged to penetrate the 2nd insulating layer (110) and electrically connect the fourth pattern electrode (173) and the fifth pattern electrode (174), a fourth through electrode (186) arranged to penetrate the 3-3 insulating layer (133) and electrically connect the fifth pattern electrode (174) and the sixth pattern electrode (175), and a fourth through electrode (186) arranged to penetrate the 3-4 insulating layer (134) and electrically connect the sixth pattern A fifth through-hole electrode (187) electrically connecting the electrode (175) and the seventh pattern electrode (176), a sixth through-hole electrode (188) penetrating the third-fifth insulating layer (135) and electrically connecting the second pattern electrode (177) and the eighth pattern electrode (178), a seventh through-hole electrode (189) penetrating the third-sixth insulating layer (136) and electrically connecting the eighth pattern electrode (178) and the ninth pattern electrode (179), an eighth through-hole electrode (190) penetrating the fourth insulating layer (120) and electrically connecting the ninth pattern electrode (179) and the tenth pattern electrode (180), and a ninth through-hole electrode (191) penetrating the third-seventh insulating layer (137) and electrically connecting the tenth pattern electrode (180) and the eleventh pattern electrode (181), It may include a 10th penetration electrode (192) that penetrates the 3rd-8th insulating layer (138) and electrically connects the 11th pattern electrode (181) and the 12th pattern electrode (182).

The first to tenth penetration electrodes (183, 184, 185, 186, 187, 188, 189, 190, 191, 192) may be provided in multiple numbers and spaced apart in the horizontal direction.

The first through-hole electrode (183) may overlap horizontally with the second via electrode (154). The second through-hole electrode (184) may overlap horizontally with the third via electrode (155). The third through-hole electrode (185) may overlap horizontally with the fourth via electrode (156). The fourth through-hole electrode (186) may overlap horizontally with the fifth via electrode (157). The fifth through-hole electrode (187) may overlap horizontally with the sixth via electrode (158). The sixth through-hole electrode (188) may overlap horizontally with the seventh via electrode (159). The seventh through-hole electrode (189) may overlap horizontally with the eighth via electrode (160). The eighth through-hole electrode (190) may overlap horizontally with the ninth via electrode (161). The ninth through electrode (191) may overlap horizontally with the tenth via electrode (162). The tenth through electrode (192) may overlap horizontally with the eleventh via electrode (163).

The first to fifth through-hole electrodes (183, 184, 185, 186, 187) may have a shape in which the horizontal width and cross-sectional area decrease as they go downward, respectively. The sixth to tenth through-hole electrodes (188, 189, 190, 191, 192) may have a shape in which the horizontal width and cross-sectional area increase as they go downward, respectively. The vertical length of each of the first to tenth through-hole electrodes (183, 184, 185, 186, 187, 188, 189, 190, 191, 192) may be shorter than the vertical length of the first via electrode (153).

The first pattern electrode (171), the third to seventh pattern electrodes (172, 173, 174, 175, 176), and the first to fifth through-hole electrodes (183, 184, 185, 186, 187) can form an inductor together with an insulating layer within the circuit board (10). The second pattern electrode (177), the eighth to twelfth pattern electrodes (178, 179, 180, 181, 182), and the sixth to tenth through-hole electrodes (188, 189, 190, 191, 192) can form an inductor together with an insulating layer within the circuit board (10). Accordingly, the circuit board (10) can have a structure in which a plurality of inductors are arranged above and below the first insulating layer (100).

According to the structure as described above, in a structure in which multiple insulating layers are stacked in a vertical direction, the vertical height of the circuit board can be reduced due to the material difference between the multiple insulating layers, so there is an advantage in that miniaturization is possible.

In addition, there is an advantage in that the rigidity of the circuit board can be reinforced by placing the first insulating layer, the second insulating layer, and the fourth insulating layer, which are composed of prepregs, between the third insulating layers.

In addition, there is an advantage in that the warpage of the circuit board due to the difference in upper and lower stress can be minimized by arranging and forming the insulating layers and circuit patterns arranged above and below the first insulating layer symmetrically.

Figures 2 to 5 are drawings showing various application examples of a circuit board (10) according to the first embodiment of the present invention.

First, referring to FIG. 2, a first protective layer (198) and a second protective layer (199) may be disposed on the upper and lower surfaces of the circuit board (10), respectively. In this case, the first protective layer (198) and the second protective layer (199) may perform a function of preventing a short circuit between solders due to low wettability with the solder when a semiconductor element is disposed on the surface of the circuit board (10) using a material such as solder. The first protective layer (198) and the second protective layer (199) may each use a photocurable insulating material. For example, the first protective layer (198) and the second protective layer (199) may use a solder resist. The first protective layer (198) may include a through hole (198a) for exposing the seventh pattern electrode (176) and the seventh pad portion (147) upward. The second protective layer (199) may include a through hole (199a) for exposing the 12th pattern electrode (182) and the 12th pad portion (152) downward.

Referring to FIGS. 3 and 4, in the present modified example, two or more regions can be mutually divided based on the first insulating layer (100) in the circuit board (10) according to the first embodiment. In this case, since the first insulating layer (100) is omitted in the circuit board (10), the plurality of divided regions can include a first circuit board (20) in which the 3-1st insulating layer to the 3-4th insulating layer (131, 132, 133, 134) are respectively arranged on the upper and lower surfaces with the second insulating layer (110) as the center, and a second circuit board (30) in which the 3-5th insulating layer to the 3-8th insulating layer (135, 136, 137, 138) are respectively arranged on the upper and lower surfaces with the fourth insulating layer (130) as the center. That is, multiple circuit boards capable of performing the function of an inductor can be manufactured by manufacturing a single circuit board (10).

In this case, as the first protective layer (198) and the second protective layer (199) are respectively arranged on the upper and lower surfaces of the first circuit board (20) and the second circuit board (30), the seventh pattern electrode (176) and the seventh pad portion (147) can be exposed upward through the through hole (198a) of the first protective layer (198) with respect to the first circuit board (20), and the first pattern electrode (171) and the first pad portion (141) can be exposed downward through the through hole (199a) of the second protective layer (199).

Meanwhile, when manufacturing a plurality of circuit boards (20, 30) by omitting the first insulating layer (100), the first via electrode (153) in the first insulating layer (100) may be omitted in the description of the circuit board (10) according to the first embodiment.

Referring to FIGS. 1 and 5, in the present modified example, the upper and lower regions of the circuit board (10) according to the first embodiment may be ground. Accordingly, a first surface (133a), which is a region where the 3-3rd insulating layer (133) and the 3-4th insulating layer (134) are ground, and a second surface (137a), which is a region where the 3-7th insulating layer (137) and the 3-8th insulating layer (138) are ground, may be formed on the upper and lower surfaces of the circuit board, respectively. The first surface (133a) may be disposed on the upper surface of the second insulating layer (110). The second surface (137a) may be disposed on the lower surface of the 4th insulating layer (120). Accordingly, the first protective layer (198) and the second protective layer (199) are arranged on the first surface (133a) and the second surface (137a), respectively, so that the fifth pad portion (145) and the fifth pattern electrode (174), and the tenth pad portion (150) and the tenth pattern electrode (180) can be exposed upward and downward.

Figure 6 is a cross-sectional view of a semiconductor package according to an embodiment of the present invention.

Referring to FIG. 6, as described above, the circuit board according to an embodiment of the present invention may be an inductor board that functions as an inductor. Accordingly, compared to conventional methods of separately manufacturing and mounting inductor elements on a board, this circuit board can be miniaturized, and the production process can be simplified by joining different types of boards.

A semiconductor package according to an embodiment of the present invention may include a main substrate (200) and a circuit substrate (10) bonded to the main substrate (200).

The main substrate (200) may include a fifth insulating layer (210), a sixth insulating layer (220), and a seventh insulating layer (230) that are stacked in a vertical direction. The fifth to seventh insulating layers (210, 220, 230) may be prepreg (PPG).

The main substrate (200) may include a 13th pad portion (241) disposed on the upper surface of the 5th insulating layer (210), a 14th pad portion (242) disposed on the upper surface of the 6th insulating layer (220), a 15th pad portion (243) disposed on the upper surface of the 7th insulating layer (230), and a 16th pad portion (244) disposed on the lower surface of the 7th insulating layer (230).

The main board (200) may include a 12th via electrode (251) that penetrates the 5th insulating layer (210) and electrically connects the 13th pad portion (241) and the 14th pad portion (242), a 13th via electrode (252) that electrically connects the 14th pad portion (242) and the 15th pad portion (243) of the 6th insulating layer (220), and a 14th via electrode (253) that penetrates the 7th insulating layer (230) and electrically connects the 15th pad portion (243) and the 16th pad portion (244).

The vertical length of the 14th via electrode (253) may be longer than the vertical length of the 12th via electrode (251) or the 13th via electrode (252).

The main substrate (200) may include a 13th pattern electrode (261) disposed on the upper surface of the 5th insulating layer (210), a 14th pattern electrode (262) disposed on the upper surface of the 6th insulating layer (220), a 15th pattern electrode (263) disposed on the upper surface of the 7th insulating layer (230), and a 16th pattern electrode (264) disposed on the lower surface of the 7th insulating layer (230).

The main substrate (200) may include an 11th through electrode (271) connecting the 13th pattern electrode (261) and the 14th pattern electrode (262), a 12th through electrode (272) connecting the 14th pattern electrode (262) and the 15th pattern electrode (263), and a 13th through electrode (273) connecting the 15th pattern electrode (263) and the 16th pattern electrode (264).

The vertical length of the 13th penetration electrode (273) may be longer than the vertical length of the 11th penetration electrode (271) or the 12th penetration electrode (272).

According to the above structure, the 12th pattern electrode (182) arranged on the lower surface of the circuit board (10) can be connected to the 13th pattern electrode (271) through solder balls (290), respectively. Accordingly, the circuit board (10) can function as an inductor on the main board (200). That is, the circuit board (10) itself can be an inductor.

Meanwhile, a recess (not shown) having a concave shape downward compared to other areas may be formed on the upper surface of the main substrate (200). The recess may have a shape penetrating the fifth insulating layer (210) or the fifth insulating layer (210) and the sixth insulating layer (220). In this case, the circuit board (10) may be placed within the recess and electrically connected to a circuit pattern formed on the bottom surface of the recess. Accordingly, the vertical height of the semiconductor package may be reduced.

Figure 7 is a cross-sectional view of a circuit board according to a second embodiment of the present invention.

This embodiment is identical to the first embodiment in other respects, with the exception that the second and fourth insulating layers are omitted. Therefore, only the characteristic aspects of this embodiment will be described below, and the description of the first embodiment will be used for the remaining portions.

Referring to FIGS. 1 and 7, in the circuit board (40) according to the present embodiment, the second insulating layer (110) and the fourth insulating layer (140) may be omitted from the circuit board (10) according to the first embodiment. In this case, a third insulating layer made of the same material as the third insulating layer may be disposed in the areas where the second insulating layer (110) and the fourth insulating layer (140) are disposed in the circuit board (10) according to the first embodiment. In this case, it can be understood that the 3-9 insulating layer (310) is disposed between the 3-2 insulating layer (132) and the 3-3 insulating layer (133), and the 3-10 insulating layer (320) is disposed between the 3-6 insulating layer (136) and the 3-7 insulating layer (137). Meanwhile, in this embodiment, the circuit patterns in the 3rd-9th insulating layer (310) and the 3rd-10th insulating layer (320) are described based on the description of the circuit patterns in the 2nd insulating layer (110) and the 4th insulating layer (120) of the 1st embodiment.

Accordingly, the thickness of the circuit board (40) can be made thinner as the relatively thick second insulating layer and fourth insulating layer are replaced with a relatively thin third insulating layer made of PID (Photo-Imageable Dielectric) or ABF (Ajinomoto Build-up Film) material, but the rigidity can be weakened compared to the first embodiment.

Figure 8 is a cross-sectional view of a circuit board according to a third embodiment of the present invention.

In this embodiment, other parts are the same as in the first embodiment, but there is a difference in that the second pattern electrode, the eighth to twelfth pattern electrodes, and the sixth to tenth through electrodes are omitted from the circuit board according to the first embodiment.

Referring to FIGS. 1 and 8, the circuit board (50) according to the present embodiment may omit the second pattern electrode (177), the eighth to twelfth pattern electrodes (178, 179, 180, 181, 182), and the sixth to tenth through electrodes (188, 189, 190, 191, 192) from the circuit board according to the first embodiment. In this case, similarly, the rigidity of the circuit board (50) may be reinforced through the second insulating layer (110) and the fourth insulating layer (120), but the bending effect may be reduced compared to the first embodiment due to the asymmetry of the upper and lower circuit patterns with respect to the first insulating layer (100), and the yield may be reduced because the manufacturing of a plurality of inductor boards is impossible as in FIG. 4.

FIG. 9 is a cross-sectional view showing the layout structure of a circuit board according to a comparative example, FIG. 10 is a drawing measuring stress distribution in a circuit board according to a comparative example, and FIG. 11 is a drawing measuring stress distribution in a circuit board according to an embodiment of the present invention.

Referring to FIG. 9, a circuit board according to a comparative example includes a first insulating layer (1100) which is a corresponding configuration of a first insulating layer (100) of a circuit board (10) according to an embodiment of the present invention, and a third insulating layer (1210, 1220, 1230, 1240, 1250) which is a corresponding configuration of a third insulating layer of a circuit board (10) according to an embodiment of the present invention. The third insulating layers (1210, 1220, 1230, 1240, 1250) are implemented as five sheets and are arranged in a vertical direction on the upper surface of the first insulating layer (1100), and a pad portion and a via electrode are arranged on each layer. That is, the circuit board according to the comparative example is a case where the third insulating layer is not arranged in an upper and lower symmetrical structure based on the first insulating layer (1100), but is arranged only on one side.

Referring to Fig. 10, it can be confirmed that in the circuit board according to the comparative example, concentrated stress is generated at the boundary between the first insulating layer (1100) and the third insulating layer (1210, 1220, 1230, 1240, 1250). It can be confirmed that the stress is generated at its highest at the boundary between the pad portions arranged in the first insulating layer (1100) and the third insulating layer (1210, 1220, 1230, 1240, 1250).

Referring to FIG. 11, in a circuit board (10) according to an embodiment of the present invention, the first insulating layer (100) has a plurality of third insulating layers (131, 132, 133, 134) and circuit patterns within the third insulating layers (131, 132, 133, 134) are arranged symmetrically in the vertical direction with respect to the first insulating layer (100), and thus it can be confirmed that the stress within the circuit board (10) is also relatively uniformly distributed across the entire region. In particular, the first insulating layer (100) according to an embodiment of the present invention generates a relatively low stress compared to the stress generated at the boundary of the first insulating layer (1100) according to a comparative example, and thus the bending phenomenon of the circuit board (10) is minimized. In the above, even though all components constituting the embodiment of the present invention have been described as being combined as one or operating in combination, the present invention is not necessarily limited to such an embodiment. That is, within the scope of the purpose of the present invention, all of the components may be selectively combined and operated one or more times. In addition, terms such as "include," "comprise," or "have" described above, unless specifically stated to the contrary, mean that the corresponding component may be inherent, and therefore should be interpreted as including other components rather than excluding other components. All terms, including technical or scientific terms, have the same meaning as generally understood by a person of ordinary skill in the art to which the present invention pertains, unless otherwise defined. Commonly used terms, such as terms defined in a dictionary, should be interpreted as being consistent with the contextual meaning of the related technology, and shall not be interpreted in an ideal or excessively formal meaning unless explicitly defined in the present invention.

The above description is merely an illustrative description of the technical idea of the present invention, and those skilled in the art will appreciate that various modifications and variations may be made without departing from the essential characteristics of the present invention. Therefore, the embodiments disclosed in the present invention are intended to illustrate rather than limit the technical idea of the present invention, and the scope of the technical idea of the present invention is not limited by these embodiments. The scope of protection of the present invention should be interpreted by the following claims, and all technical ideas within a scope equivalent thereto should be interpreted as being included in the scope of the rights of the present invention.

Meanwhile, when a circuit board having the characteristics of the invention described above is used in IT devices such as smartphones, server computers, TVs, or home appliances, it can stably perform functions such as signal transmission or power supply. For example, when a circuit board having the characteristics of the invention performs a semiconductor package function, it can safely protect semiconductor chips from external moisture or contaminants, and can solve problems such as leakage current or electrical shorts between terminals, or electrical open circuits in terminals supplying semiconductor chips. Furthermore, when it performs a signal transmission function, it can solve noise problems. Through this, the circuit board having the characteristics of the invention described above can maintain the stable function of IT devices or home appliances, thereby enabling the entire product and the circuit board to which the invention is applied to achieve functional integration or technical interoperability with each other.

When a circuit board having the characteristics of the invention described above is used in a transportation device such as a vehicle, it can solve the problem of signal distortion transmitted to the transportation device, safely protect the semiconductor chip controlling the transportation device from external sources, and solve the problem of leakage current or electrical short circuit between terminals, or electrical open of the terminal supplying the semiconductor chip, thereby further improving the stability of the transportation device. Accordingly, the transportation device and the circuit board to which the present invention is applied can achieve functional integration or technical interoperability with each other.

Claims (10)

First insulating layer; A second insulating layer disposed on the first insulating layer and made of the same material as the first insulating layer; A third insulating layer disposed between the first insulating layer and the second insulating layer and made of a different material from the first insulating layer; A first via electrode penetrating the upper and lower surfaces of the first insulating layer; and A second via electrode is included that penetrates at least a portion of the second insulating layer, A circuit board in which the vertical length of the first via electrode is longer than the vertical length of the second via electrode. In the first paragraph, A circuit board wherein the first insulating layer and the second insulating layer are prepreg (PPG). In the second paragraph, A circuit board in which the third insulating layer is a PID (Photo-Imageable Dielectric) or ABF (Ajinomoto Build-up Film). In the first paragraph, A circuit board in which the third insulating layer is provided in multiple numbers and is placed between the first insulating layer and the second insulating layer. In paragraph 4, A circuit board having the third insulating layer as two or fewer layers. In the first paragraph, A pattern electrode arranged on the surface of the second insulating layer; A pattern electrode arranged on the surface of the third insulating layer; and A circuit board including a through electrode that vertically connects the pattern electrode of the second insulating layer and the pattern electrode of the third insulating layer. In paragraph 6, A circuit board comprising a pattern electrode of the second insulating layer, a pattern electrode of the third insulating layer, and a through electrode constituting an inductor. In the first paragraph, A fourth insulating layer is disposed below the first insulating layer and is made of the same material as the first insulating layer, A circuit board in which the third insulating layer is disposed between the first insulating layer and the fourth insulating layer. In paragraph 8, A circuit board in which the second insulating layer, the third insulating layer, and the circuit pattern arranged on the upper side based on the first insulating layer are symmetrical with the fourth insulating layer, the third insulating layer, and the circuit pattern arranged on the lower side. Main board; and Includes a circuit board bonded to the main board, The above circuit board, First insulating layer; A second insulating layer disposed on the first insulating layer and made of the same material as the first insulating layer; A third insulating layer disposed between the first insulating layer and the second insulating layer and made of a different material from the first insulating layer; A first via electrode penetrating the upper and lower surfaces of the first insulating layer; and A second via electrode is included that penetrates at least a portion of the second insulating layer, A semiconductor package in which the vertical length of the first via electrode is longer than the vertical length of the second via electrode.