WO2025134776A1 - Magnetic sensor device - Google Patents

Abstract

A magnetic sensor device (1) comprises: an energizing circuit (3) that periodically excites a magnetic detection element (2); and a plurality of sample-and-hold circuits (41) that are electrically connected in parallel to the magnetic detection element (2). A peak detection clock signal generation unit: outputs a peak detection clock signal to each of the plurality of sample-and-hold circuits (41) at a different timing within one excitation period; compares a plurality of acquired hold signals using a peak detection unit; and detects a peak value or a peak timing of a voltage signal Vi.

Description

Magnetic Sensor Device

The present invention relates to a magnetic sensor device.

Magnetic sensor devices generally have a sampling circuit that is synchronized with the timing of current flow to the magnetic detection element, and the sampling timing is adjusted, for example, by a delay circuit that uses an RC circuit or the like. In such cases, a process is required to change the element constants of the resistors, capacitors, etc. that make up the delay circuit, or to manually adjust the timing of the current flow through the pulse current. Therefore, to reduce the amount of work required, studies are being conducted on automating the setting of the sampling timing.

For example, Patent Document 1 proposes a magnetic sensor that includes a magnetosensitive body and a coil, a sampler that samples the induced voltage generated in the coil to obtain a sampling voltage, and an automatic correction circuit that relatively adjusts the rising timing of the magnetosensitive body clock and the sampler clock based on the sampling voltage. The automatic correction circuit has a delay synchronization circuit with multiple cascaded delay elements, and is configured to detect the delay time until the first peak by observing the displacement of the sampling voltage for a predetermined period from the rising edge of the magnetosensitive body clock, and set the sampler clock.

JP 2022-100055 A

In the magnetic sensor disclosed in Patent Document 1, the automatic correction circuit uses a delay synchronization circuit having a delay element, and sequentially changes the delay amount of the sampler clock to sample the voltage waveform. It then sequentially compares the input sampling voltage to search for the peak value, and corrects the sampler clock for normal peak value detection using the delay amount corresponding to the timing of the peak value. This optimizes the sensing timing after automatic correction, and makes it possible to detect the sampling voltage corresponding to the peak timing based on the corrected sampler clock.

This automatic correction circuit delays sampling by a fixed amount for each sampling period, so it takes time to detect the peak voltage, and the voltage waveform may change during detection, changing the peak value and sensitivity. In addition, because the sampler clock is corrected using a fixed delay amount corresponding to the peak value, the sensitivity also changes if the voltage waveform changes after correction, and there is a risk that the peak value cannot be detected correctly.

The present invention was made in consideration of these problems, and aims to provide a magnetic sensor device that can accurately detect the peak value or peak timing of a voltage signal output from a magnetic detection element in a short period of time.

In order to solve the above problem, a magnetic sensor device according to an embodiment of the present disclosure includes:
A magnetic detection element;
a current supply circuit that periodically excites the magnetic detection element;
a plurality of sample-and-hold circuits electrically connected in parallel to the magnetic detection element;
a peak detection clock generating unit that generates a peak detection clock corresponding to each of the plurality of sample hold circuits at different timings within one period of excitation by the energizing circuit, for each of the plurality of sample hold circuits;
The magnetic sensor device includes a peak detection unit that compares multiple hold signals acquired by multiple sample-and-hold circuits when the peak detection clock is output, and detects the peak value or peak timing of the voltage signal output from the magnetic detection element.

In the magnetic sensor device configured as above, the peak detection clock generation unit generates peak detection clocks with different timings to be supplied to each of the multiple sample and hold circuits within one period of excitation by the current-carrying circuit. The multiple sample and hold circuits are electrically connected in parallel to the magnetic detection element, and can acquire the voltage signal output from the magnetic detection element at different timings. The peak detection unit can detect the peak value or peak timing of the voltage signal by comparing the multiple hold signals acquired at different timings within one period.

In this way, the magnetic sensor device of the above configuration can use multiple sample-and-hold circuits to simultaneously acquire and compare multiple hold signals corresponding to one cycle of excitation. Therefore, the peak value or peak timing of the voltage signal can be detected quickly, and for example, the peak value or peak timing of the voltage signal can be detected more accurately by adjusting the number of multiple sample-and-hold circuits or the timing of the peak detection clock according to the voltage signal. In addition, there is little risk of being affected by changes in the voltage signal, as occurs when comparing voltage signals output at different cycles.

As described above, the above aspect provides a magnetic sensor device that can accurately detect the peak value or peak timing of a voltage signal output from a magnetic detection element in a short period of time.

1 is a circuit diagram showing a configuration example of a magnetic sensor device according to a first embodiment. 4 is a timing chart showing an operation of the magnetic sensor device in the first embodiment. 4 is a waveform diagram showing an example of a voltage signal generated by energizing a magnetic detection element in the first embodiment. 10 is a timing chart showing an operation of the magnetic sensor device in the first comparative example. 10 is a timing chart showing an operation of the magnetic sensor device in the second comparative example. FIG. 11 is a diagram illustrating an example of a circuit configuration of a magnetic sensor device according to a second embodiment. 10 is a timing chart showing an operation of the magnetic sensor device in the second embodiment. 13 is a timing chart showing an operation of a signal processing circuit of a magnetic sensor device in accordance with the third embodiment. FIG. 13 is a diagram illustrating an example of a circuit configuration of a magnetic sensor device according to a fourth embodiment. 13 is a timing chart showing an operation of a signal processing circuit of a magnetic sensor device in accordance with the fourth embodiment. FIG. 13 is a diagram illustrating an example of a circuit configuration of a magnetic sensor device according to a fifth embodiment. 13 is a timing chart showing an operation of a signal processing circuit of a magnetic sensor device in accordance with the fifth embodiment. 13 is a timing chart showing an operation of a signal processing circuit of a magnetic sensor device in a modified example of the fifth embodiment. FIG. 23 is a diagram illustrating an example of a circuit configuration of a magnetic sensor device according to a sixth embodiment. 23 is a timing chart showing an operation of a signal processing circuit of a magnetic sensor device in the sixth embodiment. 23 is a timing chart showing an operation of a signal processing circuit of a magnetic sensor device in the seventh embodiment.

Each embodiment will be explained in detail below with reference to the drawings.

Note that each of the embodiments described below is either a comprehensive or specific example, and the numerical values, shapes, components, arrangement positions and connection forms of the components shown in the embodiments are merely examples and are not intended to limit the present disclosure. Furthermore, among the components in the following embodiments, components that are not described in an independent claim that indicates the highest concept will be described as optional components.

Furthermore, the magnetic sensor device of the present disclosure will be described based on the embodiments, but the magnetic sensor device according to the present disclosure is not limited to the following embodiments. The following embodiments, modifications that can be made to the following embodiments by those skilled in the art without departing from the spirit of the present disclosure, and various devices incorporating the magnetic sensor device according to the present disclosure are also included in the present disclosure.

(Embodiment 1)
FIG. 1 is a circuit diagram showing a configuration example of a magnetic sensor device 1 according to the first embodiment.

[Basic configuration of magnetic sensor device 1]
In FIG. 1, the magnetic sensor device 1 includes a magnetic detection element 2, a current supply circuit 3, a magnetic detection circuit 4 including a plurality of sample-and-hold circuits 41, a control circuit 5 including a peak detection clock generating unit 51, and a signal processing circuit 6 including a peak detection unit 61.

The current supply circuit 3 periodically excites the magnetic detection element 2 .
The magnetic detection element 2 is excited by the passage of current from the current supply circuit 3 and generates a voltage signal Vi.

The multiple sample-and-hold circuits 41 are electrically connected in parallel to the magnetic detection element 2. The voltage signal Vi generated in the magnetic detection element 2 is periodically input to the magnetic detection circuit 4, and is acquired as a hold signal SH at a predetermined timing in each of the multiple sample-and-hold circuits 41.

The peak detection clock generating unit 51 generates a peak detection clock SHAp corresponding to each of the multiple sample hold circuits 41 at different timings within one period of excitation by the energizing circuit 3. The peak detection clock SHAp is output to each of the multiple sample hold circuits 41 at different predetermined timings.

The peak detection unit 61 detects the peak value or peak timing, which is the timing at which the voltage signal Vi output from the magnetic detection element 2 reaches a peak value. When the peak detection clock SHAp is output, the peak detection unit 61 compares the multiple hold signals SH acquired by the multiple sample-and-hold circuits 41. Then, based on the comparison result, it is possible to detect the peak value or peak timing of the voltage signal Vi. As described below, the peak detection unit 61 in this embodiment is described as detecting the peak value among these. Note that the multiple hold signals SH are output from the magnetic detection circuit 4 as digital signals obtained by analog-to-digital conversion of the amplified signals, for example, and the peak detection unit 61 can detect the maximum value among them as the peak value.

The control circuit 5 may further include a voltage change detection clock generation unit 52. The voltage change detection clock generation unit 52 generates a voltage change detection clock SHAc corresponding to each of the multiple sample and hold circuits 41. The voltage change detection clock SHAc is output to each of the multiple sample and hold circuits 41 at different predetermined timings.

The signal processing circuit 6 may further include a voltage change detection unit 62 that detects a voltage change in the voltage signal Vi. When the voltage change detection clock SHAc is output, the voltage change detection unit 62 compares the multiple hold signals SH acquired by the multiple sample-and-hold circuits 41. Then, based on the comparison result, it is possible to detect, for example, a voltage change corresponding to the rising edge of the voltage signal Vi.

The control circuit 5 can perform sampling for peak detection in the peak detection clock generation unit 51 using the detection result of the voltage change detection unit 62. In this case, the peak detection clock generation unit 51 generates the peak detection clock SHAp at a timing set based on the voltage change of the detected voltage signal Vi.

When peak detection processing is performed by peak detection unit 61 after voltage change detection processing by voltage change detection unit 62, it is desirable to set the timing so that the peak detection clock SHAp is output after the point at which the voltage change is detected, based on the point at which the voltage change is detected.
As a result, the peak detection unit 61 can efficiently perform peak detection processing using the hold signal SH obtained after the voltage change is detected, and can reliably detect the peak value or peak timing of the voltage signal Vi in a short period of time.

The signal processing circuit 6 can, for example, alternately repeat the voltage change detection process by the voltage change detection unit 62 and the peak detection process by the peak detection unit 61.

By alternately performing these processes, a peak detection clock SHAp is generated based on the voltage change of the voltage signal Vi detected by the voltage change detection process, and the peak value or peak timing of the voltage signal Vi is repeatedly detected by the peak detection process.
As a result, even if changes in the voltage signal Vi are likely to occur, for example, the frequency of the voltage change detection process increases, so that the peak value or peak timing can be detected with high accuracy in the peak detection process.

The interval at which the peak detection clock SHAp is generated (hereinafter, also referred to as the "peak detection clock interval") is set to, for example, a predetermined constant interval.
Furthermore, the interval at which the voltage change detection clock SHAc is generated (hereinafter, also referred to as the "voltage change detection clock interval") is set to a predetermined constant interval.

The control circuit 5 can set the peak detection clock interval generated by the peak detection clock generation unit 51 to, for example, the same interval as the voltage change detection clock interval generated by the voltage change detection clock generation unit 52.

[Configuration of each part of the magnetic sensor device 1]
Next, each component of the magnetic sensor device 1 of this embodiment will be specifically described.
1, the magnetic detection element 2 is, for example, a magneto impedance (MI) element including a magnetic sensitive body 21 and a detection coil 22 (hereinafter, also referred to as an "MI element"). The magnetic sensitive body 21 is made of, for example, an amorphous wire, and the detection coil 22 is wound around the magnetic sensitive body 21 with an insulating layer interposed therebetween. The MI element 2 outputs an induced voltage generated in the detection coil 22 by supplying an excitation current to the magnetic sensitive body 21 as a voltage signal Vi.

The energizing circuit 3 periodically supplies an excitation current to the MI element 2. The excitation current can be, for example, a pulse current. Here, as an example, the energizing circuit 3 is configured as a pulse energizing circuit that can pass a pulse current through the magnetic sensitive body 21. The excitation current can be any periodic current, and can be, for example, a high-frequency current.

Here, the current supply circuit 3 includes a pulse generating unit 31, a pair of switches 32a, 32b driven by a pulsed control signal MI_SW supplied from the pulse generating unit 31, and a resistor 33. One of the pair, switch 32a, is inserted between one end of the magnetic sensor 21 and the high-potential power supply AVDD, and the other of the pair, switch 32b, is inserted between the other end of the magnetic sensor 21 and the low-potential power supply AVSS.

The current supply circuit 3 can start or cut off the supply of pulse current to the magnetosensitive body 21 by simultaneously turning on or off a pair of switches 32a, 32b using the control signal MI_SW. As a result, the impedance of the magnetosensitive body 21 changes in response to the strength of the external magnetic field acting on the amorphous wire, and this change in magnetization generates an induced voltage across the detection coil 22. Both ends of the detection coil 22 are electrically connected to a pair of signal lines 71, 72 that lead to the sample-and-hold circuit 41 of the magnetic detection circuit 4.

The magnetic detection element 2 may be any element capable of detecting magnetism, and may be, in addition to the MI element 2, a Hall element, an MR element (magnetoresistive element), a GMR element (giant magnetoresistive element), a TMR element (tunnel junction magnetoresistive element), or the like.

The magnetic detection circuit 4 has a plurality of sampling blocks B, each including one sample-and-hold circuit 41. The sample-and-hold circuit 41 has a pair of switches 41a, 41b and a pair of capacitors 41c, 41d that correspond to a pair of signal lines 71, 72, respectively.

The number of sample-and-hold circuits 41 (m; m≧2) corresponds to the number of hold signals SH acquired for one excitation, and can be selected arbitrarily. Specifically, it is desirable that the number of sample-and-hold circuits 41 is set in the signal processing circuit 6 so that the number is sufficient to detect the peak value of the voltage signal Vi by one voltage change detection process followed by one peak detection process.

Each sampling block B has a sample-and-hold circuit 41 and an AD (Analog Digital) conversion circuit 42. An amplifier circuit 43 is disposed between the sample-and-hold circuit 41 and the AD conversion circuit 42. The arrangement of the amplifier circuit 43 is not limited to this, and the sampling block B may be configured not to have an amplifier circuit 43.

The AD conversion circuit 42 performs an analog-to-digital conversion process (hereinafter, also referred to as "AD conversion process") that converts the analog hold signal SH into a digital signal. The amplifier circuit 43 amplifies the hold signal SH acquired by the sample-and-hold circuit 41 by a predetermined amplification factor and outputs the amplified signal to the AD conversion circuit 42.

Each sampling block B holds the hold signal SH, which has been AD converted by the AD conversion circuit 42, and outputs it to the signal processing circuit 6.

The pair of signal lines 71, 72 branch out according to the number (m) of sampling blocks B, and each pair of branch signal lines is electrically connected to the inverting input terminal and non-inverting input terminal of the corresponding amplifier circuit 43 via a sample-and-hold circuit 41. The sample-and-hold circuit 41 simultaneously turns on or off a pair of switches 41a, 41b according to the detection clock output from the control circuit 5, opening and closing the pair of signal lines 71, 72.

At this time, the potential difference between the potential CA of the signal line 71 and the potential CB of the signal line 72 becomes a voltage signal Vi (Vi = CA - CB). This voltage signal Vi is acquired by the sample-and-hold circuit 41 at a timing according to the detection clock from the control circuit 5, and is output as a hold signal SH.

The control circuit 5 selectively connects each sample-and-hold circuit 41 to the peak detection clock generation unit 51 or the voltage change detection clock generation unit 52, and outputs the peak detection clock SHAp or the voltage change detection clock SHAc. That is, each sample-and-hold circuit 41 is connected to the peak detection clock generation unit 51 during peak detection processing, and is connected to the voltage change detection clock generation unit 52 during voltage change detection processing.

Specifically, the peak detection clock generation unit 51 and the multiple sample-and-hold circuits 41 are each connected via a signal line that is opened and closed by the peak detection switch SWp. Also, the voltage change detection clock generation unit 52 and the multiple sample-and-hold circuits 41 are each connected via a signal line that is opened and closed by the voltage change detection switch SWc.

During the peak detection process, the control circuit 5 turns on the peak detection switch SWp and turns off the voltage change detection switch SWc. Also, during the voltage change detection process, the control circuit 5 turns on the voltage change detection switch SWc and turns off the peak detection switch SWp.
As a result, a detection clock corresponding to each detection process is output to each of the sample-and-hold circuits 41 at a predetermined timing during each detection process.

In addition, an AD conversion control signal for AD converting the hold signal SH in the AD conversion circuit 42 is input to the sample hold block B at a predetermined timing. The digital signal after AD conversion is output to the voltage change detection unit 62 or peak detection processing unit 61 of the signal processing circuit 6.

The peak detection clock generating unit 51 includes a delay circuit 511 in which multiple delay elements 512 are connected in series, and a multiplexer MUX1. The peak detection clock generating unit 51 is configured as a DLL (Delay Locked Loop) circuit that uses the sampling clock DLLCK as a reference and generates an internal clock whose phase is changed using multiple delay elements 512.

The delay circuit 511 can generate a signal that is delayed by a predetermined time from the input of the sampling clock DLLCK according to the number (n+1) of delay elements 512, for example, and output it as delay amounts d<0> to d<n>. The predetermined time that determines the delay amounts d<0> to d<n> can be set arbitrarily, and corresponds to the sampling interval in the peak detection process.

The peak detection clock generation unit 51 uses the multiplexer MUX1 to select m of the delay amounts d<0> to d<n>, which corresponds to the number of sample-and-hold circuits 41 (n>m). These can then be supplied as the peak detection clock SHAp to the corresponding sample-and-hold circuits 41. This allows a peak detection clock SHA with any delay amount, for example within the range of SHAp<0> to SHAp<n> shown in FIG. 1, to be selected and output to each sample-and-hold circuit 41. The same applies to the voltage change detection clock SHAc and other detection clocks SHA described below.

Similarly, the voltage change detection clock generation unit 52 includes a delay circuit 521 in which multiple delay elements 522 are connected in series, and a multiplexer MUX2. The delay circuit 521 generates delay amounts d<0> to d<i> that correspond to the number of delay elements 522 (i+1), for example. The voltage change detection clock generation unit 52 uses the multiplexer MUX2 to select m of the delay amounts d<0> to d<i> that correspond to the number of sample-and-hold circuits 41 (i>m). Then, it can supply the voltage change detection clock SHAc to the corresponding sample-and-hold circuits 41.

[Operation of the magnetic sensor device 1]
FIG. 2 is a timing chart showing the operation of each part of the magnetic sensor device 1, in which the signal processing circuit 6 performs a voltage change detection process and a peak detection process in this order.
FIG. 3 is a waveform diagram showing an example of change in the voltage signal Vi generated in the MI element 2 in response to excitation by the energizing circuit 3. In FIG.

In FIG. 2, when a control signal MI_SW is output in synchronization with a sampling clock DLLCK, a voltage signal Vi is output from the MI element 2. The multiple sample-and-hold circuits 41 acquire the voltage signal Vi at different timings based on the voltage change detection clock SHAc output from the voltage change detection clock generation unit 52.

In FIG. 3 , generally, when a pulse current is supplied to the MI element 2 by energization from the energization circuit 3, the voltage signal Vi rises with a delay between the rising edge (period _tR ) and the falling edge (period _tF ) of the pulse current (period _tHIGH ), reaches a peak value, and then falls.
At this time, the peak value of the voltage signal Vi corresponds to the strength of the external magnetic field to be detected. Note that the voltage signal Vi has a voltage waveform having a peak on the positive side or the negative side of the DC potential depending on the direction of the external magnetic field. For simplicity, the case where the peak voltage exists on the positive side is shown here.

The magnetic sensor device 1 is required to accurately detect the peak value of the voltage signal Vi in order to accurately detect the external magnetic field to be detected. To achieve this, the magnetic detection circuit 4 is provided with multiple sample-and-hold circuits 41, and sampling is performed according to the procedure shown in FIG. 2.

Here, the number of sample and hold circuits 41 is, for example, 17 (m=17), and the voltage change detection clock generation unit 52 selects 17 voltage change detection clocks SHAc<0> to SHAc<16> that include the rising edge of the sampling clock DLLCK. Each sample and hold circuit 41 acquires a voltage signal Vi at a predetermined timing. As a result, 17 samples are performed at once for the first sampling clock DLLCK, and 17 hold signals SH<0> to SH<16> are acquired.

The 17 hold signals SH<0> to SH<16> are each amplified in the amplifier circuit 43, and then the amplified signal is AD converted in the AD conversion circuit 42 into a digital signal, which is then output to the voltage change detection unit 62.
The sampling interval for the 17 samples corresponds to the voltage change detection clock interval Δt, which is the interval at which the voltage change detection clocks SHAc<0> to SHAc<16> are generated. In other words, sampling is performed with a delay amount that is incremented by Δt.

The voltage change detection unit 62 compares the digital signals corresponding to the 17 hold signals SH<0> to SH<16> in numerical order. For example, for the hold signal SH<0> generated by the first voltage change detection clock SHAc<0> and the hold signal SH<1> generated by the second voltage change detection clock SHAc<1>, the difference value of the corresponding digital signals is compared with a predetermined threshold. Then, the comparison of the hold signals SH is repeated until a voltage change to the positive side that is equal to or exceeds the predetermined threshold is detected.

When the voltage change detection unit 62 detects a voltage change equal to or greater than a predetermined threshold, it ends the voltage change detection process. Here, the voltage change detection unit 62 outputs the detection result assuming that a predetermined voltage change has been detected at the falling edge of the fourth voltage change detection clock SHAc<3>, where the hold signal SH<3> is acquired. The detection result may include, for example, time information indicating the position of the voltage change (here, the delay amount d<3> corresponding to the voltage change detection clock SHAc<3>). The detection result is, for example, output to the control circuit 5 and stored in a memory (not shown), and serves as a reference when the peak detection clock generation unit 51 generates the peak detection clock SHAp.

Then, at the next sampling clock DLLCK, the signal processing circuit 6 uses the results of the voltage change detection process to perform peak detection processing by the peak detection unit 61. In the peak detection process, the 17 sample and hold circuits 41 acquire the voltage signal Vi at different timings based on the peak detection clock SHAp output from the peak detection clock generation unit 51.

At this time, the peak detection clock generating unit 51 selects the peak detection clock SHAp so that the first sampling is performed at the same timing as the voltage change detection clock SHAc<3> in which the voltage change is detected. In other words, 17 peak change detection clocks SHAp<3> to SHAp<19> are selected and output to the corresponding sample and hold circuits 41.

As a result, 17 samples are similarly performed for the next sampling clock DLLCK, and 17 hold signals SH are obtained. The obtained hold signals SH are similarly amplified by the amplifier circuit 43, and further converted into digital signals by the AD conversion circuit 42 and output to the peak detection unit 61. Hereinafter, the signal based on the hold signal SH (amplified signal, digital signal) will be appropriately referred to as the hold signal SH.
The sampling interval in the peak detection process is the same as that in the voltage change detection process, and the peak detection clock interval Δt=voltage change detection clock interval Δt.

The peak detection unit 61 compares the 17 hold signals SH<3> to SH<19> corresponding to the peak detection clocks SHAp<3> to SHAp<19> in numerical order to detect peak values. In the peak detection process, for example, the difference values of the corresponding digital signals for the hold signal SH<3> generated by the first peak detection clock SHAp<3> and the hold signal SH<4> generated by the second peak detection clock SHAp<4> are compared in sequence. Comparison of the hold signals SH is then repeated until a change in the difference value indicates that the voltage signal Vi has changed from an increasing trend to a decreasing trend.

Here, it is assumed that the hold signal SH<8> generated by the peak detection clock SHAp<8> corresponds to the peak value of the voltage signal Vi. The peak detection unit 61 can detect the peak value by comparing the hold signal SH<8> with the hold signals SH before and after it. For example, the peak detection unit 61 can determine that a peak value has been detected when a voltage change of a predetermined threshold or more to the negative side is detected for the first time from the difference value between the hold signal SH<9> generated by the peak detection clock SHAp<9>. The peak detection unit 61 then outputs the detection result and ends the peak detection process.

The signal processing circuit 6 can generate magnetic detection information based on the peak value detected by the peak detection unit 61 and output the information to the outside. The magnetic detection information may be, for example, the magnitude or change of the external magnetic field to be detected, or may be position information of the object to be detected.
Thereafter, the signal processing circuit 6 repeats the voltage change detection process and then the peak detection process in the same manner. In this manner, the change detection period of the voltage signal Vi and the peak detection period of the voltage signal Vi are alternately repeated in response to the sampling clock DLLCK.

According to this embodiment, the magnetic sensor device 1 can use multiple sample-and-hold circuits 41 to obtain hold signals SH at multiple different timings for each excitation cycle of the MI element 2, and can repeatedly perform voltage change detection processing and peak detection processing. In this case, the peak detection processing can be performed efficiently using the results of the voltage change detection processing, and the peak value of the voltage signal Vi can be reliably detected in a short time.

As shown in FIG. 2, when the MI element 2 is excited by the energizing circuit 3 at a predetermined cycle, the rising edge of the control signal MI_SW may be shifted from the rising edge of the sampling clock DLLCK. The greater this shift, the longer the time from the rising edge of the sampling clock DLLCK to the rising edge of the voltage signal Vi. On the other hand, when the voltage signal Vi rises in conjunction with the rising edge of the control signal MI_SW, it reaches a peak value relatively quickly.

In this embodiment, the magnetic sensor device 1 first detects the rising edge from the voltage change of the voltage signal Vi in the voltage change detection unit 62, and then detects the peak value from the change in the voltage signal Vi after the rising edge in the peak detection unit 61. In this way, by appropriately setting the number of sample-and-hold circuits 41 and sequentially detecting the voltage change and peak value of the voltage signal Vi in the signal processing circuit 6, the peak value can be efficiently detected in a time equivalent to two sampling clocks.

(Comparative Example 1)
FIG. 4 is a timing chart showing an example of the operation when detecting a voltage change and detecting a peak using a conventional magnetic sensor device provided with one sample-and-hold circuit 41 for an MI element 2. In FIG.

Here, the sampling interval (Δt) in the first embodiment is used to delay the delay amount for voltage change detection and peak detection by Δt. As a result, when a control signal SMI is output to the MI element 2 in synchronization with the sampling clock CLK, the falling edge position of the sampling signal SMPL, which is the hold position of the generated voltage signal Vi, is delayed by Δt for each sampling clock CLK.

In the example shown in Figure 4, for example, at the second sampling clock CLK (delay: 2 x Δt), the rising edge of the voltage signal Vi is detected by comparison with the first hold signal, and then at the Nth sampling clock CLK (delay: N x Δt), the peak position is detected by comparison of the N-1st to N+1st hold signals. In other words, it takes a time equivalent to two sampling clocks to detect the rising edge. Here, if Δt is 2 nsec and it is N nsec from the start of detection to the peak position, then it will take a time equivalent to N/2 sampling clocks to detect the peak.

Also, as shown in Figure 4, the voltage waveform may change before the peak is detected, and the peak value may change from the initial peak value. In such cases, the peak position or magnitude may change, which may result in a longer time to detect the peak value or a change in sensitivity.

(Comparative Example 2)
5 is a timing chart showing an example of an operation when a fixed delay amount Δt opt is set and sampling is performed in a conventional magnetic sensor device. The fixed delay amount Δt opt is set in advance based on the peak position of the voltage signal Vi detected by the procedure shown in the above comparative example 1.

In this case, a control signal SMI is output in response to the sampling clock CLK, and each time a voltage signal Vi is output from the MI element 2, a hold signal is acquired by the sample-and-hold circuit 41 at the same timing, and a peak value is detected. However, as shown by the arrow in FIG. 5, for example, after the second sampling clock CLK, fluctuations may occur in the voltage signal Vi, causing the amplitude to change. Therefore, if sampling is performed at a fixed timing, detection will not be performed at the peak position, and the sensitivity may change.

In this way, the procedure shown in Comparative Example 1 takes a long time to detect the peak value of the voltage signal Vi and cannot respond to changes in the voltage signal Vi. The procedure shown in Comparative Example 2 allows repeated detection of peak values, but is similarly unable to respond to changes in the voltage signal Vi.
In contrast, according to the above-described first embodiment, it is possible to achieve both a reduction in detection time and a response to voltage changes, and a highly reliable magnetic sensor device 1 can be obtained.

(Embodiment 2)
FIG. 6 is a circuit diagram showing a configuration example of a magnetic sensor device 1 according to a second embodiment, which differs from the first embodiment in part of the configuration of a control circuit 5.
FIG. 7 is a timing chart showing the operation of the magnetic sensor device 1, in which the number of times that the signal processing circuit 6 performs the peak detection process after the voltage change detection process is changed.
In this embodiment, the basic configuration and basic operation of the magnetic sensor device 1 are similar to those of the first embodiment, and the following mainly describes the differences.

In FIG. 6, the control circuit 5 includes a common detection clock generator 50. The common detection clock generator 50 combines the functions of the peak detection clock generator 51 and the voltage change detection clock generator 52 in the first embodiment.

Specifically, the detection clock generating unit 50 includes a common delay circuit 501 and a common multiplexer MUX. The common delay circuit 501 has a plurality of delay elements 502 connected in series, and can function as the delay circuits 511 and 521 in the above-mentioned first embodiment. The common multiplexer MUX can function as the multiplexers MUX1 and MUX2 in the above-mentioned first embodiment.

　Prior to the peak detection process, the common delay circuit 501 generates delay amounts d<0> to d<i> for the voltage change detection process, similar to the delay circuit 521. The common detection clock generation unit 50, similar to the voltage change detection clock generation unit 52, can use the multiplexer MUX to select m of the delay amounts d<0> to d<i>, corresponding to the number of sample-and-hold circuits 41, and output them as the voltage change detection clock SHAc.

In addition, in the peak detection process, the common delay circuit 501 generates delay amounts d<0> to d<n> for the peak detection process, similar to the delay circuit 511. The common detection clock generation unit 50, similar to the peak detection clock generation unit 51, selects m of the delay amounts d<0> to d<n>, corresponding to the number of sample-and-hold circuits 41, based on the results of the voltage change detection process. In this case, the common detection clock generation unit 50 can use the multiplexer MUX to select m amounts after the point in time when the voltage change is detected, and output them as the peak detection clock SHAp.

In FIG. 7, the signal processing circuit 6 performs a voltage change detection process by the voltage change detection unit 62, and then performs a peak detection process by the peak detection unit 61 multiple times in succession. Here, the signal processing circuit 6 repeats a voltage change detection process once, followed by, for example, two peak detection processes.

In this embodiment, the procedure for the voltage change detection process by the voltage change detection unit 62 and the procedure for the peak detection process by the peak detection unit 61 are the same as those in the first embodiment. That is, the common detection clock generation unit 50 outputs the voltage change detection clock SHAc in response to the first sampling clock DLLCK, and the voltage change detection process is performed. The voltage change detection unit 62 performs a comparison based on the multiple hold signals SH acquired, and detects a voltage change in the voltage signal Vi.

Furthermore, for the next sampling clock DLLCK, the common detection clock generation unit 50 outputs the peak detection clock SHAp based on the voltage change detection result, and peak detection processing is performed. The peak detection unit 61 performs a comparison based on the multiple hold signals SH acquired, detects the peak value of the voltage signal Vi, and outputs the result.

Furthermore, the peak detection process is performed in a similar manner for the next sampling clock DLLCK. After that, the signal processing circuit 6 determines that the number of peak detection processes has reached a predetermined number, and performs voltage change detection process again by the voltage change detection unit 62 for the next sampling clock DLLCK.

In this manner, a state in which a change detection period of the voltage signal Vi is followed by a peak detection period of the voltage signal Vi in succession is repeated in response to the sampling clock DLLCK.
In this embodiment, the number of times the peak detection process is repeated is just an example, and can be set to any number of times, such as 2, 3 or more.

According to this embodiment, the magnetic sensor device 1 includes the common detection clock generating unit 50 in the control circuit 5, and therefore, the same effects as those of the first embodiment can be obtained with a simpler configuration.
Furthermore, in the signal processing circuit 6, the result of a single detection by the voltage change detection unit 62 is effectively utilized to continuously perform peak detection processing by the peak detection unit 61, making it possible to detect the peak value of the voltage signal Vi more quickly and accurately.

In the configuration of this embodiment, similarly to the above-described first embodiment, the common detection clock generating unit 50 may alternately generate the voltage change detection clock SHAc and the peak detection clock SHAp, and alternately repeat the voltage change detection process and the peak detection process.
Furthermore, in the configuration of the above-mentioned first embodiment, similarly to the present embodiment, after performing voltage change detection processing based on the voltage change detection clock SHAc generated by the voltage change detection clock generating unit 52, peak detection processing based on the peak detection clock SHAp generated by the peak detection clock generating unit 51 can be repeated multiple times.

(Embodiment 3)
FIG. 8 is a timing chart showing the operation of the magnetic sensor device 1 according to the third embodiment. The third embodiment differs from the first embodiment in the settings of the detection clock intervals in each detection process of the signal processing circuit 6.
In this embodiment, the basic configuration and basic operation of the magnetic sensor device 1 are similar to those of the first embodiment, and the following mainly describes the differences.

In FIG. 8, the detection clocks output from the control circuit 5 during detection processing by the signal processing circuit 6 are set to different intervals, i.e., the voltage change detection clock interval Δtc, which is the sampling interval in the voltage change detection unit 62, and the peak detection clock interval Δtp, which is the sampling interval in the peak detection unit 61. Specifically, the peak detection clock interval Δtp is set to be shorter than the voltage change detection clock interval Δtc.

Here, as an example, a case is shown in which the time from the rising edge of the sampling clock DLLCK to the rising edge of the voltage signal Vi caused by the control signal MI_SW is relatively long. In that case, it is desirable to set the voltage change detection clock interval Δtc so that the change detection period for the voltage signal Vi is longer than in the first embodiment above, and is a sufficiently long period that certainly includes the output period of the control signal MI_SW.

Specifically, the voltage change detection clock interval Δtc can be set to an interval longer than the voltage change detection clock interval Δt in the first embodiment. As a result, at the first sampling clock DLLCK, for example, a voltage change is detected by a hold signal SH<3> generated by the voltage change detection clock SHAc<3> (for example, SHA<3> shown in FIG. 8).

On the other hand, it is desirable that the peak detection clock interval Δtp in the peak detection process is a sufficiently short interval that the peak value of the voltage signal Vi can be detected with the desired accuracy. Specifically, the peak detection clock interval Δtp is shorter than the voltage change detection clock interval Δtc, and here, for example, is set to 1/2 of Δtc. Also, it can be set to be approximately equal to or shorter than the voltage change detection clock interval Δt in the first embodiment above (Δt≧Δtp=Δtc/2). As a result, in the next sampling clock DLLCK, sampling is started with the peak detection clock SHAp<6>, which corresponds to the voltage change detection clock SHAc<3>, and the peak value is detected, for example, with the hold signal SH<12> by the peak detection clock SHAp<12> (for example, SHA<12> shown in FIG. 8).

In this embodiment, the sampling interval using the multiple sample-and-hold circuits 41 is set long during the voltage change detection process, so that the voltage change detection unit 62 can reliably detect voltage changes regardless of the time until the rise of the voltage signal Vi or the voltage waveform of the voltage signal Vi. In addition, when detecting a peak value using the voltage change detection result, the sampling interval is set shorter, so that the peak value of the voltage signal Vi can be detected with high accuracy.

As shown in FIG. 8, if the time from the rising edge of the sampling clock DLLCK to the rising edge of the voltage signal Vi is relatively long, then with a sampling interval similar to that of the first embodiment, it will take longer for the voltage change detection unit 62 to detect the voltage change. Alternatively, depending on the waveform of the voltage signal Vi, the time from the rising edge to the peak value will be relatively long, and it may take a long time to detect the voltage change.

In this embodiment, by adopting a longer voltage change detection clock interval Δtc, it is possible to reliably detect voltage changes without increasing the number of samples. Furthermore, by performing the subsequent peak detection process from the detected voltage change position at a shorter peak detection clock interval Δtp, it is possible to efficiently perform the detection process while ensuring the detection accuracy of the peak value.

In addition, the same effects as those of the first embodiment can be obtained.
Furthermore, in the configuration of the second embodiment, similarly to this embodiment, the voltage change detection clock interval Δtc in the voltage change detection unit 62 and the peak detection clock interval Δtp in the peak detection unit 61 can be set to different intervals, for example, voltage change detection clock interval Δtc > peak detection clock interval Δtp. In that case, the common detection clock generation unit 50 can, for example, extract a portion of the delay amounts d<0> to d<n> for the peak detection process so that they are at desired equal intervals, and generate the delay amounts d<0> to d<i> for the voltage change detection process.

(Embodiment 4)
FIG. 9 is a diagram showing an example of a circuit configuration of a magnetic sensor device 1 according to the fourth embodiment, which differs from the first embodiment in part of the configurations of the control circuit 5 and the signal processing circuit 6.
FIG. 10 is a timing chart showing the operation of the magnetic sensor device 1, which differs from the first embodiment in the settings of the detection process in the signal processing circuit 6.
In this embodiment, the basic configuration and basic operation of the magnetic sensor device 1 are similar to those of the first embodiment, and the following mainly describes the differences.

In FIG. 9, the control circuit 5 includes a peak detection clock generator 51 that outputs a peak detection clock SHAp, and the signal processing circuit 6 includes a peak detector 61. In this embodiment, the magnetic sensor device 1 is not configured to include a circuit for voltage change detection, and does not include the voltage change detection clock generator 52 and voltage change detector 62 in the first embodiment.

In this embodiment, when generating the peak detection clock SHAp, the peak detection clock generation unit 51 selects a preset number m of delay amounts d<0> to d<n> generated by the delay circuit 501 in accordance with the number of sample hold circuits 41. The multiple sample hold circuits 41 perform sampling based on the peak detection clock SHAp, and the peak detection unit 61 performs comparison based on the multiple acquired hold signals SH to detect the peak value of the voltage signal Vi.

FIG. 10 shows, as an example, a case in which the rising edge of the sampling clock DLLCK and the rising edge of the voltage signal Vi caused by the control signal MI_SW are at approximately the same timing. In this case, when the sampling clock DLLCK rises, the voltage signal Vi rises quickly, so it is possible to repeatedly detect only the peak value without detecting voltage changes.

In the peak detection clock generation unit 51, for example, similar to the voltage change detection clock generation unit 52 in the first embodiment, 17 peak detection clocks SHAp<0> to SHAp<16> that include the rising edges of the sampling clock DLLCK are generated and output to the corresponding 17 sample and hold circuits 41. As a result, 17 samples are performed with respect to the sampling clock DLLCK, and 17 hold signals SH are obtained.

The hold signal SH acquired by 17 samplings is input to the peak detection unit 61 of the signal processing circuit 6 as a digital signal that has been AD converted from the amplified signal, and is compared in order to detect the peak value. Here, as an example, the peak value is repeatedly detected in the hold signal SH<7> generated by the peak detection clock SHAp<7> (for example, SHA<7> shown in Figure 10). In this way, the peak detection process by the peak detection unit 61 is repeatedly performed.

According to this embodiment, the magnetic sensor device 1 can omit the circuit for detecting voltage changes, and can detect the peak value of the voltage signal Vi more quickly and accurately with a simpler configuration. In addition, the same effects as those of the first embodiment can be obtained.

In this embodiment, the peak detection clock SHAp generated by the peak detection clock generating unit 51 can be determined in advance by testing, for example, at the time of product shipment of the magnetic sensor device 1. If the magnetic sensor device 1 is used in a stable environment and the magnetic detection circuit 4 has a sufficient number of sample-and-hold circuits 41 for detecting peak values, the configuration may not include the voltage change detection clock generating unit 52, making it possible to speed up magnetic detection.

In the above-described embodiment, the peak detection unit 61 performs a single peak detection process to detect the peak value of the voltage signal Vi based on a plurality of hold signals SH acquired at different timings. However, the peak timing may be detected. Alternatively, the detection process for detecting the peak timing and the detection process for detecting the peak value may be combined to perform two peak detection processes.

In the latter case, from the viewpoint of noise reduction, it is desirable to perform the second peak detection process at the same timing. Specifically, in the multiple sample-and-hold circuits 41, first, sampling is performed based on the different peak detection clocks SHAp in the same manner as in the above-mentioned embodiment, and then the acquired multiple hold signals SH are compared to detect the peak timing of the voltage signal Vi. Furthermore, within the next excitation cycle, sampling is performed based on the detected peak timing, and the acquired multiple hold signals SH are averaged. In this way, multiple hold signals SH synchronized with the first peak detection result are obtained, and further, noise components contained in these signals are removed by averaging, so that the peak value of the voltage signal Vi can be detected.
An example of a configuration for detecting a peak value by performing detection processing twice will be described below.

(Embodiment 5)
FIG. 11 is a diagram showing an example of a circuit configuration of a magnetic sensor device 1 according to embodiment 5, which differs from embodiment 4 in part in the configuration of the peak detection clock generating unit of the control circuit 5 and the peak detection unit of the signal processing circuit 6.
FIG. 12 is a timing chart showing the operation of the magnetic sensor device 1. The setting for peak detection processing in the signal processing circuit 6 is different from that in the fourth embodiment.
In this embodiment, the basic configuration and basic operation of the magnetic sensor device 1 are similar to those of the fourth embodiment, and the following mainly describes the differences.

In FIG. 11, the control circuit 5 includes a first peak detection clock generating unit 531 that generates a first peak detection clock SHAp1, and a second peak detection clock generating unit 532 that generates a second peak detection clock SHAp2. The signal processing circuit 6 includes a first peak detection unit 611 and a second peak detection unit 612, and is configured to perform peak detection processing as the first peak detection clock SHAp1 and the second peak detection clock SHAp2 are output, respectively.

In this embodiment, the first peak detection clock generating unit 531 corresponds to the peak detection clock generating unit 51 in the fourth embodiment, and includes a delay circuit 511 in which a plurality of delay elements 512 are connected in series, and a multiplexer MUX1. As a result, m delay amounts corresponding to the number of sample-and-hold circuits 41 are selected from the delay amounts d<0> to d<n> generated by the delay circuit 511, and the first peak detection clock SHAp1 is generated. The first peak detection clock SHAp1 is output to each of the m sample-and-hold circuits 41 at different timings within one period of excitation by the energization circuit 3, and a hold signal SH based on the first peak detection clock SHAp1 is obtained.

The m hold signals SH acquired by the m sample-and-hold circuits 41 are input to the first peak detection unit 611 as digital signals obtained by AD-converting the amplified signals. The first peak detection unit 611 sequentially compares the input signals based on the hold signals SH, and when a peak timing that is the peak position is detected, the detection result including the corresponding time information (e.g., delay amount d) is stored in a memory (not shown). When the first peak detection unit 611 detects a peak timing, a second peak detection clock SHAp2 corresponding to each of the m sample-and-hold circuits 41 is generated based on a control signal including the time information.

The second peak detection clock generating unit 532 has a similar configuration to the first peak detection clock generating unit 531, and here, the second peak detection clock generating unit 532 is configured using the delay circuit 511 and multiplexer MUX1 that are common to the first peak detection clock generating unit 531. This makes it possible to generate the first peak detection clock SHAp1 and the second peak detection clock SHAp2 without changing the configuration of the control circuit 5.

The second peak detection clock generation unit 532 selects the delay amount d corresponding to the detected peak timing from the delay amounts d<0> to d<n> generated by the delay circuit 511 within one cycle of the next excitation, and generates the second peak detection clock SHAp2. The second peak detection clock generation unit 532 can output the second peak detection clock SHAp2 generated using the selected delay amount d for all m sample hold circuits 41, for example. In that case, sampling is performed at the same timing in the m sample hold circuits 41, and a hold signal SH based on the second peak detection clock SHAp2 is acquired. The second peak detection unit 612 can calculate the peak value by, for example, averaging the input signal based on the acquired m hold signals SH.

FIG. 12 shows an example in which peak detection is performed by the first peak detection unit 611 and the second peak detection unit 612 when the rising edge of the sampling clock DLLCK and the rising edge of the voltage signal Vi are at approximately the same timing, as in the above-mentioned fourth embodiment. In this case, it is possible to repeatedly detect the peak timing (peak detection period of the voltage signal Vi; first time) by the first peak detection unit 611 and further detect the peak value (peak detection period of the voltage signal Vi; second time) by the second peak detection unit 612 without detecting a voltage change.

Specifically, during the first peak detection period, 17 first peak detection clocks SHAp1<0> to SHAp1<16>, including the rising edge of the sampling clock DLLCK, are generated and output to 17 sample-and-hold circuits 41, respectively, to obtain 17 hold signals SH. Here, the peak value is detected in the hold signal SH<7> corresponding to the first peak detection clock SHAp1<7> (for example, SHA<7> shown in FIG. 12).

Therefore, during the second peak detection period, a delay amount d<7> corresponding to the peak position is selected for the next sampling clock DLLCK, and a second peak detection clock SHAp2<7> is output to all 17 sample and hold circuits 41. A signal based on the 17 hold signals SH acquired by the 17 sample and hold circuits 41 is input to the second peak detection unit 612, and the peak value is calculated in the second peak detection unit 612 as an average value, for example, by averaging.

Therefore, even if the acquired sample hold signal SH varies due to individual variations of the multiple sample hold circuits 41, it is possible to reduce the detection variation by averaging the multiple sample hold signals SH. Here, in order to improve the reliability of magnetic detection by the magnetic sensor device 1, it is necessary to increase the SNR (signal to noise ratio) and improve the magnetic resolution. In this embodiment, synchronous addition averaging is used as a method for this purpose, and 17 hold signals SH can be acquired at once, so that both noise reduction and time reduction effects are obtained, contributing to improved reliability. Note that in the second peak detection period, it is not necessary to use the same delay amount d for all of the multiple sample hold circuits 41, and for example, the second peak detection clock SHAp2 may be generated so as to include the timing corresponding to the selected delay amount d and the timing before and after it.

For example, as a modified example of this embodiment, as shown in FIG. 13, if a delay amount d<7> is selected from the peak timing in the first peak detection period, delay amounts d<6> to d<8> including those before and after the first peak detection period can be used in the second peak detection period. Specifically, a delay amount d<6> can be selected for multiple circuits including the sample-and-hold circuits 41 corresponding to the first peak detection clocks SHAp1<0> to SHAp1<1>, a delay amount d<8> can be selected for multiple circuits including the sample-and-hold circuits 41 corresponding to the first peak detection clock SHAp1<16>, and a delay amount d<7> can be selected for the remainder to generate the second peak detection clocks SHAp2<6> to SHAp2<8>.

In this way, the 17 sample-and-hold circuits 41 can be divided into multiple groups, and the delay amount d can be set for each group. As a result, even if the peak position is difficult to determine in the first peak detection due to, for example, the waveform of the voltage signal Vi or the clock interval settings, the peak value can be detected with high accuracy by averaging the sample-and-hold signals SH obtained using multiple delay amounts d.

According to this embodiment, the signal processing circuit 6 has the first peak detection unit 611 and the second peak detection unit 612, and therefore the timing of peak detection by the second peak detection unit 612 can be set using the peak timing detected by the first peak detection unit 611. Furthermore, by acquiring a plurality of synchronized sample-and-hold signals SH and performing averaging processing, it is possible to reduce noise components and improve the SNR, and it is possible to more accurately detect the peak value of the voltage signal Vi in a short period of time.
In addition, the same effects as those of the fourth embodiment can be obtained.

(Embodiment 6)
FIG. 14 is a diagram showing an example of a circuit configuration of a magnetic sensor device 1 according to a sixth embodiment, in which the voltage change detection unit 62 in the first embodiment is provided in addition to the configuration of the fifth embodiment.
FIG. 15 is a timing chart showing the operation of the magnetic sensor device 1. Prior to the peak detection process, a voltage change detection process similar to that of the first embodiment is performed.
In this embodiment, the basic configuration and basic operation of the magnetic sensor device 1 are the same as those in the fifth embodiment, and the following mainly describes the differences.

In FIG. 14, the control circuit 5 includes a first peak detection clock generating unit 531 that generates a first peak detection clock SHAp1, and a second peak detection clock generating unit 532 that generates a second peak detection clock SHAp2, as in the fifth embodiment. Furthermore, the control circuit 5 includes a voltage change detection clock generating unit 52 that generates a voltage change detection clock SHAc, as in the first embodiment.

The signal processing circuit 6 also includes a voltage change detection unit 62 similar to that of the first embodiment, and performs voltage change detection processing based on the voltage change detection clock SHAc. It also includes a first peak detection unit 611 and a second peak detection unit 612 similar to those of the fifth embodiment, and performs peak detection processing as the first peak detection clock SHAp1 and the second peak detection clock SHAp2 are output, respectively.

As shown in FIG. 15, in this embodiment, the procedure of the voltage change detection process by the voltage change detection unit 62 is the same as that of the above-mentioned embodiment 1, and the procedure of the peak detection process by the first peak detection unit 611 and the second peak detection unit 612 is the same as that of the above-mentioned embodiment 5. That is, in order to detect the timing of the rising edge of the voltage signal Vi relative to the first sampling clock DLLCK, first, the voltage change detection clock generation unit 52 generates a voltage change detection clock SHAc and outputs it to the multiple sample-and-hold circuits 41.

Specifically, 17 voltage change detection clocks SHAc<0> to SHAc<16> are generated, and 17 hold signals SH are acquired by 17 sample-and-hold circuits 41. The voltage change detection unit 62 sequentially compares signals based on the acquired 17 hold signals SH to detect voltage changes. Here, a voltage change caused by the rising edge of the voltage signal Vi is detected by a hold signal SH<3> generated by the voltage change detection clock SHAc<3> (for example, SHA<3> shown in FIG. 15). The detection result is output, for example, to the control circuit 5 and stored in a memory (not shown), and is used in the subsequent peak detection process.

In this case, the peak detection process is performed twice so that sampling begins at the same timing as the voltage change detection clock SHAc<3>. Specifically, the first peak detection clock generating unit 531 first generates 17 first peak detection clocks SHAp1<3> to SHAp1<19> for the first first peak detection process, and outputs them to the corresponding sample and hold circuits 41. As a result, 17 samples are performed for the next sampling clock DLLCK, and 17 hold signals SH are obtained.

The first peak detection unit 611 sequentially compares signals based on the acquired 17 hold signals SH and detects the timing of the peak value. Here, the peak timing is detected by the hold signal SH<8> generated by the first peak detection clock SHAp1<8> (for example, SHA<8> shown in FIG. 15). The detection result is output to the control circuit 5, for example, and stored in a memory (not shown), and is used in the second second peak detection process.

Specifically, the second peak detection clock generation unit 532 outputs the second peak detection clock SHAp2<8> to all sample and hold circuits 41 so that the second peak detection process is performed at the same timing as the first. As a result, signals based on the 17 hold signals SH acquired by the 17 sample and hold circuits 41 are input to the second peak detection unit 612, and the peak value is calculated as an average value by, for example, averaging.

Even in this case, after the voltage change detection unit 62 detects a voltage change (voltage change detection period of the voltage signal Vi), the first peak detection unit 611 detects the peak timing (peak detection period of the voltage signal Vi; first time), and the second peak detection unit 612 detects the peak value (peak detection period of the voltage signal Vi; second time). Note that the sampling intervals in the first peak detection process and the second peak detection process are the same as those in the voltage change detection process (i.e., peak detection clock interval Δt = voltage change detection clock interval Δt).

In this embodiment, when the rising timing of the sampling clock DLLCK and the voltage signal Vi differ, the voltage change process is performed in advance, and the result can be used to perform two peak detection processes. The first peak detection result is then used to obtain multiple synchronized signals for the second time and perform averaging, thereby improving the SNR and enabling more accurate peak detection.

(Seventh embodiment)
FIG. 16 is a timing chart showing the operation of the magnetic sensor device 1 according to the seventh embodiment, which differs from the sixth embodiment in the settings of the detection clock intervals in the voltage change detection process and the peak detection process.
In this embodiment, the basic configuration and basic operation of the magnetic sensor device 1 are the same as those in the sixth embodiment, and the following mainly describes the differences.

As shown in FIG. 16, in this embodiment, the signal processing circuit 6 sets the voltage change detection clock interval Δtc in the voltage change detection unit 62 to an interval different from the peak detection clock interval Δtp in the first peak detection unit 611 and the second peak detection unit 612. Specifically, similar to the above embodiment 3, the voltage change detection clock interval Δtc in the voltage change detection unit 62 is set to be longer than the peak detection clock interval Δtp in the first peak detection unit 611 and the second peak detection unit 612 (i.e., voltage change detection clock interval Δtc>peak detection clock interval Δtp).

As an example, the voltage change detection clock generating unit 52 sets the voltage change detection clock interval Δtc so that the sampling interval is about half that during peak detection processing, and generates 17 voltage change detection clocks SHAc<0> to SHAc<16>. The peak detection clock interval Δtp generated by the peak detection clock generating unit 51 can be equal to or less than that in the sixth embodiment above (i.e., Δt≧Δtp=Δtc/2).

At this time, 17 hold signals SH are obtained for the sampling clock DLLCK, and the voltage change detection unit 62 detects a voltage change in the hold signal SH<3> generated by the voltage change detection clock SHAc<3> (for example, SHA<3> shown in FIG. 16). Using this result, the first peak detection clock generation unit 531 generates 17 first peak detection clocks SHAp1<6> to SHAp1<22> so that sampling is started at the timing when the voltage change is detected for the next sampling clock DLLCK.

The first peak detection unit 611 detects peak timing from the hold signal SH acquired by the 17 sample hold circuits 41. As a result, for example, the hold signal SH<12> by the first peak detection clock SHAp1<12> (for example, SHA<12> shown in FIG. 16) is set as the peak position, and peak detection processing is performed at the same timing for the next sampling clock DLLCK. That is, the second peak detection clock generation unit 532 generates the second peak detection clock SHAp1<12> for all sample hold circuits 41, and sampling is performed at the same timing in the 17 sample hold circuits 41. Then, in the second peak detection unit 612, the signals based on the acquired 17 hold signals SH are, for example, averaged to calculate the peak value.

According to this embodiment, even if the time from the rising edge of the sampling clock DLLCK to the rising edge of the voltage signal Vi is relatively long, the voltage change detection unit 62 can reliably detect the voltage change (voltage change detection period of the voltage signal Vi). Then, after the first peak detection unit 611 detects the peak timing (peak detection period of the voltage signal Vi; first time), the second peak detection unit 612 detects the peak value (peak detection period of the voltage signal Vi; second time), thereby improving the SNR and enabling the peak value to be detected more accurately in a short time.

In the above embodiments 1 to 7, the timing of excitation of the MI element 2 by the current supply circuit 3 is described as corresponding to the rising edge of the pulse-shaped control signal MI_SW, but it can also be made to correspond to the falling edge of the control signal MI_SW. As described above, the voltage signal Vi may also be a voltage waveform having a peak on the negative side, in which case the voltage change detection unit 62 will detect a voltage change to the negative side of the voltage signal Vi.

The present invention is not limited to the above-described embodiments, and can be applied to various embodiments without departing from the spirit of the present invention.

Claims (16)

A magnetic detection element;
a current supply circuit that periodically excites the magnetic detection element;
a plurality of sample-and-hold circuits electrically connected in parallel to the magnetic detection element;
a peak detection clock generating unit that generates a peak detection clock corresponding to each of the plurality of sample hold circuits at different timings within one period of excitation by the energizing circuit, for each of the plurality of sample hold circuits;
a peak detection unit that detects a peak value or peak timing of a voltage signal output from the magnetic detection element by comparing multiple hold signals acquired by the multiple sample-and-hold circuits when the peak detection clock is output. moreover,
a voltage change detection clock generating unit that generates a voltage change detection clock corresponding to each of the plurality of sample-and-hold circuits at different timings within one period of excitation by the energizing circuit, for each of the plurality of sample-and-hold circuits;
a voltage change detection unit that detects a voltage change in the voltage signal by comparing a plurality of hold signals acquired by the plurality of sample-and-hold circuits when the voltage change detection clock is output,
The magnetic sensor device according to claim 1 , wherein the peak detection clock generating section generates the peak detection clock at a timing that is set based on a voltage change of the voltage signal. The magnetic sensor device according to claim 2, wherein the voltage change detection unit alternates between detecting a voltage change in the voltage signal and the peak detection unit alternates between detecting a peak in the voltage signal. The magnetic sensor device according to claim 2, wherein the voltage change detection unit performs a voltage change detection process on the voltage signal, and then the peak detection unit performs a peak detection process on the voltage signal multiple times. The magnetic sensor device according to any one of claims 2 to 4, wherein the voltage change detection clock interval when the voltage change detection clock is generated and the peak detection clock interval when the peak detection clock is generated are set to the same interval for each of the multiple sample-and-hold circuits. The magnetic sensor device according to any one of claims 2 to 4, wherein the peak detection clock interval when the peak detection clock is generated is set shorter than the voltage change detection clock interval when the voltage change detection clock is generated for each of the multiple sample-and-hold circuits. the peak detection clock generating unit generates the peak detection clock at a timing that is set based on an excitation timing by the energizing circuit;
5. The magnetic sensor device according to claim 1, wherein the peak detection clock generating section repeatedly performs peak detection processing of the voltage signal. The magnetic detection element includes a magnetic sensitive body and a detection coil, and an induced voltage generated in the detection coil by supplying an excitation current to the magnetic sensitive body is output as the voltage signal;
5. The magnetic sensor device according to claim 1, wherein the current supply circuit periodically supplies the excitation current to the magnetic detection element. The magnetic sensor device according to claim 8, further comprising a signal processing circuit that generates magnetic detection information based on the peak value of the voltage signal. the peak detection clock generating unit is a first peak detection clock generating unit that generates a first peak detection clock that is the peak detection clock,
the peak detection unit is a first peak detection unit that detects the peak timing,
moreover,
a second peak detection clock generating unit configured to generate second peak detection clocks corresponding to each of the plurality of sample hold circuits within a next period of excitation by the energizing circuit when the peak timing is detected by the first peak detection unit;
a second peak detection unit that, when the second peak detection clock is output, averages a plurality of hold signals acquired by the plurality of sample-and-hold circuits to detect a peak value of a voltage signal output from the magnetic detection element,
The magnetic sensor device according to claim 1 , wherein the second peak detection clock generating section generates the second peak detection clock based on the peak timing. The magnetic sensor device according to claim 10, wherein the second peak detection clock generating unit sets the timing at which the second peak detection clock corresponding to each of the plurality of sample-and-hold circuits is generated to the peak timing. The magnetic sensor device according to claim 10, wherein the second peak detection clock generating unit sets the timing at which the second peak detection clock corresponding to each of the plurality of sample-and-hold circuits is generated to include the peak timing and timings before and after the peak timing. The magnetic sensor device according to any one of claims 10 to 12, wherein the peak detection process of the voltage signal by the first peak detection unit and the peak detection process of the voltage signal by the second peak detection unit are alternately repeated. moreover,
a voltage change detection clock generating unit that generates a voltage change detection clock corresponding to each of the plurality of sample-and-hold circuits at different timings within one period of excitation by the energizing circuit, for each of the plurality of sample-and-hold circuits;
a voltage change detection unit that detects a voltage change in the voltage signal by comparing a plurality of hold signals acquired by the plurality of sample-and-hold circuits when the voltage change detection clock is output,
13. The magnetic sensor device according to claim 10, wherein the peak detection clock generating section generates the peak detection clock at a timing set based on a voltage change of the voltage signal. The magnetic sensor device according to claim 14, wherein the voltage change detection process of the voltage signal by the voltage change detection unit, the peak detection process of the voltage signal by the first peak detection unit, and the peak detection process of the voltage signal by the second peak detection unit are alternately repeated. The magnetic sensor device according to claim 15, wherein the peak detection clock interval when the peak detection clock is generated for each of the plurality of sample-and-hold circuits is set to be the same as the voltage change detection clock interval when the voltage change detection clock is generated or shorter than the voltage change detection clock interval.

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