WO2025113431A1 - Memory array, electronic device, and operation method for memory array - Google Patents

Abstract

At least one embodiment of the present disclosure provides a memory array, an electronic device, and an operation method for a memory array. The memory array comprises a plurality of non-volatile static memory storage units, a plurality of power lines, and a plurality of ground lines. The plurality of non-volatile static memory storage units are arranged into a plurality of rows and a plurality of columns and are configured to perform data storage and data backup and recovery. The plurality of power lines are configured to provide the plurality of non-volatile static memory storage units with a first power supply voltage, the plurality of power lines each being electrically connected to a corresponding column of storage units in a first direction, and the plurality of power lines being shorted in a second direction. The plurality of ground lines are configured to provide the plurality of non-volatile static memory storage units with a second power supply voltage, the plurality of ground lines each being electrically connected to a corresponding column of storage units in the first direction, and the plurality of ground lines being shorted in the second direction. According to the described memory array, when data recovery is performed in one row of storage units at the same time, the voltages of the power lines can be kept stable.

Description

Memory array, electronic device, and memory array operation method

This application claims priority to Chinese Patent Application No. 202311595782.3 filed on November 27, 2023. The contents of the above-mentioned Chinese patent application disclosure are hereby cited in their entirety as a part of this application.

Technical Field

Embodiments of the present disclosure relate to a memory array, an electronic device, and a method for operating the memory array.

Background Art

When the memory array is performing data operations, a conductive channel from the power supply to the ground may be formed in the memory cell. If the same power line in the memory array is simultaneously connected to multiple memory cells that need to perform data operations simultaneously, this may cause problems such as excessive power current and insufficient power supply capacity during data operations, which in turn may cause data operation failure.

Summary of the invention

Some embodiments of the present disclosure provide a memory array, which includes: a plurality of non-volatile static memory storage cells, arranged in a plurality of rows and columns and configured to perform data storage as well as data backup and recovery; a plurality of power lines, configured to provide a first power supply voltage to the plurality of non-volatile static memory storage cells, wherein the plurality of power lines are electrically connected to corresponding storage cell columns in a first direction, respectively, and the plurality of power lines are short-circuited in a second direction, and the first direction is different from the second direction; a plurality of ground lines, configured to provide a second power supply voltage to the plurality of non-volatile static memory storage cells, wherein the plurality of ground lines are electrically connected to corresponding storage cell columns in the first direction, respectively, and the plurality of ground lines are short-circuited in the second direction.

For example, a memory array provided in some embodiments of the present disclosure also includes: a plurality of bit lines, respectively electrically connected to the corresponding columns of the non-volatile static memory storage cells in the first direction to transmit data signals; a plurality of first control lines, respectively electrically connected to the corresponding rows of the non-volatile static memory storage cells in the second direction to transmit first control signals; and a plurality of word lines, respectively electrically connected to the corresponding rows of the non-volatile static memory storage cells in the second direction to transmit word line signals.

For example, in a memory array provided in some embodiments of the present disclosure, each of the multiple non-volatile static memory storage units includes a volatile storage sub-unit and a non-volatile storage sub-unit; the volatile storage sub-unit is configured to transfer the stored first data and/or second data to the non-volatile storage sub-unit for the data backup, or receive the third data and/or fourth data transmitted by the non-volatile storage sub-unit for the data recovery; the non-volatile storage sub-unit is configured to transfer the stored third data and/or fourth data to the volatile storage sub-unit for the data recovery, or receive the first data and/or second data transmitted by the volatile storage sub-unit for the data backup.

For example, in a memory array provided in some embodiments of the present disclosure, the non-volatile storage sub-unit includes a first non-volatile storage device, a second non-volatile storage device, a first switching transistor and a second switching transistor; the first non-volatile storage device is connected to the volatile storage sub-unit via the first switching transistor; the second non-volatile storage device is connected to the volatile storage sub-unit via the second switching transistor.

For example, in a memory array provided in some embodiments of the present disclosure, the first non-volatile memory device is configured to store the third data; the second non-volatile memory device is configured to store the fourth data; the third data and the fourth data are configured as differential signals; the first non-volatile memory device and the second non-volatile memory device are resistive memory devices or phase change memory devices or magnetoresistive memory devices. For example, in a memory array provided in some embodiments of the present disclosure, the plurality of first control lines are electrically connected to the gate of the first switch transistor and the gate of the second switch transistor of each memory cell in the corresponding non-volatile static memory cell row.

For example, in a memory array provided in some embodiments of the present disclosure, for each column of non-volatile static memory storage cells, the multiple bit lines include a first bit line and a second bit line, the first bit line is electrically connected to the first non-volatile memory device of each storage cell in each column of the non-volatile static memory storage cells, and the second bit line is electrically connected to the second non-volatile memory device of each storage cell in each column of the non-volatile static memory storage cells.

For example, in a memory array provided in some embodiments of the present disclosure, the volatile storage sub-unit is a static random access storage unit.

For example, in a memory array provided in some embodiments of the present disclosure, the static random access memory cell includes a first inverter, a second inverter, a first access transistor and a second access transistor; the first inverter and the second inverter are connected between a power line and a ground line corresponding to the non-volatile static memory storage cell; the output end of the first inverter is connected to the input end of the second inverter, and the input end of the first inverter is connected to the output end of the second inverter; the first source and drain of the first access transistor are connected to the output end of the first inverter; and the first source and drain of the second access transistor are connected to the output end of the second inverter.

For example, in a memory array provided by some embodiments of the present disclosure, for each column of non-volatile static memory storage cells, the multiple bit lines include a first bit line and a second bit line, the first bit line is electrically connected to the second source and drain of the first access transistor of each storage cell in each column of the non-volatile static memory storage cells, and the second bit line is electrically connected to the second source and drain of the second access transistor of each storage cell in each column of the non-volatile static memory storage cells.

For example, in a memory array provided in some embodiments of the present disclosure, the first inverter and the second inverter are connected between a power line and a ground line corresponding to the non-volatile static memory storage unit through a power switch component.

For example, in a memory array provided in some embodiments of the present disclosure, the power switch component includes a third switching transistor and a fourth switching transistor, the first inverter is electrically connected to the power line via the third switching transistor, and the second inverter is electrically connected to the power line via the fourth switching transistor; or, the power switch component includes a third switching transistor, and the first inverter and the second inverter are electrically connected to the power line via the third switching transistor.

For example, a memory array provided in some embodiments of the present disclosure also includes: multiple second control lines, which are electrically connected to the power switch component of each storage cell in the corresponding non-volatile static memory storage cell row in the second direction to transmit a second control signal, and the second control signal is used to control the switching state of the power switch component.

For example, in a memory array provided by some embodiments of the present disclosure, the plurality of word lines are electrically connected to the gate of the first access transistor and the gate of the second access transistor of each memory cell in the corresponding nonvolatile static memory cell row.

For example, in a memory array provided in some embodiments of the present disclosure, the plurality of word lines are also electrically connected to the corresponding power switch components to transmit a second control signal, and the second control signal is used to control the switching state of the power switch components.

For example, in a memory array provided in some embodiments of the present disclosure, the multiple power lines are short-circuited at one or both ends of the memory array in the second direction; and/or the multiple ground lines are short-circuited at one or both ends of the memory array in the second direction.

Some embodiments of the present disclosure provide an electronic device, which includes the memory array described in any of the above embodiments.

Some embodiments of the present disclosure provide a method for operating a memory array, which is used for the memory array described in any of the above embodiments, and the method includes: selecting the i-th row of non-volatile static memory storage cells in the memory array; performing data backup or data recovery on the i-th row of non-volatile static memory storage cells according to a control signal, wherein I is a positive integer.

For example, in a memory array operation method provided in some embodiments of the present disclosure, multiple rows or all non-volatile static memory storage cells in the memory array are selected; data backup or data recovery is performed on the selected multiple rows or all non-volatile static memory storage cells according to control signals in the same operation.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, but are not intended to limit the present disclosure.

FIG1 is a schematic diagram of the structure of a 6T-SRAM;

FIG2 is a schematic diagram of a combination of a volatile storage subunit and a non-volatile storage subunit;

FIG3 is a schematic diagram of a storage array provided by at least one embodiment of the present disclosure;

FIG4 is a schematic diagram of the structure of a non-volatile static RAM (NVSRAM) storage unit provided by at least one embodiment of the present disclosure;

FIG5 is a schematic diagram of an NVSRAM storage unit provided by at least one embodiment of the present disclosure;

FIG6 is a schematic diagram of another NVSRAM storage unit provided by at least one embodiment of the present disclosure;

FIG7 is a timing diagram of a data backup operation performed by an NVSRAM storage unit according to at least one embodiment of the present disclosure;

FIG8 is a timing diagram of a data recovery operation performed by an NVSRAM storage unit according to at least one embodiment of the present disclosure;

FIG9 is a schematic flow chart of a method for operating a storage array according to at least one embodiment of the present disclosure;

FIG10 is a schematic diagram of a flow chart of a SET operation and a RESET operation respectively performed when backing up data on a storage array according to at least one embodiment of the present disclosure;

FIG11 is a schematic diagram of a flow chart of simultaneously performing a SET operation and a RESET operation when backing up data on a storage array according to at least one embodiment of the present disclosure;

FIG12 is a flowchart of a method for performing data backup on a storage array by using separate row-by-row operations of RESET and SET, provided by at least one embodiment of the present disclosure;

FIG13 is a flow chart of a method for performing data backup on a storage array using separate RESET and SET full-chip operations, provided by at least one embodiment of the present disclosure;

FIG14 is a flow chart of a data backup method for performing row-by-row operations on a storage array using RESET and SET simultaneously, provided by at least one embodiment of the present disclosure; and

FIG. 15 is a flowchart illustrating a method of recovering data from a storage array according to at least one embodiment of the present disclosure.

DETAILED DESCRIPTION

In order to enable those skilled in the art to better understand the technical solution of the present disclosure, the embodiments of the present disclosure will be further described in detail in conjunction with the accompanying drawings. The specific embodiments and drawings described herein are only used to explain the present disclosure, rather than to limit the disclosed embodiments. In the absence of conflict, the various embodiments of the present disclosure and the various features in the embodiments can be combined with each other. For ease of description, the drawings of the embodiments of the present disclosure only show the parts related to the embodiments of the present disclosure, and the parts not related to the embodiments of the present disclosure are not shown in the drawings. Each unit and module involved in the embodiments of the present disclosure may correspond to only one entity structure, or may be composed of multiple entity structures, or multiple units and modules may be integrated into one entity structure. In the absence of conflict, the functions and steps marked in the flowcharts and block diagrams of the embodiments of the present disclosure may occur in an order different from that marked in the drawings. The flowcharts and block diagrams of the embodiments of the present disclosure show the possible architecture, functions and operations of the systems, devices, equipment and methods according to the embodiments of the present disclosure. Among them, each box in the flowchart or block diagram may represent a unit, module, program segment, code, which contains executable instructions for implementing the specified functions. Furthermore, each block or combination of blocks in the block diagrams and flow charts may be implemented by a hardware-based system that implements the specified functions, or may be implemented by a combination of hardware and computer instructions.

Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and similar words mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

The present disclosure is described below through several specific embodiments. In order to keep the following description of the embodiments of the present disclosure clear and concise, the detailed description of known functions and known components (elements) may be omitted. When any part (element) of the embodiments of the present disclosure appears in more than one figure, the part (element) is represented by the same or similar reference numeral in each figure.

Memory is an important part of computer structure, used to store program code, data, etc. Basic memory can be divided into volatile memory and non-volatile memory according to the characteristics of the storage medium. Volatile memory refers to memory in which the stored data will be lost after power failure, while non-volatile memory refers to memory in which the stored data will not be lost after power failure. Generally, volatile memory operates quickly, while non-volatile memory has a long storage time.

For example, the volatile memory may be DRAM (dynamic random access memory) or SRAM (static random access memory). For example, DRAM may use one transistor and one capacitor to store one bit of data, and the data stored in DRAM needs to be updated periodically; SRAM may use multiple transistors to store one bit of data, and SRAM can permanently save the stored data as long as it remains powered on.

For example, SRAM can also have multiple types, such as 6T-SRAM (i.e., six-transistor type SRAM), 7T-SRAM (i.e., seven-transistor type SRAM), 8T-SRAM (i.e., eight-transistor type SRAM) and other multi-transistor type SRAM.

FIG. 1 is a schematic diagram showing an exemplary structure of a 6T-SRAM memory cell.

As shown in FIG1 , the 6T-SRAM memory cell includes transistors P0, P1, N0, N1, N2, N3, and bit lines BL, BLN, WL, CVDD, and VSS for operating the memory cell. The memory cell has a storage node Q and a storage node QN, wherein N represents that the type of transistor is NMOS (N-Metal-Oxide-Semiconductor) transistor, and P represents that the type of transistor is PMOS (P-type metal-oxide-semiconductor) transistor. The bit lines BL and BLN are used to read and write data, and the word line WL is used to control the read and write operations. The transistors P0 and N0 form an inverter, and the transistors P1 and N1 form another inverter. The two inverters are cross-connected to provide storage nodes Q and QN. The SRAM memory cell has a bistable structure. When the storage node Q is at a high level, the storage node QN is at a low level, and the stored data can be selected as "1". Correspondingly, when the storage node Q is at a low level, the storage node QN is at a high level, and the stored data can be selected as "0". Transistor N2 and transistor N3 are controlled by the word line WL to turn on or off the storage unit.

The above SRAM storage cell can have three states: data retention, reading and writing. In the data retention state, the word line WL maintains a low level, the transistor N2 and the transistor N3 are turned off, and the two sets of inverters are isolated from the corresponding bit lines and maintain the original state.

During the read operation, assuming that the stored data is 1, the storage node Q is at a high level and the storage node QN is at a low level. The bit lines BL and BLN are first precharged to a high potential, and then the word line WL is set to a high level, so that the transistors N2 and N3 are turned on. Since the storage node QN is at a low level, the transistor P0 is turned on, and the bit line BL is connected to the power line CVDD through the transistors N2 and P0. The level of the bit line BL (high level) and the storage state of the storage node Q (high level) remain unchanged; the high level of the storage node Q turns on the transistor N1, and the bit line BLN is connected to the ground line VSS through the transistors N3 and N1. The bit line BLN discharges and the level decreases, but the storage state of the storage node QN (low level) remains unchanged. Therefore, by reading the voltage difference between the bit lines BL and BLN (the difference is positive), it can be known that the storage cell currently stores "1".

Assuming that the stored data is 0, the storage node Q is at a low level, and the storage node QN is at a high level. First, the bit line BL and the bit line BLN are pre-charged to a high potential, and then the word line WL is set to a high level, so that the transistor N2 and the transistor N3 are turned on. Since the storage node QN is at a high level, the transistor N0 is turned on, and the bit line BL is connected to the ground line VSS through the transistor N2 and the transistor N0. Then the bit line BL is discharged and the level is reduced, but the storage state of the storage node Q (low level) remains unchanged; the low level of the storage node Q turns on the transistor P1, and the bit line BLN is connected to the power line CVDD through the transistor N3 and the transistor P1. The level of the bit line BLN (high level) and the storage state of the storage node QN (high level) remain unchanged. Therefore, by reading the voltage difference between the bit lines BL and BLN (the difference is negative), it can be known that the storage cell currently stores "0".

During the write operation, the written state needs to be loaded to the bit line BL and the bit line BLN to modify the levels of the storage nodes Q and QN in the storage unit. For example, if data 1 is to be written, the storage node Q needs to be changed to a high level, and the corresponding storage node QN needs to be changed to a low level. At this time, the bit line BL is set to a high level, the bit line BLN is set to a low level, and then the word line WL is set to a high level, so that the transistors N2 and N3 are turned on, the high level of the bit line BL sets the storage node Q to a high level, and the low level of the bit line BLN sets the storage node QN to a low level, thereby turning on the transistors P0 and N1 and turning off the transistors N0 and P1, thereby the power line CVDD keeps the storage node Q at a high level through the transistor P0, and the ground line VSS keeps the storage node QN at a low level through the transistor N1, thereby realizing the writing of data 1 and the continuous storage of data 1 in the case of power failure.

For example, if data 0 is to be written, the storage node Q needs to be changed to a low level, and the storage node QN correspondingly changes to a low level. At this time, the bit line BL is set to a low level, the bit line BLN is set to a high level, and then the word line WL is set to a high level, so that the transistors N2 and N3 are turned on, the low level of the bit line BL sets the storage node Q to a low level, and the high level of the bit line BLN sets the storage node QN to a high level, thereby the transistors N0 and P1 are turned on and the transistors P0 and N1 are turned off, thereby the power line CVDD keeps the storage node QN at a high level through the transistor P1, and the ground line VSS keeps the storage node Q at a low level through the transistor N0, thereby realizing the writing of data 0 and the continuous storage of data 0 in the case of power failure.

For example, non-volatile memory can be RRAM (Resistive Random Access Memory), PRAM (Phase-Change Random Access Memory), MRAM (Magnetoresistive Random Access Memory), Flash, etc. For example, RRAM and PRAM store data by changing resistance. For example, RRAM uses the resistance of thin film materials under different applied voltage conditions to be in different resistance states - high resistance state (HRS) and low resistance state (LRS) - to achieve data storage. The external manifestations of different high and low configurations represent logical "1" and logical "0", thereby achieving data storage, and can be maintained for a long time after the power is cut off. The process of RRAM changing from high resistance state (HRS) to low resistance state (LRS) is called SET process, which can also be called setting process. The change from low configuration to high resistance state is called RESET process, which can also be called reset process.

Typically, nonvolatile memory includes a nonvolatile memory device and one or more switch transistors, where the switch transistor can be a transistor or a combination of multiple transistors that can control the on and off of current. Nonvolatile memory typically operates at a relatively slow speed and requires a relatively large operating current or voltage.

As mentioned above, SRAM (Static Random Access Memory) is a volatile memory. After power failure, data is lost. Therefore, power needs to be supplied all the time to maintain the data storage of SRAM, which consumes a lot of energy and is not conducive to low-power design of the system. On the other hand, non-volatile memory usually operates slowly and requires a large operating current or voltage. Therefore, people have proposed non-volatile static random access memory (NVSRAM), which combines the advantages of the above two types of memory, integrates non-volatile memory (NVM) with SRAM memory, and uses non-volatile memory to back up the data stored in SRAM. It can not only retain the advantages of SRAM high-speed operation, but also save data in non-volatile memory after power failure and restore data to SRAM after power-on, thereby realizing low-power design of processors. It is an ideal memory for future mobile terminals, personal computers and servers.

FIG2 is a schematic diagram of a non-volatile static random access memory storage unit (NVSRAM) obtained by combining a volatile storage subunit with a non-volatile storage subunit, wherein the volatile storage subunit is the same 6T-SRAM as shown in FIG1 , and the non-volatile storage subunit includes a resistive random access memory device (RRAM) R, a resistive random access memory device RN, a transistor N4, and a transistor N5. The non-volatile storage subunit is connected to the volatile storage subunit in a differential manner, the resistive random access memory device R is connected to the storage node Q through the transistor N4, the resistive random access memory device RN is connected to the storage node QN through the transistor N5, the gates of the transistors N4 and N5 are connected to the control line CWLN, and the switch states of the transistors N4 and N5 are controlled by the control line CWLN, for example, the state where the resistance of the resistive random access memory device R is greater than the resistance of the resistive random access memory device RN is set as data "1", and vice versa, it is set as data "0".

In other forms, the non-volatile memory sub-unit may be connected to the volatile memory sub-unit in a differential connection manner or in a single-ended connection manner, for example, only including the resistive random access memory device R and the transistor N4. In addition, in addition to using RRAM at the non-volatile memory sub-unit, a phase change random access memory (PRAM) or the like may also be used.

In current NVSRAM storage arrays, power lines are routed along the row direction and electrically connected to the storage cells in the row. The storage cells in the same row are connected to the same power line. In this case, when data is recovered from a whole row of storage cells at the same time, the total current of the power line is the sum of the power currents of the whole row of storage cells. Excessive current can easily cause insufficient power supply capacity, unstable or reduced power supply voltage, and lead to data recovery failure.

At least in view of the above problems, at least one embodiment of the present disclosure provides a memory array, including: a plurality of non-volatile static memory (NVSRAM) storage cells, a plurality of power lines, and a plurality of ground lines. The plurality of NVSRAM storage cells are arranged in a plurality of rows and columns and are configured to perform data storage and data backup and recovery; the plurality of power lines are configured to provide a first power supply voltage to the plurality of NVSRAM storage cells, wherein the plurality of power lines are electrically connected to the corresponding storage cell columns in a first direction, and the plurality of power lines are short-circuited in a second direction, and the first direction is different from the second direction; the plurality of ground lines are configured to provide a second power supply voltage to the plurality of NVSRAM storage cells, wherein the plurality of ground lines are electrically connected to the corresponding storage cell columns in a first direction, and the plurality of ground lines are short-circuited in a second direction.

In the structure of the memory array provided in the above-mentioned embodiment of the present disclosure, when data is recovered simultaneously in a row of memory cells, the current of each power line in the first direction is only the power current of one memory cell, and the current of each ground line in the first direction is only the ground current of one memory cell. Therefore, the total current on the power line and the ground line is low, the power supply voltage and the ground line voltage remain stable, and the success rate of data recovery can be improved.

FIG. 3 is a schematic diagram of a memory array provided by at least one embodiment of the present disclosure.

As shown in FIG3 , the memory array includes a plurality of NVSRAM memory cells arranged in m rows and n columns, n power lines CVDD and n ground lines VSS, each power line CVDD is electrically connected to a column of NVSRAM memory cells, and all power lines CVDD are short-circuited in the row direction, each ground line is electrically connected to a column of NVSRAM memory cells, and all ground lines VSS are short-circuited in the row direction. Therefore, when a row of memory cells is simultaneously recovering data, the current of each power line CVDD in the first direction is only the power current of one memory cell, so the total current on the power line CVDD is low, the power supply voltage remains stable, and the success rate of data recovery can be improved. For example, the first direction is the column direction, and the second direction is the row direction.

The memory array further includes a plurality of bit lines, a plurality of first control lines CWLN, and a plurality of word lines WL. The plurality of bit lines include a plurality of first bit lines BL and a plurality of second bit lines BLN, each pair of bit lines BL and BLN being electrically connected to a corresponding NVSRAM memory cell column in a first direction to transmit a data signal, which is used to control a volatile memory sub-unit and a non-volatile memory sub-unit in the NVSRAM memory cell (see below); the plurality of first control lines CWLN are electrically connected to a corresponding NVSRAM memory cell row in a second direction to transmit a first control signal, for example, the first control signal is used to control a non-volatile memory sub-unit in the NVSRAM memory cell (see below); the plurality of word lines WL are electrically connected to a corresponding NVSRAM memory cell row in a second direction to transmit a word line signal, which is used to control a volatile memory sub-unit in the NVSRAM memory cell (see below).

In Figure 3, WLi represents the i-th word line, for example, WL1 represents the 1st word line; CWLNi represents the i-th first control line, for example, CWLN1 represents the 1st first control line; BLi and BLNi represent the i-th first bit line and the i-th second bit line, for example, BL1 and BLN1 represent the 1st first bit line and the 1st second bit line, respectively; NVSRAMij represents the i-th row and j-th column NVSRAM storage cell, for example, NVSRAM11 represents the 1st row and 1st column NVSRAM storage cell, wherein i and j are positive integers, 1≤i≤m, 1≤j≤n; in the memory array, by controlling the voltages on the first bit line BL, the second bit line BLN, the first control line CWLN and the word line WL, the control of the state of each device on the NVSRAM storage cell can be achieved.

In this embodiment, a plurality of power lines CVDD may be short-circuited at one or both ends of the memory array in the row direction, and a plurality of ground lines VSS may be short-circuited at one or both ends of the memory array in the row direction. Short-circuiting the power line CVDD and the ground line VSS at both ends of the memory array can prevent data backup and recovery failure of the memory array when a line used for shorting at one end fails.

For example, FIG4 is a schematic diagram of the structure of an NVSRAM storage unit according to at least one embodiment of the present disclosure. As shown in FIG4, in one example, each of the multiple NVSRAM storage units includes a volatile storage subunit and a non-volatile storage subunit; the volatile storage subunit is configured to transfer the stored first data and/or second data to the non-volatile storage subunit for data backup, or receive the third data and/or fourth data transmitted by the non-volatile storage subunit for data recovery; the non-volatile storage subunit is configured to transfer the stored third data and/or fourth data to the volatile storage subunit for data recovery, or receive the first data and/or second data transmitted by the volatile storage subunit for data backup.

For example, the third data and/or the fourth data may be the first data and/or the second data in the volatile memory device obtained by the nonvolatile memory device through data backup, or may be data inherent in the nonvolatile memory device or data stored in the nonvolatile memory device by other means.

For example, in one example, the volatile storage sub-unit is a static random access memory (SRAM) unit, and the SRAM unit may be a 6T-SRAM, a 7T-SRAM, or other SRAM structures capable of implementing a static random access memory function.

For example, in one example, the non-volatile memory sub-cell may include an RRAM and a switch transistor, wherein the RRAM is electrically connected to the volatile memory sub-cell through the switch transistor.

For example, FIG5 is a schematic diagram of an NVSRAM storage unit provided by at least one embodiment of the present disclosure.

As shown in Figure 5, the non-volatile storage sub-unit of the NVSRAM storage unit includes a first non-volatile storage device R, a second non-volatile storage device RN, a first switching transistor N4 and a second switching transistor N5; the first non-volatile storage device R is connected to the volatile storage sub-unit via the first switching transistor N4; the second non-volatile storage device RN is connected to the volatile storage sub-unit via the second switching transistor N5.

The static random access memory cell of the NVSRAM memory cell includes a first inverter V1, a second inverter V2, a first access transistor N2 and a second access transistor N3; the first inverter V1 and the second inverter V2 are connected between a power line CVDD and a ground line VSS corresponding to the NVSRAM memory cell; the output end of the first inverter V1 is connected to the input end of the second inverter V2, and the input end of the first inverter V1 is connected to the output end of the second inverter V2; the first access transistor N2 is connected to the output end of the first inverter V1; and the second access transistor N3 is connected to the output end of the second inverter V2.

For example, the static random access memory cell is a 6T-SRAM, and the first inverter V1 and the second inverter V2 are connected between a power line CVDD and a ground line VSS corresponding to the NVSRAM memory cell through a power switch component.

The power switch assembly includes a third switch transistor P2 and a fourth switch transistor P3. The first inverter V1 is electrically connected to the power line CVDD via the third switch transistor P2. The second inverter V2 is electrically connected to the power line CVDD via the fourth switch transistor P3.

The first inverter V1 includes a transistor P0 and a transistor N0, the second inverter V2 includes a transistor P1 and a transistor N1, the gate of the third switch transistor P2 is connected to the gate of the fourth switch transistor P3, and is connected to the second control line RECP, the source of the third switch transistor P2 and the fourth switch transistor P3 is connected to the power line CVDD, the drain of the third switch transistor P2 is connected to the source of the transistor P0, and the drain of the fourth switch transistor P3 is connected to the drain of the transistor P1; the second control line RECP is connected to the gate of the transistor in the power switch component, and can be connected to the word line WL at the same time, and can also provide voltage to the power switch component alone.

The storage nodes of the 6T-SRAM include storage nodes Q and QN, and the voltages of the storage nodes Q and QN can be read to obtain the first data and/or the second data stored in the static random access memory cell. For example, the first data is stored in the storage node Q, and the second data is stored in the storage node QN; for example, assuming that the stored data is 1, the storage node Q is at a high level, and the storage node QN is at a low level. The bit line BL and the bit line BLN are first precharged to a high potential, and then the word line WL is set to a high level, so that the transistor N2 and the transistor N3 are turned on. Since the storage node QN is at a low level, the transistor P0 is turned on, and the bit line BL is connected to the power line CVDD through the transistor N2 and the transistor P0, and the level of the bit line BL (high level) and the storage state of the storage node Q (high level) remain unchanged; the high level of the storage node Q turns on the transistor N1, and the bit line BLN is connected to the ground line VSS through the transistor N3 and the transistor N1, and the bit line BLN is discharged, and the level is reduced, but the storage state of the storage node QN (low level) remains unchanged. Therefore, by reading the voltage difference between the bit lines BL and BLN (the difference is positive), it can be known that the memory cell currently stores "1".

Since the SRAM cell is a bistable structure, the storage nodes Q and QN are mutually clamped, so their levels are not easy to change, which also leads to a low success rate of data recovery under power. By changing the switching state of the power switch component, the conductive channel between the volatile storage sub-unit and the power line can be closed during data recovery, so that the timing of power off and power on can be freely controlled during data recovery, thereby improving the success rate of data recovery.

In the above 6T-SRAM, the gate of transistor P0 and the gate of transistor N0 are connected to serve as the input of the first inverter V1, the gate of transistor P1 and the gate of transistor N1 are connected to serve as the input of the second inverter V2, the drain of transistor P0 and the drain of transistor N0 are respectively connected to the storage node Q to serve as the output of the first inverter V1, the drain of transistor P1 and the drain of transistor N1 are respectively connected to the storage node QN to serve as the output of the second inverter V2. The source of the first access transistor N2 is connected to the storage node Q, and the source of the second access transistor is connected to the storage node QN.

For example, the first non-volatile memory device R and the second non-volatile memory device RN can be configured to be connected to the storage node of the volatile memory subunit in a single-ended or differential connection mode. As described above, for example, the first non-volatile memory device R and the second non-volatile memory device RN can be a resistive memory device, or a non-volatile memory device such as a phase change memory device, a magnetoresistive memory device, etc. having a variable resistance property. For example, each resistive random access memory device includes a resistive memory layer sandwiched between two electrodes (for example, an upper electrode and a lower electrode), and the resistance of the resistive memory layer is changed by applying an operating voltage to the two electrodes.

For example, the first nonvolatile memory device R and the second nonvolatile memory device RN are resistive random access memory devices, and the first nonvolatile memory device R stores third data, the second nonvolatile memory device RN stores fourth data, and the third data and the fourth data are configured as differential signals. The lower electrode of the memory device R is connected to the drain of the first switch transistor N4, the lower electrode of the memory device RN is connected to the drain of the second switch transistor N5, the source of the first switch transistor N4 is connected to the storage node Q, and the source of the second switch transistor N5 is connected to the storage node QN.

For example, when the voltage difference between the two ends of the first nonvolatile memory device R or the second nonvolatile memory device RN is greater than the operation threshold voltage of the first nonvolatile memory device R or the second nonvolatile memory device RN, the resistance state of the first nonvolatile memory device R or the second nonvolatile memory device RN is changed according to whether the voltage between the two ends of the first nonvolatile memory device R and the second nonvolatile memory device RN is a set voltage or a reset voltage. For example, the set voltage is a forward voltage, that is, the voltage of the first nonvolatile memory device R or the second nonvolatile memory device RN close to the bit line is greater than the voltage of the end close to the storage node; the reset voltage is a reverse voltage, that is, the voltage of the first nonvolatile memory device R or the second nonvolatile memory device RN close to the bit line is less than the voltage of the end close to the storage node. When the voltage across the first nonvolatile memory device R or the second nonvolatile memory device RN is a reset voltage to perform a RESET operation, the first nonvolatile memory device R or the second nonvolatile memory device RN turns to a high resistance state; when the voltage across the first nonvolatile memory device R or the second nonvolatile memory device RN is a set voltage to perform a SET operation, the first nonvolatile memory device R or the second nonvolatile memory device RN turns to a low resistance state; when the voltage difference across the first nonvolatile memory device R or the second nonvolatile memory device RN is 0 or less than the operation threshold voltage, the resistance state of the first nonvolatile memory device R or the second nonvolatile memory device RN does not change, and the resistive memory stores data in the form of a resistance state.

When the forward voltage difference between the upper and lower electrodes of the storage device R or RN is large, R or RN turns into a low resistance state; when the reverse voltage difference between the upper and lower electrodes of the storage device R or RN is large, R or RN turns into a high resistance state; when the voltage difference between the upper and lower electrodes of the storage device R or RN is 0 or less than the operating threshold voltage, the resistance state of the storage device R or RN does not change, and the resistive memory stores data in the form of a resistance state.

For example, in one example, a plurality of first control lines CWLN are electrically connected to the first switch transistor N4 and the second switch transistor N5 of each storage cell in the corresponding NVSRAM storage cell row. The first control line CWLN is connected to the gate of the first switch transistor N4 and the gate of the second switch transistor N5. By controlling the voltage of the first control line CWLN, the switch state of the first switch transistor N4 and the second switch transistor N5 can be controlled. When the voltage of the first control line CWLN meets the conduction condition of the first switch transistor N4 and the second switch transistor N5, the first switch transistor N4 and the second switch transistor N5 are in the open state, otherwise, the first switch transistor N4 and the second switch transistor N5 are closed. When the first switch transistor N4 and the second switch transistor N5 are in the open state, the connection between the storage node and the non-volatile storage device can be realized, for example, the first data and/or the second data stored in the storage node can be transferred to the non-volatile storage sub-unit, or the third data and/or the fourth data in the non-volatile storage sub-unit can be transferred to the storage node.

For example, in one example, for each column of NVSRAM memory cells, the first bit line BL is electrically connected to the first access transistor N2 of each memory cell in each column of NVSRAM memory cells, and the second bit line BLN is electrically connected to the second access transistor N3 of each memory cell in each column of NVSRAM memory cells. In addition, the first bit line BL is electrically connected to the first non-volatile memory device R of each memory cell in each column of NVSRAM memory cells, and the second bit line BLN is electrically connected to the second non-volatile memory device RN of each memory cell in each column of NVSRAM memory cells. Thus, the bit lines BL and BLN can be used to operate both SRAM memory cells and non-volatile memory devices.

For example, in one example, a plurality of word lines WL are electrically connected to the first access transistor N2 and the second access transistor N3 of each memory cell in the corresponding NVSRAM memory cell row. The word line WL is connected to the gates of the first access transistor N2 and the second access transistor N3, and the conduction state of the first access transistor N2 and the second access transistor N3 can be controlled by controlling the voltage of the word line WL. When the word line WL voltage meets the conduction condition of the first access transistor N2 and the second access transistor N3, the first access transistor N2 and the second access transistor N3 are turned on, otherwise, the first access transistor N2 and the second access transistor N3 are not turned on.

FIG. 6 is a schematic diagram of another NVSRAM storage cell according to at least one embodiment of the present disclosure.

Compared with FIG5 , the power switch component of the NVSRAM storage unit shown in FIG6 includes a third switch transistor P2, the first inverter V1 and the second inverter V2 are electrically connected to the power line via the third switch transistor P2, and the connection method of the remaining devices is the same as that of the NVSRAM storage unit shown in FIG5 . At this time, the source of the third switch transistor P2 is connected to the power line CVDD, the drain is connected to the source of the transistor P0 and the transistor P1, and the gate is connected to the second control line RECP, and the second control line RECP is used to transmit a second control signal to control the switching state of the third switch transistor P2.

The memory array formed by arranging the NVSRAM memory cells shown in FIG6 further includes a plurality of second control lines RECP, which are electrically connected to the power switch components of each memory cell in the corresponding NVSRAM memory cell row in the second direction to transmit a second control signal. The second control line RECP is connected to the gate of the transistor in the power switch component, and can be connected to the word line WL at the same time, or can provide voltage to the power switch component alone.

The process of performing data backup and data recovery for the NVSRAM storage unit shown in FIG. 5 can be as follows:

The data backup operation is divided into SET and RESET operations on the non-volatile storage device: one of the non-volatile storage devices is selected to perform a SET operation and the other to perform a RESET operation according to the data of the storage node in the volatile storage subunit.

For example, the data stored in the volatile storage subunit is 0. At this time, the storage node Q is at a low level, and the storage node QN is at a high level. At this time, the non-volatile storage device R is SET operated, and the non-volatile storage device RN is RESET operated.

FIG. 7 is a timing diagram of the data backup operation performed by the NVSRAM storage unit shown in FIG. 5 .

When performing a SET operation (right side of the figure), the voltage of the power line CVDD is set to the voltage VDD, the voltage of the word line WL is set to VSS, the voltage of the first control line CWLN is set to the voltage VDD, and the voltages of the first bit line BL and the second bit line BLN are set to the voltage VSET (i.e., the voltage for performing a SET operation). At this time, the storage node Q is at a low level (i.e., VSS), and the first switch transistor N4 is turned on, the voltage difference VR across the non-volatile memory device R is VSET and is greater than the SET operation threshold voltage, so the SET operation is performed on the non-volatile memory device R, turning it into a low resistance state; the storage node QN is at a high level (i.e., VDD), the second switch transistor N5 is turned off, and the voltage difference VR across the non-volatile memory device RN is 0, so the non-volatile memory device RN is not operated, and its resistance value remains unchanged.

When performing a RESET operation (left side of the figure), the voltage of the power line CVDD is set to VRST (i.e., the voltage for performing a RESET operation), the voltage of the word line WL is set to VSS, the voltage of the first control line CWLN is set to voltage VDDH, and the voltages of the first bit line BL and the second bit line BLN are set to voltage VSS, wherein voltage VDDH is higher than or equal to voltage VDD. At this time, the storage node Q is at a low level (i.e., VSS), the first switch transistor N4 is turned on, the voltage difference VR across the non-volatile memory device R is 0, and the resistance state of the non-volatile memory device R does not change; the storage node QN is at a high level (i.e., VRST), the second switch transistor N5 is turned on, and the voltage difference VR across the non-volatile memory device RN is a lower value between VRST and VDDH-VTN, wherein VTN is the threshold voltage of the second switch transistor N5; by presetting VRST and VDDH, VRST and VDDH-VTN are both greater than the reverse threshold voltage required for the RESET operation, and at this time, the RESET operation is performed on the non-volatile memory device RN to change it to a high resistance state.

The process of performing data backup and data recovery by the NVSRAM storage unit shown in FIG. 6 is the same as the process of performing data backup by the NVSRAM storage unit shown in FIG. 5 , and will not be described in detail here.

FIG. 8 is a timing diagram of a data recovery operation performed by the NVSRAM storage unit shown in FIG. 5 .

The data recovery operation restores the data stored in the non-volatile memory devices R and RN (in a differential manner) to the SRAM device, restores the storage nodes corresponding to the high-resistance side of the non-volatile memory devices R and RN to a high level, and restores the storage nodes corresponding to the low-resistance side to a low level.

The data recovery operation of the NVSRAM storage unit shown in Figure 5 is divided into the following three stages:

Phase 1: Set the voltage of the power line CVDD to voltage VDD, the voltage of the word line WL to voltage VDD, the voltage of the first control line CWLN to voltage VDD, the voltage of the first bit line BL and the second bit line BLN to voltage VSS. At this time, the third switch transistor P2 and the fourth switch transistor P3 are turned off, cutting off the power supply of the SRAM memory cell, thereby destroying the bistable state of the SRAM memory cell, and the voltage of the storage node Q is discharged to voltage VSS through the first switch transistor N4 and transistor N2, and the voltage of the storage node QN is discharged to voltage VSS through the second switch transistor N5 and transistor N3.

The second stage: the voltage of the power line CVDD is set to the voltage VDD, the voltage of the word line WL is set to the voltage VSS, the voltage of the first control line CWLN is set to the voltage VDD, and the voltage of the first bit line BL and the second bit line BLN is set to the voltage VSS. At this time, the first switch transistor N4 and the second switch transistor N5 and the third switch transistor P2 and the fourth switch transistor P3 are all in the on state, and a conduction path is formed from the power line CVDD through the third switch transistor P2, the transistor P0, the transistor N4, the first non-volatile memory device R to the first bit line BL, and a conduction path is formed from the power line CVDD through the fourth switch transistor P3, transistor P1, the second switching transistor N5, the second non-volatile memory device RN to the second bit line BLN form a conduction path, the circuit generates current, and the voltage of the storage nodes Q and QN increases. Since the resistance values of the non-volatile memory devices on both sides are different, the voltage on the high-resistance side increases faster and the voltage on the low-resistance side increases slower, and a voltage difference ΔVQ is generated between the storage nodes Q and QN. The positive feedback effect of the cross-coupled inverter in the volatile storage sub-unit is amplified, and the voltage of the storage nodes Q and QN is pulled to VDD and VSS, and the data is restored from the non-volatile storage sub-unit to the SRAM storage unit.

In the third stage, the power line CVDD voltage is set to voltage VDD, the word line WL voltage is set to voltage VSS, the first control line CWLN voltage is set to voltage VSS, the first bit line BL and the second bit line BLN voltage are set to voltage VDD, the first switch transistor N4 and the second switch transistor N5 are turned off, the first access transistor N2 and the second access transistor N3 are turned off, and the data recovery operation is completed.

The timing diagram of the data recovery operation of the NVSRAM storage unit shown in FIG6 is the same as FIG8 . The data recovery operation of the NVSRAM storage unit shown in FIG6 is divided into the following three stages:

Phase 1: Set the voltage of the power line CVDD to voltage VDD, the voltage of the word line WL to voltage VDD, the voltage of the first control line CWLN to voltage VDD, the voltage of the first bit line BL and the second bit line BLN to voltage VSS. At this time, the third switch transistor P2 is turned off, cutting off the power supply of the volatile storage sub-unit, destroying the bistable state of the SRAM storage unit, and the voltage of the storage node Q is discharged to voltage VSS through the first switch transistor N4 and transistor N2, and the voltage of the storage node QN is discharged to voltage VSS through the second switch transistor N5 and transistor N3.

The second stage: the voltage of the power line CVDD is set to the voltage VDD, the voltage of the word line WL is set to the voltage VSS, the voltage of the first control line CWLN is set to the voltage VDD, the voltage of the first bit line BL and the second bit line BLN is set to the voltage VSS, at this time, the first switch transistor N4, the second switch transistor N5 and the third switch transistor P2 are in the on state, and a conduction path is formed from the power line CVDD through the third switch transistor P2, the transistor P0, the transistor N4, the first non-volatile memory device R to the first bit line BL, and a conduction path is formed from the power line CVDD through the third switch transistor P2, the transistor P0, the transistor N4, the first non-volatile memory device R to the first bit line BL. A conduction path is formed from the body transistor P1, the second switch transistor N5, the second non-volatile memory device RN to the second bit line BLN, and the voltages of the storage nodes Q and QN increase. Due to the different resistance values of the non-volatile memory devices on both sides, the voltage on the high-resistance side increases faster, and the voltage on the low-resistance side increases slower, and a voltage difference ΔVQ is generated between the storage nodes Q and QN. The positive feedback effect of the cross-coupled inverter in the volatile memory sub-unit is amplified, and the voltages of the storage nodes Q and QN are pulled to voltages VDD and VSS, respectively, and the data is restored from the non-volatile memory sub-unit to the volatile memory sub-unit.

In the third stage, the power line CVDD voltage is set to voltage VDD, the word line WL voltage is set to voltage VSS, the first control line CWLN voltage is set to voltage VSS, the first bit line BL and the second bit line BLN voltage are set to voltage VDD, the first switch transistor N4 and the second switch transistor N5 are turned off, the first access transistor N2 and the second access transistor N3 are turned off, and the data recovery operation is completed.

Since the SRAM memory cell has a bistable structure, during the data recovery operation, if the connection between the SRAM memory cell and the power line is not cut off, a small voltage difference will make it difficult to change the storage state of the SRAM memory cell. By cutting off the power supply of the volatile storage sub-cell through the power switch component and destroying the bistable storage state of the SRAM, the success rate of data recovery can be improved.

At least one embodiment of the present disclosure further provides an electronic device, which includes any storage array described in any of the above embodiments. The electronic device can be, for example, any product or component including the storage array or used in conjunction with the storage array, such as a storage device or a computer. The technical effects of the electronic device can refer to the technical effects of the storage array described in the above embodiments, which will not be repeated here.

At least one embodiment of the present disclosure provides a method for operating a storage array, which can be used for the storage array of any of the above embodiments. Taking the storage array shown in FIG3 as an example, the NVSRAM storage unit in the storage array is shown in FIG5.

FIG. 9 is a flow chart of a method for operating a storage array provided by at least one embodiment of the present disclosure.

As shown in FIG9 , the operation method of the storage array includes the following steps:

Step S101: Select the i-th row of NVSRAM storage cells in the memory array.

Step S102: the NVSRAM storage units in the i-th row perform data backup or data recovery according to the control signal, where i is a positive integer, 1≤i≤m.

In the above embodiment, the data read and write operations of the memory array with m rows and n columns as shown in FIG. 3 are consistent with the data read and write operations of the memory array based on the SRAM memory cell of FIG. 1 , and will not be described in detail.

For example, the i-th row to the (i+k-1)-th row may be selected to perform operations simultaneously, where i and k are positive integers, 1≤i≤m, 1≤k≤m and 1≤(i+k-1)≤m. When k=1, one row is selected for data backup or data recovery operations; when 1<k<m, multiple rows are selected for data backup or data recovery operations simultaneously; when i=1 and k=m, all rows of the m-row array are simultaneously backed up or restored.

In the embodiments of the present disclosure, for example, a data backup operation may be performed with a word as the smallest unit, or may be performed with a row as the smallest unit; for example, a data recovery operation may be performed with a row as the smallest unit. Performing an operation with a word as the smallest unit means that each time an operation is performed on a non-volatile storage sub-unit, all non-volatile storage sub-units in a selected word or multiple words are operated at the same time. Performing an operation with a row as the smallest unit means that each time an operation is performed on a non-volatile storage sub-unit, all non-volatile storage sub-units in a selected row or multiple rows of storage units are operated at the same time. Taking the operation with a row as the smallest unit as an example, the operation method of data backup and data recovery is introduced.

In the operation method of the memory array of at least one embodiment of the present disclosure, for example, multiple rows or all non-volatile static memory storage units in the memory array are selected sequentially or simultaneously; then data backup or data recovery is performed on the selected multiple rows or all non-volatile static memory storage units according to control signals in the same operation, for example, the same operation is an operation step performed according to the same control signal. When performing the data backup operation, there are two data backup operation methods according to whether the SET operation and the RESET operation are performed simultaneously:

The first method is a two-step data backup operation method, that is, the SET operation and RESET operation in the data backup operation are divided into two steps. There is no requirement for the operation order of the SET operation or the RESET operation. The RESET operation can be performed first and then the SET operation, or the SET operation can be performed first and then the RESET operation.

FIG. 10 is a schematic diagram of a flow chart of performing a dual-step data backup operation on a storage array according to at least one embodiment of the present disclosure.

As shown in FIG10 , the unit operation steps of performing a RESET operation first and then a SET operation are as follows:

Step S001: Perform RESET operation on all selected cells;

Step S002: Perform SET operation on all selected cells.

The double-step data backup operation method does not require additional data reading control or other external data interaction control, has a simple circuit structure, and is easy and convenient to operate. The operation method can perform data backup operations with words as the smallest unit, or with rows as the smallest unit, and can perform data backup operations on multiple rows or all rows of the entire array at the same time.

FIG. 11 is a schematic diagram of a process of performing a single-step data backup operation on a storage array according to at least one embodiment of the present disclosure. In the process, a SET operation and a RESET operation are performed simultaneously.

As shown in FIG. 11 , the second method is a single-step data backup operation method, and the steps are as follows:

Step S011: reading the data stored in the SRAM of the selected unit;

Step S012: setting the bit line according to the read data to output a corresponding voltage;

The bit line voltage on the side corresponding to the storage node "0" is VSET, and the bit line voltage on the side corresponding to the storage node "1" is 0;

Step S013: all selected cells perform RESET operation and SET operation simultaneously.

In the above embodiment, when performing a single-step data backup operation on the NVSRAM storage unit, the data of the storage nodes in the SRAM of all selected NVSRAM storage units are read; then the bit lines are set according to the read data to output corresponding voltages respectively, the voltage of the bit line corresponding to the low potential side of the storage node is set to VSET, and the voltage of the bit line corresponding to the high potential side of the storage node is set to 0; then, the bit lines BL and BLN output corresponding voltages, and all selected units perform RESET and SET operations at the same time; the non-volatile memory device on the side of the storage node with a low potential performs a SET operation, and the non-volatile memory device on the side of the storage node with a high potential performs a RESET operation. The SET and RESET operations are performed simultaneously, which can improve the operation speed of the array. The single-step data backup operation method can perform data backup operations with words as the minimum unit, or it can perform data backup operations with rows, but when operating with rows, data backup operations can be performed on at most one row at a time.

For a two-step data backup operation or a data recovery operation, the row operation timing of the storage array can be divided into two methods according to the difference in the row operation timing.

Mode 1 is a row-by-row operation, wherein, during array operation, after completing a single operation on all cells in the currently selected row or rows of the array, a single operation is performed on the next row or rows. A single operation may include a data backup operation or a data recovery operation, and during the data backup operation and the data recovery operation, the sequence number (i) or the number of rows (k) of the selected row may be the same or different.

Method 2 is a full-film operation, in which the first step is first performed on the entire film in a row-by-row operation mode, and then the second step is performed on the entire film in a row-by-row operation mode.

For a single-step data backup operation, the row operation sequence of the storage array adopts a row-by-row operation, and at most only one row of storage cells is selected at a time for the data backup operation.

FIG. 12 is a flow chart of at least one embodiment of the present disclosure of a dual-step data backup operation on a storage array using a row-by-row operation method.

As shown in FIG12 , the steps of the operation method are as follows:

The first step is to select rows from i to i+k-1;

The second step is to perform RESET operation on the selected k rows at the same time;

The third step is to perform SET operations on the selected k rows simultaneously;

The fourth step is to determine whether all data has been backed up. If not, update i to equal i plus k and return to the first step; if yes, end this process.

Wherein, i and k are positive integers, 1≤i≤m, 1≤k≤m and 1≤(i+k-1)≤m. When k=1, select 1 row for data backup or data recovery operation; when 1<k<m, select multiple rows for data backup or data recovery operation at the same time; when i=1 and k=m, perform data backup or data recovery operation on all rows of the m-row array at the same time. In actual operation, the value 1 is usually selected when i is initialized, that is, the operation starts from the first row of the array, and it can also be not 1, that is, the operation starts from any row in the array; when the data backup operation is performed on the mth row, the whole process ends. When this operation method performs data backup, no additional data reading control and other external data interaction controls are required, the circuit structure is simple, does not occupy the data bus, and the operation is simple and convenient.

13 is a flowchart of a method for performing data backup on a storage array using separate full-chip operations of RESET and SET according to at least one embodiment of the present disclosure.

As shown in FIG13 , the steps of the operation method are as follows:

The first step is to select rows from i to i+k-1;

The second step is to perform RESET operation on the selected k rows at the same time;

Step 3: Check whether all rows have been reset. If so, proceed to step 4. Otherwise, update i to equal i plus k and return to step 1.

Step 4: Select rows from x to x+y-1;

Step 5: Perform SET operation on the selected y rows at the same time;

Step 6: Determine whether all rows have been SET. If so, the data backup operation ends. Otherwise, update x to equal x plus y and return to step 4.

Wherein, i and k are positive integers, 1≤i≤m, 1≤k≤m and 1≤(i+k-1)≤m; x and y are positive integers, 1≤x≤m, 1≤y≤m and 1≤(x+y-1)≤m; wherein i and x can be the same or different; k and y can be the same or different. In this operation method, since the SET and RESET operations are all performed on the whole chip, the voltage conversion of the power line CVDD, the first bit line BL, and the second bit line BLN is only performed once after the SET or RESET operation of the entire array is completed, which reduces the frequency of voltage conversion and reduces the dynamic power consumption of the circuit.

FIG. 14 is a flow chart of a single-step data backup operation on a storage array using a row-by-row operation method according to at least one embodiment of the present disclosure.

As shown in FIG. 14 , the steps of the data backup method are as follows:

The first step is to select the i-th row;

The second step is to read the i-th row of data;

The third step is to encode the bit lines according to the read data;

Step 4: Perform RESET and SET operations on the selected i-th row at the same time;

The fifth step is to determine whether the data backup is completed. If so, the data backup operation is completed, i is increased by 1, and the process returns to the first step.

When backing up data using the single-step data backup operation method, the RESET operation and the SET operation are performed simultaneously, thereby increasing the speed of data backup.

For example, in the above embodiment, the data recovery operation adopts a row-by-row operation method.

FIG15 is a flow chart of a method for recovering data from a storage array according to at least one embodiment of the present disclosure. As shown in FIG15 , the steps of the data recovery method are as follows:

The first step is to select rows from i to i+k-1;

The second step is to perform data recovery operations on the selected k rows simultaneously;

The third step is to determine whether the data recovery is complete. If not, update i to be equal to i+k and return to the first step; if yes, end the data recovery operation.

At least one embodiment of the present disclosure provides a storage array, an electronic device, and an operation method of the storage array. The power lines of all NVSRAM storage cells in the same column are connected and routed along the column direction of the array. The power lines of all columns are short-circuited along the row direction of the array. When a whole row of storage cells is simultaneously recovering data, the current of each power line in the column direction is only the power current of one NVSRAM storage cell. Therefore, the total current on the power line is reduced, the power voltage remains stable, and the data recovery success rate can be improved.

It is to be understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of the present disclosure, but the present disclosure is not limited thereto. For those of ordinary skill in the art, various modifications and improvements can be made without departing from the spirit and substance of the present disclosure, and these modifications and improvements are also considered to be within the scope of protection of the present disclosure.

Claims (19)

A memory array comprising: a plurality of non-volatile static memory storage cells arranged in a plurality of rows and columns and configured to perform data storage and data backup and recovery; A plurality of power lines configured to provide a first power supply voltage to the plurality of nonvolatile static memory storage cells, wherein the plurality of power lines are electrically connected to corresponding storage cell columns in a first direction, respectively, and the plurality of power lines are short-circuited in a second direction, and the first direction is different from the second direction; A plurality of ground lines are configured to provide a second power supply voltage to the plurality of nonvolatile static memory storage cells, wherein the plurality of ground lines are electrically connected to corresponding storage cell columns in the first direction respectively, and the plurality of ground lines are short-circuited in the second direction. The memory array according to claim 1, further comprising: a plurality of bit lines, respectively electrically connected to corresponding columns of storage cells of the nonvolatile static memory in the first direction to transmit data signals; a plurality of first control lines, respectively electrically connected to corresponding rows of the nonvolatile static memory cells in the second direction to transmit a first control signal; A plurality of word lines are electrically connected to corresponding nonvolatile static memory storage unit rows in the second direction to transmit word line signals. The memory array according to claim 2, wherein each of the plurality of non-volatile static memory storage cells comprises a volatile storage sub-cell and a non-volatile storage sub-cell; The volatile storage subunit is configured to transfer the stored first data and/or second data to the non-volatile storage subunit to perform the data backup, or receive the third data and/or fourth data transmitted by the non-volatile storage subunit to perform the data recovery; The non-volatile storage subunit is configured to transfer the stored third data and/or fourth data to the volatile storage subunit for data recovery, or receive the first data and/or second data transmitted by the volatile storage subunit for data backup. The memory array according to claim 3, wherein the nonvolatile memory subunit comprises a first nonvolatile memory device, a second nonvolatile memory device, a first switch transistor, and a second switch transistor; The first non-volatile memory device is connected to the volatile memory subunit via the first switch transistor; The second non-volatile memory device is connected to the volatile memory sub-unit via the second switch transistor. The memory array according to claim 4, wherein the first non-volatile memory device is configured to store the third data; The second non-volatile memory device is configured to store the fourth data; The third data and the fourth data are configured as differential signals; The first nonvolatile memory device and the second nonvolatile memory device are resistive memory devices, phase change memory devices, or magnetoresistive memory devices. The memory array according to claim 4 or 5, wherein the plurality of first control lines are electrically connected to the gate of the first switch transistor and the gate of the second switch transistor of each memory cell in the corresponding row of the nonvolatile static memory cells. The memory array according to any one of claims 4 to 6, wherein for each column of non-volatile static memory storage cells, the plurality of bit lines comprises a first bit line and a second bit line, The first bit line is electrically connected to the first non-volatile memory device of each memory cell in each column of the non-volatile static memory memory cells. The second bit line is electrically connected to the second non-volatile memory device of each memory cell in each column of the non-volatile static memory memory cells. The memory array according to any one of claims 3 to 7, wherein the volatile storage sub-unit is a static random access storage unit. The memory array according to claim 8, wherein the static random access memory cell comprises a first inverter, a second inverter, a first access transistor, and a second access transistor; The first inverter and the second inverter are connected between a power line and a ground line corresponding to the non-volatile static memory storage unit; The output end of the first inverter is connected to the input end of the second inverter, and the input end of the first inverter is connected to the output end of the second inverter; A first source and drain of the first access transistor are connected to an output terminal of the first inverter; A first source and a drain of the second access transistor are connected to an output terminal of the second inverter. The memory array of claim 9, wherein for each column of nonvolatile static memory cells, the plurality of bit lines comprises a first bit line and a second bit line, The first bit line is electrically connected to the second source and drain of the first access transistor of each memory cell in each column of the non-volatile static memory memory cells. The second bit line is electrically connected to the second source and drain of the second access transistor of each memory cell in each column of the non-volatile static memory cells. The memory array according to claim 9 or 10, wherein the first inverter and the second inverter are connected between a power line and a ground line corresponding to the non-volatile static memory storage cell through a power switch component. The memory array according to claim 11, wherein the power switch component comprises a third switch transistor and a fourth switch transistor, the first inverter is electrically connected to the power line via the third switch transistor, and the second inverter is electrically connected to the power line via the fourth switch transistor; or The power switch component includes a third switch transistor, and the first inverter and the second inverter are electrically connected to the power line via the third switch transistor. The memory array of claim 12, further comprising: a plurality of second control lines, respectively electrically connected to the power switch components of each storage unit of the corresponding non-volatile static memory storage unit row in the second direction to transmit a second control signal, The second control signal is used to control the switching state of the power switch component. The memory array according to any one of claims 9 to 13, wherein the plurality of word lines are electrically connected to a gate of a first access transistor and a gate of a second access transistor of each memory cell in a corresponding row of nonvolatile static memory cells. The memory array according to claim 14, wherein the plurality of word lines are further electrically connected to the corresponding power switch components to transmit a second control signal, The second control signal is used to control the switching state of the power switch component. The memory array according to any one of claims 1 to 15, wherein: The plurality of power lines are short-circuited at one or both ends of the memory array in the second direction; and/or The plurality of ground lines are short-circuited at one or both ends of the memory array in the second direction. An electronic device comprising the memory array according to any one of claims 1 to 16. A method for operating a memory array according to any one of claims 1 to 16, comprising: Selecting an i-th row of non-volatile static memory cells in the memory array; Performing data backup or data recovery on the non-volatile static memory storage units in the i-th row according to the control signal, Wherein, i is a positive integer. The method for operating a memory array according to claim 18, wherein: selecting a plurality of rows or all of the non-volatile static memory cells in the memory array; Data backup or data recovery is performed on the selected multiple rows or all non-volatile static memory storage cells according to the control signal in the same operation.