CN117636953A

CN117636953A - Memory array, electronic device and method of operating memory array

Info

Publication number: CN117636953A
Application number: CN202311595782.3A
Authority: CN
Inventors: 潘立阳; 梁英真; 吴华强
Original assignee: Tsinghua University
Current assignee: Tsinghua University
Priority date: 2023-11-27
Filing date: 2023-11-27
Publication date: 2024-03-01
Also published as: WO2025113431A1

Abstract

At least one embodiment of the present disclosure provides a memory array, an electronic device, and a method of operating the memory array. The memory array includes a plurality of nonvolatile static memory cells, a plurality of power lines, and a plurality of ground lines. The plurality of nonvolatile static memory storage units are arranged in a plurality of rows and a plurality of columns and are configured to perform data storage and data backup and recovery; the plurality of power lines are configured to provide a first power supply voltage for the plurality of nonvolatile static memory storage units, wherein the plurality of power lines are respectively and electrically connected with the corresponding storage unit columns in a first direction, and the plurality of power lines are in short circuit in a second direction; the plurality of ground lines are configured to provide a second power supply voltage to the plurality of nonvolatile static memory cells, wherein the plurality of ground lines are electrically connected with the corresponding memory cell columns in a first direction respectively, and the plurality of ground lines are shorted in a second direction. The memory array can keep the voltage of the power line stable when a row of memory cells simultaneously recover data.

Description

Memory array, electronic device and operation method of memory array

Technical Field

Embodiments of the present disclosure relate to a memory array, an electronic device, and a method of operating the memory array.

Background

In the memory array, when performing data operation, a conductive channel from power supply to ground may be formed in the memory cells, and if the same power line in the memory array is simultaneously connected to a plurality of memory cells that need to perform data operation simultaneously, then a problem that the power supply current is too large and the power supply capacity is insufficient during data operation may occur, which in turn may cause data operation failure.

Disclosure of Invention

Some embodiments of the present disclosure provide a memory array comprising: a plurality of nonvolatile static memory storage units arranged in a plurality of rows and a plurality of columns and configured to perform data storage and data backup and recovery; a plurality of power lines configured to provide a first power voltage to the plurality of nonvolatile static memory cells, wherein the plurality of power lines are electrically connected to corresponding memory cell columns in a first direction, respectively, and the plurality of power lines are shorted in a second direction, the first direction being different from the second direction; and the plurality of ground wires are configured to provide a second power supply voltage for the plurality of nonvolatile static memory storage units, wherein the plurality of ground wires are respectively and electrically connected with the corresponding storage unit columns in the first direction, and the plurality of ground wires are in short circuit in the second direction.

For example, a memory array provided in some embodiments of the present disclosure further includes: a plurality of bit lines electrically connected to the corresponding nonvolatile static memory cell columns in the first direction, respectively, to transmit data signals; a plurality of first control lines electrically connected with the corresponding nonvolatile static memory cell rows in the second direction respectively to transmit first control signals; and a plurality of word lines electrically connected with the corresponding nonvolatile static memory cell rows in the second direction respectively so as to transmit word line signals.

For example, in one memory array provided by some embodiments of the present disclosure, each of the plurality of nonvolatile static memory storage units includes a volatile storage subunit and a nonvolatile storage subunit; the volatile storage subunit is configured to transmit the stored first data and/or second data to the nonvolatile storage subunit for data backup or receive third data and/or fourth data transmitted by the nonvolatile storage subunit for data recovery; the nonvolatile storage subunit is configured to transmit the stored third data and/or fourth data to the volatile storage subunit for data recovery, or receive the first data and/or second data transmitted by the volatile storage subunit for data backup.

For example, in one memory array provided by some embodiments of the present disclosure, the non-volatile memory sub-unit includes a first non-volatile memory device, a second non-volatile memory device, a first switching transistor, and a second switching transistor; the first nonvolatile memory device is connected with the volatile memory subunit through the first switch transistor; the second nonvolatile memory device is connected to the volatile memory subunit via the second switching transistor.

For example, in one memory array provided by some embodiments of the present disclosure, the first nonvolatile memory device is configured to store the third data; the second nonvolatile memory device is configured to store the fourth data; the third data and the fourth data are configured as differential signals; the first nonvolatile memory device and the second nonvolatile memory device are resistance change memory devices or phase change memory devices or magnetoresistive memory devices. For example, in some embodiments of the present disclosure, a memory array is provided in which the plurality of first control lines are electrically connected to the gates of the first switching transistor and the gates of the second switching transistor of each memory cell in the corresponding row of non-volatile static memory cells.

For example, in a memory array provided in some embodiments of the present disclosure, for each column of nonvolatile static memory cells, the plurality of bit lines includes a first bit line electrically connected to a first nonvolatile memory device of each of the nonvolatile static memory cells of the each column, and a second bit line electrically connected to a second nonvolatile memory device of each of the nonvolatile static memory cells of the each column.

For example, in one memory array provided by some embodiments of the present disclosure, the volatile memory sub-cells are static random access memory cells.

For example, in one memory array provided by some embodiments of the present disclosure, the static random access memory cell includes a first inverter, a second inverter, a first access transistor, and a second access transistor; the first inverter and the second inverter are connected between a power line and a ground line corresponding to the storage unit of the nonvolatile static memory; the output end of the first inverter is connected with the input end of the second inverter, and the input end of the first inverter is connected with the output end of the second inverter; the first source drain electrode of the first access transistor is connected with the output end of the first inverter; the first source drain electrode of the second access transistor is connected with the output end of the second inverter.

For example, in a memory array provided in some embodiments of the present disclosure, for each column of nonvolatile static memory cells, the plurality of bit lines includes a first bit line electrically connected to a second source drain of a first access transistor of each of the nonvolatile static memory cells of the column, and a second bit line electrically connected to a second source drain of a second access transistor of each of the nonvolatile static memory cells of the column.

For example, in a memory array provided in some embodiments of the present disclosure, the first inverter and the second inverter are connected between a power line and a ground line corresponding to a nonvolatile static memory cell where the first inverter and the second inverter are located through a power switching component.

For example, in one memory array provided in some embodiments of the present disclosure, the power switching assembly includes a third switching transistor and a fourth switching transistor, the first inverter is electrically connected to the power line via the third switching transistor, and the second inverter is electrically connected to the power line via the fourth switching transistor; alternatively, the power switching assembly includes a third switching transistor, and the first inverter and the second inverter are electrically connected to the power line through the third switching transistor.

For example, a memory array provided in some embodiments of the present disclosure further includes: and a plurality of second control lines electrically connected with the power switch assembly of each memory cell of the corresponding nonvolatile static memory cell row in the second direction respectively so as to transmit a second control signal, wherein the second control signal is used for controlling the switch state of the power switch assembly.

For example, in some embodiments of the present disclosure, a memory array is provided in which the plurality of word lines are electrically connected to the gates of the first access transistor and the gates of the second access transistor of each memory cell in a corresponding row of non-volatile static memory cells.

For example, in a memory array provided in some embodiments of the present disclosure, the plurality of word lines are further electrically connected to the corresponding power switch assemblies to transmit a second control signal for controlling a switching state of the power switch assemblies.

For example, in one memory array provided by some embodiments of the present disclosure, the plurality of power supply lines are shorted at one or both ends of the memory array in the second direction; and/or the plurality of ground lines are shorted at one or both ends of the memory array in the second direction.

Some embodiments of the present disclosure provide an electronic device comprising a memory array as described in any one of the embodiments above.

Some embodiments of the present disclosure provide a method for operating a memory array, which is used in the memory array according to any one of the above embodiments, the method including: selecting an ith row of nonvolatile static memory cells in the memory array; and carrying out data backup or data recovery on the storage units of the ith row of nonvolatile static memory according to a control signal, wherein I is a positive integer.

For example, in a method of operating a memory array provided by some embodiments of the present disclosure, a plurality of rows or all non-volatile static memory cells in the memory array are selected; and carrying out data backup or data recovery on the selected multiple rows or all nonvolatile static memory storage units in the same operation according to the control signals.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly described below, and it is apparent that the drawings in the following description relate only to some embodiments of the present disclosure, not to limit the present disclosure.

FIG. 1 is a schematic diagram of a 6T-SRAM structure;

FIG. 2 is a schematic diagram of a combination of volatile and non-volatile memory sub-units;

FIG. 3 is a schematic diagram of a memory array according to at least one embodiment of the present disclosure;

FIG. 4 is a schematic diagram of a nonvolatile static memory (NVSRAM) memory cell according to at least one embodiment of the present disclosure;

FIG. 5 is a schematic diagram of an NVSRAM memory cell provided in at least one embodiment of the present disclosure;

FIG. 6 is a schematic diagram of yet another NVSRAM memory cell provided by at least one embodiment of the present disclosure;

FIG. 7 is a timing diagram of performing a data backup operation in an NVSRAM memory cell provided in at least one embodiment of the present disclosure;

FIG. 8 is a timing diagram of performing a data recovery operation for an NVSRAM cell in accordance with at least one embodiment of the present disclosure;

FIG. 9 is a flow chart of a method of operating a memory array according to at least one embodiment of the present disclosure;

FIG. 10 is a schematic flow chart diagram of a SET operation and a RESET operation respectively performed when data backup is performed on a storage array according to at least one embodiment of the present disclosure;

FIG. 11 is a schematic flow chart of a simultaneous SET operation and RESET operation when backing up data of a storage array according to at least one embodiment of the present disclosure;

FIG. 12 is a flow chart of a method for performing data backup on a storage array using RESET and SET separate progressive operation according to at least one embodiment of the present disclosure;

FIG. 13 is a flow chart of a method for performing data backup on a storage array using RESET and SET split full-chip operation according to at least one embodiment of the present disclosure;

FIG. 14 is a schematic flow chart of a data backup method for performing a row-by-row operation on a memory array using RESET and SET simultaneously according to at least one embodiment of the present disclosure;

FIG. 15 is a flow chart illustrating data recovery for a storage array according to at least one embodiment of the present disclosure.

Detailed Description

For a better understanding of the technical solutions of the present disclosure, the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings, and the specific embodiments and the accompanying drawings described herein are only for explaining the present disclosure and are not limiting of the embodiments of the present disclosure, and the embodiments of the present disclosure and the features of the embodiments may be combined with each other without conflict, only the portions related to the embodiments of the present disclosure are shown in the accompanying drawings of the embodiments of the present disclosure for convenience of description, and the portions unrelated to the embodiments of the present disclosure are not shown in the drawings. Each unit, module referred to in the embodiments of the present disclosure may correspond to only one physical structure, may be composed of a plurality of physical structures, or may be integrated into one physical structure. In the absence of conflict, the functions noted in the flowcharts and block diagrams of the disclosed embodiments may occur out of the order noted in the figures. The architecture, functionality, and operation of possible implementations of systems, apparatuses, devices, methods according to various embodiments of the present disclosure are shown in the flowcharts and block diagrams of the disclosed embodiments. Where each block in the flowchart or block diagrams may represent a unit, module, segment, code, or the like, which comprises executable instructions for implementing the specified functions. Moreover, each block or combination of blocks in the block diagrams and flowchart illustrations can be implemented by hardware-based systems that perform the specified functions, or by combinations of hardware and computer instructions.

Unless defined otherwise, technical or scientific terms used in this disclosure should be given the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The terms "first," "second," and the like, as used in this disclosure, do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that elements or items preceding the word are included in the element or item listed after the word and equivalents thereof, but does not exclude other elements or items. The terms "connected" or "connected," and the like, are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", etc. are used merely to indicate relative positional relationships, which may also be changed when the absolute position of the object to be described is changed.

The present disclosure is illustrated by the following several specific examples. Detailed descriptions of known functions and known parts (elements) may be omitted for the sake of clarity and conciseness in the following description of the embodiments of the present disclosure. When any part (element) of an embodiment of the present disclosure appears in more than one drawing, the part (element) is denoted by the same or similar reference numeral in each drawing.

Memory is an important component of a computer architecture for storing, for example, program code, data, etc. Basic memory can be classified into volatile memory and nonvolatile memory according to the characteristics of a storage medium. Volatile memory refers to memory in which data stored after power-down will be lost, and correspondingly nonvolatile memory refers to memory in which data stored after power-down will not be lost. Generally, volatile memory operates faster, while non-volatile memory has a longer retention time.

For example, the volatile memory may be DRAM (dynamic random access memory) or SRAM (static random access memory). For example, a DRAM may use a transistor and a capacitor to store one bit of data, and the data stored in the DRAM may need to be periodically updated; SRAM may use multiple transistors to store one bit of data and may persist the stored data as long as the SRAM remains powered on.

For example, the SRAM may also be of various types, such as a multi-transistor type SRAM, such as 6T-SRAM (i.e., six-transistor type SRAM), 7T-SRAM (i.e., seven-transistor type SRAM), 8T-SRAM (i.e., eight-transistor type SRAM), and the like.

FIG. 1 is a schematic diagram of an exemplary structure of a 6T-SRAM cell.

As shown in fig. 1, the 6T-SRAM memory cell includes a transistor P0, a transistor P1, a transistor N0, a transistor N1, a transistor N2, a transistor N3, and a bit line BL, a bit line BLN, a word line WL, a power line CVDD, and a ground line VSS for operating the memory cell, where the memory cell has a storage node Q and a storage node QN therein, where N represents a transistor of an NMOS (N-Metal-Oxide-Semiconductor) type, and P represents a transistor of a PMOS (P-Metal-Oxide-Semiconductor) type. The bit line BL and the bit line BLN are used for reading and writing data, the word line WL is used for controlling reading and writing operation, the transistor P0 and the transistor N0 form one inverter, the transistor P1 and the transistor N1 form the other inverter, and the two inverters are cross-connected, so that a storage node Q and a storage node QN are provided. The SRAM memory cell has a bistable structure. When the storage node Q is at a high level, the storage node QN is at a low level, and data which can be selected to be stored is "1" at this time, and correspondingly, when the storage node Q is at a low level, the storage node QN is at a high level, and data which can be selected to be stored is "0" at this time; transistor N2 and transistor N3 are controlled by word line WL to turn the memory cell on or off.

The SRAM memory cell can have three states: data retention, reading, and writing. In the data retention state, the word line WL remains low, the transistors N2 and N3 are turned off, and the two sets of inverters are isolated from the corresponding bit lines and remain in the original state.

In a read operation, assuming that the stored data is 1, the storage node Q is at a high level, the storage node QN is at a low level, the bit line BL and the bit line BLN are precharged to a high level, and then the word line WL is at a high level, so that the transistors N2 and N3 are turned on, the transistor P0 is turned on due to the low level of the storage node QN, the bit line BL is connected to the power supply line CVDD through the transistor N2 and the transistor P0, and the level (high level) of the bit line BL and the storage state of the storage node Q (high level) remain unchanged; the high level of the storage node Q turns on the transistor N1, the bit line BLN is connected to the ground line VSS through the transistor N3, the transistor N1, the bit line BLN is discharged, the level decreases, but the storage state of the storage node QN (low level) remains unchanged. Thus, by reading the voltage difference (positive difference) on bit lines BL and BLN, it can be known that the memory cell is currently storing a "1".

Assuming that the stored data is 0, the storage node Q is low, the storage node QN is high, the bit line BL and the bit line BLN are precharged to high, then the word line WL is high, the transistors N2 and N3 are turned on, the transistor N0 is turned on due to the high level of the storage node QN, the bit line BL is connected to the ground line VSS through the transistor N2 and the transistor N0, the bit line BL is discharged, the level is lowered, but the storage state of the storage node Q (low level) is maintained; the low level of the storage node Q turns on the transistor P1, the bit line BLN is connected to the power supply line CVDD through the transistor N3, the transistor P1, and the storage states of the level (high level) of the bit line BLN and the storage node QN (high level) remain unchanged. Thus, by reading the voltage difference (negative difference) on bit lines BL and BLN, it can be known that the memory cell is currently storing a "0".

At the time of a write operation, a written state needs to be loaded to the bit line BL and the bit line BLN to modify the levels of the storage nodes Q and QN in the memory cell. For example, if data 1 is to be written, it is necessary to make the storage node Q high, and correspondingly the storage node QN low. At this time, the bit line BL is set to a high level, the bit line BLN is set to a low level, and then the word line WL is set to a high level, so that the transistors N2, N3 are turned on, the high level of the bit line BL sets the storage node Q to a high level, the low level of the bit line BLN sets the storage node QN to a low level, whereby the transistors P0, N1 are turned on and the transistors N0, P1 are turned off, whereby the power supply line CVDD keeps the storage node Q to a high level via the transistor P0, and the ground line VSS keeps the storage node QN to a low level via the transistor N1, thereby achieving writing of the data 1 and continuous storage of the data 1 in a continuous power-off condition.

For example, if data 0 is to be written, it is necessary to make the storage node Q low, and correspondingly the storage node QN low. At this time, the bit line BL is set to a low level, the bit line BLN is set to a high level, then the word line WL is set to a high level, so that the transistors N2 and N3 are turned on, the low level of the bit line BL sets the storage node Q to a low level, the high level of the bit line BLN sets the storage node QN to a high level, thereby the transistors N0 and P1 are turned on and the transistors P0 and N1 are turned off, thereby the power line CVDD keeps the storage node QN to a high level via the transistor P1, and the ground line VSS keeps the storage node Q to a low level via the transistor N0, thereby achieving the writing of the data 0 and the continuous storage of the data 0 in the uninterrupted power state

For example, the nonvolatile memory may be RRAM (Resistive Random Access Memory ), PRAM (Phase-Change Random Access Memory, phase-change random access memory), MRAM (Magnetoresistive Random Access Memory, magnetoresistive memory), flash memory (Flash), or the like, for example, RRAM and PRAM store data by changing a resistance value. For example, resistive random access memories utilize the resistance of thin film materials under different applied voltage conditions to achieve data storage in different resistance states, high Resistance States (HRS) and Low Resistance States (LRS). The logic '1' and the logic '0' are represented by the external expressions of different high and low configurations, so that the data storage is realized, and the data storage can be kept for a long time after the power supply is cut off. This process of switching a resistive random access memory from a High Resistive State (HRS) to a Low Resistive State (LRS) is referred to as a SET process, and may also be referred to as a SET process. The transition from the low configuration to the high resistance state is referred to as a RESET process, and may also be referred to as a RESET process.

Typically, nonvolatile memory includes a nonvolatile memory device and one or more switching transistors, which may be transistors or a combination of transistors that enable control of current on and off. Nonvolatile memory is typically slow to operate and requires a large operating current or voltage.

As described above, SRAM (Static Random Access Memory) is a volatile memory, and data is lost after power failure, so that power is required to be supplied all the time to maintain the data storage of the SRAM, which consumes a lot of energy, and is disadvantageous for low power design of the system. Non-volatile memory, on the other hand, is typically slower in operating speed and requires a larger operating current or voltage. Therefore, a nonvolatile static random access memory (Nonvolatile Static random Access Memory, NVSRAM) is proposed, the advantages of the two types of memories are combined, a nonvolatile memory (Nonvolatile Memory, NVM) is integrated with an SRAM memory, the nonvolatile memory is utilized to backup data stored in the SRAM, the advantage of high-speed operation of the SRAM can be reserved, the data stored in the nonvolatile memory after power failure can be realized, and the data can be restored to the SRAM after power failure, so that the low-power consumption design of a processor is realized, and the nonvolatile memory is an ideal memory for future mobile terminals, personal computers and servers.

Fig. 2 is a schematic diagram of a nonvolatile static random access memory (NVSRAM) cell obtained by combining a volatile memory sub-cell, which is the same 6T-SRAM as shown in fig. 1, with a nonvolatile memory sub-cell, which includes a Resistive Random Access Memory (RRAM) R, a resistive random access memory RN, a transistor N4, and a transistor N5. The nonvolatile memory subunit is connected to the volatile memory subunit in a differential manner, the resistive random access memory device R is connected to the storage node Q through the transistor N4, the resistive random access memory device RN is connected to the storage node QN through the transistor N5, the gates of the transistor N4 and the transistor N5 are connected to the control line CWLN, and the on-off states of the transistors N4 and N5 are controlled through the control line CWLN, for example, the state in which the resistance of the resistive random access memory device R is greater than the resistance of the resistive random access memory device RN is set to data "1", and otherwise, the state is set to data "0".

In other forms, instead of being connected to the volatile memory sub-unit by a differential connection, the non-volatile memory sub-unit may be connected by a single-ended connection, for example, would include only the resistive random access memory device R and the transistor N4. In addition to the RRAM used for the nonvolatile memory subunit, a phase change random access memory (PRAM) or the like may be used.

In the current NVSRAM memory array, a power line is routed along a row direction and electrically connected to memory cells of the row, and the memory cells of the same row are connected to the same power line, so that when the memory cells of an entire row perform data recovery simultaneously, the total current of the power line is the sum of the power currents of the memory cells of the entire row, the power supply capacity is easily insufficient due to the overlarge current, the power supply voltage is unstable or reduced, and the data recovery fails.

At least in view of the foregoing, at least one embodiment of the present disclosure provides a memory array comprising: a plurality of non-volatile static memory (NVSRAM) memory cells, a plurality of power supply lines, and a plurality of ground lines. The plurality of NVSRAM memory cells are arranged in a plurality of rows and a plurality of columns and configured to perform data storage and data backup and restore; the plurality of power lines are configured to provide a first power voltage to the plurality of NVSRAM memory cells, wherein the plurality of power lines are respectively electrically connected with the corresponding memory cell columns in a first direction, the plurality of power lines are short-circuited in a second direction, and the first direction is different from the second direction; the plurality of ground lines are configured to provide a second power supply voltage to the plurality of NVSRAM memory cells, wherein the plurality of ground lines are electrically connected with the corresponding memory cell columns in a first direction, respectively, and the plurality of ground lines are shorted in a second direction.

In the structure of the memory array provided in the above embodiment of the present disclosure, when a row of memory cells perform data recovery at the same time, the current of each power line in the first direction is only the power current of one memory cell, and the ground current in each first direction is only the ground current of one memory cell, so the total current on the power line and the ground is low, the power voltage and the ground voltage remain stable, and the success rate of data recovery can be improved.

FIG. 3 is a schematic diagram of a memory array according to at least one embodiment of the present disclosure.

As shown in fig. 3, the memory array includes a plurality of NVSRAM memory cells arranged in m rows and n columns, n power supply lines CVDD each electrically connected to one column of NVSRAM memory cells, and n ground lines VSS each electrically connected to one column of NVSRAM memory cells, and all of the power supply lines CVDD are shorted in the row direction, and all of the ground lines VSS are shorted in the row direction. Therefore, when one row of memory cells simultaneously perform data recovery, the current of each power line CVDD in the first direction is only the power current of one memory cell, so that the total current on the power lines CVDD is lower, the power voltage is kept stable, and the success rate of data recovery can be improved. For example, the first direction is a column direction and the second direction is a row direction.

The memory array further includes a plurality of bit lines, a plurality of first control lines CWLN, and a plurality of word lines WL. The plurality of bit lines includes a plurality of first bit lines BL and a plurality of second bit lines BLN, each pair of bit lines BL and BLN being electrically connected to a corresponding NVSRAM memory cell column, respectively, in a first direction to transmit data signals for controlling volatile memory sub-cells and nonvolatile memory sub-cells in the NVSRAM memory cells (see below); a plurality of first control lines CWLN are respectively electrically connected to the corresponding NVSRAM memory cell rows in the second direction to transmit first control signals for controlling, for example, nonvolatile memory sub-cells in the NVSRAM memory cells (see below); a plurality of word lines WL are electrically connected to corresponding rows of NVSRAM memory cells in a second direction, respectively, to transmit word line signals for controlling volatile memory sub-cells in the NVSRAM memory cells (see below).

In fig. 3, WLi represents an i-th word line, e.g., WL1 represents a 1-th word line; CWLNi represents the i-th first control line, e.g., CWLN1 represents the 1-th first control line; BLi and BLNi represent the ith first bit line and the ith second bit line, respectively, e.g., BL1 and BLN1 represent the 1 st first bit line and the 1 st second bit line, respectively; NVSRAMij represents an ith row and a jth column of NVSRAM memory cells, for example NVSRAM11 represents a 1 st row and a 1 st column of NVSRAM memory cells, wherein i and j are positive integers, i is equal to or less than 1 and equal to or less than m, and j is equal to or less than 1 and equal to or less than n; in the memory array, control of the individual device states on the NVSRAM memory cells can be achieved by controlling the voltages on the first bit line BL, the second bit line BLN, the first control line CWLN, and the word line WL.

In this embodiment, the plurality of power supply lines CVDD may be shorted, for example, at one or both ends of the memory array in the row direction, and the plurality of ground lines VSS may be shorted, for example, at one or both ends of the memory array in the row direction. The power line CVDD and the ground line VSS are short-circuited at both ends of the memory array, so that the situation that the memory array fails in data backup and recovery when a circuit with one end for short-circuiting fails can be avoided.

For example, fig. 4 is a schematic structural diagram of an NVSRAM memory cell in accordance with at least one embodiment of the present disclosure. As shown in FIG. 4, in one example, the plurality of NVSRAM memory cells each include a volatile memory subunit and a nonvolatile memory subunit; the volatile storage subunit is configured to transmit the stored first data and/or second data to the nonvolatile storage subunit for data backup, or receive the third data and/or fourth data transmitted by the nonvolatile storage subunit for data recovery; the nonvolatile storage subunit is configured to transmit the stored third data and/or fourth data to the volatile storage subunit for data recovery, or receive the first data and/or second data transmitted by the volatile storage subunit for data backup.

For example, the third data and/or the fourth data may be the first data and/or the second data in the volatile memory device obtained by the nonvolatile memory device through data backup, or may be data inherent in the nonvolatile memory device or data stored in the nonvolatile memory device in other manners.

For example, in one example, the volatile memory sub-cells are Static Random Access Memory (SRAM) cells, which may be 6T-SRAM, 7T-SRAM, or other SRAM structures capable of implementing static random access memory functions.

For example, in one example, the nonvolatile memory subunit may include a RRAM and a switching transistor, where the RRAM is electrically connected with the volatile memory subunit through the switching transistor.

For example, fig. 5 is a schematic diagram of an NVSRAM memory cell provided in accordance with at least one embodiment of the present disclosure.

As shown in fig. 5, the nonvolatile memory subunit of the NVSRAM memory cell includes a first nonvolatile memory device R, a second nonvolatile memory device RN, a first switching transistor N4, and a second switching transistor N5; the first nonvolatile memory device R is connected with the volatile memory subunit through a first switching transistor N4; the second nonvolatile memory device RN is connected to the volatile memory subunit via a second switching transistor N5.

The static random access memory cell of the NVSRAM memory cell comprises a first inverter V1, a second inverter V2, a first access transistor N2 and a second access transistor N3; the first inverter V1 and the second inverter V2 are connected between the power supply line CVDD and the ground line VSS corresponding to the NVSRAM memory cell where they are located; the output end of the first inverter V1 is connected with the input end of the second inverter V2, and the input end of the first inverter V1 is connected with the output end of the second inverter V2; the first access transistor N2 is connected with the output end of the first inverter V1; the second access transistor N3 is connected to the output of the second inverter V2.

For example, the SRAM cell is a 6T-SRAM, and the first inverter V1 and the second inverter V2 are connected between the power line CVDD and the ground line VSS corresponding to the NVSRAM cell through a power switching element.

The power switching assembly comprises a third switching transistor P2 and a fourth switching transistor P3, the first inverter V1 is electrically connected with the power line CVDD through the third switching transistor P2, and the second inverter V2 is electrically connected with the power line CVDD through the fourth switching transistor P3.

The first inverter V1 includes a transistor P0 and a transistor N0, the second inverter V2 includes a transistor P1 and a transistor N1, a gate of the third switching transistor P2 is connected to a gate of the fourth switching transistor P3 and to the second control line RECP, sources of the third switching transistor P2 and the fourth switching transistor P3 are connected to the power supply line CVDD, a drain of the third switching transistor P2 is connected to a source of the transistor P0, and a drain of the fourth switching transistor P3 is connected to a drain of the transistor P1; the second control line RECP is connected to the gate of a transistor in the power switching element, and may be connected to the word line WL, or may separately supply a voltage to the power switching element.

The storage nodes of the 6T-SRAM include storage nodes Q and QN, and the first data and/or the second data stored in the static random access memory unit can be obtained by reading the voltages of the storage nodes Q and QN. For example, the first data is stored in the storage node Q, and the second data is stored in the storage node QN; for example, assuming that the stored data is 1, the storage node Q is high and the storage node QN is low, the bit line BL and the bit line BLN are precharged to high, and then the word line WL is set to high, so that the transistors N2 and N3 are turned on, the transistor P0 is turned on due to the low level of the storage node QN, the bit line BL is connected to the power supply line CVDD through the transistor N2 and the transistor P0, and the level (high level) of the bit line BL and the storage state of the storage node Q (high level) remain unchanged; the high level of the storage node Q turns on the transistor N1, the bit line BLN is connected to the ground line VSS through the transistor N3, the transistor N1, the bit line BLN is discharged, the level decreases, but the storage state of the storage node QN (low level) remains unchanged. Thus, by reading the voltage difference (positive difference) on bit lines BL and BLN, it can be known that the memory cell is currently storing a "1".

Because the SRAM unit is of a bistable structure, the storage nodes Q and QN are clamped with each other, the level of the storage nodes Q and QN is not easy to change, the success rate of live recovery data is low, the conduction channel between the volatile storage subunit and the power line can be closed when the data is recovered through the switch state of the power switch assembly, the time of power failure and power supply can be freely controlled when the data is recovered, and the success rate of data recovery is improved.

In the above 6T-SRAM, the gate of the transistor P0 and the gate of the transistor N0 are connected to serve as the input terminal of the first inverter V1, the gate of the transistor P1 and the gate of the transistor N1 are connected to serve as the input terminal of the second inverter V2, the drain of the transistor P0 and the drain of the transistor N0 are respectively connected to the storage node Q to serve as the output terminal of the first inverter V1, and the drain of the transistor P1 and the drain of the transistor N1 are respectively connected to the storage node QN to serve as the output terminal of the second inverter V2. The source of the first access transistor N2 is connected to the storage node Q and the source of the second access transistor is connected to the storage node QN.

For example, the first nonvolatile memory device R and the second nonvolatile memory device RN may be configured to be connected to the storage node of the volatile memory sub-unit in a single-ended or differential connection manner. As described above, for example, the first nonvolatile memory device R and the second nonvolatile memory device RN may be resistance variable memory devices, or may be nonvolatile memory devices such as phase change memory devices, magnetoresistive memory devices, and the like having resistance variable characteristics. For example, each of the resistive random access memory devices includes a resistive memory layer interposed between two electrodes (e.g., referred to as an upper electrode and a lower electrode), and the resistance value of the resistive memory layer is changed by applying an operating voltage across the two electrodes.

For example, the first nonvolatile memory device R and the second nonvolatile memory device RN are resistance random access memory devices, and the first nonvolatile memory device R stores third data, the second nonvolatile memory device RN stores fourth data, and the third data and the fourth data are configured as differential signals. The lower electrode of the memory device R is connected to the drain of the first switching transistor N4, the lower electrode of the memory device RN is connected to the drain of the second switching transistor N5, the source of the first switching transistor N4 is connected to the storage node Q, and the source of the second switching transistor N5 is connected to the storage node QN.

For example, when the voltage difference between the two ends of the first nonvolatile memory device R or the second nonvolatile memory device RN is greater than the operation threshold voltage of the first nonvolatile memory device R or the second nonvolatile memory device RN, the resistance state of the first nonvolatile memory device R or the second nonvolatile memory device RN is changed according to the voltage between the two ends of the first nonvolatile memory device R and the second nonvolatile memory device RN being the set voltage or the reset voltage, for example, the set voltage is the forward voltage, that is, the voltage of the first nonvolatile memory device R or the second nonvolatile memory device RN near the end of the bit line is greater than the voltage near the end of the storage node; the RESET voltage is a reverse voltage, that is, the voltage of one end of the first nonvolatile memory device R or the second nonvolatile memory device RN near the bit line is smaller than the voltage of one end near the storage node, and when the voltage of two ends of the first nonvolatile memory device R or the second nonvolatile memory device RN is the RESET voltage to execute the RESET operation, the first nonvolatile memory device R or the second nonvolatile memory device RN is turned into a high resistance state; when the voltage across the first or second nonvolatile memory device R or RN is a SET voltage to perform a SET operation, the first or second nonvolatile memory device R or RN is turned into a low resistance state; when the voltage difference between the two ends of the first nonvolatile memory device R or the second nonvolatile memory device RN is 0 or less than the operation threshold voltage, the resistance state of the first nonvolatile memory device R or the second nonvolatile memory device RN is not changed, and the resistance change memory stores data in the form of resistance state.

When the forward voltage difference between the two ends of the upper electrode and the lower electrode of the storage device R or RN is larger, the R or RN is converted into a low-resistance state; when the reverse voltage difference between the two ends of the upper electrode and the lower electrode of the storage device R or RN is larger, the R or RN is converted into a high-resistance state; when the voltage difference between the upper electrode and the lower electrode of the memory device R or RN is 0 or less than the operation threshold voltage, the resistance state of the memory device R or RN is not changed, and the resistive random access memory stores data in the form of resistance state.

For example, in one example, a plurality of first control lines CWLN are electrically connected to the first switching transistor N4 and the second switching transistor N5 of each memory cell in a corresponding row of NVSRAM memory cells. The first control line CWLN is connected to the gate of the first switching transistor N4 and the gate of the second switching transistor N5, and the switching states of the first switching transistor N4 and the second switching transistor N5 can be controlled by controlling the voltage of the first control line CWLN. When the first control line CWLN voltage meets the on condition of the first switching transistor N4 and the second switching transistor N5, the first switching transistor N4 and the second switching transistor N5 are in an on state, otherwise, the first switching transistor N4 and the second switching transistor N5 are turned off. When the first switching transistor N4 and the second switching transistor N5 are turned on, connection of the storage node to the nonvolatile memory device may be achieved, for example, the first data and/or the second data stored in the storage node may be transferred to the nonvolatile memory subunit, or the third data and/or the fourth data in the nonvolatile memory subunit may be transferred to the storage node.

For example, in one example, for each column of NVSRAM cells, a first bit line BL is electrically connected to a first access transistor N2 of each of the cells in each column of NVSRAM cells, and a second bit line BLN is electrically connected to a second access transistor N3 of each of the cells in each column of NVSRAM cells. In addition, the first bit line BL is electrically connected to the first nonvolatile memory device R of each memory cell in each column of NVSRAM memory cells, and the second bit line BLN is electrically connected to the second nonvolatile memory device RN of each memory cell in each column of NVSRAM memory cells. Thus, bit lines BL and BLN can be used to operate both SRAM memory cells and nonvolatile memory devices.

For example, in one example, a plurality of word lines WL are electrically connected to the first access transistor N2 and the second access transistor N3 of each memory cell in a corresponding row of NVSRAM memory cells. The word line WL is connected to the gates of the first access transistor N2 and the second access transistor N3, and the on state of the first access transistor N2 and the second access transistor N3 can be controlled by controlling the voltage of the word line WL. When the word line WL voltage meets the conduction condition of the first access transistor N2 and the second access transistor N3, the first access transistor N2 and the second access transistor N3 are turned on, otherwise, the first access transistor N2 and the second access transistor N3 are not turned on.

FIG. 6 is a schematic diagram of another NVSRAM memory cell in accordance with at least one embodiment of the present disclosure.

Compared with fig. 5, the power switch assembly of the NVSRAM memory cell shown in fig. 6 includes a third switch transistor P2, the first inverter V1 and the second inverter V2 are electrically connected to the power line through the third switch transistor P2, and the other devices are connected in the same manner as the NVSRAM memory cell shown in fig. 5. At this time, the source of the third switching transistor P2 is connected to the power line CVDD, the drain is connected to the source of the transistor P0 and the source of the transistor P1, and the gate is connected to the second control line RECP, which is used for transmitting a second control signal to control the switching state of the third switching transistor P2.

The memory array in which the NVSRAM memory cells shown in fig. 6 are arranged further includes a plurality of second control lines RECP electrically connected to the power switching assembly of each memory cell in the corresponding NVSRAM memory cell row in the second direction, respectively, to transmit the second control signals. The second control line RECP is connected to the gate of a transistor in the power switching element, and may be connected to the word line WL, or may separately supply a voltage to the power switching element.

The process of data backup and data recovery for the NVSRAM memory cell shown in fig. 5 can be as follows:

The data backup operation is classified into a SET operation and a RESET operation for the nonvolatile memory device: one of the non-volatile memory devices is selected for a SET operation according to the data of the storage node in the volatile memory subunit, and the other is selected for a RESET operation.

Taking the data stored in the volatile storage subunit as 0 as an example, the storage node Q is at a low level and the storage node QN is at a high level. At this time, the SET operation is performed on the nonvolatile memory device R, and the RESET operation is performed on the nonvolatile memory device RN.

FIG. 7 is a timing diagram of the data backup operation of the NVSRAM cell shown in FIG. 5.

In the SET operation (right side in the figure), the power line CVDD voltage is SET to the voltage VDD, the word line WL voltage is SET to VSS, the first control line CWLN voltage is SET to the voltage VDD, and the voltages of the first bit line BL and the second bit line BLN are SET to the voltage VSET (i.e., the voltage at which the SET operation is performed). At this time, the storage node Q is at a low level (i.e., VSS), and the first switching transistor N4 is turned on, and the voltage difference VR between the two ends of the nonvolatile memory device R is VSET and greater than the SET operation threshold voltage, so that the SET operation is performed on the nonvolatile memory device R to change it into a low resistance state; the storage node QN is high (i.e., VDD), the second switching transistor N5 is turned off, and the voltage difference VR across the nonvolatile memory device RN is 0, so that the nonvolatile memory device RN is not operated, and its resistance value is unchanged.

In the RESET operation (left side in the figure), the power line CVDD voltage is VRST (i.e., the voltage for the RESET operation), the word line WL voltage is VSS, the first control line CWLN voltage is VDDH, and the voltages of the first bit line BL and the second bit line BLN are VSS, where VDDH is higher than or equal to VDD. At this time, the storage node Q is at a low level (i.e., VSS), the first switching transistor N4 is turned on, the voltage difference VR between the two ends of the nonvolatile memory device R is 0, and the resistance state of the nonvolatile memory device R is not changed; the storage node QN is at a high level (i.e., VRST), the second switching transistor N5 is turned on, and the voltage difference VR across the non-volatile storage device RN is a low value between VRST and VDDH-VTN, where VTN is the threshold voltage of the second switching transistor N5; by presetting VRST and VDDH so that both VRST and VDDH-VTN are greater than the reverse threshold voltage required for the RESET operation, the nonvolatile memory device RN is RESET to a high resistance state at this time.

The process of data backup and data recovery of the NVSRAM memory cell shown in fig. 6 is the same as the process of data backup of the NVSRAM memory cell shown in fig. 5, and will not be repeated here.

Fig. 8 is a timing diagram of the data recovery operation performed by the NVSRAM memory cell shown in fig. 5.

The data recovery operation recovers the data stored (differentially) in the nonvolatile memory devices R and RN into the SRAM device, recovers the high-resistance-side corresponding storage node in the nonvolatile memory devices R and RN to a high level, and recovers the low-resistance-side corresponding storage node to a low level.

The NVSRAM memory cell shown in fig. 5 performs a data recovery operation in three stages:

the first stage: the voltage of the power line CVDD is set to be the voltage VDD, the voltage of the word line WL is set to be the voltage VDD, the voltage of the first control line CWLN is set to be the voltage VDD, the voltages of the first bit line BL and the second bit line BLN are set to be the voltage VSS, at this time, the third switching transistor P2 and the fourth switching transistor P3 are turned off, the power supply of the SRAM memory cell is cut off, the bistable state of the SRAM memory cell is destroyed, the voltage of the storage node Q is discharged to the voltage VSS through the paths of the first switching transistor N4 and the transistor N2, and the voltage of the storage node QN is discharged to the voltage VSS through the paths of the second switching transistor N5 and the transistor N3.

And a second stage: the power line CVDD is set to be the voltage VDD, the word line WL is set to be the voltage VSS, the first control line CWLN is set to be the voltage VDD, the first bit line BL and the second bit line BLN are set to be the voltage VSS, at this time, the first switching transistor N4 and the second switching transistor N5 and the third switching transistor P2 and the fourth switching transistor P3 are both in an on state, an on-state is formed from the power line CVDD to the first bit line BL through the third switching transistor P2, the transistor P0, the transistor N4, the first nonvolatile memory device R, and an on-state is formed from the power line CVDD to the first bit line BL through the fourth switching transistor P3, the transistor P1, the second switching transistor N5, the second nonvolatile memory device RN to the second bit line BLN, the circuit generates a current, the voltages of the storage nodes Q and QN are raised, the voltages on the high-resistance side are raised to be slow due to the difference in resistance values of the nonvolatile memory devices on both sides, the low-resistance-side voltage is raised to be slow, the voltage on the side between the storage nodes Q and QQ is generated from the power line CVDD to the nonvolatile memory cell through the fourth switching transistor P3, the transistor RN to the fourth switching transistor P5, the second nonvolatile memory device N and the nonvolatile memory device on the second nonvolatile memory device on the two sides are amplified to the nonvolatile memory cell on the two sides, and the nonvolatile memory cell to the nonvolatile memory cell and the nonvolatile memory cell to the nonvolatile memory cell.

In the third stage, the voltage of the power line CVDD is set to be the voltage VDD, the voltage of the word line WL is set to be the voltage VSS, the voltage of the first control line CWLN is set to be the voltage VSS, the voltages of the first bit line BL and the second bit line BLN are set to be the voltage VDD, the first switching transistor N4 and the second switching transistor N5 are turned off, the first access transistor N2 and the second access transistor N3 are turned off, and the data recovery operation is ended.

The timing diagram of the data recovery operation performed by the NVSRAM memory cell shown in fig. 6 is the same as that of fig. 8, and the data recovery operation performed by the NVSRAM memory cell shown in fig. 6 is divided into the following three phases:

the first stage: the voltage of the power line CVDD is set to be the voltage VDD, the voltage of the word line WL is set to be the voltage VDD, the voltage of the first control line CWLN is set to be the voltage VDD, the voltages of the first bit line BL and the second bit line BLN are set to be the voltage VSS, at this time, the third switching transistor P2 is turned off, the power supply of the volatile memory subunit is cut off, the bistable state of the SRAM memory unit is destroyed, the voltage of the storage node Q is discharged to the voltage VSS through the first switching transistor N4 and the transistor N2, and the voltage of the storage node QN is discharged to the voltage VSS through the second switching transistor N5 and the transistor N3.

And a second stage: the voltage of the power line CVDD is set to be the voltage VDD, the voltage of the word line WL is set to be VSS, the voltage of the first control line CWLN is set to be the voltage VDD, the voltage of the first bit line BL and the voltage of the second bit line BLN are set to be the voltage VSS, at this time, the first switching transistor N4, the second switching transistor N5 and the third switching transistor P2 are in an on state, an on path is formed from the power line CVDD to the first bit line BL through the third switching transistor P2, the transistor P0, the transistor N4 and the first nonvolatile memory device R, and an on path is formed from the power line CVDD to the second bit line BLN through the third switching transistor P2, the transistor P1, the second switching transistor N5 and the second nonvolatile memory device RN, the voltages of the memory nodes Q and QN are raised, the voltages of the nonvolatile memory devices on the high resistance side are raised to be fast due to the difference in resistance values of the nonvolatile memory devices on the two sides, the voltages on the low resistance side are raised to be slow, a delta Q is generated between the memory nodes Q and QN, and the voltage difference is amplified through the cross-coupled inverter in the memory sub-cells, and the volatile data is pulled from the positive and negative to the nonvolatile memory cells.

Because the SRAM memory cell has a bistable structure, when the data recovery operation is performed, if the connection between the SRAM memory cell and the power line is not cut off, the memory state of the SRAM memory cell is difficult to change due to the small voltage difference, the power supply of the volatile memory subunit is cut off through the power switch component, and the damaged bistable memory state of the SRAM can be improved.

At least one embodiment of the present disclosure further provides an electronic device including any of the storage arrays described in any of the above embodiments. The electronic device may be, for example, a memory device, a computer, or any other product or component that includes or is used with the memory array. The technical effects of the electronic device can be seen from the technical effects of the memory array described in the above embodiments, and will not be described herein.

At least one embodiment of the present disclosure provides a method of operating a memory array, which may be used, for example, in any of the foregoing embodiments of the memory array. Taking the memory array shown in fig. 3 as an example, NVSRAM memory cells in the memory array are shown in fig. 5.

Fig. 9 is a flowchart of a method for operating a memory array according to at least one embodiment of the present disclosure.

As shown in fig. 9, the operation method of the memory array includes the steps of:

step S101: an ith row of NVSRAM memory cells in the memory array is selected.

Step S102: and carrying out data backup or data recovery on the ith NVSRAM memory unit according to the control signal, wherein i is a positive integer which is more than or equal to 1 and less than or equal to m.

In the above embodiment, the data read/write operation for the memory array with the m rows and n columns scale as shown in fig. 3 is consistent with the data read/write operation for the memory array based on the SRAM memory cell of fig. 1, and will not be described in detail.

For example, the i-th line to the (i+k-1) -th line may be selected to operate simultaneously, where i, k are positive integers, 1.ltoreq.i.ltoreq.m, 1.ltoreq.k.ltoreq.m, and 1.ltoreq.i+k-1.ltoreq.m. When k=1, select 1 to perform a data backup or data restore operation; when 1< k < m, selecting a plurality of rows to simultaneously perform data backup or data recovery operation; when i=1 and k=m, data backup or data recovery operations are performed simultaneously for all rows of the m-row array.

In the embodiments of the present disclosure, for example, the data backup operation may be performed in a word minimum unit or may be performed in a line minimum unit; for example, the data recovery operation operates in a row minimum unit. The operation with the word as the minimum unit means that all nonvolatile memory sub-units in the selected word or words are operated simultaneously each time the operation is performed on the nonvolatile memory sub-units. Operation in the smallest unit of row refers to all nonvolatile memory sub-cells in a selected row or rows of memory cells operating simultaneously each time a nonvolatile memory sub-cell is operated. Taking the operation in the minimum unit of row as an example, the operation method of data backup and data recovery is described.

In a method of operation of a memory array of at least one embodiment of the present disclosure, for example, multiple rows or all non-volatile static memory cells in the memory array are selected sequentially or simultaneously; and then performing data backup or data recovery on the selected multiple rows or all nonvolatile static memory storage units according to the control signals in the same operation, for example, the same operation is an operation step performed according to the same control signals. When the data backup operation is performed, two data backup operation methods can be classified according to whether the SET operation and the RESET operation are performed simultaneously:

The first method is a dual-step data backup operation method, that is, the SET operation and the RESET operation in the data backup operation are divided into two steps, and there is no requirement on the operation sequence of the SET operation or the RESET operation, and the SET operation may be performed after the RESET operation, or the RESET operation may be performed after the SET operation.

FIG. 10 is a flow diagram of a dual-step data backup operation for a storage array in accordance with at least one embodiment of the present disclosure.

As shown in fig. 10, the unit operation steps of performing the SET operation after the RESET operation are as follows:

step S001: performing RESET operation on all selected units;

step S002: and carrying out SET operation on all selected units.

The dual-step data backup operation method does not need additional data reading control and the like to interactively control external data, and has simple circuit structure and simple and convenient operation. The operation method can carry out data backup operation by taking the word as the minimum unit, can also carry out data backup operation by taking the line minimum unit, and can simultaneously carry out data backup operation on all lines or all lines of the whole array.

FIG. 11 is a flow diagram of a single step data backup operation on a storage array in which a SET operation and a RESET operation are performed simultaneously, in accordance with at least one embodiment of the present disclosure.

As shown in fig. 11, the second method is a single-step data backup operation method, and the steps are as follows:

step S011: reading data stored in the SRAM of the selected cell;

step S012: setting bit lines according to the read data to output corresponding voltages;

the voltage of the corresponding storage node is VSET, and the voltage of the storage node is 0;

step S013: all selected cells perform the RESET operation and the SET operation simultaneously.

In the above embodiment, when performing a single-step data backup operation on the NVSRAM memory cells, data of storage nodes in SRAMs of all selected NVSRAM memory cells are read; setting bit lines according to the read data, respectively outputting corresponding voltages, setting the voltage of the bit line corresponding to the low-level side of the storage node as VSET, and setting the voltage of the bit line corresponding to the high-level side of the storage node as 0; then, bit lines BL and BLN output corresponding voltages, and all selected cells simultaneously perform RESET and SET operations; the non-volatile memory device on the side where the storage node is low potential performs a SET operation, and the non-volatile memory device on the side where the storage node data is high potential performs a RESET operation. The SET and RESET operations are performed simultaneously, so that the operation speed of the array can be improved. The single-step data backup operation method can perform data backup operation by taking a word as a minimum unit and can also perform data backup operation by taking a row unit, but when the operation is performed by taking the row unit, the data backup operation can be performed on one row at most at a time.

For a dual-step data backup operation or a data restore operation, the row operation timing of the memory array can be divided into two methods according to the difference of the row operation timing.

The first mode is row-by-row operation, wherein, when the array is operated, after finishing single operation on all units in one or more rows selected by the array, single operation is carried out on the next row or rows. The single operation may include a data backup operation or a data restore operation, and the sequence number (i) or the number of rows (k) of the selected row may be the same or different at the time of the data backup operation and the data restore operation.

The second method is full-sheet operation, wherein the first step is finished for the full-sheet by a progressive operation mode, and the second step is finished for the full-sheet by a progressive operation mode.

For single step data backup operation, row operation time sequence of the memory array adopts row-by-row operation, and only one row of memory cells is selected at most at the same time for data backup operation.

FIG. 12 is a flow chart of a dual-step data backup operation for a memory array using a progressive operation method in accordance with at least one embodiment of the present disclosure.

As shown in fig. 12, the steps of the operation method are as follows:

the first step, selecting the ith to the (i+k-1) th rows;

Secondly, carrying out RESET operation on the selected k rows simultaneously;

thirdly, performing SET operation on the selected k rows simultaneously;

fourth, judging whether all data are backed up, if not, updating i to be equal to i plus k, and returning to the first step; if yes, the process is ended.

Wherein, i and k are positive integers, i is more than or equal to 1 and less than or equal to m, k is more than or equal to 1 and less than or equal to m, and (i+k-1) is more than or equal to 1 and less than or equal to m. When k=1, select 1 to perform a data backup or data restore operation; when 1< k < m, selecting a plurality of rows to simultaneously perform data backup or data recovery operation; when i=1 and k=m, data backup or data recovery operations are performed simultaneously for all rows of the m-row array. In actual operation, the value 1 is usually selected in the process of initializing i, namely, the operation starts from the 1 st row of the array, or the value is not 1, namely, the operation starts from any row in the array; when the data backup operation is completed in the m line, the whole flow is ended. When the operation method is used for carrying out data backup, additional data reading control and other interactive control with external data are not needed, the circuit structure is simple, the data bus is not occupied, and the operation is simple and convenient.

FIG. 13 is a flow chart of a method of performing data backup on a storage array using RESET and SET split full-chip operation in accordance with at least one embodiment of the present disclosure.

As shown in fig. 13, the steps of the operation method are as follows:

the first step, selecting the ith to the (i+k-1) th rows;

secondly, carrying out RESET operation on the selected k rows simultaneously;

thirdly, judging whether all rows of RESET are finished, if yes, performing a fourth step, otherwise, updating i to be equal to i plus k, and returning to the first step;

step four, selecting x to x+y-1 rows;

fifthly, performing SET operation on the selected y rows simultaneously;

and step six, judging whether all the rows SET are finished, if yes, ending the data backup operation, otherwise, updating x to be equal to x plus y, and returning to the step four.

Wherein i and k are positive integers, i is more than or equal to 1 and less than or equal to m, k is more than or equal to 1 and less than or equal to m, and (i+k-1) is more than or equal to 1 and less than or equal to m; x and y are positive integers, x is more than or equal to 1 and less than or equal to m, y is more than or equal to 1 and less than or equal to m, and (x+y-1) is more than or equal to 1 and less than or equal to m; wherein i and x may be the same or different; k and y may be the same or different. In the operation method, the SET operation and the RESET operation are all performed in a full-chip mode, so that the voltage conversion of the power line CVDD, the first bit line BL and the second bit line BLN is performed only once after the SET operation or the RESET operation of the whole array is completed, the frequency of the voltage conversion is reduced, and the dynamic power consumption of the circuit is reduced.

FIG. 14 is a flow chart of a single step data backup operation of a memory array using a progressive operation method in accordance with at least one embodiment of the present disclosure.

As shown in fig. 14, the data backup method includes the following steps:

step one, selecting an ith row;

step two, reading the ith row data;

thirdly, encoding bit lines according to the read data;

fourthly, simultaneously carrying out RESET operation and SET operation on the selected ith row;

and fifthly, judging whether the data backup is finished, if yes, finishing the data backup operation, adding 1 to i, and returning to the first step.

When the single-step data backup operation method is adopted to backup the data, the RESET operation and the SET operation are simultaneously carried out, so that the data backup speed is improved.

For example, in the above embodiment, the data recovery operation adopts a line-by-line operation method.

FIG. 15 is a flow chart of a method for data recovery for a storage array in accordance with at least one embodiment of the present disclosure. As shown in fig. 15, the data recovery method includes the steps of:

step one, selecting the i-th to i+k-1 rows;

secondly, carrying out data recovery operation on the selected k rows simultaneously;

thirdly, judging whether the data recovery is finished, if not, updating i to be equal to i+k, and returning to the first step; if yes, ending the data recovery operation.

According to the memory array, the electronic device and the operation method of the memory array provided by at least one embodiment of the present disclosure, the power lines of all NVSRAM memory cells in the same column are connected and routed along the column direction of the array, the power lines of all columns are shorted along the row direction of the array, and when a whole row of memory cells perform data recovery at the same time, the current of the power line in each column direction is only the power current of one NVSRAM memory cell, so that the total current on the power lines is reduced, the power voltage is kept stable, and the data recovery success rate can be improved.

It is to be understood that the above embodiments are merely exemplary embodiments employed to illustrate the principles of the present disclosure, however, the present disclosure is not limited thereto. Various modifications and improvements may be made by those skilled in the art without departing from the spirit and substance of the disclosure, and are also considered to be within the scope of the disclosure.

Claims

1. A memory array, comprising:

a plurality of nonvolatile static memory storage units arranged in a plurality of rows and a plurality of columns and configured to perform data storage and data backup and recovery;

a plurality of power lines configured to provide a first power voltage to the plurality of nonvolatile static memory cells, wherein the plurality of power lines are electrically connected to corresponding memory cell columns in a first direction, respectively, and the plurality of power lines are shorted in a second direction, the first direction being different from the second direction;

and the plurality of ground wires are configured to provide a second power supply voltage for the plurality of nonvolatile static memory storage units, wherein the plurality of ground wires are respectively and electrically connected with the corresponding storage unit columns in the first direction, and the plurality of ground wires are in short circuit in the second direction.

2. The memory array of claim 1, further comprising:

a plurality of bit lines electrically connected to the corresponding nonvolatile static memory cell columns in the first direction, respectively, to transmit data signals;

a plurality of first control lines electrically connected with the corresponding nonvolatile static memory cell rows in the second direction respectively to transmit first control signals;

and a plurality of word lines electrically connected with the corresponding nonvolatile static memory cell rows in the second direction respectively so as to transmit word line signals.

3. The memory array of claim 2, wherein each of the plurality of non-volatile static memory storage units comprises a volatile storage sub-unit and a non-volatile storage sub-unit;

the volatile storage subunit is configured to transmit the stored first data and/or second data to the nonvolatile storage subunit for data backup or receive third data and/or fourth data transmitted by the nonvolatile storage subunit for data recovery;

the nonvolatile storage subunit is configured to transmit the stored third data and/or fourth data to the volatile storage subunit for data recovery, or receive the first data and/or second data transmitted by the volatile storage subunit for data backup.

4. The memory array of claim 3, wherein the non-volatile storage sub-unit comprises a first non-volatile storage device, a second non-volatile storage device, a first switching transistor, and a second switching transistor;

the first nonvolatile memory device is connected with the volatile memory subunit through the first switch transistor;

the second nonvolatile memory device is connected to the volatile memory subunit via the second switching transistor.

5. The memory array of claim 4, wherein the first non-volatile storage device is configured to store the third data;

the second nonvolatile memory device is configured to store the fourth data;

the third data and the fourth data are configured as differential signals;

the first nonvolatile memory device and the second nonvolatile memory device are resistance change memory devices or phase change memory devices or magnetoresistive memory devices.

6. The memory array of claim 4, wherein the first plurality of control lines are electrically connected to gates of the first switching transistor and gates of the second switching transistor of each memory cell in the corresponding row of non-volatile static memory cells.

7. The memory array of claim 4 wherein, for each column of nonvolatile static memory cells, the plurality of bit lines includes a first bit line and a second bit line,

the first bit line is electrically connected to a first nonvolatile memory device of each of the nonvolatile static memory cells of each column,

the second bit line is electrically connected to the second nonvolatile memory device of each of the memory cells in each column of nonvolatile static memory cells.

8. The memory array of any of claims 3-6, wherein the volatile memory sub-cells are static random access memory cells.

9. The memory array of claim 8, wherein the sram cell comprises a first inverter, a second inverter, a first access transistor, and a second access transistor;

the first inverter and the second inverter are connected between a power line and a ground line corresponding to the storage unit of the nonvolatile static memory;

the output end of the first inverter is connected with the input end of the second inverter, and the input end of the first inverter is connected with the output end of the second inverter;

The first source drain electrode of the first access transistor is connected with the output end of the first inverter;

the first source drain electrode of the second access transistor is connected with the output end of the second inverter.

10. The memory array of claim 9, wherein for each column of non-volatile static memory cells, the plurality of bit lines comprises a first bit line and a second bit line,

the first bit line is electrically connected with the second source drain electrode of the first access transistor of each memory cell in each column of nonvolatile static memory cells,

the second bit line is electrically connected with a second source drain electrode of a second access transistor of each memory cell in each column of nonvolatile static memory cells.

11. The memory array of claim 9, wherein the first inverter and the second inverter are connected between a power line and a ground line corresponding to a nonvolatile static memory cell where they are located through a power switch assembly.

12. The memory array of claim 11, wherein the power switching component comprises a third switching transistor and a fourth switching transistor, the first inverter being electrically connected to the power line via the third switching transistor, the second inverter being electrically connected to the power line via the fourth switching transistor; or,

The power switch assembly comprises a third switch transistor, and the first inverter and the second inverter are electrically connected with the power line through the third switch transistor.

13. The memory array of claim 12, further comprising:

a plurality of second control lines electrically connected to the power switch assembly of each memory cell of the corresponding nonvolatile static memory cell row in the second direction, respectively, to transmit a second control signal,

the second control signal is used for controlling the switching state of the power switch assembly.

14. The memory array of claim 9, wherein the plurality of word lines are electrically connected to the gates of the first access transistor and the gates of the second access transistor of each memory cell in the corresponding row of non-volatile static memory cells.

15. The memory array of claim 14, wherein the plurality of word lines are further electrically connected to the corresponding power switch assembly to transmit a second control signal,

16. A memory array according to any one of claims 1-3, wherein,

The plurality of power lines are shorted at one or both ends of the memory array in the second direction; and/or

The plurality of ground lines are shorted at one or both ends of the memory array in the second direction.

17. An electronic device comprising a memory array as claimed in any one of claims 1 to 16.

18. A method of operation for the memory array of any of claims 1-16, comprising:

selecting an ith row of nonvolatile static memory cells in the memory array;

performing data backup or data recovery on the i-th row nonvolatile static memory storage unit according to a control signal,

wherein i is a positive integer.

19. The method of operation of a memory array of claim 18, wherein,

selecting a plurality of rows or all non-volatile static memory cells in the memory array;

and carrying out data backup or data recovery on the selected multiple rows or all nonvolatile static memory storage units in the same operation according to control signals.