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WO2025154774A1 - Procédé de fabrication de substrat avec trou d'interconnexion traversant conducteur, pâte métallique et substrat avec trou d'interconnexion traversant conducteur - Google Patents

Procédé de fabrication de substrat avec trou d'interconnexion traversant conducteur, pâte métallique et substrat avec trou d'interconnexion traversant conducteur

Info

Publication number
WO2025154774A1
WO2025154774A1 PCT/JP2025/001207 JP2025001207W WO2025154774A1 WO 2025154774 A1 WO2025154774 A1 WO 2025154774A1 JP 2025001207 W JP2025001207 W JP 2025001207W WO 2025154774 A1 WO2025154774 A1 WO 2025154774A1
Authority
WO
WIPO (PCT)
Prior art keywords
metal
substrate
particles
less
metal particles
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
PCT/JP2025/001207
Other languages
English (en)
Japanese (ja)
Inventor
芳則 江尻
真澄 坂本
千晶 清水
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Resonac Corp
Original Assignee
Resonac Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Resonac Corp filed Critical Resonac Corp
Priority to JP2025524223A priority Critical patent/JP7722619B1/ja
Publication of WO2025154774A1 publication Critical patent/WO2025154774A1/fr
Priority to JP2025127145A priority patent/JP2025160391A/ja
Pending legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits

Definitions

  • the inventors conducted extensive research to achieve the above-mentioned objective, and discovered that the reason for the high connection resistance value after wiring formation is that the flatness (or smoothness) of the conductive vias on the surface of the substrate with conductive vias is low (in other words, the step between the conductive via portion and the substrate surface is large). Based on this knowledge, the inventors investigated methods for reducing the step, and discovered that by forming conductive vias through a specific process using a metal paste containing specific metal particles and a volatile solvent, a sufficiently low connection resistance value can be obtained even when wiring connected to the conductive vias is further formed, and that the resulting wiring substrate has excellent connection reliability, which led to the completion of the present invention.
  • a method for manufacturing a substrate with conductive vias comprising: a step a) of preparing a substrate having a hole; and providing a metal paste portion containing metal particles and a volatile solvent so as to fill the inside of the hole and cover at least the surface of the substrate around the hole; a step b) of heating the metal paste portion to remove a part of the volatile solvent; a step c) of removing a part of the metal paste portion after heating so as to expose the surface, thereby forming a conductive via precursor containing the metal particles and the remainder of the volatile solvent and having a flattened exposed surface inside the hole; and a step d) of baking the conductive via precursor, wherein the metal particles include first metal particles having a volume average particle size of 0.8 ⁇ m or more and second metal particles having a volume average particle size of 0.5 ⁇ m or less, a metal particle concentration of the metal paste portion provided
  • the above metal paste has sufficient printability, and the metal paste portion can be efficiently formed in the above manufacturing method for a substrate with conductive vias.
  • a substrate with conductive vias comprising: a substrate having a through hole; and a conductive via provided in the through hole, the conductive via comprising a sintered body of the metal paste according to any one of [4] to [6].
  • the present invention provides a method for manufacturing a substrate with conductive vias that can exhibit a sufficiently low connection resistance even after wiring is formed, and the resulting wiring board has excellent connection reliability, as well as a metal paste that can be used in the method, and a substrate with conductive vias.
  • the metal paste of the present embodiment contains metal particles and a volatile solvent, and the content of the metal particles is 95.0 mass% or more based on the total amount of the metal paste.
  • the metal paste of the present embodiment can be used to form a metal paste portion in a manufacturing method of a substrate with conductive vias, which will be described later.
  • the content of metal particles in the metal paste of this embodiment may be 95.2% by mass or more, 95.5% by mass or more, 95.7% by mass or more, or 96% by mass or more based on the total amount of the metal paste, and may be 98% by mass or less, 97% by mass or less, or 96.5% by mass or less, or may be 95.0 to 98% by mass, 95.2 to 97% by mass, or 95.7 to 96.5% by mass.
  • the metal particles include nickel, silver, copper, gold, palladium, platinum, solder, and the like.
  • the metal particles may include a plurality of metals, such as silver-coated copper particles.
  • the metal paste includes copper particles, it is easy to obtain a conductor having sufficient conductivity and a resistance value that is unlikely to increase even when subjected to temperature changes, and a substrate having a through electrode having sufficient conductivity and excellent connection reliability.
  • the metal particles include first metal particles having a volume average particle size of 0.8 ⁇ m or more and second metal particles having a volume average particle size of 0.5 ⁇ m or less.
  • the first copper particles may contain particles such as spherical particles with an aspect ratio of 2 or less in an amount of 40% by mass or more, 50% by mass or more, 60% by mass or more, 80% by mass or more, or 100% by mass, or may be 40 to 90% by mass, 50 to 80% by mass, or 60 to 70% by mass.
  • the aspect ratio (major axis/minor axis) of the particles can be determined, for example, by observing an SEM image of the particles and measuring the major axis and minor axis (e.g., thickness).
  • the metal paste of this embodiment may contain flake-shaped copper particles as the first copper particles from the viewpoint of suppressing voids and cracks by reducing shrinkage due to firing, and may contain spherical copper particles and flaky copper particles from the viewpoint of lowering the viscosity of the metal paste to improve filling into microvias and suppressing voids and cracks by reducing shrinkage due to firing.
  • the mass ratio thereof (spherical copper particles)/(flaky copper particles) may be 1 to 9, 1.2 to 2.5, or 1.4 to 4.
  • the mass ratio (spherical copper particles)/(flaky copper particles) may be 0.6 to 9, 1.0 to 4.0, or 1.5 to 2.4.
  • the copper particles may contain wet copper powder and atomized copper powder. In this case, it is possible to improve the printability of the metal paste, reduce the step between the conductive via portion to be formed and the substrate surface, and easily suppress the fluctuation of the connection resistance even after a reliability test (for example, a temperature cycle test). The reason for obtaining such an effect is presumed to be the following.
  • the coexistence of wet copper powder, which is easily bonded to the second copper particles and has a uniform particle size, and atomized copper powder, which has a wide particle size distribution, allows the wet copper powder to bond between the atomized copper powder particles while also bonding with the second copper particles, forming a strong sintered body with a close-packed structure, and suppressing the occurrence of voids and cracks as well as dents due to the suppression of shrinkage during sintering.
  • the atomized copper powder may have a D90/D50 of 1.6 or more, 1.7 or more, or 1.8 or more.
  • the second copper particles can act as copper particles that effectively bond the first copper particles together.
  • the second copper particles have better sinterability than the first copper particles and can have the function of promoting sintering of the copper particles. For example, it becomes possible to sinter the copper particles at a lower temperature compared to when the first copper particles are used alone as the copper particles.
  • the second copper particles may be synthetic or commercially available.
  • Examples of commercially available second copper particles include CH0200L1 (manufactured by Mitsui Kinzoku Co., Ltd., product name, average particle size (D50): 200 nm, spherical) and Tn-Cu100 (manufactured by Taiyo Nippon Sanso Co., Ltd., average particle size (D50): 120 nm, spherical).
  • the amount of the surface treatment agent may be an amount that adheres to the surface of the second copper particles in a monolayer to trilayer form.
  • the amount of the surface treatment agent may be 0.07% by mass or more, 0.10% by mass or more, or 0.2% by mass or more, and may be 2.1% by mass or less, 1.6% by mass or less, or 1.1% by mass or less.
  • the amount of the surface treatment agent of the second copper particles can be calculated by the method described above for the first copper particles. The same applies to the specific surface area, the molecular weight of the surface treatment agent, and the minimum coverage area of the surface treatment agent.
  • the metal paste of this embodiment may contain a solvent having a vapor pressure of 4 Pa or more and 30 Pa or less at 20°C (hereinafter also referred to as a "high vapor pressure solvent") as a volatile solvent from the viewpoint of printability and suppressing volumetric shrinkage before and after firing the conductive via precursor (for example, between step C of forming the conductive via precursor and step d of firing the conductive via precursor) to suppress voids and cracks.
  • the high vapor pressure solvent may be used alone or in combination of two or more types.
  • Low vapor pressure solvents include isobornylcyclohexanol (MTPH), dimethyl phthalate, and diethylene glycol mono-n-butyl ether.
  • the content of the volatile solvent in the metal paste of this embodiment may be 2 mass% or more, 3 mass% or more, or 3.5 mass% or more, and may be 5 mass% or less, 4.8 mass% or less, 4.5 mass% or less, 4.3 mass% or less, or 4 mass% or less, or may be 2 to 5 mass%, 3 to 4.8 mass%, or 3.5 to 4.5 mass%, based on the total mass of the metal paste.
  • the metal paste of this embodiment may contain a resin component such as an epoxy resin.
  • the metal paste of this embodiment may have a resin component content of 10 mass % or less, or 5 mass % or less, or may not contain a resin component.
  • the second copper particles, the surface treatment agent, and the dispersion medium may be mixed in advance, and a dispersion treatment may be performed to prepare a dispersion of the second copper particles, and the first copper particles, and if necessary, other metal particles and any additives may be further mixed to prepare the dispersion.
  • a dispersion treatment may be performed to prepare a dispersion of the second copper particles, and the first copper particles, and if necessary, other metal particles and any additives may be further mixed to prepare the dispersion.
  • the dispersion of the second copper particles may be subjected to a classification operation to remove agglomerates.
  • the method for manufacturing a substrate with conductive vias of the present embodiment includes the steps of: preparing a substrate having holes provided therein; providing a metal paste portion containing metal particles and a volatile solvent so as to fill the insides of the holes while covering at least the surface of the substrate around the holes; heating the metal paste portion to remove a portion of the volatile solvent; removing a portion of the metal paste portion after heating so as to expose the surface, thereby forming a conductive via precursor containing metal particles and the remainder of the volatile solvent and having a flattened exposed surface inside the holes; and baking the conductive via precursor to form conductive vias, wherein the metal particles include first metal particles having a volume average particle size of 0.8 ⁇ m or more and second metal particles having a volume average particle size of 0.5 ⁇ m or less, the metal particle concentration of the metal paste portion provided in the step a is 95.0 mass % or more, and the content of the second metal particles in the metal paste portion provided in the step
  • FIGS. 1 to 3 are schematic diagrams showing an example of a method for manufacturing a substrate with conductive vias according to this embodiment.
  • FIG. 1 shows an example of a substrate used in the method for manufacturing a substrate with conductive vias.
  • the method for manufacturing a substrate with conductive vias according to this embodiment will be described with reference to these figures.
  • this embodiment shows an example in which the metal paste contains the above-mentioned copper particles as metal particles, so the copper particles, copper layer, and copper sintered body can be read as metal particles, metal layer, and metal sintered body, respectively.
  • Examples of the substrate having holes prepared in this process include an organic substrate, a silicon substrate, a glass substrate, a ceramic substrate, a printed wiring board, and a semiconductor package substrate.
  • the silicon substrate may be a substrate made of polycrystalline silicon, or may be a rectangular silicon substrate made of polycrystalline silicon.
  • the holes may be through holes or non-through holes.
  • a silicon substrate 40 having a silicon wafer 1 having a through hole 30 and a metal coating 2 provided on the wall surface of the through hole and the surface of the silicon wafer 1 can be prepared.
  • the through hole 30 is connected to both main surfaces of the silicon substrate 40.
  • An example of providing a conductive via in the silicon substrate 40 will be described, but the following description may be replaced with another insulating substrate instead of the silicon wafer.
  • the number of through holes 30 provided in the silicon substrate 40 may be 100 or more, 200 or more, or 300 or more per 1 cm 2 of the main surface of the substrate, from the viewpoint of increasing the density of the resulting semiconductor device.
  • the metal coating 2 may be provided on both main surfaces of the silicon wafer 1 and on the wall surfaces of the through holes 30, or on at least one of the main surfaces of the silicon wafer 1 and on the wall surfaces of the through holes 30, or may be provided only on the wall surfaces of the through holes 30, or may not be provided at all.
  • the silicon substrate 40 has the metal coating 2 on both main surfaces of the silicon wafer 1 and on the wall surfaces of the through holes 30.
  • a conductive via which is a through electrode
  • grinding methods include mechanical polishing and chemical-mechanical polishing.
  • the composition of the metal particles and volatile solvent in the metal particle-containing layer can be appropriately set so as to satisfy the conditions for the metal paste of this embodiment described above.
  • the thickness of the metal particle-containing layer may be 100 ⁇ m or less. From the viewpoint of easily ensuring sufficient filling of the through holes or non-through holes, the thickness of the metal particle-containing layer may be 30 ⁇ m or more, 40 ⁇ m or more, or 50 ⁇ m or more.
  • the metal particle-containing layer may have a waviness (height difference) on the surface opposite the support film of 20 ⁇ m or less, or 10 ⁇ m or less.
  • a waviness (height difference)
  • the metal particle film is pressed to fill the holes in the base with the metal particle composition, it becomes easier to simultaneously fill the numerous through holes or non-through holes present in the base, making it easier to reduce the number of through holes or non-through holes that are completely unfilled and through holes or non-through holes where voids are partially generated.
  • the waviness (height difference) can be evaluated by a non-contact method using a laser displacement meter or the like.
  • Methods for applying metal paste include, for example, screen printing, transfer printing, offset printing, jet printing, and application using a dispenser, jet dispenser, needle dispenser, comma coater, slit coater, die coater, gravure coater, slit coat, letterpress printing, intaglio printing, gravure printing, stencil printing, soft lithography, bar coat, applicator, particle deposition method, spray coater, spin coater, dip coater, etc.
  • the process of drying the coating film to form the metal particle-containing layer can be carried out at room temperature or at a temperature between room temperature and 100°C, and the atmosphere may be air or nitrogen.
  • step a the metal particle film is pressed against the silicon substrate 40 so that the metal particle-containing layer 3p of the metal particle film is in contact with the silicon substrate 40, and the through-holes 30 of the silicon substrate 40 are filled with metal paste.
  • the metal particle film and the silicon substrate 40 can be sandwiched and pressed from above and below by a pressure jig A.
  • the pressure jig A is not particularly limited, but may be a commercially available one, and may also be made using a metal member having a flat portion.
  • a pressure jig having two or more of the above-mentioned metal members can press the metal particle film against the silicon substrate by sandwiching the metal particle film and the silicon substrate between the metal members arranged so that the flat portions face each other.
  • the pressure jig A may have a mechanism for adjusting the pressure applied to the metal particle film and the silicon substrate.
  • a spring or the like can be used as the pressure adjustment means.
  • a vacuum pressing method in which pressing is performed in a vacuum atmosphere may be used.
  • the pressing conditions can be, for example, a temperature between room temperature and 50°C or less, and the atmosphere can be a vacuum, air, or nitrogen.
  • the metal particle film can be pressed onto the silicon substrate after maintaining a vacuum of 1000 Pa or less, or a vacuum of 200 Pa or less.
  • the pressure of the pressing tool when pressing the metal particle film onto the silicon substrate can be any pressure within the range in which the silicon wafer does not crack, and can be, for example, 0.01 MPa or more, 0.1 MPa or more, or 1 MPa or more.
  • Step b the metal paste portion is heated to remove a part of the volatile solvent, in other words, the metal paste portion is heated so that a part of the volatile solvent remains.
  • the metal paste portion can be heated after peeling off the support film.
  • a hot plate for example, a hot plate, a hot air dryer, a hot air heating furnace, a nitrogen dryer, an infrared dryer, an infrared heating furnace, a far-infrared heating furnace, a microwave heating device, a laser heating device, an electromagnetic heating device, a heater heating device, a steam heating furnace, a hot plate press device, etc. can be used.
  • the heating temperature may be 70°C or higher but lower than 100°C, or 80°C or higher but lower than 95°C, from the viewpoint of suppressing oxidation of the copper particles, and the heating time may be 5 to 60 minutes, or 10 to 30 minutes, from the viewpoint of suppressing oxidation of the copper particles.
  • heating may be performed so that the concentration of metal particles in the metal paste portion becomes 96 mass % or more, 97.5 mass % or more, or 98 mass % or more.
  • Step c In this step, as shown in (a) to (d) of Fig. 3, the metal paste portion 3a after heating obtained in step b is planarized (or smoothed) while removing the metal paste covering the surface of the substrate, thereby forming a conductive via precursor 3b having a planarized exposed surface VP1 and containing metal particles and a remainder of the volatile solvent inside the hole (through hole 30) ((d) of Fig. 3).
  • the metal paste portion can be removed using a rubber squeegee 42, for example, as shown in (b) and (d) of Fig. 3. This allows a part of the metal paste portion (the metal paste covering the surface of the substrate and the metal paste protruding from the hole) to be removed so that the surface SP0 of the substrate 40 and the exposed surface VP1 of the conductive via precursor 3b are flush with each other.
  • Another method is removal using a metal squeegee such as SUS.
  • the step between the surface SP0 of the substrate 40 and the exposed surface VP1 of the conductive via precursor 3b may be 5 ⁇ m or less, or may be 3 ⁇ m or less, in a direction perpendicular to the substrate surface.
  • the average step calculated by the following method may be in the above range. (Average step height) An image of a cross section passing through the center of the hole (via) is obtained, and the cross-sectional image is binarized to determine the cross-sectional area Sa surrounded by the inner wall of the hole (via), the exposed surface of the conductive via precursor, and the opening surface of the hole (via), and the average step difference is calculated by dividing this by the spacing Wa of the inner walls of the hole.
  • the conductive via precursor 3b formed in step c is fired.
  • the metal body may include a copper sintered body having a porous structure.
  • the porosity of the conductive via may be 7% or less, 1.0 to 6.5%, or 1.5 to 5.0%, from the viewpoint of suppressing the penetration of a chemical solution into the copper sintered body when immersed in a chemical solution such as a resist stripper or a plating pretreatment in a later step and improving reliability.
  • the porosity of the copper sintered body may be in the above range. The porosity can be determined by the method described in the examples.
  • the maximum temperature reached during the heat treatment may be 150°C or higher, and may be 350°C or lower, 300°C or lower, or 260°C or lower, from the viewpoint of reducing thermal damage to each component and improving yield. If the maximum temperature reached is 150°C or higher, sintering tends to proceed sufficiently when the maximum temperature is held for 60 minutes or less. From the viewpoint of volatilizing all volatile solvents and improving yield, the maximum temperature held for may be 1 minute or more, and may be 60 minutes or less, 40 minutes or less, or 30 minutes or less.
  • the conductive via precursor may be fired without pressure or with pressure.
  • the pressure in an atmosphere containing pure hydrogen gas, the pressure may be 0.05 MPa or more, 0.1 MPa or more, or 0.3 MPa or more, and 20 MPa or less, 15 MPa or less, or 10 MPa or less.
  • the pressure in an atmosphere containing nitrogen gas, the pressure may be 1 MPa or more, or 3 MPa or more, and 20 MPa or less, 15 MPa or less, or 10 MPa or less.
  • the pressure should be 0.05 MPa or more, and when using nitrogen gas, 1 MPa or more, which makes it easier to suppress the generation of voids in the conductive via formed in the center of the through hole 30, and makes it easier to obtain a conductive via with good conductivity.
  • the silicon substrate 40 has a metal coating 2, by setting the pressure to the above lower limit or more, it makes it easier to improve the bonding strength between the metal coating 2 and the conductive via.
  • the copper sintered body contained in the metal body may have a copper element ratio of 95 mass% or more, 97 mass% or more, 98 mass% or more, or 100 mass% among the constituent elements excluding light elements. If the copper element ratio in the copper sintered body is within the above range, the formation of intermetallic compounds or the precipitation of different elements at the metallic copper crystal boundaries can be suppressed, the properties of the metallic copper that constitutes the copper sintered body are likely to be strengthened, and even better connection reliability is likely to be obtained.
  • the step between the surface SP0 of the substrate 40 and the exposed surface VP2 of the conductive via 3c (or the recess of the conductive via 3c) may be 5 ⁇ m or less in the direction perpendicular to the substrate surface, or may be 3 ⁇ m or less.
  • the average step calculated by the following method may be in the above range. (Average step height) An image of a cross section passing through the center of the hole (via) is obtained, and the cross-sectional image is binarized to determine the cross-sectional area Sb surrounded by the inner wall of the hole (via), the exposed surface of the conductive via, and the opening surface of the hole (via), and the average step is calculated by dividing this by the spacing Wb of the inner walls of the hole.
  • Methods for removing conductors include chemical polishing, mechanical polishing, chemical-mechanical polishing, fly-cutting, and plasma treatment.
  • Fly-cutting refers to cutting and flattening using a surface planer.
  • Methods for laminating a film-like negative photosensitive resin composition include using a roll laminator, laminator, press, etc.
  • the pressure may be 0.1 MPa or more, 0.4 MPa or more, or 1 MPa or more from the viewpoint of making it easier to impregnate the conductive vias with the photosensitive resin composition.
  • the upper limit of the pressure may be 10 MPa or less from the viewpoint of minimizing the effect on the substrate.
  • step S2 may further include step S2-3a of curing the negative-type photosensitive resin composition contained in the resin-containing portion.
  • liquid negative photosensitive compositions such as PSR-4000 G24K/CA-40 G24 (product name, manufactured by Taiyo Ink Mfg. Co., Ltd.), TER-20HF (product name, manufactured by Taiyo Ink Mfg. Co., Ltd.), and TMMR NA1000PM (product name, manufactured by Tokyo Ohka Kogyo Co., Ltd.) may be used.
  • Methods for applying the liquid negative photosensitive composition include, for example, screen printing, transfer printing, offset printing, jet printing, dispenser, jet dispenser, needle dispenser, comma coater, slit coater, die coater, gravure coater, slit coat, letterpress printing, intaglio printing, gravure printing, stencil printing, soft lithography, bar coater, applicator, particle deposition method, spray coater, spin coater, dip coater, etc. From the viewpoints of application workability and uniformity of the coating thickness, application may be performed by screen printing or spin coat.
  • the depth to which the conductive vias are impregnated with the photosensitive resin composition and the method for developing the coating of the liquid negative photosensitive resin composition may be the same as in steps S2-1a and S2-2a described above.
  • step S2-2c may be followed by step S2-3c, in which the positive-type photosensitive resin composition contained in the resin-containing portion is thermally cured.
  • step S2-4c may be followed by step S2-3c, in which at least the exposed surfaces of the conductive vias are desmeared, similar to step S2-4a described above.
  • the metal pastes obtained in Preparation Examples A to W and Comparative Preparation Examples A to I were evaluated for viscosity, printability, bondability, and volume resistivity of the sintered bodies according to the following methods.
  • the resistance value of a predetermined number of vias connected together was measured as the initial resistance value of the test piece 55.
  • the number of vias is set according to the via diameter as follows. Based on this connected resistance value, the initial resistance value was evaluated according to the following criteria. A rating of B or higher can be judged as good.
  • connection reliability The test piece 55 was set in a temperature cycle tester (TSA-72SE-W, manufactured by Espec Corporation), and a temperature cycle connection reliability test was performed under the following conditions: low temperature side: -55°C, 15 minutes, room temperature: 2 minutes, high temperature side: 125°C, 15 minutes, defrost cycle: automatic, number of cycles: 50, 100, 300, 500, 1000 cycles.
  • TSA-72SE-W temperature cycle tester
  • defrost cycle automatic, number of cycles: 50, 100, 300, 500, 1000 cycles.
  • the connection reliability was evaluated according to the following criteria.
  • Judgment criteria A: The rate of resistance change is less than 1% of the initial resistance value.
  • B The rate of resistance change is 1% or more and less than 3% of the initial resistance value.
  • C The rate of resistance change is 3% or more and less than 5% of the initial resistance value.
  • D The rate of resistance change is 5% or more and less than 10% of the initial resistance value.
  • E The rate of resistance change is 10% or more and less than 20% of the initial resistance value.
  • F The rate of resistance change is 20% or more of the initial resistance value.
  • the test piece 55 was visually inspected to check for the presence or absence of cracks in the silicon substrate.
  • Observation 1 For the silicon substrate with conductive vias prepared in Example 1, a focused ion beam processing observation device (manufactured by Hitachi High-Technologies Corporation, product name: MI4050) was used to expose the cross section of the central part of the conductive via of the silicon substrate with conductive vias by a focused ion beam, and the cross section was observed. For the observation, a scanning electron microscope (manufactured by Hitachi High-Technologies Corporation, product name: S-3700N) was used to take a cross-sectional image of the copper sintered body at a magnification of 5,000 times and 20,000 times (see FIG. 6). The images shown in FIG.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Conductive Materials (AREA)
  • Parts Printed On Printed Circuit Boards (AREA)
  • Powder Metallurgy (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)

Abstract

L'invention concerne un procédé de fabrication d'un substrat avec un trou d'interconnexion traversant conducteur, ledit procédé comprenant : une étape (a) de préparation d'un substrat pourvu d'un trou, et de fourniture d'une partie de pâte métallique contenant des particules métalliques et un solvant volatil de façon à remplir l'intérieur du trou et à recouvrir au moins une surface autour du trou du substrat ; une étape (b) de chauffage de la partie de pâte métallique pour éliminer une partie du solvant volatil ; une étape (c) d'élimination d'une partie de la partie de pâte métallique après chauffage de telle sorte que la surface est exposée, formant ainsi, à l'intérieur du trou, un précurseur de trou d'interconnexion traversant conducteur qui a une surface exposée aplatie et qui contient un reste des particules métalliques et du solvant volatil ; et une étape (d) de calcination du précurseur de trou d'interconnexion traversant conducteur. Les particules métalliques comprennent des premières particules métalliques ayant un diamètre de particule moyen en volume de 0,8 µm ou plus, et des secondes particules métalliques ayant un diamètre de particule moyen en volume inférieur ou égal à 0,5 µm. La concentration de particules métalliques de la partie de pâte métallique fournie à l'étape (a) est de 95,0% en masse ou plus. La teneur en secondes particules métalliques dans la partie de pâte métallique fournie à l'étape (a) est de 50% en masse ou moins sur la base de la quantité totale des particules métalliques.　Ce procédé de fabrication d'un substrat avec un trou d'interconnexion traversant conducteur est également utile en tant que technique pour réduire une charge environnementale due au placage.
PCT/JP2025/001207 2024-01-17 2025-01-16 Procédé de fabrication de substrat avec trou d'interconnexion traversant conducteur, pâte métallique et substrat avec trou d'interconnexion traversant conducteur Pending WO2025154774A1 (fr)

Priority Applications (2)

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JP2025524223A JP7722619B1 (ja) 2024-01-17 2025-01-16 導電ビア付基板の製造方法
JP2025127145A JP2025160391A (ja) 2024-01-17 2025-07-30 金属ペースト及び導電ビア付基板

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JP2024005289 2024-01-17
JP2024-005289 2024-01-17

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WO2025154774A1 true WO2025154774A1 (fr) 2025-07-24

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PCT/JP2024/035330 Pending WO2025154333A1 (fr) 2024-01-17 2024-10-02 Procédé de fabrication de substrat à trous d'interconnexion conducteurs, pâte métallique et substrat à trous d'interconnexion conducteurs
PCT/JP2025/001207 Pending WO2025154774A1 (fr) 2024-01-17 2025-01-16 Procédé de fabrication de substrat avec trou d'interconnexion traversant conducteur, pâte métallique et substrat avec trou d'interconnexion traversant conducteur

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PCT/JP2024/035330 Pending WO2025154333A1 (fr) 2024-01-17 2024-10-02 Procédé de fabrication de substrat à trous d'interconnexion conducteurs, pâte métallique et substrat à trous d'interconnexion conducteurs

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JP2010123830A (ja) * 2008-11-21 2010-06-03 Panasonic Corp プリント配線板とその製造方法
CN104332447A (zh) * 2013-07-22 2015-02-04 赛方塊股份有限公司 电极的构造,构成材料及其制造方法
US20160128201A1 (en) * 2014-11-04 2016-05-05 Intrinsiq Materials, Inc. Method for forming vias on printed circuit boards
WO2020217358A1 (fr) * 2019-04-24 2020-10-29 日立化成株式会社 Procédé de fabrication de substrat de trou traversant rempli de conducteurs, et substrat de trou traversant rempli de conducteurs
WO2020217361A1 (fr) * 2019-04-24 2020-10-29 日立化成株式会社 Procédé de production d'un substrat ayant des trous d'interconnexion traversant le silicium, substrat ayant des trous d'interconnexion traversant le silicium, et pâte de cuivre destinée au trou d'interconnexion traversant le silicium
WO2022138271A1 (fr) * 2020-12-25 2022-06-30 田中貴金属工業株式会社 Carte d'interposition et procédé de fabrication d'un dispositif au moyen de ladite carte d'interposition

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JP7484437B2 (ja) * 2020-06-02 2024-05-16 株式会社レゾナック 金属粒子フィルム、金属粒子フィルムの製造方法、及び、貫通電極を有する基体の製造方法
WO2021245912A1 (fr) * 2020-06-05 2021-12-09 三ツ星ベルト株式会社 Procédé de production d'un substrat de trous d'interconnexion rempli et kit de pâte conductrice

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2003007370A1 (fr) * 2001-07-12 2003-01-23 Hitachi, Ltd. Substrat de cablage en verre et procede de fabrication associe, pate conductrice et module de semi-conducteurs utilises pour ce substrat de cablage en verre, ainsi que procede de formation d'un substrat de cablage et d'un conducteur
JP2010123830A (ja) * 2008-11-21 2010-06-03 Panasonic Corp プリント配線板とその製造方法
CN104332447A (zh) * 2013-07-22 2015-02-04 赛方塊股份有限公司 电极的构造,构成材料及其制造方法
US20160128201A1 (en) * 2014-11-04 2016-05-05 Intrinsiq Materials, Inc. Method for forming vias on printed circuit boards
WO2020217358A1 (fr) * 2019-04-24 2020-10-29 日立化成株式会社 Procédé de fabrication de substrat de trou traversant rempli de conducteurs, et substrat de trou traversant rempli de conducteurs
WO2020217361A1 (fr) * 2019-04-24 2020-10-29 日立化成株式会社 Procédé de production d'un substrat ayant des trous d'interconnexion traversant le silicium, substrat ayant des trous d'interconnexion traversant le silicium, et pâte de cuivre destinée au trou d'interconnexion traversant le silicium
WO2022138271A1 (fr) * 2020-12-25 2022-06-30 田中貴金属工業株式会社 Carte d'interposition et procédé de fabrication d'un dispositif au moyen de ladite carte d'interposition

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JP7722619B1 (ja) 2025-08-13
JPWO2025154774A1 (fr) 2025-07-24
WO2025154333A1 (fr) 2025-07-24

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