[go: up one dir, main page]

WO2025142996A1 - Dispositif de détection de lumière - Google Patents

Dispositif de détection de lumière Download PDF

Info

Publication number
WO2025142996A1
WO2025142996A1 PCT/JP2024/045854 JP2024045854W WO2025142996A1 WO 2025142996 A1 WO2025142996 A1 WO 2025142996A1 JP 2024045854 W JP2024045854 W JP 2024045854W WO 2025142996 A1 WO2025142996 A1 WO 2025142996A1
Authority
WO
WIPO (PCT)
Prior art keywords
transistor
contacts
substrate
wiring
floating diffusion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
PCT/JP2024/045854
Other languages
English (en)
Japanese (ja)
Inventor
泰啓 榎本
雅之 高瀬
真知子 亀谷
弘貴 山崎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Semiconductor Solutions Corp
Original Assignee
Sony Semiconductor Solutions Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Semiconductor Solutions Corp filed Critical Sony Semiconductor Solutions Corp
Publication of WO2025142996A1 publication Critical patent/WO2025142996A1/fr
Pending legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/10—Integrated devices
    • H10F39/12—Image sensors
    • H10F39/18—Complementary metal-oxide-semiconductor [CMOS] image sensors; Photodiode array image sensors

Definitions

  • This disclosure relates to a light detection device.
  • Patent Document 1 describes arranging sensor pixels and readout circuits on separate substrates.
  • Patent Document 2 describes reducing the parasitic capacitance between the through-wires extending from the floating diffusion region in the stacking direction and the through-wires extending from the gate of the transfer transistor in the stacking direction by increasing the distance between the two through-wires mentioned above using a wiring layer provided between the two stacked substrates.
  • this disclosure provides a photodetector device that can suppress variations in parasitic capacitance.
  • the first wiring layer may be connected to the corresponding third contact and may extend to a side closer to the first contact than a connection point with the corresponding third contact.
  • the two first contacts are connected to the two floating diffusion regions;
  • the first wiring layer arranged on one end side in the one direction is arranged closer to the first contact arranged on one end side in the one direction than the other first wiring layers;
  • the first wiring layer arranged on the other end side in the one direction may be arranged to a position closer to the first contact arranged on the other end side in the one direction than the other first wiring layers.
  • the device may also include two second wiring layers that are connected to the two first contacts extending from the two floating diffusion regions in the stacking direction and that are arranged along the two first wiring layers that are arranged on one end side and the other end side of the one direction.
  • the semiconductor device may further include a fourth wiring layer connected to the first contact and disposed in a direction away from the amplifying transistor in a plan view.
  • a plurality of photoelectric conversion elements each accumulating an electric charge according to the amount of incident light; a floating diffusion region shared by the plurality of photoelectric conversion elements and holding charges transferred from the plurality of photoelectric conversion elements; a plurality of transfer transistors that transfer charges stored in the plurality of photoelectric conversion elements to the floating diffusion region; a first contact extending in a stacking direction from the floating diffusion region; a plurality of second contacts extending in a stacking direction from the gates of the plurality of transfer transistors; a plurality of first wiring layers respectively connected to the plurality of second contacts; a second wiring layer disposed along at least a part of the first wiring layers among the plurality of first wiring layers and adjusting a capacitance between the plurality of first wiring layers and the first contact; A light detection device is provided.
  • the second wiring layer may be disposed in a location that reduces variation in capacitance between the plurality of first wiring layers and the first contacts.
  • the first wiring layers are arranged around the first contact, A plurality of the second wiring layers may be disposed along two or more of the first wiring layers.
  • the second wiring layer may be disposed between two adjacent first wiring layers among the plurality of first wiring layers.
  • the second wiring layer may be disposed opposite the first contact.
  • first substrate on which the photoelectric conversion element, the transfer transistor, and the floating diffusion region are disposed; a second substrate laminated on the first substrate, on which a pixel transistor is disposed for generating a pixel signal corresponding to the charge held in the floating diffusion region;
  • the first wiring layer and the second wiring layer may be disposed in a first wiring region between the first substrate and the second substrate.
  • a first insulating layer covering the first wiring layer and the second wiring layer in the first wiring region may have a higher dielectric constant than a second insulating layer covering the third wiring layer in the second wiring region.
  • the second wiring layer may transmit a boost voltage, a power supply voltage, a ground voltage, or a signal connected to a conversion efficiency switching transistor.
  • the second wiring layer may include polysilicon, tungsten (W), copper (Cu), or aluminum (Al).
  • a plurality of photoelectric conversion elements each accumulating an electric charge according to the amount of incident light; a floating diffusion region shared by the plurality of photoelectric conversion elements and holding charges transferred from the plurality of photoelectric conversion elements; a plurality of transfer transistors that transfer charges stored in the plurality of photoelectric conversion elements to the floating diffusion region; a first substrate on which the photoelectric conversion element, the transfer transistor, and the floating diffusion region are disposed; a second substrate that is stacked on the first substrate and has a pixel transistor disposed thereon, the pixel transistor being used to generate a pixel signal corresponding to the charge held in the floating diffusion region; a plurality of contacts connecting the first substrate and the second substrate; There is provided a photodetector device, in which at least one transistor constituting the pixel transistor is disposed in a position not facing the plurality of contacts in a plan view.
  • the multiple contacts may be arranged diagonally across the pixel transistor when viewed in a plan view.
  • Each of the plurality of pixels includes the photoelectric conversion element, the floating diffusion region, and the transfer transistor, the pixel transistor includes an amplification transistor, a selection transistor, a reset transistor, and a conversion efficiency switching transistor; the reset transistor and the conversion efficiency switching transistor are connected in series or in parallel;
  • the floating diffusion region may be connected to the source of the conversion efficiency switching transistor and the gate of the amplifying transistor, or may be connected to the source of the reset transistor, the drain of the conversion efficiency switching transistor, and the gate of the amplifying transistor.
  • FIG. 1 is a diagram showing a schematic configuration of a light detection device according to the present disclosure.
  • 1 is a circuit diagram of a pixel circuit according to the present disclosure.
  • FIG. 2 is a diagram showing an example of a vertical cross-sectional configuration of a light detection device according to the present disclosure.
  • FIG. 2 is a planar layout diagram of a first substrate and an intermediate layer of the photodetector according to the first embodiment.
  • FIG. 11 is a planar layout diagram of a first substrate and an intermediate layer of a photodetector according to a second embodiment.
  • FIG. 11 is a planar layout diagram of a first substrate and an intermediate layer of a photodetector according to a third embodiment.
  • FIG. 13 is a layout diagram showing a first substrate, an intermediate layer, and a second substrate of a photodetector according to a fourth embodiment in a plan view.
  • FIG. 13 is a planar layout diagram of a first substrate and an intermediate layer of a photodetector according to a fifth embodiment.
  • FIG. 13 is a layout diagram of a second substrate of the photodetector according to the fifth embodiment.
  • 10A is a cross-sectional view taken along line AA in FIG. 8
  • FIG. 10B is a cross-sectional view taken along line BB in FIG. 13 is a diagram showing parasitic capacitances between an FD wiring layer, a TG wiring layer, and an adjustment wiring layer.
  • FIG. 13 is a layout diagram of a second substrate of the photodetector according to the sixth embodiment.
  • FIG. 11 is a layout diagram of a second substrate of a photodetector according to a comparative example.
  • 18B is a cross-sectional view taken along line AA in FIG. 18A.
  • 13 is a diagram for explaining the positional relationship between an amplifying transistor and a TG contact when the amplifying transistor and the selection transistor are arranged horizontally.
  • FIG. 11 is a layout diagram of a second substrate of a photodetector according to a comparative example.
  • 18B is a cross-sectional view taken along line AA in FIG. 18A.
  • the light detection device will be described with reference to the drawings.
  • the following description will focus on the main components of the light detection device, but the light detection device may have components and functions that are not shown or described.
  • the following description does not exclude components and functions that are not shown or described.
  • FIG. 1 is a diagram showing a schematic configuration of a light detection device 1 according to the present disclosure.
  • the light detection device 1 includes three substrates, namely, a first substrate 10, a second substrate 20, and a third substrate 30.
  • the structure of the light detection device 1 is a three-dimensional structure formed by bonding together three substrates, the first substrate 10, the second substrate 20, and the third substrate 30.
  • the first substrate 10, the second substrate 20, and the third substrate 30 are stacked in the order of description.
  • the first substrate 10 is the topmost first layer
  • the second substrate 20 is the second layer
  • the third substrate 30 is the bottommost third layer.
  • the upper surface of the first substrate 10 is a light incidence surface.
  • the first substrate 10 includes a semiconductor substrate 11 and a plurality of sensor pixels 12 that perform photoelectric conversion.
  • the sensor pixels 12 will be simply referred to as pixels.
  • the semiconductor substrate 11 has a plurality of pixels 12. These pixels 12 are arranged in a matrix (two-dimensional array) within a pixel region 13 in the first substrate 10.
  • Each pixel 12 has a photoelectric conversion element and a transfer transistor, as described below.
  • a pixel circuit is connected to each pixel 12.
  • the second substrate 20 includes a semiconductor substrate 21, a pixel circuit 22 that outputs pixel signals, a plurality of pixel drive lines 23 extending in the row direction, and a plurality of vertical signal lines 24 extending in the column direction.
  • the semiconductor substrate 21 has one pixel circuit 22 for every four pixels 12. This pixel circuit 22 outputs a pixel signal based on the charge output from the pixel 12.
  • the pixel circuit 22 is also called a readout circuit.
  • the third substrate 30 includes a semiconductor substrate 31 and a logic circuit 32 that processes pixel signals.
  • the semiconductor substrate 31 includes a logic circuit 32.
  • the logic circuit 32 includes, for example, a vertical drive circuit 33, a column signal processing circuit 34, a horizontal drive circuit 35, and a system control circuit 36.
  • the logic circuit 32 outputs the output voltage Vout for each pixel 12 to the outside.
  • a low-resistance region made of silicide such as CoSi2 or NiSi formed using a salicide (Self Aligned Silicide) process may be formed on the surface of the impurity diffusion region in contact with the source electrode and the drain electrode.
  • the vertical drive circuit 33 selects multiple pixels 12 in sequence, row by row.
  • the column signal processing circuit 34 performs, for example, correlated double sampling (CDS) processing on the pixel signals output from each pixel 12 in the row selected by the vertical drive circuit 33. For example, the column signal processing circuit 34 extracts the signal level of each pixel signal by performing CDS processing, and holds pixel data corresponding to the amount of light received by each pixel 12.
  • CDS correlated double sampling
  • the horizontal drive circuit 35 for example, sequentially outputs the pixel data held in the column signal processing circuit 34 to the outside.
  • Each pixel 12 that performs phase difference detection (hereinafter, sometimes referred to as a phase difference detection pixel 12) has a photoelectric conversion element PD and a transfer transistor TR.
  • the photoelectric conversion element PD is, for example, a photodiode.
  • the pixel circuit 22 shared by the eight pixels 12 has an amplification transistor AMP, a selection transistor SEL, a reset transistor RST, and a conversion efficiency switching transistor FDG.
  • the conversion efficiency switching transistor FDG may be omitted.
  • the transistors constituting the pixel circuit 22 may be collectively referred to as pixel transistors.
  • the pixel transistors are composed of, for example, NMOS (N-type Metal Oxide Semiconductor) transistors.
  • the amplification transistor AMP and the selection transistor SEL form a source follower circuit.
  • the gate of the amplification transistor AMP is connected to two floating diffusion regions FD and to the source of the conversion efficiency switching transistor FDG.
  • the conversion efficiency switching transistor FDG is a transistor that switches the photoelectric conversion efficiency and may be omitted.
  • the drain of the conversion efficiency switching transistor FDG is connected to the source of the reset transistor RST.
  • the drain of the reset transistor RST and the drain of the amplification transistor AMP are connected to a power supply voltage node.
  • the source of the amplification transistor AMP is connected to the drain of the selection transistor SEL.
  • the source of the selection transistor SEL is connected to a vertical signal line VSL.
  • the vertical signal lines VSL extend in the second direction (column direction) and are arranged at a predetermined interval in the first direction (row direction).
  • a current source 14 is connected to each vertical signal line VSL.
  • the two floating diffusion regions FD in each pixel circuit 22 in the Recta structure may be referred to as FD1 and FD2.
  • FIG. 3 is a diagram showing an example of a longitudinal sectional configuration (vertical sectional configuration) of the photodetector 1 according to the present disclosure.
  • the light detection device 1 is configured by stacking a first substrate 10, a second substrate 20, and a third substrate 30 in the order shown, and further includes a color filter 40 and a light receiving lens 50 on the back side (light incident surface side) of the first substrate 10.
  • a color filter 40 and a light receiving lens 50 are each provided for each pixel 12.
  • the light detection device 1 is a back-illuminated type.
  • the first substrate 10 is formed by laminating an insulating layer 46 on a semiconductor substrate 11.
  • the insulating layer 46 is also called an interlayer insulating layer.
  • the insulating layer 46 is provided in the gap between the semiconductor substrate 11 and a semiconductor substrate 21, which will be described later.
  • the semiconductor substrate 11 is composed of a silicon substrate.
  • the semiconductor substrate 11 has a p-well layer 42, for example, in a part of the surface and in its vicinity, and has a photodiode PD of a different conductivity type from the p-well layer 42 in the other region (region deeper than the p-well layer 42).
  • the p-well layer 42 is composed of a p-type semiconductor region.
  • the photodiode PD is composed of a semiconductor region of a different conductivity type (specifically, n-type) from the p-well layer 42.
  • the semiconductor substrate 11 has a floating diffusion region FD in the p-well layer 42 as a semiconductor region of a different conductivity type (specifically, n-type) from the p-well layer 42.
  • one floating diffusion region FD has four adjacent diffusion layers (floating diffusion layers) FDa and one connection layer FDb.
  • a diffusion layer FDa is provided for each photodiode PD, and the individual diffusion layers FDa of the four adjacent photodiodes PD are electrically connected by one connection layer FDb.
  • the connection layer FDb is positioned above each diffusion layer FDa so as to be in contact with each diffusion layer FDa, and is provided in the insulating layer 46.
  • This connection layer FDb is formed from the same material (e.g., polysilicon) as the transfer gate TG.
  • the first substrate 10 has a photodiode PD and a transfer transistor TR for each pixel 12, and furthermore, a floating diffusion region FD and a well tap WT are shared by four pixels 12.
  • the transfer transistor TR, the floating diffusion region FD and the well tap WT are provided on the front surface side (the side opposite to the light incident surface side, the second substrate 20 side) of the semiconductor substrate 11.
  • the well tap WT is electrically connected to the p-well layer 42 (for example, a well contact formed in the p-well layer 42).
  • the color filter 40 is provided on the back surface side of the semiconductor substrate 11.
  • the color filter 40 is provided, for example, in contact with the back surface of the semiconductor substrate 11 and in a position facing the pixels 12.
  • the light receiving lens 50 is provided, for example, in contact with the back surface of the color filter 40 and in a position facing the pixels 12 via the color filter 40.
  • the second substrate 20 is formed by laminating an insulating layer 52 on a semiconductor substrate 21.
  • the insulating layer 52 is also called an interlayer insulating layer.
  • the insulating layer 52 is provided in the gap between the semiconductor substrate 21 and a semiconductor substrate 31, which will be described later.
  • the semiconductor substrate 21 is formed of a silicon substrate.
  • the second substrate 20 has one pixel circuit 22 for every four pixels 12 (see Figures 2 and 3).
  • the pixel circuits 22 are provided on the back side (first substrate 10 side) of the semiconductor substrate 21.
  • the second substrate 20 is bonded to the first substrate 10 with the back side of the semiconductor substrate 21 facing the front side of the semiconductor substrate 11. In other words, the second substrate 20 is bonded to the first substrate 10 face-to-back.
  • the second substrate 20 further includes an insulating layer 53 that penetrates the semiconductor substrate 21 in the same layer as the semiconductor substrate 21.
  • the insulating layer 53 is also called an interlayer insulating layer.
  • the insulating layer 53 is provided so as to cover the side surfaces of the through wiring 54 described below.
  • the laminate consisting of the first substrate 10 and the second substrate 20 has an interlayer insulating layer 51 including insulating layers 46, 52, and 53, and a through-wire 54 provided within the interlayer insulating layer 51.
  • the laminate has one through-wire 54 for every four pixels 12.
  • the through-wire 54 extends in the normal direction of the semiconductor substrate 21, and is provided by penetrating a portion of the interlayer insulating layer 51 including the insulating layer 53.
  • the first substrate 10 and the second substrate 20 are electrically connected to each other by the through-wire 54.
  • the through-wire 54 is, for example, a through contact for the floating diffusion region FD (FD1 to FD4).
  • FIG. 26 is a plan view showing a third example of a pixel structure applicable to the photodetector 1 according to the first to sixth embodiments.
  • the pixel structure according to the third example is called a square pixel structure.
  • each pixel 12 has a transfer transistor TR, and a TG contact TGC is arranged extending from each transfer gate of each transfer transistor TR to the intermediate layer 70.
  • the pixel circuit 22 may have a circuit configuration in which the reset transistor RST and the conversion efficiency switching transistor FDG are connected in series as shown in FIG. 16, or may have a circuit configuration in which the reset transistor RST and the conversion efficiency switching transistor FDG are connected in parallel as shown in FIG. 17.
  • the layout of the first substrate 10 is the same when the reset transistor RST and the conversion efficiency switching transistor FDG are connected in series as compared to when they are connected in parallel, but the layout of the second substrate 20 is different.
  • the pixel circuit 22 in the photodetector 1 may have a circuit configuration in which the conversion efficiency switching transistor FDG is omitted from the circuit configuration of FIG. 2, FIG. 16, or FIG. 17.
  • FIG. 29 is a layout diagram of the second substrate 20 for one pixel block shown in FIG. 28.
  • the layout in FIG. 29 is an example, and various modifications are possible.
  • FIG. 30 is a layout diagram of the photodetector 1 according to the tenth embodiment.
  • FIG. 31 is a cross-sectional view taken along line A-A' in FIG. 30.
  • the photodetector 1 includes two first contacts FDC1 that are connected to two floating diffusion regions FD spaced apart along the first direction X and extend in the stacking direction, two first wiring layers FDW that are connected to the first contacts FDC1, a second wiring layer SHW that is arranged between the two first wiring layers FDW, a plurality of second contacts FDC2 that extend in the stacking direction from the two first wiring layers FDW, and a third contact SHC that extends in the stacking direction from the second wiring layer SHW.
  • the first wiring layer FDW may be referred to as the FD wiring layer
  • the second wiring layer SHW may be referred to as the shield layer.
  • the second wiring layer SHW shield layer
  • the shield layer is provided to prevent capacitive coupling between two floating diffusion regions FD adjacent in the first direction X.
  • the floating diffusion region FD in the tenth embodiment is shared by multiple photoelectric conversion elements and holds the charges transferred from the multiple photoelectric conversion elements.
  • the photodetector 1 includes a first substrate 10, an intermediate layer 70, and a second substrate 20, which are stacked together, as in FIG. 3.
  • Two floating diffusion regions FD adjacent to each other in the first direction X are arranged in the first substrate 10.
  • the first contact FDC1, the first wiring layer FDW, and the second wiring layer SHW are arranged in the intermediate layer 70.
  • the second contact FDC2 and the third contact SHC are arranged in the second substrate 20.
  • the intermediate layer 70 may be referred to as the wiring region 70.
  • the wiring region 70 mainly wiring layers and contacts for various signals transmitted and received between the first substrate 10 and the second substrate 20 are arranged.
  • the photodetector 1 includes two or more floating diffusion regions FD arranged along the first direction X, but below, two floating diffusion regions FD adjacent to each other in the first direction X and the structure around them will be described. Similar structures are repeatedly arranged along the first direction X.
  • the two first wiring layers FDW and the second wiring layer SHW connected to the two first contacts FDC1 adjacent in the first direction X are arranged along the first direction X. More specifically, the two first wiring layers FDW and at least a portion of the second wiring layer SHW are arranged in a line along the first direction X.
  • the second wiring layer SHW is set to, for example, a predetermined voltage.
  • the predetermined voltage is arbitrary, but is, for example, a power supply voltage.
  • Two first wiring layers FDW adjacent to each other in the first direction X are electrically connected to two floating diffusion regions FD via two first contacts FDC1 extending in the stacking direction. By arranging the second wiring layer SHW between the two first wiring layers FDW, capacitive coupling between the two first wiring layers FDW can be prevented.
  • the second wiring layer SHW extends in a second direction Y intersecting the first direction X.
  • the third contact SHC extending from the second wiring layer SHW in the stacking direction may be a columnar shape extending in the stacking direction, or a wall shape extending in the stacking direction and the second direction Y. In other words, the shape of the third contact SHC is arbitrary.
  • the second wiring layer SHW is, for example, a polysilicon layer. Note that the material of the second wiring layer SHW is not limited to a polysilicon layer.
  • FIG. 32A is a diagram showing a first example of the cross-sectional shape of the third contact SHC according to the tenth embodiment
  • FIG. 32B is a diagram showing a second example of the cross-sectional shape of the third contact SHC.
  • the third contact SHC has a wall-like structure extending in the second direction Y and the stacking direction. This results in the second wiring layer SHW and the third contact SHC being disposed between two floating diffusion regions FD, two first contacts FDC1, two first wiring layers FDW, and two second contacts FDC2 that are adjacent to each other in the first direction X, thereby preventing capacitive coupling between the two floating diffusion regions FD, two first contacts FDC1, two first wiring layers FDW, and two second contacts FDC2.
  • the second example shown in FIG. 32B has multiple third contacts SHC that are connected at a distance to the second wiring layer SHW extending in the second direction Y and extend in the stacking direction. There is no limit to the number and spacing of the third contacts SHC. These third contacts SHC have a columnar structure. These third contacts SHC and the second wiring layer SHW are arranged between two floating diffusion regions FD, two first contacts FDC1, two first wiring layers FDW, and multiple second contacts FDC2 that are adjacent to each other in the first direction X. This makes it possible to prevent capacitive coupling between the two floating diffusion regions FD, two first contacts FDC1, two first wiring layers FDW, and two second contacts FDC2.
  • FIG. 33 is a layout diagram of a photodetector 1 according to a modified example of the tenth embodiment
  • FIG. 34 is a cross-sectional view along line A-A' in FIG. 33.
  • the photodetector 1 according to the modified example shown in FIGS. 33 and 34 has a different structure of the second wiring layer SHW and the third contact SHC from those in FIGS. 30 and 31.
  • Two second wiring layers SHW are arranged between two first wiring layers FDW adjacent to each other in the first direction X. These two second wiring layers SHW are electrically connected to different transfer gates TRG (TRG4 in this case) via different fourth contacts TGC. Two third contacts SHC extending in the stacking direction are connected to these two second wiring layers SHW.
  • At least a portion of the two first wiring layers FDW and the two second wiring layers SHW are arranged in a line along the first direction X.
  • the floating diffusion region FD and the transfer gate TRG are disposed on the first substrate 10.
  • the first contact FDC1 connected to the floating diffusion region FD, the first wiring layer FDW connected to the first contact FDC1, the fourth contact TGC connected to the transfer gate TRG, and the second wiring layer SHW connected to the fourth contact TGC are disposed on the intermediate layer 70.
  • the second contact FDC2 connected to the first wiring layer FDW and the third contact SHC connected to the second wiring layer SHW are disposed on the second substrate 20.
  • the second wiring layer SHW is connected to the transfer gate TRG via the fourth contact TGC, and therefore has the same potential as the transfer gate TRG.
  • the fourth contact TGC, the second wiring layer SHW (shield layer), and the third contact SHC are disposed between two floating diffusion regions FD adjacent in the first direction X, and therefore capacitive coupling between these two floating diffusion regions FD can be prevented.
  • the third contact SHC connected to the second wiring layer SHW in one modified example has, for example, the same structure and arrangement as those in FIG. 32A or FIG. 32B.
  • a second wiring layer SHW shield layer
  • a third contact SHC extending from the second wiring layer SHW in the stacking direction is arranged between two second contacts FDC2 extending from the two first wiring layers FDW in the stacking direction.
  • the second wiring layer SHW and the third contact SHC are set to, for example, a predetermined potential or the same potential as the transfer gate TRG.
  • the technology disclosed herein can be applied to a variety of products.
  • the technology disclosed herein may be realized as a device mounted on any type of moving object, such as an automobile, electric vehicle, hybrid electric vehicle, motorcycle, bicycle, personal mobility, airplane, drone, ship, robot, etc.
  • FIG. 35 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile object control system to which the technology disclosed herein can be applied.
  • the vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001.
  • the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside vehicle information detection unit 12030, an inside vehicle information detection unit 12040, and an integrated control unit 12050.
  • Also shown as functional components of the integrated control unit 12050 are a microcomputer 12051, an audio/video output unit 12052, and an in-vehicle network I/F (Interface) 12053.
  • the drive system control unit 12010 controls the operation of devices related to the drive system of the vehicle according to various programs.
  • the drive system control unit 12010 functions as a control device for a drive force generating device for generating the drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a braking force for the vehicle.
  • the outside-vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000.
  • the image capturing unit 12031 is connected to the outside-vehicle information detection unit 12030.
  • the outside-vehicle information detection unit 12030 causes the image capturing unit 12031 to capture images outside the vehicle and receives the captured images.
  • the outside-vehicle information detection unit 12030 may perform object detection processing or distance detection processing for people, cars, obstacles, signs, characters on the road surface, etc. based on the received images.
  • the microcomputer 12051 can also output control commands to the body system control unit 12020 based on information outside the vehicle acquired by the outside information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside information detection unit 12030, and perform cooperative control aimed at preventing glare, such as switching from high beams to low beams.
  • the microcomputer 12051 can obtain the distance to each solid object within the imaging ranges 12111 to 12114 and the change in this distance over time (relative speed with respect to the vehicle 12100) based on the distance information obtained from the imaging units 12101 to 12104, and can extract as a preceding vehicle, in particular, the closest solid object on the path of the vehicle 12100 that is traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km/h or faster). Furthermore, the microcomputer 12051 can set the inter-vehicle distance that should be maintained in advance in front of the preceding vehicle, and perform automatic braking control (including follow-up stop control) and automatic acceleration control (including follow-up start control). In this way, cooperative control can be performed for the purpose of automatic driving, which runs autonomously without relying on the driver's operation.
  • automatic braking control including follow-up stop control
  • automatic acceleration control including follow-up start control

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Solid State Image Pick-Up Elements (AREA)

Abstract

L'objectif de la présente invention est de fournir un dispositif de détection de lumière capable de supprimer la variation de la capacité parasite. À cet effet, l'invention concerne un dispositif de détection de lumière comprenant : une pluralité d'éléments de conversion photoélectrique, dont chacun accumule une charge électrique correspondant à la quantité de lumière incidente ; une zone de diffusion flottante qui est partagée par la pluralité d'éléments de conversion photoélectrique et qui retient la charge électrique transférée depuis la pluralité d'éléments de conversion photoélectrique ; une pluralité de transistors de transfert qui transfèrent la charge électrique stockée dans la pluralité d'éléments de conversion photoélectrique à la zone de diffusion flottante ; un premier contact s'étendant dans la direction d'empilement à partir de la zone de diffusion flottante ; une pluralité de seconds contacts s'étendant dans la direction d'empilement à partir des grilles de la pluralité de transistors de transfert ; et une pluralité de premières couches d'interconnexion connectées respectivement à la pluralité de seconds contacts, les premières couches d'interconnexion connectées à certains des seconds contacts, parmi la pluralité de premières couches d'interconnexion, s'étendant jusqu'à un emplacement plus proche du premier contact que les premières interconnexions connectées aux autres seconds contacts.
PCT/JP2024/045854 2023-12-28 2024-12-25 Dispositif de détection de lumière Pending WO2025142996A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2023-223679 2023-12-28
JP2023223679 2023-12-28

Publications (1)

Publication Number Publication Date
WO2025142996A1 true WO2025142996A1 (fr) 2025-07-03

Family

ID=96219117

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2024/045854 Pending WO2025142996A1 (fr) 2023-12-28 2024-12-25 Dispositif de détection de lumière

Country Status (1)

Country Link
WO (1) WO2025142996A1 (fr)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2020262383A1 (fr) * 2019-06-26 2020-12-30 ソニーセミコンダクタソリューションズ株式会社 Dispositif de capture d'image
WO2020262558A1 (fr) * 2019-06-26 2020-12-30 ソニーセミコンダクタソリューションズ株式会社 Dispositif d'imagerie
WO2020262559A1 (fr) * 2019-06-26 2020-12-30 ソニーセミコンダクタソリューションズ株式会社 Dispositif d'imagerie
WO2021106732A1 (fr) * 2019-11-29 2021-06-03 ソニーセミコンダクタソリューションズ株式会社 Dispositif d'imagerie et instrument électronique
JP2022083871A (ja) * 2020-11-25 2022-06-06 ソニーセミコンダクタソリューションズ株式会社 撮像素子及び撮像装置
WO2022172711A1 (fr) * 2021-02-12 2022-08-18 ソニーセミコンダクタソリューションズ株式会社 Élément de conversion photoélectrique et dispositif électronique

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2020262383A1 (fr) * 2019-06-26 2020-12-30 ソニーセミコンダクタソリューションズ株式会社 Dispositif de capture d'image
WO2020262558A1 (fr) * 2019-06-26 2020-12-30 ソニーセミコンダクタソリューションズ株式会社 Dispositif d'imagerie
WO2020262559A1 (fr) * 2019-06-26 2020-12-30 ソニーセミコンダクタソリューションズ株式会社 Dispositif d'imagerie
WO2021106732A1 (fr) * 2019-11-29 2021-06-03 ソニーセミコンダクタソリューションズ株式会社 Dispositif d'imagerie et instrument électronique
JP2022083871A (ja) * 2020-11-25 2022-06-06 ソニーセミコンダクタソリューションズ株式会社 撮像素子及び撮像装置
WO2022172711A1 (fr) * 2021-02-12 2022-08-18 ソニーセミコンダクタソリューションズ株式会社 Élément de conversion photoélectrique et dispositif électronique

Similar Documents

Publication Publication Date Title
US12272714B2 (en) Solid-state imaging device
TW202015395A (zh) 固態攝像裝置及其驅動方法以及電子機器
US20240170518A1 (en) Solid-state imaging device and electronic device
US12349487B2 (en) Solid-state image pickup device and electronic apparatus
KR20240155219A (ko) 고체 촬상 장치
US20250201639A1 (en) Semiconductor device, manufacturing method thereof, and electronic apparatus
TW202335273A (zh) 固態攝像裝置
WO2024095743A1 (fr) Dispositif d'imagerie à semi-conducteurs, son procédé de fabrication et appareil électronique
WO2023171147A1 (fr) Dispositif à semi-conducteur, dispositif de détection optique et appareil électronique
WO2025142996A1 (fr) Dispositif de détection de lumière
WO2025173725A1 (fr) Elément semi-conducteur
US20250194280A1 (en) Photodetection device and electronic apparatus
JP2025047905A (ja) 光検出装置、電子機器及び光検出装置の製造方法
WO2025154549A1 (fr) Dispositif de détection de lumière et appareil électronique
WO2024202511A1 (fr) Dispositif de détection de lumière et appareil électronique
WO2024127854A1 (fr) Élément d'imagerie, procédé de fabrication d'élément d'imagerie et dispositif électronique
JP2025056833A (ja) 光検出装置
WO2025069370A1 (fr) Dispositif d'imagerie à semi-conducteurs
JP2023154356A (ja) 光検出装置および測距装置ならびに撮像装置
WO2024241867A1 (fr) Dispositif de détection de lumière et appareil électronique
WO2024210220A1 (fr) Dispositif de détection de lumière
WO2025158777A1 (fr) Dispositif d'imagerie
JP2024138782A (ja) 固体撮像装置およびその製造方法、並びに電子機器
WO2025169613A1 (fr) Élément d'imagerie, appareil électronique
WO2024242014A1 (fr) Dispositif de détection de lumière et appareil électronique

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 24912882

Country of ref document: EP

Kind code of ref document: A1