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WO2025038369A1 - Structures fefet utilisant des canaux semi-conducteurs d'oxyde amorphe sur des circuits intégrés - Google Patents

Structures fefet utilisant des canaux semi-conducteurs d'oxyde amorphe sur des circuits intégrés Download PDF

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Publication number
WO2025038369A1
WO2025038369A1 PCT/US2024/041400 US2024041400W WO2025038369A1 WO 2025038369 A1 WO2025038369 A1 WO 2025038369A1 US 2024041400 W US2024041400 W US 2024041400W WO 2025038369 A1 WO2025038369 A1 WO 2025038369A1
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WO
WIPO (PCT)
Prior art keywords
integrated circuit
oxide
column
data
read
Prior art date
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PCT/US2024/041400
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English (en)
Inventor
Milind Weling
Michael Chu
Shridhar Mukund
Stephan Dertinger
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Versum Materials US LLC
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Versum Materials US LLC
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Publication of WO2025038369A1 publication Critical patent/WO2025038369A1/fr
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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/40—Crystalline structures
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/16—Constructional details or arrangements
    • G06F1/18—Packaging or power distribution
    • G06F1/183—Internal mounting support structures, e.g. for printed circuit boards, internal connecting means
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/022—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in I/O circuitry
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17748—Structural details of configuration resources
    • H03K19/1776—Structural details of configuration resources for memories
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B51/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors
    • H10B51/30—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0415—Manufacture or treatment of FETs having insulated gates [IGFET] of FETs having ferroelectric gate insulators
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/701—IGFETs having ferroelectric gate insulators, e.g. ferroelectric FETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/031—Manufacture or treatment of data-storage electrodes
    • H10D64/033—Manufacture or treatment of data-storage electrodes comprising ferroelectric layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/689—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having ferroelectric layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
    • H10D30/6756—Amorphous oxide semiconductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D99/00—Subject matter not provided for in other groups of this subclass

Definitions

  • the present disclosure relates to integrated circuits. More particularly, the present disclosure relates to integrated circuits having FeFETs for storing memory.
  • Chiplets refer to miniature chips that are designed to work as a single entity while using advanced packaging technology. These miniaturized chips are created by dividing the larger chip into several smaller chips, each with its own function or capability. The concept originated from the semiconductor industry's need to overcome the physical restrictions of traditional monolithic chip designs and achieve higher levels of integration. The idea behind chiplets is to create a modular system of interconnected and interchangeable chips that can be combined in different configurations to create advanced computing systems with improved performance, power efficiency, and functionality.
  • Chiplets can be based on different architectures, such as CPU, GPU, memory, or IO, and can be assembled and stacked in a variety of ways, depending on the specific application requirements.
  • One of the advantages of the chiplet approach is the ability to mix and match different chiplets from different manufacturers to create custom solutions that meet specific computing needs. This approach also allows for faster time to market, reduced development costs, and increased flexibility, as chiplets can be upgraded or replaced without the need for a complete system redesign.
  • chiplets may be used in various industries, including consumer electronics, cloud computing, and data centers, where the demand for high-performance computing and energy efficiency is high. Chiplets are expected to play a significant role in the future of computing and are likely to unlock new possibilities for creating more powerful and/or sophisticated electronic devices.
  • An integrated circuit is disclosed herein that may be part of a semiconductor device.
  • a method of manufacturing or a method of writing and reading data to modules are disclosed herein and can be used with all examples, embodiments, and aspects as described herein.
  • the integrated circuit may comprise a plurality of microvaults, with each of the microvaults disposed in a spaced relation relative to one another and adjacent to a first surface.
  • the plurality of microvaults includes a first microvault.
  • the integrated circuit may comprise a plurality of bonding areas, with each bonding area disposed on the first surface and adjacent to a respective one of the plurality of microvaults.
  • the plurality of bonding areas includes a first bonding area in operative communication with the first microvault.
  • the integrated circuit may comprise a first bonding area disposed on the first surface and adjacent to the first microvault.
  • This first bonding area can optionally include a plurality of bonds, with each bond in operative communication with the first microvault.
  • the first bonding area may include a plurality of bonds each in operative communication with the first microvault.
  • these plurality of bonds may be bumpless bonds.
  • the integrated circuit may have a first microvault with a capacity between 4 kilobytes and 1 megabyte.
  • the first microvault has a capacity between 4 kilobytes and 128 kilobytes.
  • the microvaults may have a storage capacity ranging from 4 kilobytes to 16 kilobytes.
  • the first microvault may have dimensions of less than 256 micrometers by less than 256 micrometers and extend in a vertical dimension a predetermined distance.
  • the first microvault has dimensions of 32 micrometers by 32 micrometers and extends vertically a predetermined distance.
  • the integrated circuit may involve the first microvault having a vertical dimension that corresponds to at least 8 memory layers.
  • the first microvault as having dimensions of 32 micrometers by 32 micrometers, and extending in a vertical dimension a predetermined distance. This vertical dimension corresponds to at least 8 memory layers in some embodiments.
  • the bit density of the first microvault may be greater than 0.2 Gigabits per square millimeter for each layer of the microvault.
  • the plurality of microvaults may be disposed on a Back-End-Of-the-Line portion of a die.
  • the integrated circuit embodiment can include an SRAM vault that is disposed adjacent to the first microvault.
  • the integrated circuit may comprise an SRAM vault disposed adjacent to the first microvault, wherein the first bonding area is in operative communication with the SRAM vault.
  • the integrated circuit may include a second bonding area disposed on the first surface that is in operative communication with the SRAM vault.
  • the integrated circuit may further comprise a second bonding area disposed on the first surface and in operative communication with the SRAM vault.
  • the second bonding area enables connection and data transfer between the SRAM vault component and other components in the system.
  • the integrated circuit may involve the plurality of microvaults being formed on a first die and the SRAM vault being formed on a second die, where the first and second dies are bonded together.
  • the integrated circuit may further comprise a DRAM (dynamic random access memory) vault disposed adjacent to the microvault.
  • DRAM dynamic random access memory
  • the DRAM vault provides an additional memory storage area that can be utilized along with the microvault memory.
  • the integrated circuit may involve a DRAM vault disposed adjacent to the plurality of microvaults.
  • the first bonding area may be in operative communication with this DRAM vault to facilitate data transfers between the first microvault and the DRAM vault.
  • the integrated circuit further comprises a second bonding area disposed on the first surface mentioned previously.
  • This second bonding area is in operative communication with the DRAM vault also mentioned previously. Operative communication allows data and signals to be exchanged between the second bonding area and the DRAM vault.
  • the integrated circuit may comprise a plurality of microvaults formed on a first die and a DRAM vault formed on a third die.
  • the first and third dies may be rigidly fixed together.
  • the integrated circuit further comprises a read address register operatively coupled to the first bonding area.
  • the read address register may be configured to hold and communicate a read address to the first microvault.
  • the integrated circuit further comprises a read data register.
  • the read data register may be operatively coupled to the first microvault to receive and hold read data from the first microvault.
  • the integrated circuit further comprises a read data register operatively coupled to the first microvault to receive and hold read data from the first microvault.
  • the read data register may be operatively coupled to the first bonding area to communicate the held read data thereto.
  • the integrated circuit may include a read data register that is operatively coupled to a second bonding area of the plurality of bonding areas to communicate read data thereto.
  • the read data register receives and holds read data from the first microvault and then communicates this read data to the second bonding area.
  • the integrated circuit may further comprise a second read data register in operative communication with the first read data register.
  • the second read data register may be configured to receive and hold read data from the first read data register.
  • the integrated circuit may involve a second read data register disposed on a die having a second face, wherein the second face includes a read data bonding area operatively coupled to the first bonding area of the first surface.
  • the integrated circuit may further comprise a second read data register disposed on a die having a second face.
  • This second read data register is configured to receive and hold read data from the first read data register.
  • this second face of the die includes a read data bonding area that is operatively coupled to the second bonding area of the first surface, in order to facilitate communication of data between the dies. Through this bonding, data can be transferred from the first read data register on the first die to the second read data register on the second die.
  • the integrated circuit may further comprise a second read data register disposed on a different die than the die that has the plurality of microvaults.
  • the integrated circuit further comprises a second read address register disposed on a different die than the die containing the plurality of microvaults.
  • This additional read address register located on a separate die may be utilized for various purposes such as increasing storage capacity or bandwidth for reading data from the microvaults.
  • the integrated circuit further comprises a second read address register.
  • the second read address register is configured to receive and hold a read address.
  • the second read address register communicates the read address to the first microvault.
  • the integrated circuit may further comprise a second bonding area disposed on a second surface, in addition to the read address register and second read address register.
  • the second bonding area provides an interface on the second surface to facilitate communication and data transfers related to the read addressing functions. By having this second bonding area, the integrated circuit enables interfacing the read addressing architecture across multiple surfaces and dies.
  • the integrated circuit may further comprise a second read address register.
  • the second read address register can be disposed on a second die having a second surface.
  • the second read address register may be configured to receive and hold the read address. Additionally, the second read address register can communicate the read address to the read address register of the first die via the second surface, wherein the second surface of the second die and the first surface of the first die may be bonded together.
  • the integrated circuit further comprises a second surface with a second read address register disposed on it.
  • the second read address register is configured to receive and hold the read address and communicate the read address to the read address register of the first surface.
  • the second surface and the first surface may be bonded together to facilitate communication of the read address between the two surfaces.
  • the integrated circuit further comprises a Through- Silicon Via operatively coupled to a third surface on a first end of the Through-Silicon Via, where the third surface is on an opposite side of the first surface.
  • the integrated circuit further comprises an interconnect coupled to the first surface where the plurality of microvaults are disposed.
  • This interconnect is also coupled to a second end of a Through-Silicon Via that facilitates communication between dies.
  • the Through-Silicon Via has a first end coupled to a third surface on the opposite side of the first surface.
  • the integrated circuit further comprises a second microvault that is in operative communication with the first bonding area.
  • the integrated circuit may further comprise a multiplexer operatively coupled to the first microvault to receive a first read data therefrom.
  • the multiplexer may also be operatively coupled to the second microvault to receive a second read data therefrom.
  • the multiplexer can be configured to select between the first read data from the first microvault and the second read data from the second microvault for output.
  • the integrated circuit further comprises a counter operatively coupled to the multiplexer.
  • the counter is configured to control the multiplexer to serially read out the first read data from the first microvault and the second read data from the second microvault.
  • the integrated circuit further comprises a read data register configured to receive the first read data from the first microvault or the second read data from the second microvault selected by the multiplexer. The read data register holds the received first read data or second read data therein.
  • the integrated circuit further comprises a second bonding area on the first surface.
  • the read data register is coupled to this second bonding area to communicate the held first read data or second read data from the multiplexer to the second bonding area.
  • the integrated circuit further comprises an assembly including a first die having the plurality of microvaults.
  • the integrated circuit further comprises an assembly including a first die that has the plurality of microvaults. This plurality of microvaults on the first die includes the first microvault and a second microvault.
  • the integrated circuit further comprises an assembly including a first die having the plurality of microvaults including a first microvault and a second microvault, as well as a second die comprising a read address register and a read data register.
  • the first die may be bonded to the second die in this assembly.
  • the integrated circuit may involve an assembly with a first die and a second die bonded together.
  • the first die may have a plurality of microvaults including a first microvault and a second microvault, while the second die may have a read address register and a read data register.
  • the first die may include a second bonding area on the first surface, in addition to the first bonding area described previously.
  • the second die may include a third bonding area and a fourth bonding area. The various bonding areas may be connected such that the first bonding area of the first die is coupled to the third bonding area of the second die, while the second bonding area of the first die is coupled to the fourth bonding area of the second die.
  • the integrated circuit further comprises a read address register operatively coupled to the third bonding area of the second die to communicate read addresses there.
  • the read address register is configured to hold and communicate read addresses to the first microvault on the first die via the third bonding area, which is coupled to the first bonding area of the first die.
  • the integrated circuit further comprises a read data register operatively coupled to a fourth bonding area of the second die to receive read data therefrom.
  • the read data register is configured to receive and hold read data communicated from the fourth bonding area of the second die which is bonded to the first die having the plurality of microvaults.
  • the integrated circuit may involve an assembly including a first die with a plurality of microvaults such as a first microvault and a second microvault.
  • the first die may also include a second read address register configured to receive and hold a read address. This second read address register can be configured to communicate a read address to the first microvault and the second microvault.
  • the assembly may include a first die with a plurality of microvaults including a first microvault and a second microvault.
  • the first die can further comprise a multiplexer configured to select between an output of the first microvault and an output of the second microvault.
  • the integrated circuit may further comprise a second bonding area on a second surface of the first die having the plurality of microvaults.
  • An interconnect may connect this second bonding area to an input of a multiplexer, which is configured to select among the output of the first microvault, the output of the second microvault, and communication received from the second bonding area.
  • the integrated circuit may further comprise a phase counter configured to control the multiplexer that selects between outputs from the first microvault and second microvault.
  • the phase counter facilitates sequentially reading out data from the multiple microvaults through the use of the multiplexer.
  • the integrated circuit may further comprise a third address register configured to receive and hold an output of the multiplexer.
  • the multiplexer may be configured to select between one of the plurality of microvaults, and a phase counter may be configured to control the selection of the multiplexer.
  • the third address register could receive and hold the output that is selected by the multiplexer.
  • the integrated circuit may involve an assembly including a first die having a plurality of microvaults including a first microvault and a second microvault, as well as a second die with a read address register and a read data register, where the first die is bonded to the second die.
  • the first die may further comprise a multiplexer configured to select among an output of the first microvault and an output of the second microvault, as well as a third address register configured to receive and hold an output of the multiplexer.
  • the third address register could be operatively coupled to a second bonding area of the first die.
  • the integrated circuit may further comprise a Through-Silicon Via (TSV) coupled to the read address register and a second surface of the die on which the read address register is disposed.
  • TSV Through-Silicon Via
  • the TSV facilitates communication of data such as a read address between the read address register and components located on the opposite side of the die.
  • the integrated circuit further comprises a second Through-Silicon Via (TSV) coupled to a second bonding area of the first die on the second surface and to a second read data register.
  • TSV Through-Silicon Via
  • the second TSV facilitates communication of data between the second bonding area on the second surface of the first die and the second read data register on another die. This configuration enables efficient transfer of read data between multiple dies that are stacked and bonded together.
  • the integrated circuit may comprise a multiplexer configured to select between one of the plurality of microvaults.
  • the multiplexer enables accessing data from different microvaults in a selective manner.
  • the integrated circuit may further comprise a phase counter configured to control the selection operation of the multiplexer that selects between one of the plurality of microvaults.
  • the phase counter provides control signals to the multiplexer to facilitate sequentially accessing data from multiple microvaults.
  • the integrated circuit further comprises a Through- Silicon Via (TSV) that is operatively coupled to the first surface and a second surface of a die that has the plurality of microvaults.
  • TSV Through- Silicon Via
  • the TSV facilitates communication between the first surface having the plurality of microvaults and bonding areas and the opposite second surface of the die.
  • the integrated circuit further comprises a Through- Silicon Via configured to facilitate communication between a second die coupled to a first die having the plurality of microvaults.
  • the Through-Silicon Via enables inter-die communication and integration between the microvault die and additional dies in a multi-die assembly.
  • the integrated circuit may involve the first microvault comprising at least one column of 3D-NORs formed from a plurality of transistors.
  • Each transistor in these 3D-NOR columns may include a gate coupled to a read-write enable line, a source coupled to a bit line, and a drain coupled to a select line.
  • the integrated circuit may comprise a first microvault that includes a column of 3D-NANDs formed from multiple transistors. Each transistor in the column can have a gate terminal coupled to a read/write enable line, a source terminal coupled to a bit line, and a drain terminal coupled to a source terminal of an adjacent second transistor in the column.
  • the 3D-NAND column configuration in the first microvault can facilitate dense vertical stacking of the transistors while allowing for separate control of read and write operations through the independent enable line.
  • the integrated circuit may comprise a first microvault that includes a column of 3D-NANDs with a pass gate formed from a plurality of transistors.
  • Each transistor in the column of 3D-NANDs may have a gate coupled to a read/write enable line, a source coupled to a bit line, and a drain coupled to a source of a second transistor.
  • a pass gate may be coupled to all of the plurality of transistors in the column of 3D-NANDs.
  • the integrated circuit may comprise a first microvault that includes a column of 3D-NORs (three-dimensional NOR gates) with independent read and write enables formed from multiple transistors.
  • Each transistor within the 3D-N0R gates can have a source terminal coupled to a bit line, a drain terminal coupled to a read enable line, and a gate terminal coupled to a write enable line.
  • the independent read and write enable lines allow separate control over reading from and writing to the microvault.
  • the plurality of microvaults may include a thermal management layer configured to dissipate heat generated by the microvaults during operation.
  • This thermal management layer could optionally involve a material with high thermal conductivity selected from a group consisting of copper, aluminum, diamond, and graphene to facilitate heat dissipation.
  • the integrated circuit further comprises a thermal management layer configured to dissipate heat generated by the microvaults during operation.
  • This thermal management layer may optionally comprise a material with high thermal conductivity selected from a group consisting of copper, aluminum, diamond, and graphene.
  • the integrated circuit further comprises a hardware-based encryption module operatively coupled to at least one microvault.
  • the encryption module functions to secure data that is written to or read from the microvault.
  • the integrated circuit further comprises a power management circuit configured to adjust the voltage and current supplied to the plurality of microvaults.
  • the adjustment of voltage and current by the power management circuit may be based on the operational status of the microvaults.
  • the power management circuit may include a low-power mode that reduces power supply to the microvaults during periods of inactivity.
  • the integrated circuit may include a power management circuit configured to adjust voltage and current supplied to the plurality of microvaults based on their operational status.
  • the power management circuit includes a low-power mode that reduces power supply to the microvaults during periods of inactivity.
  • the integrated circuit may further comprise a signal conditioning circuit operatively coupled to the plurality of microvaults.
  • the signal conditioning circuit may be configured to enhance signal integrity of data transfers to and from the microvaults.
  • Optional components of the signal conditioning circuit may include filters, amplifiers, or error- correction coders.
  • the integrated circuit further comprises a signal conditioning circuit operatively coupled to the plurality of microvaults to enhance signal integrity of data transfers.
  • the signal conditioning circuit may involve filters, amplifiers, or error-correction coders to enhance the signal integrity.
  • the integrated circuit further comprises a diagnostic module configured to monitor the health and performance of the microvaults and report metrics to an external controller.
  • the diagnostic module may be capable of performing self-tests on the microvaults and generating alerts if malfunctions are detected.
  • the integrated circuit further comprises a diagnostic module configured to monitor the health and performance of the microvaults and report metrics to an external controller.
  • this diagnostic module is capable of performing self-tests on the microvaults and generating alerts if malfunctions are detected.
  • each microvault may include a built-in self-repair mechanism that is capable of isolating and bypassing faulty memory cells.
  • the self-repair mechanism can optionally utilize redundancy in the form of spare memory cells that can be dynamically allocated to replace the faulty cells.
  • each microvault may include a built-in self-repair mechanism capable of isolating and bypassing faulty memory cells.
  • This self-repair mechanism may utilize redundancy in the form of spare memory cells that can be dynamically allocated to replace any faulty cells that are detected.
  • the microvaults may be arranged in a matrix configuration to enable parallel processing and data retrieval.
  • the microvaults may be arranged in a matrix configuration to enable parallel processing and data retrieval.
  • the matrix configuration may optionally include row and column decoders to facilitate access to individual microvaults.
  • the integrated circuit further comprises a flexible substrate.
  • the flexible substrate enables the integrated circuit to conform to non-planar surfaces.
  • the integrated circuit further comprises a flexible substrate that enables the circuit to conform to non-planar surfaces.
  • the flexible substrate may be comprised of materials such as polyimide, PEEK (polyether ether ketone), liquid crystal polymer, flexible glass, or combinations thereof.
  • the integrated circuit may involve the first microvault being configured to operate as a cache memory for a processor.
  • the cache memory can function in one or more modes such as write-through, write-back, write-around, or a combination thereof.
  • the first microvault may be configured to operate as a cache memory for a processor.
  • the cache memory may operate in one or more cache modes such as write-through, write-back, write-around, or a combination thereof.
  • the plurality of microvaults may form a redundant array of independent memory elements.
  • the redundant array of independent memory elements enables error correction and facilitates data recovery in the event of memory failures.
  • the first microvault can be configured as one element in an array of redundant, independent memory blocks, allowing data errors or failures in one block to be reconstructed from the other independent blocks.
  • the redundant array architecture provides fault tolerance and reliability to help ensure operational continuity.
  • the first microvault may include a crossbar switch architecture to facilitate data routing between memory cells.
  • This crossbar switch architecture can enable non-blocking data transfer within the integrated circuit.
  • the integrated circuit may involve a crossbar switch architecture associated with the first microvault to facilitate data routing between memory cells.
  • this crossbar switch architecture is configured to enable non-blocking data transfer within the integrated circuit.
  • the integrated circuit may involve the first microvault including a dedicated read peripheral.
  • the first microvault can optionally have its own read peripheral, separate from other components, to facilitate data reads.
  • This dedicated read peripheral for the first microvault enables optimized readout performance.
  • the integrated circuit may include a dedicated read port operatively coupled to the first microvault. This allows read operations to be performed on the first microvault independently of write operations, enabling concurrent read and write access.
  • the dedicated read port improves overall data throughput by eliminating contention between reading and writing data.
  • the integrated circuit may include a dedicated write peripheral associated with the first microvault. This allows write operations to the first microvault to be handled by specialized write circuitry tailored for efficient writing.
  • the dedicated write peripheral facilitates quick and reliable data storage within the microvault by optimizing the write path.
  • the integrated circuit may include a dedicated write port operatively coupled to the first microvault.
  • This dedicated write port facilitates writing data to the first microvault independently of read operations, enabling concurrent read and write access.
  • the dedicated write port can improve overall data throughput to and from the microvault.
  • the integrated circuit may comprise a first transistor with a channel layer formed using a semiconductor material and a ferroelectric layer rigidly coupled to the channel layer.
  • the first transistor may further comprise a source terminal fixed to the channel layer, a drain terminal fixed to the channel layer, and a gate terminal fixed to the ferroelectric layer.
  • the channel layer of the first transistor may be formed from a polycrystalline silicon.
  • the use of polycrystalline silicon for the channel layer provides known electrical properties that allow proper functioning of the transistor.
  • the channel layer of the transistor may be formed from an Amorphous Oxide Semiconductor.
  • This amorphous oxide semiconductor material can provide desirable properties such as high carrier mobilities and low off-state currents when used as the channel layer, while also being compatible with deposition on top of standard CMOS materials during back-end-of-line processing.
  • amorphous oxide semiconductors examples include Indium Oxide, Indium Gallium Zinc Oxide (IGZO), Zinc Tin Oxide (ZTO), Indium Zinc Oxide (IZO), Gallium Zinc Oxide (GZO), Aluminum Zinc Oxide (AZO), Cadmium Oxide, Hafnium Indium Zinc Oxide (HIZO), Tin Oxide, and Indium-Tin-Zinc Oxide (ITZO), among others.
  • the amorphous oxide semiconductor channel layer may also be doped with elements such as Gallium, Indium, Zinc, Tin, Hafnium, Silicon, Aluminum, and others to optimize carrier concentration and mobility.
  • the amorphous oxide semiconductor forming the channel layer of the first transistor may include at least one of indium oxide, indium gallium zinc oxide, zinc tin oxide, indium zinc oxide, gallium zinc oxide, aluminum zinc oxide, cadmium oxide, hafnium indium zinc oxide, tin oxide, stannous tin oxide, stannic tin oxide, indium-tin-zinc oxide, indium-tungsten oxide, indium-gallium-zinc-tin oxide, indium-gallium-zinc-ozynitride, aluminum-indium-gallium-zinc oxide, and zinc-indium oxide.
  • the Amorphous Oxide Semiconductor channel layer may be doped with at least one dopant selected from the group consisting of Gallium (Ga), Indium (In), Zinc (Zn), Tin (Sn), Hafnium (Hf), Silicon (Si), Aluminum (Al), Magnesium (Mg), Calcium (Ca), Strontium (Sr), Barium (Ba), Titanium (Ti), Zirconium (Zr), Molybdenum (Mo), Tantalum (Ta), Niobium (Nb), Chromium (Cr), Iron (Fe), Cobalt (Co), Nickel (Ni), Copper (Cu), Silver (Ag), Gold (Au), Cerium (Ce), Lanthanum (La), Neodymium (Nd), Samarium (Sm), Europium (Eu), Gadolinium (Gd), Terbium (Tb), Dysprosium (Dy), Holmium (Ho), Erbium (Er), Thulium (Ta), Tin (Sn), Haf
  • the channel layer of the first transistor is formed from two dimensional materials including transition metal dichalcogenides.
  • the transition metal dichalcogenides may be in a monovalent or divalent form.
  • the chalcogenide element in the transition metal dichalcogenides is sulfur, selenium or tellurium.
  • the transition metal dichalcogenides (TMDs) may be written as MX2 where M refers to transition metal atom, such as molybdenum (Mo), tungsten (W), platinum (Pt), and palladium (Pd), while X is the chalcogen atom, such as sulfur (S), selenium (Se), and tellurium (Te).
  • the TMDs present a wide range of electrical properties from semiconducting [molybdenum disulfide (MoS2), molybdenum diselenide (MoSe2), tungsten disulfide (WS2), and tungsten diselenide (WSe2)], to semimetallic [molybdenum ditelluride (MoTe2), tungsten ditelluride (WTe2), and titanium diselenide (TiSe2)], to metallic niobium disulfide (NbS2), titanium disulfide (TiS2), nickel disulfide (NiS2), and vanadium diselenide (VSe2)], and to superconducting [niobium diselenide (NbSe2) and tantalum sulfide (TaS2)] regimes.
  • the channel layer of the integrated circuit is formed from two dimensional materials including transition metal dichalcogenides.
  • the transition metal dichalcogenides may be monovalent
  • the channel layer of the integrated circuit embodiment may be formed from two dimensional transition metal dichalcogenides materials. Specifically, these transition metal dichalcogenides may have a divalent transition metal composition. The use of divalent transition metal dichalcogenides for the channel layer enables favorable electrical properties for the operation of transistors formed from the integrated circuit components.
  • the transition metal dichalcogenides from which the channel layer is formed can have a chalcogenide element that is sulfur.
  • the integrated circuit may comprise transition metal dichalcogenides wherein the channel layer is formed.
  • the transition metal dichalcogenides may be monovalent or divalent.
  • the chalcogenide element in the transition metal dichalcogenides could be selenium.
  • the integrated circuit may involve the channel layer being formed from two dimensional materials including transition metal dichalcogenides.
  • the transition metal dichalcogenides may have a chalcogenide element such as tellurium.
  • the channel layer of the transistor may be formed from Indium Tungsten Oxide (IWO). This material can provide desirable properties for the channel layer, such as high mobility for charge carriers.
  • IWO Indium Tungsten Oxide
  • the use of IWO allows for fabrication of high performance transistors suitable for various integrated circuit applications.
  • the channel layer of the transistor may be formed from an indium gallium zinc oxide (IGZO).
  • IGZO indium gallium zinc oxide
  • the IGZO material provides desirable properties for the channel layer such as high electron mobility and stability when deposited as a thin film, allowing effective operation of the transistors within the integrated circuit.
  • the channel layer may be a thin film.
  • the embodiment may involve the ferroelectric layer being composed of hafnium zirconium oxide with an equal molar ratio of hafnium to zirconium (Hf0.5Zr0.5O2).
  • the integrated circuit comprising the ferroelectric FET may be disposed on a back-end-of-the-line (BEOL) portion of a semiconductor device fabrication flow. More specifically, this would involve fabricating the integrated circuit containing the ferroelectric layer and channel layer of the FET on the higher layers above the transistor level after the front-end-of-line processing has been completed. Disposing the integrated circuit in the BEOL portion enables integration with underlying transistor structures and metal interconnect layers that have already been fabricated on the chip.
  • BEOL back-end-of-the-line
  • the ferroelectric layer in the integrated circuit is made of transition metal oxides, a perovskite, or a two-dimensional material.
  • the integrated circuit further comprises a metal layer disposed between the channel layer and the ferroelectric layer.
  • the integrated circuit further comprises an insulator layer disposed between the metal layer and the channel layer.
  • a metal layer may be disposed between the channel layer and the ferroelectric layer.
  • an insulator layer is disposed between this metal layer and the underlying channel layer.
  • the integrated circuit further comprises a metal layer disposed on the ferroelectric layer, wherein the ferroelectric layer is disposed on the channel layer.
  • the integrated circuit further comprises a metal layer disposed on the ferroelectric layer, wherein the ferroelectric layer is disposed on the channel layer. Additionally, in some embodiments, an insulation layer is disposed on the channel layer, and the ferroelectric layer is also disposed on the insulation layer.
  • the embodiment may further comprise a metal layer disposed on the ferroelectric layer, wherein the ferroelectric layer is disposed on the channel layer.
  • This additional metal layer on top of the ferroelectric material can serve various purposes, such as providing an improved electrical contact or acting as a barrier layer. Its integration on top of the ferroelectric and channel layers enables optimization of the electrical performance and reliability of the ferroelectric field-effect transistor.
  • the channel layer of the integrated circuit may have a thickness of less than 30 nm. Constructing the channel layer to be this thin allows for reduced dimensions and potentially improved performance of the transistors formed using the channel layer.
  • the channel layer may have a thickness between 1 to 30 nm. Configuring the channel layer to be less than 30 nm in thickness enables effective charge modulation by the adjacent ferroelectric layer within this ultra-scaled dimension. Maintaining dimensions on the lower end of this range, between 1 to 10 nm for example, allows the integrated circuit to leverage improvements in channel controllability and reduced shortchannel effects. The relatively thin channel layer dimension thus facilitates low voltage operation and efficient switching.
  • the channel layer of the transistor may be formed using physical vapor deposition or chemical vapor deposition. These deposition techniques can be used to deposit very thin films needed for the channel layer. The channel layer formed in this way may be less than 30 nm in thickness or between 1 to 30 nm in thickness.
  • the channel layer of the integrated circuit is formed using atomic layer deposition. This manufacturing process enables precise thickness control and uniform coverage during the deposition of the thin channel layer. By building up the channel layer one atomic layer at a time through sequential, self-limiting surface reactions, atomic layer deposition allows for sub-nanometer thickness control.
  • the embodiment may involve the channel layer being formed by adding a dopant comprising at least one of tungsten, gallium (Ga), and zinc (Zn).
  • a dopant comprising at least one of tungsten, gallium (Ga), and zinc (Zn).
  • the channel layer is formed using physical vapor deposition or chemical vapor deposition, and the dopant helps enable deposition of the thin channel layer.
  • the embodiment may involve the ferroelectric layer being formed using atomic layer deposition.
  • the integrated circuit's ferroelectric layer may be formed using vapor deposition.
  • the ferroelectric layer in the integrated circuit is formed by adding a dopant comprising at least one of Lanthanum, Niobium, Manganese, Zirconium, Tin, Strontium, Calcium, Yttrium, or Magnesium.
  • the doped ferroelectric layer may be formed using atomic layer deposition or vapor deposition methods. Doping the ferroelectric material can potentially enhance characteristics such as crystallization temperature, remanent polarization, and leakage current.
  • the channel layer may be configured to have a carrier concentration ranging from 10 A l 7 to 10 A 20 per cubic centimeter.
  • the channel layer comprises a two-dimensional material.
  • the two-dimensional material may maintain an electron mobility of at least 0.1 cm-squared per Volt-second when the channel layer is less than 30nm in thickness.
  • the channel layer comprises fewer than 5 monolayers of the two-dimensional material.
  • the channel layer comprises a two-dimensional material.
  • the two-dimensional material may be configured to maintain an electron mobility of at least 0.1 cm-squared per Volt-second when the channel layer is less than 30nm in thickness.
  • the channel layer may comprise a two-dimensional material that maintains high electron mobility even when the channel layer is less than 30nm in thickness.
  • the channel layer may comprise fewer than 5 monolayers of this two- dimensional material. Using only a few monolayers can help minimize thickness while retaining the beneficial properties of the two-dimensional material.
  • the ferroelectric layer utilized in the integrated circuit is Hafnium Zirconium Oxide.
  • the integrated circuit has a ferroelectric layer with a coercive voltage between -3 volts to 3 volts. This specifies the range of voltages that can switch the electric polarization of the ferroelectric material within the layer. By tuning the composition and thickness of the ferroelectric layer, it may exhibit a coercive voltage within this range which enables switching at low voltages compatible with transistor operation. Keeping the coercive voltage relatively low can help reduce the operating voltages and power consumption of devices incorporating the ferroelectric layer.
  • the integrated circuit may have a ferroelectric layer with an off-state current less than 10 A -7 amps per centimeter cubed.
  • the integrated circuit may involve a ferroelectric layer with an on-state current greater than 10 A -7 amps per centimeter cubed.
  • the integrated circuit has a ferroelectric layer with a crystallization anneal temperature less than or equal to 500 degrees Celsius.
  • the integrated circuit may involve a ferroelectric layer with a remanent polarization greater than 10 microcoulombs per square centimeter.
  • the integrated circuit may involve a channel layer that is annealed at a temperature less than 450 degrees Celsius.
  • the channel layer forming part of the transistor structure in the integrated circuit can undergo an annealing process below 450 Celsius. Maintaining a sufficiently low anneal temperature for the channel layer facilitates integration of the ferroelectric material while preserving the integrity of the channel layer itself during device fabrication.
  • the embodiment comprises a channel layer with a channel mobility of less than 100 centimeters squared per volt-second.
  • the channel layer that is part of the integrated circuit with a transistor including a channel layer, a ferroelectric layer, a source terminal, a drain terminal, and a gate terminal has a channel mobility that is configured to be less than 100 cm A 2/V-s.
  • the integrated circuit comprises a channel layer with a subthreshold swing of less than 0.3 volts per decade.
  • the subthreshold swing refers to the change in gate voltage needed to reduce the current in the transistor by one decade, and a lower subthreshold swing enables faster switching speeds and lower power consumption.
  • the channel layer can achieve this ultra-low subthreshold swing.
  • the channel layer in the integrated circuit may be configured to have an off-state current of less than 10 A -7 amps per micrometer.
  • the embodiment includes a channel layer that is configured to have a channel bandgap greater than 2.5 electron-volts.
  • the channel layer may be configured to have a postanneal threshold voltage between -1.5 Volts to 1.5 Volts.
  • the integrated circuit may involve a first transistor having a width of less than 200 nm and a length of 50 nm.
  • the first transistor may have a device area of less than 30 times the square of the feature size.
  • the integrated circuit may have a first transistor with a low-voltage threshold (LVT) level greater than -2.5 V.
  • LVT low-voltage threshold
  • the integrated circuit may have a first transistor with a high-voltage threshold (HVT) level greater than -2V.
  • HVT high-voltage threshold
  • a memory cell incorporating the first transistor has a read voltage between 0V to IV. Operating the memory cell having the first transistor at a read voltage in this range may facilitate low power consumption during read operations. Configuring the transistor characteristics to enable a low read voltage can also contribute to minimizing the overall power requirements of the integrated circuit.
  • a memory cell incorporating the first transistor may have low read energy consumption of less than 10 picojoules.
  • a memory cell containing the ferroelectric field effect transistor detailed previously can optionally be designed and configured to enable read operations that dissipate less than 10 picojoules of energy. The extremely low read energy would allow the fabrication of low-power nonvolatile memories well-suited for battery-powered and energy-constrained applications.
  • a memory cell incorporating the first transistor may have a read pulse width of less than 20 nanoseconds.
  • a memory cell having the first transistor may have a read endurance greater than or equal to 10 A 9 cycles. This indicates that the memory cell can reliably withstand at least one billion read operations without failure, contributing to high reliability and long operating lifetime.
  • a memory cell incorporating the first transistor may have a read disturb tolerance greater than 10 A 9 cycles. This indicates that the memory cell can withstand at least 10 A 9 read cycles without the stored data being disturbed or corrupted, enabling reliable long-term data storage.
  • the high read disturb tolerance is achieved in part due to the properties and configuration of the ferroelectric layer, channel layer, and other components in the first transistor.
  • a memory cell incorporating the first transistor may have a read after write latency less than or equal to 10 microseconds. This indicates that the time delay between completing a write operation to the memory cell and being able to reliably read back the stored data is very short. Enabling such fast read access times allows building high performance memory systems.
  • a memory cell incorporating the first transistor described herein has a write voltage less than or equal to 3.0 Volts (V).
  • a memory cell incorporating the first transistor may have a write speed less than or equal to 10 microseconds.
  • a memory cell having the first transistor described herein has a write energy that is less than 10 picojoules.
  • a memory cell incorporating the first transistor may have a write endurance greater than 10 A 8 cycles. This indicates that the memory cell can withstand at least 100 million write cycles without failure, enabling reliable data storage and retrieval over an extended lifespan. By leveraging the performance characteristics of the underlying ferroelectric field effect transistor, each memory cell can offer improved durability and longevity compared to conventional alternatives. The high write endurance further translates to enhanced data integrity and a reduced need for error correction or redundancy.
  • a memory cell having the first transistor described herein has an off-state resistance to on-state resistance ratio (Roff/Ron) of about 10 A 3 or greater than 10 A 2.
  • a memory cell incorporating the first transistor may have an on-state current to off-state current ratio (lon/Off) at Vread from DC measurement greater than 100.
  • the memory cell with the ferroelectric field effect transistor can achieve a high on-state to off-state current ratio during read operations, indicating good discrimination between logic 0 and logic 1 states stored in the cell. The high lon/Ioff ratio contributes to reliable read operations at low voltages.
  • the memory cell may include the first transistor as described herein and a second transistor having the same configuration as the first transistor. The first transistor and the second transistor can form a bit state for storing a binary value in the memory cell.
  • the integrated circuit may involve a memory cell having the first transistor, wherein the first transistor is configured to have 3 or more states. Each of these states corresponds to a stored value of the memory cell. This allows for multi-level data storage within a single memory cell.
  • the integrated circuit may involve a first transistor that has an on-state current to off-state current ratio (lon/Ioff) at Vread from pulse measurement that is greater than 10 A 2.
  • the integrated circuit comprises a first transistor, as described herein.
  • the first transistor may include an off-state leakage current (loff) that is less than ten to the negative fourteenth amps per micrometer, providing very low leakage when the transistor is not conducting in the off-state.
  • Loff off-state leakage current
  • the transistor By having an off-state leakage current below this threshold, the transistor exhibits very little leakage through the channel and maintains the off-state effectively, allowing for low static power consumption.
  • a memory cell having the first transistor may have a reliability endurance greater than or equal to 10 A l 1 cycles. This high reliability endurance allows the memory cell to withstand an extremely large number of read/write cycles without failure over its lifetime. The robust endurance enables applications requiring frequent data access with minimal downtime for repairs or replacements.
  • a memory cell having the first transistor described herein has a retention time of at least 1 minute when measured at room temperature of 25 C.
  • the channel layer of the first transistor may involve incorporation of another two-dimensional material configured to enhance the on-state current (ION) through the transistor.
  • the additional two-dimensional material provides increased conductivity to allow higher ION when the transistor is switched on.
  • the channel layer in the integrated circuit is configured to maintain high mobility despite the presence of the ferroelectric layer.
  • the channel layer and ferroelectric layer are designed such that the ferroelectric layer does not significantly impede the electron mobility within the channel layer. This allows the integrated circuit transistor to operate with high channel mobility for improved performance while still utilizing the benefits of the ferroelectric layer.
  • the integrated circuit may be configured such that the ferroelectric layer does not significantly impede the electron mobility within the channel layer.
  • the ferroelectric layer and the channel layer may be designed to maintain high mobility despite the presence of the ferroelectric layer on top of the channel layer.
  • the interface between the ferroelectric layer and the channel layer may be optimized to minimize scattering of electrons flowing through the channel.
  • the channel layer is configured to be directly in contact with the ferroelectric layer without an interfacial layer in between.
  • the direct contact between the channel layer and the ferroelectric layer may facilitate minimized voltage drops across the interface, thereby enabling low voltage operation of the transistor.
  • the absence of an interfacial layer between the channel layer and ferroelectric layer can allow for low voltage operation and decreased power consumption.
  • the integrated circuit may comprise a first transistor with a channel layer that is in direct contact with the ferroelectric layer, without an interfacial layer in between.
  • This direct contact configuration may help to minimize voltage drops across the interface between the channel layer and the ferroelectric layer. By reducing such parasitic voltage drops, the first transistor can potentially be operated at lower voltages, thereby enabling low voltage operation and reduced power consumption.
  • the absence of an interfacial layer can also contribute to faster switching times and improved transient characteristics.
  • the integrated circuit may involve a first transistor characterized by low voltage operation and low power consumption. This is due to the absence of an interfacial layer between the channel layer and the ferroelectric layer in some embodiments.
  • the integrated circuit may involve a first transistor characterized by low voltage operation and low power consumption. This can be due to the absence of an interfacial layer between the ferroelectric layer and the gate layer of the first transistor.
  • the reduced voltage operation can contribute to a decrease in overall power consumption of the integrated circuit.
  • the integrated circuit is characterized by low voltage operation and low power consumption due to the absence of an interfacial layer between the channel layer and the ferroelectric layer or between the ferroelectric layer and the gate layer. This reduced voltage operation may contribute to a decrease in the overall power consumption of the integrated circuit.
  • the integrated circuit may involve the first transistor being characterized by improved switching characteristics such as faster turn-on and turn-off times. This may be due to the absence of an interfacial layer between the ferroelectric layer and the channel layer or between the ferroelectric layer and the gate layer. The lack of an interfacial layer can contribute to reduced parasitic capacitance at these interfaces, enabling faster charging and discharging of the ferroelectric layer during write and erase operations of the transistor.
  • the integrated circuit may be characterized by reduced parasitic capacitance at the interface between the channel layer and the ferroelectric layer due to the absence of an interfacial layer between them.
  • the direct contact between the channel layer and the ferroelectric layer can minimize voltage drops across the interface, enabling low voltage operation of the transistors.
  • the reduced parasitic capacitance can also contribute to improved switching characteristics of the transistors, including faster turn-on and turn-off times.
  • the ferroelectric layer may be configured for a substantially uniform electric field distribution across the ferroelectric layer.
  • the integrated circuit may involve the ferroelectric layer being configured for a gradient in the electric field distribution across the ferroelectric layer.
  • the integrated circuit further comprises a microvault formed from a plurality of transistors including the first transistor as described herein.
  • the microvault may be organized into columns comprising 3 terminal bit-cells.
  • the microvault is formed via a column in one of a 3D-N0R, a 3D-AND, a 3D-NAND, or a 3D- NAND-PG configuration.
  • the microvault comprises columns of 3-terminal bit cells.
  • each microvault may be arranged into vertical columns, with each column functioning as a bit cell having three terminals - source, drain, and gate terminals corresponding to the transistors in that column.
  • This 3-terminal bit cell configuration in columnar form facilitates compact integration and wiring of the microvault memory structure.
  • the integrated circuit may comprise a microvault formed from a plurality of transistors.
  • the microvault may be organized into columns comprising 3 terminal bit-cells in one of several configurations, including a 3D-NOR, a 3D-AND, a 3D- NAND, or a 3D-NAND with an additional pass gate (3D-NAND-PG).
  • the integrated circuit may comprise a channel material that includes Indium Gallium Zinc Oxide (IGZO) in some embodiments.
  • IGZO Indium Gallium Zinc Oxide
  • the channel material formed from IGZO can be incorporated into the transistors described herein.
  • the embodiment may comprise a source terminal fixed to the channel layer.
  • the source terminal is formed from at least one of Tungsten, Titanium Nitride, Nickel, and Molybdenum.
  • the drain terminal of the first transistor comprises at least one of Tungsten, Titanium Nitride, Nickel, and Molybdenum. These materials may be utilized to form the drain contact to enable effective carrier transport and integration within the fabrication process flow.
  • the gate terminal of the first transistor comprises at least one of tungsten, titanium nitride, nickel, and molybdenum. These materials are utilized for their conductive properties and integration compatibility in semiconductor fabrication processes. The selection of an appropriate gate terminal material can impact transistor performance and reliability.
  • the integrated circuit further comprises a memory formed from a plurality of the first transistors.
  • the memory may be formed as a 3D vertical device architecture selected from NAND and NOR configurations.
  • the integrated circuit comprises a microvault column comprising a plurality of transistors.
  • Each of the plurality of transistors in the microvault column may be configured the same as the first transistor described previously.
  • the microvault column comprising the plurality of identical transistors may be organized into a 3D vertical architecture such as a 3D-NOR, a 3D-AND, a 3D-NAND, or a 3D-NAND with pass gate.
  • the integrated circuit may comprise a microvault column comprising a plurality of transistors, each of the transistors configured identically to the first transistor.
  • the microvault column may be organized in a 3D-NOR configuration.
  • the integrated circuit comprises a microvault column comprising a plurality of transistors, each of the transistors configured according to the first transistor.
  • the microvault column may be configured as a 3D-AND structure.
  • the integrated circuit may comprise a microvault column comprising a plurality of transistors, each configured similar to the first transistor.
  • the microvault column may be arranged in a 3D-NAND configuration.
  • the integrated circuit may comprise a microvault column comprising a plurality of transistors, wherein each of the plurality of transistors is configured according to the first transistor design as described previously.
  • the microvault column may be organized in a 3D-NAND architecture with a pass gate coupled to all of the plurality of transistors.
  • the integrated circuit may involve a microvault column comprising a plurality of transistors, wherein each transistor includes a source coupled to a bit line, a drain coupled to a read enable line, and a gate coupled to a write enable line. This microvault column configuration enables independent control of reading and writing operations through separate read and write enable lines.
  • the integrated circuit may comprise a microvault column comprising a plurality of transistors, each formed similarly to the first transistor.
  • the microvault column may be configured as a 3D-AND architecture with an independent read/write enable line coupled to each transistor.
  • each transistor in the 3D-AND microvault column may have a source terminal coupled to a bit line, a drain terminal coupled to a select line, and a gate terminal coupled to a read/write enable line that is independent from the other transistors.
  • the ferroelectric layer utilized in the integrated circuit is formed from various ferroelectric materials including but not limited to perovskites, lead zirconate titanate (PZT), barium titanate (BaTiO3), strontium titanate (SrTiO3), bismuth ferrite (BiFeO3), potassium niobate (KNbO3), lithium niobate (LiNbO3), lithium tantalate (LiTaO3), sodium bismuth titanate (Na0.5Bi0.5TiO3), bismuth titanate (Bi4Ti3O12), bismuth zinc niobate (Bi(Znl/2Ti 1/2)03), bismuth lanthanum titanate (BiLaTiO3), bismuth nickel titanate (BiNiTiO3), lead magnesium niobate-lead titanate (PMN-PT), lead lanthanum zirconate titanate (PLZT), lead zirconate titanate
  • the integrated circuit comprises a first vertical structure with a dielectric column, a channel column disposed around the dielectric column, and a ferroelectric column disposed around the channel column along its length.
  • the integrated circuit further comprises a plurality of horizontal gate-electrode layers, each disposed a predetermined distance from each other. Each of the horizontal gate-electrode layers is disposed adjacent to the ferroelectric column along its length.
  • the integrated circuit embodiment may have a dielectric column that is substantially cylindrical in shape.
  • the dielectric column around which the channel column is disposed can be formed to have a circular or elliptical cross-section along its vertical length. Making the dielectric column cylindrical can facilitate conformal deposition of the surrounding channel material.
  • the dielectric column in the first vertical structure is substantially cylindrical.
  • the dielectric column may have a first diameter on a first end and a second diameter on the second end.
  • the first and second diameters can be the same or the first diameter can be larger than the second diameter.
  • the dielectric column of the first vertical structure is substantially cylindrical, with a first diameter on a first end and a second diameter on a second, opposite end.
  • the first and second diameters of the dielectric column may be configured to be the same.
  • the dielectric column in the first vertical structure has a first diameter on a first end and a second diameter on the second end, where the first diameter is larger than the second diameter.
  • the integrated circuit comprises a first vertical structure with a dielectric column.
  • the dielectric column may be configured as a solid column rather than a hollow column. Forming the dielectric column as a solid structure can provide mechanical stability and robustness to the overall vertical stack.
  • the integrated circuit may involve a dielectric column that is hollow.
  • the dielectric column that is disposed around the channel column in the first vertical structure can optionally be configured as a hollow column, rather than a solid column. This hollow configuration of the dielectric column can facilitate certain fabrication processes or enable additional components to be integrated within the column.
  • the dielectric column may be implemented as a solid column instead.
  • the channel column formed around the dielectric column in the first vertical structure may be substantially cylindrical in shape.
  • the channel column could have a circular or oval cross-section along its vertical length.
  • a cylindrical channel column configuration may provide certain advantages related to current flow, capacitance, or ease of manufacturing.
  • the channel column formed around the dielectric column is substantially cylindrical, as described in the summary section.
  • the channel column has a first diameter on a first end and a second diameter on the second end.
  • the first and second diameters may be the same.
  • the first diameter may be larger than the second diameter.
  • the channel column of the first vertical structure has a substantially cylindrical shape with a uniform diameter from a first end to a second end.
  • the integrated circuit comprises a first vertical structure with a dielectric column that has a first diameter on a first end and a second diameter on the second end, wherein the first diameter is larger than the second diameter.
  • the ferroelectric column may be substantially cylindrical.
  • the integrated circuit further comprises a first vertical structure with a ferroelectric column disposed around a channel column.
  • this ferroelectric column may be formed in a substantially cylindrical shape.
  • the integrated circuit may have a ferroelectric column that is substantially cylindrical, as described for the first vertical structure.
  • This ferroelectric column may have a first diameter on a first end and a second diameter on the second, opposing end.
  • the first and second diameters may be the same or the first diameter may be larger than the second diameter in some cases.
  • the integrated circuit has a ferroelectric column that is substantially cylindrical, with a first diameter on a first end and a second diameter on a second end, where the first and second diameters may be configured to be the same.
  • the integrated circuit may involve a ferroelectric column that is substantially cylindrical.
  • the ferroelectric column may have a first diameter on a first end and a second diameter on the second end, wherein the first diameter is larger than the second diameter.
  • the integrated circuit further comprises a dielectric end column disposed around an end of the channel column. This dielectric end column is positioned adjacent to an end of the length of the channel column and also adjacent to the ferroelectric column.
  • the integrated circuit further comprises a drain select layer disposed in parallel with the plurality of horizontal gate-electrode layers and adjacent to the dielectric end column.
  • This drain select layer is arranged adjacent to the dielectric end column that surrounds one end of the channel column.
  • the integrated circuit further comprises a second dielectric end column disposed around another end of the channel column. This second dielectric end column is adjacent to another end of the length of the channel column and also adjacent to the ferroelectric column.
  • the integrated circuit may further comprise a source select layer disposed in parallel with the plurality of horizontal gate-electrode layers. This source select layer would be adjacent to the second dielectric end column that is disposed around another end of the channel column. The second dielectric end column is adjacent to another end of the length of the channel column and adjacent to the ferroelectric column in some embodiments.
  • the integrated circuit further comprises a second vertical structure.
  • the second vertical structure may be formed to be substantially identical to the first vertical structure, but disposed adjacent to the first vertical column at a predetermined horizontal distance.
  • the integrated circuit may comprise a second vertical structure.
  • the second vertical structure may be formed to be substantially identical to the first vertical structure, but disposed adjacent the first vertical column at a predetermined horizontal distance.
  • the integrated circuit may comprise a first vertical structure and a second vertical structure, wherein the second vertical structure is formed to be substantially identical to the first vertical structure, but disposed adjacent the first vertical column at a predetermined horizontal distance.
  • the first and second vertical structures may be configured to form a single-port 3D NAND structure.
  • the plurality of horizontal gate-electrode layers of the first vertical structure are formed from at least one of Tungsten, Titanium Nitride, Tantalum Nitride, Nickel, Molybdenum, Platinum, Palladium, Cobalt, Gold, Aluminum, Copper, Hafnium, Hafnium Nitride, Iridium, Iridium Oxide, Ruthenium, Ruthenium Oxide, Silicides, TiSi2, CoSi2, NiSi, Graphene, Carbon Nanotubes, Doped Polysilicon, Indium Tin Oxide, Silver, Aluminum-doped Zinc Oxide, Gallium, Gallium Arsenide, Indium Gallium Zinc Oxide, Metal Alloys, AICu, TiW, and Conducting Polymers.
  • the ferroelectric column of the first vertical structure is formed from at least one of the following materials: Perovskites; Lead Zirconate Titanate (PZT); Barium Titanate (BaTiO3); Strontium Titanate (SrTiO3); Bismuth Ferrite (BiFeO3); Potassium Niobate (KNbO3); Lithium Niobate (LiNbO3); Lithium Tantalate (LiTaO3); Sodium Bismuth Titanate (Na0.5Bi0.5TiO3); Bismuth Titanate (Bi4Ti3O12); Bismuth Zinc Niobate (Bi(Znl/2Ti 1/2)03); Bismuth Lanthanum Titanate (BiLaTiO3); Bismuth Nickel Titanate (BiNiTiO3); Lead Magnesium Niobate-Lead Titanate (PMN-PT); Lead Lanthanum Zirconate Titanate (PLZT);
  • PZT Lead Zircon
  • the channel column of the first vertical structure is formed from at least one of Indium Gallium Zinc Oxide (IGZO), Indium Zinc Oxide (IZO), Zinc Tin Oxide (ZTO), Aluminum Zinc Oxide (AZO), Indium Tungsten Oxide (IWO), Gallium Zinc Oxide (GZO), Hafnium Indium Oxide (HIO), Cadmium Oxide (CdO), Polysilicon, Polygermanium, Cadmium Selenide (CdSe), Copper Indium Gallium Selenide (CIGS), Crystalline Silicon (c-Silicon), Crystalline Germanium (c-Germanium), Gallium Arsenide (GaAs), Indium Phosphide (InP), Indium Antimonide (InSb), Silicon Carbide (SiC), Gallium Nitride (GaN), Zinc Oxide (ZnO), Pentacene, P3HT (Poly(3 -hexylthiophene)), Polythiophene
  • the dielectric column of the first vertical structure is formed from at least one of Hafnium Oxide (HfO2), Zirconium Oxide (ZrO2), Aluminum Oxide (A12O3), Silicon Dioxide (SiO2), Titanium Dioxide (TiO2), Tantalum Oxide (Ta2O5), Lanthanum Oxide (La2O3), Yttrium Oxide (Y2O3), Silicon Nitride (Si3N4), Aluminum Nitride (AIN), Silicon Carbide (SiC), Strontium Titanate (SrTiO3), Barium Strontium Titanate (BST), Lead Zirconate Titanate (PZT), Bismuth Ferrite (BiFeO3), Magnesium Oxide (MgO), Cerium Oxide (CeO2), Nickel Oxide (NiO), Cobalt Oxide (CoO), Copper Oxide (CuO), Manganese Oxide (MnO), Zinc Oxide (ZnO), Zinc Oxide (ZnO
  • one of the plurality of horizontal gate-electrode layers and the first vertical structure may be configured to form a plurality of transistors. These transistors can include the first transistor as described herein.
  • the first vertical structure comprises a dielectric column, a channel column disposed around the dielectric column, a ferroelectric column disposed around the channel column, and a plurality of horizontal gateelectrode layers disposed adjacent to the ferroelectric column.
  • the integrated circuit may comprise a first vertical structure.
  • the first vertical structure may comprise a pass-gate electrode column.
  • a dielectric column may be disposed around the pass-gate electrode column.
  • a channel column may be disposed around the dielectric column.
  • a ferroelectric column may be disposed around the channel along a length of the channel column.
  • the integrated circuit may further comprise a plurality of horizontal gate-electrode layers, where each layer is disposed a predetermined distance between each other. Each of the plurality of horizontal gate-electrode layers may be disposed adjacent to the ferroelectric column along the length of the ferroelectric column.
  • the integrated circuit may involve a pass-gate electrode column that is substantially cylindrical in form.
  • This cylindrical pass-gate electrode column can optionally have a first diameter on one end and a second diameter on the other end, with the diameters either being the same or the first diameter larger than the second.
  • the pass-gate electrode column may also be configured as either a solid column or a hollow column in different variants.
  • the integrated circuit may have a pass-gate electrode column that is substantially cylindrical, according to one embodiment.
  • this pass-gate electrode column has a first diameter on a first end and a second diameter on the second end. These first and second diameters may be the same or different in various embodiments, with the first diameter optionally being larger than the second diameter in some cases.
  • the pass-gate electrode column of the first vertical structure is substantially cylindrical, with a first diameter on a first end and a second diameter on a second, opposite end.
  • the integrated circuit may be configured such that the first diameter and the second diameter of the pass-gate electrode column are the same.
  • the pass-gate electrode column of the first vertical structure is substantially cylindrical, with a first diameter on a first end and a second diameter on the second end.
  • the first diameter of the pass-gate electrode column may be larger than the second diameter.
  • the integrated circuit may comprise a pass-gate electrode column that is part of the first vertical structure.
  • This pass-gate electrode column may be substantially cylindrical in form.
  • the pass-gate electrode column is solid rather than hollow.
  • the integrated circuit may have a pass-gate electrode column that is hollow.
  • the pass-gate electrode column that is part of the first vertical structure and is disposed around the dielectric column and within the channel column may be hollow rather than a solid column. Forming the pass-gate electrode column in a hollow configuration may provide certain advantages related to materials cost or processing simplicity.
  • the integrated circuit may comprise a dielectric column that is substantially cylindrical in shape. This cylindrical dielectric column is disposed around a pass-gate electrode column as part of a first vertical structure. The diameter of the dielectric column may be uniform along its length or may vary from one end to the other.
  • the dielectric column of the first vertical structure is substantially cylindrical.
  • the dielectric column may have a first diameter on a first end and a second diameter on the second end. The first and second diameters of the dielectric column may be configured to be the same or different in various embodiments.
  • the dielectric column in the first vertical structure is substantially cylindrical, with a first diameter on a first end and a second diameter on the second end.
  • the first and second diameters of the dielectric column may be configured to be the same.
  • the integrated circuit may comprise a dielectric column that is substantially cylindrical, wherein the dielectric column has a first diameter on a first end and a second diameter on the second end. In some embodiments, the first diameter of the dielectric column is larger than the second diameter.
  • the integrated circuit may comprise a channel column that is substantially cylindrical in shape.
  • the channel column is disposed around a dielectric column, which itself is disposed around a pass-gate electrode column.
  • a ferroelectric column is disposed around the cylindrical channel column along the length of the channel column.
  • the channel column formed around the dielectric column in the first vertical structure is substantially cylindrical in shape.
  • the channel column may have a first diameter on a first end and a second diameter on a second, opposite end.
  • the first and second diameters of the channel column may be the same or the first diameter may be larger than the second diameter.
  • the channel column in the first vertical structure may have a substantially cylindrical shape with a uniform diameter along its entire length. Specifically, the channel column has a first diameter on a first end and a second diameter on a second, opposite end, wherein the first and second diameters are identical. This uniform cylindrical channel column runs parallel to the ferroelectric column and plurality of horizontal gate-electrode layers in the vertical structure.
  • the integrated circuit may involve a channel column that is substantially cylindrical, wherein the channel column has a first diameter on a first end and a second diameter on the second end.
  • the first diameter of the channel column is configured to be larger than the second diameter.
  • the integrated circuit may have a ferroelectric column that is substantially cylindrical in shape.
  • the ferroelectric column is disposed around the channel column along the length of the channel column.
  • the cylindrical ferroelectric column optionally has a first diameter on a first end and a second diameter on the second end, where the diameters may be the same or the first diameter may be larger than the second diameter.
  • the integrated circuit may comprise a ferroelectric column that is substantially cylindrical.
  • the ferroelectric column may have a first diameter on a first end and a second diameter on the second end.
  • the first diameter and the second diameter can be the same or the first diameter can be larger than the second diameter.
  • the ferroelectric column of the first vertical structure is substantially cylindrical, having a first diameter on a first end and a second diameter on the second end.
  • the first and second diameters of the ferroelectric column are configured to be the same.
  • the integrated circuit may have a ferroelectric column that is substantially cylindrical, with a first diameter on a first end and a second diameter on the second end, where the first diameter is larger than the second diameter.
  • the integrated circuit further comprises a dielectric end column disposed around an end of the channel column. This dielectric end column is adjacent to an end of the length of the channel column and also adjacent to the ferroelectric column.
  • the integrated circuit further comprises a drain select layer disposed in parallel with the plurality of horizontal gate-electrode layers.
  • the drain select layer is positioned adjacent to the dielectric end column surrounding an end of the channel column.
  • the dielectric end column is adjacent to an end of the length of the channel column and adjacent to the ferroelectric column in the first vertical structure.
  • the integrated circuit further comprises a second dielectric end column disposed around another end of the channel column. This second dielectric end column is adjacent to another end of the length of the channel column and also adjacent to the ferroelectric column.
  • the integrated circuit further comprises a source select layer disposed in parallel with the plurality of horizontal gate-electrode layers and adjacent to the second dielectric end column surrounding the other end of the channel column.
  • the source select layer is positioned adjacent to the end of the length of the channel column and the ferroelectric column.
  • the integrated circuit further comprises a dielectric horizontal layer disposed within the channel column and adjacent to an end of the pass-gate electrode column.
  • a dielectric layer may be incorporated horizontally within the cylindrical channel column structure, positioned next to the end of the vertical pass-gate electrode column. This dielectric isolation layer aids in delimiting the pass-gate region within the 3D NAND string.
  • the integrated circuit may comprise a second vertical structure in addition to the first vertical structure.
  • the first vertical structure comprises a pass-gate electrode column, a dielectric column disposed around the pass-gate electrode column, a channel column disposed around the dielectric column, and a ferroelectric column disposed around the channel column along its length.
  • Each of the plurality of horizontal gate-electrode layers is disposed a predetermined distance between each other and adjacent to the ferroelectric column.
  • the second vertical structure may be formed substantially identically to the first vertical structure, but disposed horizontally adjacent to the first vertical structure at a predetermined distance.
  • the integrated circuit may comprise a second vertical structure in addition to the first vertical structure described previously.
  • this second vertical structure is formed to have substantially the same composition and dimensions as the first vertical structure.
  • the second structure is disposed horizontally adjacent to the first vertical structure at a predetermined distance between them. Configuring two identical vertical structures in this parallel arrangement enables certain circuit configurations such as forming a dual-port 3D NAND structure with the paired vertical structures.
  • the integrated circuit may comprise first and second vertical structures, wherein the second vertical structure is formed to be substantially identical to the first vertical structure, but disposed adjacent to the first vertical column at a predetermined horizontal distance.
  • these first and second vertical structures are configured to form a dualport 3D NAND structure.
  • the plurality of horizontal gate-electrode layers of the first vertical structure may be formed from at least one conductive material selected from a group consisting of Tungsten, Titanium Nitride, Tantalum Nitride, Nickel, Molybdenum, Platinum, Palladium, Cobalt, Gold, Aluminum, Copper, Hafnium, Hafnium Nitride, Iridium, Iridium Oxide, Ruthenium, Ruthenium Oxide, Silicides such as TiSi2, CoSi2, and NiSi, Graphene, Carbon Nanotubes, Doped Polysilicon, Indium Tin Oxide, Silver, Aluminum-doped Zinc Oxide, Gallium, Gallium Arsenide, Indium Gallium Zinc Oxide, Metal Alloys such as AICu and TiW, and Conducting Polymers.
  • Tungsten Titanium Nitride, Tantalum Nitride, Nickel, Molybdenum, Platinum, Palladium, Cobalt
  • Gold Aluminum, Copper, Hafnium, Hafnium Nitride,
  • the pass-gate electrode column of the first vertical structure is formed from at least one of the following materials: Tungsten, Titanium Nitride, Tantalum Nitride, Nickel, Molybdenum, Platinum, Palladium, Cobalt, Gold, Aluminum, Copper, Hafnium, Hafnium Nitride, Iridium, Iridium Oxide, Ruthenium, Ruthenium Oxide, Silicides such as TiSi2, CoSi2, and NiSi, Graphene, Carbon Nanotubes, Doped Poly silicon, Indium Tin Oxide, Silver, Aluminum-doped Zinc Oxide, Gallium, Gallium Arsenide, Indium Gallium Zinc Oxide, Metal Alloys such as AICu and TiW, and Conducting Polymers.
  • the passgate electrode column may be constructed using one or more of these conductive materials.
  • the ferroelectric column of the first vertical structure is formed from at least one of the following ferroelectric materials: Perovskites; Lead Zirconate Titanate (PZT); Barium Titanate (BaTiO3); Strontium Titanate (SrTiO3); Bismuth Ferrite (BiFeO3); Potassium Niobate (KNbO3); Lithium Niobate (LiNbO3); Lithium Tantalate (LiTaO3); Sodium Bismuth Titanate (Na0.5Bi0.5TiO3); Bismuth Titanate (Bi4Ti3O12); Bismuth Zinc Niobate (Bi(Znl/2Ti 1/2)03); Bismuth Lanthanum Titanate (BiLaTiO3); Bismuth Nickel Titanate (BiNiTiO3); Lead Magnesium Niobate-Lead Titanate (PMN-PT); Lead Lanthanum Zirconate Titanate (PL
  • the channel column of the first vertical structure is formed from at least one of the following materials: Indium Gallium Zinc Oxide (IGZO), Indium Zinc Oxide (IZO), Zinc Tin Oxide (ZTO), Aluminum Zinc Oxide (AZO), Indium Tungsten Oxide (IWO), Gallium Zinc Oxide (GZO), Hafnium Indium Oxide (HIO), Cadmium Oxide (CdO), Polysilicon, Polygermanium, Cadmium Selenide (CdSe), Copper Indium Gallium Selenide (CIGS), Crystalline Silicon (c-Silicon), Crystalline Germanium (c- Germanium), Gallium Arsenide (GaAs), Indium Phosphide (InP), Indium Antimonide (InSb), Silicon Carbide (SiC), Gallium Nitride (GaN), Zinc Oxide (ZnO), Pentacene, P3HT (Poly(3- hexylthiophene)), Poly
  • the dielectric column described herein is formed from at least one of Hafnium Oxide (HfO2), Zirconium Oxide (ZrO2), Aluminum Oxide (A12O3), Silicon Dioxide (SiO2), Titanium Dioxide (TiO2), Tantalum Oxide (Ta2O5), Lanthanum Oxide (La2O3), Yttrium Oxide (Y2O3), Silicon Nitride (Si3N4), Aluminum Nitride (AIN), Silicon Carbide (SiC), Strontium Titanate (SrTiO3), Barium Strontium Titanate (BST), Lead Zirconate Titanate (PZT), Bismuth Ferrite (BiFeO3), Magnesium Oxide (MgO), Cerium Oxide (CeO2), Nickel Oxide (NiO), Cobalt Oxide (CoO), Copper Oxide (CuO), Manganese Oxide (MnO), Zinc Oxide (ZnO), Ga
  • one of the plurality of horizontal gate-electrode layers and the first vertical structure may be configured to form a plurality of transistors. These transistors can include the first transistor as described herein.
  • the first vertical structure comprises a pass-gate electrode column, a dielectric column disposed around the passgate electrode column, a channel column disposed around the dielectric column, and a ferroelectric column disposed around the channel column along its length.
  • the plurality of horizontal gate-electrode layers are each disposed a predetermined distance between one another and adjacent to the ferroelectric column along its length. Together, one of these horizontal gate-electrode layers and the first vertical structure form the plurality of transistors, which can include the first transistor with the configuration set forth herein.
  • the integrated circuit comprises a first vertical structure.
  • This vertical structure may involve a vertical plug column. Adjacent to this vertical plug column, there may be disposed a source electrode column and a drain electrode column.
  • a channel column may be disposed around the vertical plug column, the source electrode column, and the drain electrode column.
  • a ferroelectric column may be disposed around this channel column.
  • the integrated circuit may also involve a plurality of horizontal gateelectrode layers, each disposed a predetermined distance apart from each other. These horizontal gate-electrode layers may each be disposed adjacent to the ferroelectric column along its length.
  • the integrated circuit further comprises an Oxide/Nitride/Oxide stack disposed adjacent to each of the plurality of horizontal gateelectrode layers.
  • the Oxide/Nitride/Oxide stack may provide electrical isolation between the gate-electrode layers while enabling the layers to control channel formation in the vertical channel column structure.
  • the integrated circuit's vertical plug column has a first diameter on a first end and a second diameter on the second end.
  • the first and second diameters may be the same or different.
  • the vertical plug column of the first vertical structure has a first diameter on a first end and a second diameter on a second end.
  • the first and second diameters may be configured to be the same.
  • the vertical plug column in the first vertical structure has a first diameter on a first end and a second diameter on the second end, where the first diameter is larger than the second diameter.
  • the vertical plug column of the first vertical structure is configured to be solid rather than hollow.
  • the vertical plug column has a continuous material filling rather than being an empty conduit. Forming the vertical plug column in a solid configuration may provide certain advantages for the overall integrated circuit structure related to simplicity of fabrication or integrity of adjacent components. However, other embodiments may utilize a hollow configuration for the vertical plug column depending on the specific design considerations.
  • the integrated circuit may have a vertical plug column that is hollow.
  • the vertical plug column that is disposed adjacent to the source electrode column and the drain electrode column in the first vertical structure may be hollow rather than solid. Forming a hollow vertical plug column structure enables additional design flexibility.
  • the integrated circuit further comprises a second vertical structure.
  • the second vertical structure may be formed to be substantially identical to the first vertical structure, but disposed adjacent to the first vertical structure at a predetermined horizontal distance.
  • the first and second vertical structures can be configured to form a 3D AND-structure or a 3D NOR- structure.
  • the integrated circuit further comprises a second vertical structure.
  • the second vertical structure may be formed to be substantially identical to the first vertical structure, but disposed adjacent to the first vertical structure at a predetermined horizontal distance.
  • the integrated circuit may comprise a first vertical structure and a second vertical structure, wherein the second vertical structure is formed to be substantially identical to the first vertical structure but disposed adjacent to the first vertical structure at a predetermined horizontal distance.
  • the first and second vertical structures may be configured to form a 3D AND-structure.
  • the integrated circuit may comprise a first vertical structure and a second vertical structure, wherein the second vertical structure is formed to be substantially identical to the first vertical structure but disposed adjacent to the first vertical structure at a predetermined horizontal distance.
  • the first and second vertical structures may be configured to form a 3D NOR-structure.
  • the plurality of horizontal gate-electrode layers of the first vertical structure may be formed from at least one material selected from a group consisting of Tungsten, Titanium Nitride, Tantalum Nitride, Nickel, Molybdenum, Platinum, Palladium, Cobalt, Gold, Aluminum, Copper, Hafnium, Hafnium Nitride, Iridium, Iridium Oxide, Ruthenium, Ruthenium Oxide, Silicides such as TiSi2, CoSi2, NiSi, Graphene, Carbon Nanotubes, Doped Polysilicon, Indium Tin Oxide, Silver, Aluminum-doped Zinc Oxide, Gallium, Gallium Arsenide, Indium Gallium Zinc Oxide, Metal Alloys such as AICu and TiW, and Conducting Polymers.
  • Tungsten Titanium Nitride, Tantalum Nitride, Nickel, Molybdenum, Platinum, Palladium, Cobalt
  • Gold Aluminum, Copper, Hafnium, Hafnium Nitride, Iridium
  • the source electrode column of the first vertical structure is formed from at least one of Tungsten, Titanium Nitride, Tantalum Nitride, Nickel, Molybdenum, Platinum, Palladium, Cobalt, Gold, Aluminum, Copper, Hafnium, Hafnium Nitride, Iridium, Iridium Oxide, Ruthenium, Ruthenium Oxide, Silicides, TiSi2, CoSi2, NiSi, Graphene, Carbon Nanotubes, Doped Polysilicon, Indium Tin Oxide, Silver, Aluminum-doped Zinc Oxide, Gallium, Gallium Arsenide, Indium Gallium Zinc Oxide, Metal Alloys such as AICu and TiW, and Conducting Polymers.
  • the integrated circuit further comprises a gate electrode column formed from at least one of Tungsten, Titanium Nitride, Tantalum Nitride, Nickel, Molybdenum, Platinum, Palladium, Cobalt, Gold, Aluminum, Copper, Hafnium, Hafnium Nitride, Iridium, Iridium Oxide, Ruthenium, Ruthenium Oxide, Silicides such as TiSi2, CoSi2, NiSi, Graphene, Carbon Nanotubes, Doped Polysilicon, Indium Tin Oxide, Silver, Aluminum- doped Zinc Oxide, Gallium, Gallium Arsenide, Indium Gallium Zinc Oxide, Metal Alloys such as AICu and TiW, and Conducting Polymers.
  • a gate electrode column formed from at least one of Tungsten, Titanium Nitride, Tantalum Nitride, Nickel, Molybdenum, Platinum, Palladium, Cobalt, Gold, Aluminum, Copper, Hafnium, Hafnium Nitride, Iridium, Iridium Oxide
  • the ferroelectric column of the first vertical structure is formed from at least one of Perovskites, Lead Zirconate Titanate (PZT), Barium Titanate (BaTiO3), Strontium Titanate (SrTiO3), Bismuth Ferrite (BiFeO3), Potassium Niobate (KNbO3), Lithium Niobate (LiNbO3), Lithium Tantalate (LiTaO3), Sodium Bismuth Titanate (Na0.5Bi0.5TiO3), Bismuth Titanate (Bi4Ti3O12), Bismuth Zinc Niobate (Bi(Znl/2Ti 1/2)03), Bismuth Lanthanum Titanate (BiLaTiO3), Bismuth Nickel Titanate (BiNiTiO3), Lead Magnesium Niobate-Lead Titanate (PMN-PT), Lead Lanthanum Zirconate Titanate (PLZT), Neodymium-
  • the channel column of the first vertical structure is formed from at least one of Indium Gallium Zinc Oxide (IGZO), Indium Zinc Oxide (IZO), Zinc Tin Oxide (ZTO), Aluminum Zinc Oxide (AZO), Indium Tungsten Oxide (IWO), Gallium Zinc Oxide (GZO), Hafnium Indium Oxide (HIO), and Cadmium Oxide (CdO), Polysilicon, Polygermanium, Cadmium Selenide (CdSe), Copper Indium Gallium Selenide (CIGS), Crystalline Silicon (c-Silicon), Crystalline Germanium (c-Germanium), Gallium Arsenide (GaAs), Indium Phosphide (InP), Indium Antimonide (InSb), Silicon Carbide (SiC), Gallium Nitride (GaN), Zinc Oxide (ZnO), Pentacene, P3HT (Poly(3 -hexylthiophene)), Polythiophen
  • the vertical plug column of the first vertical structure is formed from at least one of Hafnium Oxide (HfO2), Zirconium Oxide (ZrO2), Aluminum Oxide (A12O3), Silicon Dioxide (SiO2), Titanium Dioxide (TiO2), Tantalum Oxide (Ta2O5), Lanthanum Oxide (La2O3), Yttrium Oxide (Y2O3), Silicon Nitride (Si3N4), Aluminum Nitride (AIN), Silicon Carbide (SiC), Strontium Titanate (SrTiO3), Barium Strontium Titanate (BST), Lead Zirconate Titanate (PZT), Bismuth Ferrite (BiFeO3), Magnesium Oxide (MgO), Cerium Oxide (CeO2), Nickel Oxide (NiO), Cobalt Oxide (CoO), Copper Oxide (CuO), Manganese Oxide (MnO), Zinc Oxide (ZnO), Zinc Oxide (ZnO
  • the integrated circuit may comprise a plurality of transistors formed from one of the horizontal gate-electrode layers and the first vertical structure according to any of the transistors described herein.
  • the first vertical structure may include components such as a vertical plug column, source and drain electrode columns, a channel column, and a ferroelectric column.
  • the horizontal gate-electrode layers may be disposed at predetermined distances from one another adjacent to the ferroelectric column. Configuring a horizontal gate-electrode layer and the first vertical structure in this manner allows for the formation of transistors with properties such as those described herein.
  • Fig. 1 is a block diagram of an integrated circuit that may be part of a semiconductor device such as a chiplet in accordance with an embodiment of the present disclosure
  • Fig. 2 shows a perspective view of an assembly having the integrated circuit of Fig. 1 implemented on a semiconductor device that is electrically connected to another device to form the assembly in accordance with an embodiment of the present disclosure
  • Fig. 3 shows a block diagram illustrating the memory address space of the integrated circuit of Fig. 1 in accordance with an embodiment of the present disclosure
  • Fig. 4 shows a block diagram illustrating the memory address space with the signal interfaces of the integrated circuit of Fig. 1 in accordance with an embodiment of the present disclosure
  • FIG. 5 shows an illustration of an integrated circuit that may be part of a semiconductor device such as a chiplet in accordance with an embodiment of the present disclosure
  • Fig. 6 shows a perspective of an assembly having the integrated circuit of Fig.
  • Fig. 7 shows a perspective view of an assembly having a semiconductor device with an array of processing elements and a second semiconductor device having an array of microvaults;
  • Fig. 8 shows an assembly of a semiconductor devices including several memory types in accordance with an embodiment of the present disclosure
  • Fig. 9 shows an assembly of semiconductor devices including a semiconductor device with a system-on-chip and another semiconductor with microvaults disposed on top in accordance with an embodiment of the present disclosure
  • Fig. 10 shows a semiconductor assembly incorporating a daisy-chained configuration of microvaults operatively connected to a multiplexer and managed by a counter for coordinated data selection and retrieval, in accordance with an embodiment of the present disclosure.
  • Fig. 11 shows a semiconductor assembly incorporating a daisy-chained configuration of microvaults in multiple semiconductor devices that are operatively connected to multiplexers and managed by counters for coordinated data selection and retrieval, in accordance with an embodiment of the present disclosure;
  • Fig. 12 illustrates a three-dimensional (3D) memory column configured as a 3D-NOR or 3D-AND structure, featuring a series of ferroelectric field-effect transistors (FeFETs) with interconnected drain terminals linked to a common select line and individual gate terminals connected to respective read/write enable lines, all coupled to a common bit line, in accordance with an embodiment of the present disclosure;
  • FeFETs ferroelectric field-effect transistors
  • Fig. 13 depicts a three-dimensional (3D) memory column configured as a 3D- NAND structure, consisting of a vertical stack of ferroelectric field-effect transistors (FeFETs), in accordance with an embodiment of the present disclosure
  • Fig. 14 depicts a three-dimensional (3D) memory column configured as a 3D- NAND with an integrated pass gate, in accordance with an embodiment of the present disclosure
  • Fig. 15 illustrates a three-dimensional (3D) memory column 1500, which may be configured as either a 3D-NOR or a 3D- AND structure with independent Read/Write enable capabilities, in accordance with an embodiment of the present disclosure
  • Fig. 16 shows a cross-sectional view of a 3D memory structure configured as a single-port 3D NAND, in accordance with an embodiment of the present disclosure
  • Fig. 17 shows a cross-sectional view of a 3D memory structure that is a dualport 3D NAND arrangement, in accordance with an embodiment of the present disclosure
  • Fig. 18 illustrates a 3D memory structure that can be configured as a 3D NOR Vertical Transistor memory array, in accordance with an embodiment of the present disclosure
  • Fig. 19 shows a planar FeFET in accordance with an embodiment of the present disclosure
  • Fig. 20 shows electrical characteristics of an embodiment of a FeFET in accordance with an embodiment of the present disclosure.
  • Fig. 1 shows a block diagram of an integrated circuit 100 that may be packaged as a bondable chiplet (e.g., face-to-face chiplet bondable) in accordance with an embodiment of the present disclosure.
  • the integrated circuit (IC) 100 includes a modules group 106 consisting of modules 108, 110, 112, and 114.
  • the IC 100 also features a shared write port 102, configured to write to the modules group 106 using a write peripheral 104. Additionally, it includes read peripherals 116, 118, 120, and 122 and read ports 124, 126, 128, and 130, configured to read from the modules 108, 110, 112, 114.
  • the write port 102 may be configured to provide a single write address space for all of the modules group 106 where each of the modules 108, 110, 112, 114 has a dedicated read port 124, 126, 128, 130 respectively.
  • the integrated circuit 100 may be packaged as part of a chiplet configured to be electrically connected to another integrated circuit device (e.g., another chiplet, or IC package, with or without electrical contacts, electrical bumps, etc.).
  • the chiplet may be electrically connected to another device including, for example, by bonding, soldering, wafer-to-wafer bonding, face-to-face chiplet bonding, chiplet-to-wafer bonding, chiplet-to-interposer bonding, and/or may be connected together with an interposer or other interfacing technology. None, one, or more of interposers may be used or other interfacing technologies that are common to heterogeneous 3D system-in-package solutions may be utilized in electrically connecting a chiplet to another device.
  • Each read port (124, 126, 128, 130) in the chiplet may feature electrical contacts on a side of the chiplet or on multiple sides of the chiplet.
  • the read ports 124, 126, 128, 130 may use multi-cycle pipelined circuitry.
  • the electrical contacts may line up in a manner that provides dedicated access to specific modules of the modules 108, 110, 112, 114.
  • a processing/computing element may have exclusive access to module 108 via the read port 124, which may contain the neural network weights in a register file.
  • a different processing/computing element may have exclusive read access to module 110 via the read port 126, which includes a different register file.
  • this arrangement of the electrical contacts ensures that each computing/processing element has the dedicated access it needs to carry out its specific computation efficiently thereby providing a compact, modular, and scalable system that allows different processing elements to maintain dedicated access to specific modules 108, 110, 112, 114. Without dedicated access, different processing elements might have to queue up to use the same resource which would slow down overall processing speed.
  • the proposed chiplet ensures that each processing element can operate at its maximum capability without interference from other computing elements in this specific embodiment.
  • the write peripheral 104 is a peripheral circuitry responsible for processing and writing data into the memory cells found within the modules 108, 110, 112, 114.
  • the write peripheral 104 may include dedicated contacts so that a chip electrically connected (e.g., bonded) to a chiplet of the integrated circuit, such that the write port 102 is accessible via a shared write logic system that involves utilizing a shift register-based, different voltage design, preferably high voltage design, that has a shared write address and data components.
  • This shared write logic system is designed to be accessed via a bonded chip, another bonded chiplet, and/or via other circuitry in the same package as the integrated circuit 100.
  • a shift register could allow the system to move data through a series of stages, with each subsequent stage receiving the data from the previous stage. By utilizing a shift register, the system can increase the data throughput while maintaining a low rate of data transfers.
  • the shared write address space refers to the location where data is written in the chiplet.
  • an interlock 132 may disable the read ports 124, 126, 128, 130 while data is being written to the modules group 106 via the write port 102. Likewise, the interlock 132 may disable the write port 102 when read operations are being carried out on the read ports 124, 126, 128, 130.
  • the written data can later be accessed concurrently by all processing elements that need to read the data via a respective one of the read ports 124, 126, 128, 130. This ensures that all processing elements have the most commonly used data available to them without regard to other reads being concurrently carried out by other processing elements.
  • the write peripheral 104 circuit includes a write driver. This unit receives the data to be written and converts it into suitable signals that can change the state of the memory cells. Depending on the type of memory technology used, these signals could involve voltage levels, current pulses, or other types of energy.
  • the shared write logic system may be high voltage due to the specific voltage requirements of the chiplet.
  • the write driver must provide enough power to reliably change the state of the memory cells, but it must also operate within suitable parameters to avoid causing damage or unnecessary wear.
  • the write peripheral 104 circuit may also feature a data buffer or write buffer. This component temporarily stores the data to be written, allowing the write operation to be performed at an optimal pace. By balancing the speed of incoming data with the speed at which the memory cells can be written, the write buffer helps prevent data loss and optimizes system performance.
  • the write peripheral 104 may also include, in some embodiment, a write control unit that orchestrates the sequence of operations in the write process. It generates control signals to activate the write driver at the appropriate times, controls the flow of data from the write buffer, and coordinates the timing of the write operations. By synchronizing these various activities, the write control unit ensures efficient and reliable write operations.
  • the write peripheral 104 may also include data encoding mechanisms to improve reliability and data integrity. For example, before the data is written to the memory cells, these mechanisms encode it in a way that allows potential errors to be detected, and in some cases, corrected when the data is later read. This can be helpful in systems where data integrity has a higher priority, such as in servers or scientific research devices.
  • the write peripheral 104 may also include a timing unit that serves as the system's heartbeat, supplying clock signals that synchronize the operation of the system's various components. In some systems, it may include components like oscillators, clock generators, or phase-locked loops.
  • the timing unit may ensure that all operations occur at the suitable time relative to each other.
  • the IC 100 may be implemented as a face-to-face bonded chiplet, with modules 108, 110, 112, and 114 formed from a non-volatile memory.
  • the IC 100 may also feature a dynamic allocation circuitry to allocate memory blocks to the modules group 106 based on the usage of the modules group 106 (e.g., each module 108 may include dynamic allocation circuitry for dynamically allocating a range of read locations for a respective processing element).
  • the IC 100 features a plurality of clocks, with each clock of the plurality of clocks feeding a respective module of the plurality of modules, providing each respective module with decoupled timing relative to the other modules of the plurality of modules.
  • the modules group 106 may be arranged in any topology known to one of ordinary skill in the relevant art. Bit-cell density can be up to 10 times more dense than embedded SRAM cells in the modules group 106.
  • the IC 100 may be formed on a chiplet that includes a first side and a second side, with the second side configured for bonding to a second semiconductor device.
  • the IC 100 may include a high voltage write logic adjacent to the first side of the chiplet.
  • a decoder circuitry, a driver circuitry, and a register circuitry may be formed on the silicon substrate portion of the chiplet, while the modules group 106 is formed on a second layer portion of the chiplet.
  • the second semiconductor device may comprise a plurality of processing elements. Each processing element includes a respective interface to communicate with a respective module of the plurality of modules on the modules group 106 when the second semiconductor device is bonded to the chiplet.
  • the silicon substrate traditionally serves as the initial stage of IC fabrication, focusing on the creation of active components, particularly transistors. Techniques like diffusion, ion implantation, oxidation, and material deposition are employed to fashion the intricate structures of transistors. These processes operate at small scales. The application of photolithography, etching, and implantation techniques enables the definition of transistor structures with precision.
  • the silicon substrate’s significance lies in its ability to establish the fundamental building blocks necessary for signal processing, amplification, and control within the IC. This layer is sometimes called Front-End-Of-The-Line (“FEOL”).
  • FEOL Front-End-Of-The-Line
  • a second layer may be added that traditionally takes on the role of interconnect fabrication, facilitating the electrical connections between various IC components.
  • the second layer processes typically differ from the processes used on the silicon substrate in terms of precision and scale.
  • the interconnects are formed by depositing and patterning metal layers, typically aluminum or copper, to construct the wiring network.
  • Dielectric layers such as silicon dioxide or low-k dielectrics, are introduced to insulate the interconnects and prevent signal interference between different wiring layers.
  • the second layer’s traditional function is to establish the necessary interconnections that enable the routing and distribution of electrical signals throughout the IC.
  • circuity may be utilized within this second layer (sometimes referred to as Back-End-Of-The-Line (“BEOL”)).
  • Alternate embodiments of the IC 100 may be implemented as a stacked die, a monolithic design, TSVs, or silicon through vias.
  • a stacked die design several dies may be stacked on top of each other, with each die performing different functions, such as memory and processing.
  • the stacked die may communicate through wire bonds, microbumps, or bump-less bonds.
  • the various functions and modules of the IC 100 may be integrated onto a single die, forming a more compact and power-efficient design.
  • the IC 100 may include one or more interlocks 132 to prevent conflicts in reading and writing data.
  • the modules group 106 may be formed from a variety of non-volatile or semi-volatile (e.g., very long refresh periods) memory technologies, such as Static Random-Access Memory (SRAM), Ferroelectric Field Effect Transistor (FeFET), Ferroelectric Random Access Memory (FeRAM), Resistive Random Access Memory (ReRAM), Spin-Orbit Torque (SOT) Memory, Spin Transfer Torque (STT) Memory, charge trap, floating gate memories, and/or Schottky diodes.
  • SRAM Static Random-Access Memory
  • FeFET Ferroelectric Field Effect Transistor
  • FeRAM Ferroelectric Random Access Memory
  • ReRAM Resistive Random Access Memory
  • SOT Spin-Orbit Torque
  • STT Spin Transfer Torque
  • the modules group 106 may utilize a Static Random- Access Memory (SRAM) Topology.
  • SRAM Static Random- Access Memory
  • the SRAM topology may employ a cross-coupled flip-flop structure (e.g., latching flip-flops), ensuring the stored data remains intact as long as power is supplied.
  • the modules group 106 may utilize heterogeneous types of memory including volatile and non-volatile memory types.
  • the modules group 106 may utilize a Flash Memory Topology.
  • the Flash memory is a non-volatile memory technology used in applications where data persistence is needed, such as solid-state drives (SSDs) and USB flash drives.
  • SSDs solid-state drives
  • the flash memory topology disclosed herein features a matrix of memory cells, each consisting of a floating-gate transistor or charge trap device.
  • the modules group 106 may also use wear-leveling techniques to prolong the lifespan of the memory cells.
  • the modules group 106 may utilize a Ferroelectric Random- Access Memory (FeRAM) Topology.
  • FeRAM Ferroelectric Random- Access Memory
  • the FeRAM topology utilizes a ferroelectric material capable of retaining polarization states.
  • One such memory topology may, in specific embodiments, utilize a FeFET to retain state information and program the ferroelectric material. These ferroelectric materials may be used to retain state information and act as a memory bit cell.
  • the modules group 106 may utilize a Phase Change Memory (PCM) Topology, which is a non-volatile memory technology that utilizes reversible phase changes in materials to store data.
  • PCM Phase Change Memory
  • the PCM topology may include any phase change material, for example a chalcogenide alloy or a chalcogenide glass housed within a memory cell.
  • the modules group 106 may utilize a Resistive Random-Access Memory (ReRAM) Topology, which is a non-volatile memory technology based on resistive switching phenomena.
  • the ReRAM topology may utilize a thin-film material that exhibits reversible changes in resistance upon the application of electrical stimuli.
  • the modules group 106 may utilize a Spin-Orbit Torque (SOT) Magnetic Random-Access Memory Topology.
  • SOT-MRAM is a type of non-volatile memory that utilizes spin-orbit torque to switch the magnetic state of a storage element.
  • the SOT-MRAM topology may incorporate a magnetic tunnel junction (MTJ) structure and leverages the spinorbit coupling effect to write and read data.
  • the magnetic tunnel junction may have a dielectric layer between a magnetic fixed layer and a magnetic free layer. Writing may be done by switching magnetization of the free magnetic layer by injecting an in-plane current in an adj acent SOT layer. Reading may be done by putting current into the magnetic tunnel junction.
  • the SOT-MRAM can optimize the spin-orbit materials by using current-driven switching schemes while minimizing write energy consumption, in some specific embodiments.
  • the modules group 106 may utilize a Spin Transfer Torque (STT) Magnetic Random-Access Memory Topology.
  • STT-MRAM is another type of non-volatile memory that relies on spin transfer torque to manipulate the magnetic state of a storage element.
  • the STT-MRAM topology can use a magnetic tunnel junction (MTJ) structure, where the magnetization orientation determines the stored data. Additionally, the orientation of a magnetic layer in a magnetic tunnel junction or spin valve can be changed using a spin- polarized current, for example.
  • MTJ magnetic tunnel junction
  • the IC 100 may include a single write peripheral 104 with a dedicated clock, or each module 108, 110, 112, 114 may have its own dedicated write peripheral utilizing a shared clock (not shown in Fig. 1). Additionally, the modules group 106 may be organized into separate partitions, each with a dedicated read peripheral 116, 118, 120, 122 having an independent clock.
  • IC 100 includes an interface (e.g., the same, different, higher or lower voltage) to enable data transfer external to the packaging of the IC 100.
  • the IC 100 may also include an integrated microcontroller unit (MCU) or a digital signal processor (DSP) for processing data within the IC in yet additional specific embodiments.
  • MCU microcontroller unit
  • DSP digital signal processor
  • Fig. 2 shows a perspective view an assembly 200 of the integrated circuit 212 of Fig. 1 implemented on a chiplet 230 that is bonded to a second device 226 in accordance with an embodiment of the present disclosure.
  • the integrated circuit 212 is the circuitry within the chiplet 230.
  • the second device 226 may be a chiplet, semiconductor wafer, semiconductor package, encased circuitry, etc.
  • the second device 226 may be an Al accelerator such that each processing unit has read access to one module (or a predetermined set) of the modules group 236.
  • the second device 226 may be a network controller where there is an offload circuit to read the data from each of the modules to processing incoming/outgoing packets, etc.
  • the assembly 200 includes a modules group 236 having a plurality of modules, including a first module 232 and a second module 234. Fig. 2 shows several modules, however, for clarity, only modules 232, 234 have reference numbers.
  • the integrated circuit 212 further comprises a shared write port 222. The shared write port 222 interfaces into the write peripheral 202.
  • the second device 226 may use the shared write port 222 via an address & data bus with a clock and a enable signal to write data to any modules within the modules group 236, other ways of writing data may be considered.
  • serial connections, parallel connections, various buses, or ports may be used, such as a DDR (Double Data Rate) Interface, a SRAM (Static Random-Access Memory) Interface, a NAND Flash Memory Interface, a NOR Flash Memory Interface, a HBM (High Bandwidth Memory) Interface, a GDDR (Graphics Double Data Rate) Interface, a NVMe (Non-Volatile Memory Express) Interface, SPI, IC2, etc.
  • Each of the modules has a read port with a read address 218 (to send an address to a module 234) and read data 214 (which is the data read from the module 232.
  • the modules group 236 is formed on a chiplet 230 having two sides including a surface 228 that can be bonded to and complement a second device 226.
  • the chiplet 230 may be formed by forming circuitry on a silicon substrate 204 and then by adding a second layer 206. In other embodiments, these layers may be reversed and/or other layers may be added, removed, etc.
  • the read address 218 and read data 220 are used for reading the module 232.
  • the second device 226 may use an address & data bus with a clock and a enable signal to read data from the module 232, other ways of reading data may be considered.
  • serial connections, parallel connections, various buses, or ports may be used, such as a DDR (Double Data Rate) Interface, a SRAM (Static Random-Access Memory) Interface, a NAND Flash Memory Interface, a NOR Flash Memory Interface, a HBM (High Bandwidth Memory) Interface, a GDDR (Graphics Double Data Rate) Interface, a NVMe (Non-Volatile Memory Express) Interface, SPI, IC2, etc.
  • DDR Double Data Rate
  • SRAM Static Random-Access Memory
  • NAND Flash Memory Interface a NAND Flash Memory Interface
  • NOR Flash Memory Interface NOR Flash Memory Interface
  • HBM High Bandwidth Memory
  • GDDR Graphics Double Data Rate
  • NVMe Non-Volatile Memory Express
  • All of the read ports are configured to be inactive when a write operation is applied to the shared write port 222.
  • the read ports may also be configured to process reads concurrently with each other.
  • the shared write port 222 is configured to write to an address space, where the shared write port 222 is configured to write to the first module 232 via a first portion of the address space and write to the second module 234 via a second portion of the address space.
  • Each module of the plurality of modules 236 includes an independent read port for concurrent reading via a respective independent read port of any of the plurality of modules.
  • Each read port for a respective module may include contacts for circuitry found within the second device 226 to interface via metallic contacts.
  • metallic contacts on the top layer 208 that are configured to interface with metallic contacts on the surface 228 of the chiplet 230 such that the metallic contacts allow for a read space that is coextensive with a read space of a module of the modules 236.
  • the read spaces of the modules group 236 may all be coextensive with each other (as is described with reference to Figs. 3 and 4).
  • the read peripheral for the first module 232 is implemented on a silicon substrate 204 (sometimes referred to as a Front-end-of-the-line).
  • the second layer 206 (sometimes call the Back-end-of-the-line) may be built next in the manufacturing process on top of the silicon substrate 204 (and any circuitry) and may contain the respective memory bit cells.
  • the read peripheral for the first module 232 is implemented in the second layer 206 and is disposed between the modules group 236 and the surface 228 of the chiplet 230.
  • the modules group 236 may be configured to process write commands only during reset.
  • the write commands may be “slow write” commands. That is, the modules group 236 may have very low write speeds relative to its read speed.
  • the write logic may be frozen (or disabled) when the modules group 236 are used for reading data.
  • the integrated circuit 212 provides functionality to allocate memory blocks to the modules group 236 based on the usage of the modules group 236. In other embodiments, the memory addresses are fixed along with the allocation.
  • the integrated circuit 212 may be implemented as a face-to-face bonded chiplet 230. The face-to face bonding may be bumpless wafter bonding.
  • the modules group 236 can have a single write peripheral 202.
  • each module of the modules group 236 may have a dedicated write peripheral that utilizes a shared clock.
  • the modules group 236 may also be organized into separate partitions each with partition having a dedicated read peripheral, where each dedicated read peripheral has an independent clock. The partitions may be one, two, or more modules of the modules group 236.
  • the write peripheral 202 circuitry's overall architecture may include a series of different components, including write driver, address decoders, sense amplifiers, data input latches, data bus, etc. and/or some combination thereof.
  • Write drivers or write buffers may be tasked with transferring data onto the memory cell. They may enhance the input signal to achieve a level appropriate for the memory cell.
  • Address decoders may be used to interpret the memory address that is fed as an input where the data needs to be written. By activating the specific row and column of the memory array linked to that address, they may be used to select the target memory cell.
  • Sense amplifiers may be used to identify and boost the signal from the memory cells during reading operations, also participate in refreshing the memory cell post data write in write operations.
  • the write operation is instigated by a write enable signal. When a write command is initiated, this signal propels the write drivers and decoders into the writing process.
  • Data input latches may be used as temporary storage units, retaining the data set to be written into the memory until the write operation is implemented.
  • a data bus with a transmission route can be used to facilitate the movement of data from the data input latches to the memory cells.
  • a write operation to the modules group may be performed through a priority arbitration circuit that facilitates the modules to be accessed in a predetermined order, and the shared write port 222 may be configured to write to a virtual address space that is mapped onto a physical memory space.
  • the integrated circuit 212 may include a high voltage write logic used within the write peripheral 202, and the second semiconductor device 226 may comprise a plurality of processing elements, whereby each processing element includes a respective interface to communicate with a respective module of the modules group 236. Furthermore, the chiplet 230 may include an interface to the shared write port 222 on the second side to thereby interface with a complementary interface on the second semiconductor device 226.
  • the integrated circuit 212 may also include a power gating circuitry that selectively powers down a module of the modules 236 when not in use. Additionally, the integrated circuit 212 may have a write peripheral 202 of the modules group 236 connected to a dedicated I/O pad to enable data transfer external to the package of the integrated circuit.
  • the integrated circuit 212 may utilize multiple modules of the modules group 234 grouped together. These modules may be synchronized with one another in specific embodiments. In some cases, all the modules are synchronized, while in other instances, only specific modules are to be synchronized. For instance, the circuit on a second device 226 may need to synchronize with a specific module when reading data from one of the modules in the module group 236.
  • the integrated circuit 212 may use various timing technologies.
  • a plurality of clocks may feed each respective module of the modules group 236, thereby allowing each module to have decoupled timing relative to the other modules in the group. This decoupling ensures that any delay in one module will not affect the functioning of other modules.
  • the clocks used may or may not need to be synchronized.
  • a common clock can be used to synchronize the modules.
  • the clock signal or signals may be provided by the second device 226.
  • synchronization techniques can be used, such as phase comparison of the clock signals or a phase-locked loop (PLL) synchronization method.
  • PLL phase-locked loop
  • Another embodiment for synchronizing the modules in the IC could use delay-locked loop (DLL) synchronization. In this method, a delay element is added to the clock signal path, and the output is compared to the input clock signal. The feedback loop adjusts the delay element until the output of the DLL matches the input, resulting in synchronization of the clock signals.
  • the integrated circuit 212 could use a combination of different synchronization techniques to achieve synchronization between the modules. For example, some modules may use PLL synchronization while others use clock delay lines or DLL synchronization, depending on their specific requirements.
  • the integrated circuit 212 can also use redundant synchronization techniques to ensure reliability and redundancy in case one method fails.
  • the integrated circuit 212 could use both PLL synchronization and DLL synchronization simultaneously, so that if one method fails, the other can still maintain synchronization.
  • Fig. 3 shows a block diagram 300 illustrating the memory address space of the integrated circuit of Fig. 1 in accordance with an embodiment of the present disclosure.
  • the memory address space includes a write address space 316 and read data address spaces 310, 312, 314.
  • the write address space 316 consists of various units where data, e.g., weights, and/or instructions can be stored. These units are referred to as memory addresses.
  • the module group 302 includes multiple memory modules 304, 306, 308.
  • the write address space 316 may be distributed among the memory modules 304, 306, 308 such that the write address space 316 spans from 0 to N*M-1.
  • the modules group 302 has N memory modules 304, 306, 308, where N is a positive integer, and each module has a memory size of M.
  • the total number of unique write memory addresses in the write address space will be N*M, which can be referenced by an integer from 0 to N*M-1.
  • memory addresses of the write address space 316 are ordered sequentially up to N*M-1.
  • the first address is 0 and the final address is N*M- 1, encompassing a total of N*M addresses.
  • This ordering can be linear (each address increases by one) or some other specified pattern depending.
  • the write memory addressing can be implemented in a variety of ways based on the system architecture.
  • One method used in a specific embodiment is to use the base and limit registers.
  • the base register holds the smallest legal physical write memory address, and the limit register specifies the size of the range. Therefore, to generate a logical address, you would add the base to the relative address.
  • a memory addressing scheme may be used where the base used is set to be 0. Yet additional write addressing techniques will be appreciated by one or ordinary skill in the relevant art.
  • each memory module can possess a unique set of write memory addresses such all memory addresses within the modules group 302 is unique with respect to writing data, e.g., the first module starting at 0 and the last one ending at N*M-1.
  • This allocation may be dependent on the memory management system of the device writing data to the modules 304, 306, 308, which could range from simple fixed partitioning schemes to more complex dynamic partitioning models.
  • each module (304, 306, or 308) has an equal size of M addresses
  • the first module 304 would possess write addresses 0 to M-l
  • the second module would have write addresses M to 2M-1
  • the third module would have write addresses 2M to 3*M-1
  • the Nth module 308, therefore, would possess write addresses from (N-1)*M to N*M-1.
  • the modules group 302 has different read data address spaces 310, 312, 314. These read address spaces 310, 312, 314 may have overlapping addresses spaces, may have contiguous address spaces, or may have coextensive address spaces.
  • the read address spaces 310, 312, 314 may be independent relative to each other.
  • the system includes three independent read address spaces, labeled as read address spaces 310, 312, and 314. Each of these read address spaces is distinct from the others, meaning that reads can be performed in each space without affecting the others.
  • the read address spaces 310, 312, 314 may be defined as contiguous blocks of memory addresses, each with its own starting address and ending address.
  • each read address space 310, 312, 314 may have a range of addresses that corresponds to values from 0 to M-l, where M is a maximum value determined by the size of the modules 304, 306, 308 being used.
  • allowing one processing unit to interface with each read address space 310, 312, 314, the concurrent reads may be implemented as described herein.
  • the independence of the read address spaces 310, 312, 314 ensures that each processing unit can access its desired data without causing any interference or conflict with other processing units.
  • Fig. 4 shows a block diagram illustrating the memory address space with the signal interfaces of the integrated circuit of Fig. 1 in accordance with an embodiment of the present disclosure.
  • the signals used in Fig. 4 may be used with any embodiment described herein. However, one of ordinary skill in the relevant art will appreciate that different signaling schemes may be used.
  • the modules group 402 includes modules 404, 406, 408 that share a common write peripheral 411.
  • the write peripheral 411 includes a write address bus that includes the address of the data being written, a write data bus that includes the data, a write clock cause the writes to occur (e.g., either on a leading or trailing edge of the clock signal, etc.). The writes only occur if the write enable signal indicates a write should occur.
  • the write peripheral 411 may be on the chiplet 230 and in other embodiments, the write peripheral 411 is on the second device 226.
  • the modules group 402 has modules 404, 406, 408 where each has a respective read peripheral 410, 412, 414.
  • Each of the read peripheral 410, 412, 414 has a read address bus to send an address for reading, a read data bus to receive the data, a read clock which is the clock used to control the timing of the output of the digital data, and an output enable that is a precondition to outputting data. Any logic may be used, e.g., high voltage may correspond to 1 and a low voltage may correspond to 0, or vice versa. In yet additional embodiments, multibit or analog data storage may be used.
  • one or more of the read peripherals 410, 412, 414 may be on the chiplet 230 and in other embodiments, one or more of the read peripherals 410, 412, 414 are on the second device 226.
  • Fig. 5 shows an illustration of an integrated circuit 500 that may be part of a semiconductor device such as a chiplet in accordance with an embodiment of the present disclosure.
  • the integrated circuit 500 may be disposed on a semiconductor device, such as a chiplet, that has a silicon substrate 506 and a second layer portion 508.
  • a semiconductor device such as a chiplet
  • the integrated circuit 500 may include a modules group having a plurality of modules including a first module and a second module, etc. even though only a single module 502 is shown.
  • the memory bit cells 522 are written to by the shared write port 512, 516, which includes both a write address bus line 512 and a write data bus 516. These buses run through the second layer 508 and can be connected to a second semiconductor device via an interposer. The second device has electrical contacts that complement those on the surface 518, allowing it to be electrically coupled to the write address and data buses.
  • the memory bit cells 522 can be read from via the read port 524, 526, which includes a read address bus line 524 and a read data bus 526. Both of these buses can also run through the second layer 508 to the second semiconductor device coupled to the surface 518, which also has complementary electrical contacts to allow it to be electrically coupled to the read address and data buses.
  • Various kinds of memory technologies may be used for the memory bit cells 522, such as a vertical connectivity fabric structure formed from non-volatile memory unit cells arranged in a three-dimensional column array 522.
  • the memory bit cells 522 may utilize one or more of a cross-point, 3D NANDs, 3D NORs, 3D ANDs, and/or a stacked planar layer.
  • the integrated circuit 500 is electrically connected to a second semiconductor device (not shown in Fig. 5) comprising another integrated circuit, which may be a system-on-chip or a Field-Programmable-Gate-Array.
  • the memory bit cells 522 may be formed from various non-volatile memory types, such as FeFET, FeRAM, ReRAM, SOT, or STT. Additionally, alternatively, or optionally, the memory bit cells may be formed from non-volatile memory unit cells having 2-terminal devices, 3-terminal devices, or 4-terminal devices.
  • the memory unit bit cells 522 may be formed from ferroelectric materials, such as a ferroelectric tunnel junction, a diode, a capacitor, a single-gate transistor, or a dual-gate transistor.
  • the memory unit bit cells 522 may be formed from memristive materials, such as at least one ReRAM, or magnetic materials, such as at least one spin-orbit-torque device or at least one spin-transfer-torque device.
  • the non-volatile memory unit cells 522 may also be formed from phase-change materials or anti-ferroelectric materials.
  • the non-volatile memory unit cells522 can be formed from other types of materials, such as phase change materials, anti -ferroelectric materials, or multi-bit PCM materials.
  • the non-volatile unit cells can be formed utilizing different structures, such as resistive random-access memory (RRAM) technology, magnetic random-access memory (MRAM) technology, or ferroelectric random-access memory (FRAM) technology.
  • RRAM resistive random-access memory
  • MRAM magnetic random-access memory
  • FRAM ferroelectric random-access memory
  • the memory unit bit cells 522 may be formed from stacked memory layers where each layer includes a plurality of memory cells that can be accessed using shared bit lines.
  • the read port 524, 526 may be coupled to the bit lines
  • the write port 512, 516 may be coupled to the word lines that control the access to each layer.
  • the 3D connectivity fabric structure can be built with stacked layers of either NAND gates, NOR gates, or AND gates, and in some cases, different types of logic gates may be combined to optimize the structure's functionality.
  • the 3D connectivity fabric structure may be formed utilizing through-silicon-via (TSV) technology, which allows the vertical interconnection of the different layers of the structure.
  • TSV through-silicon-via
  • the non-volatile memory unit cells may include 2-terminal devices, such as a capacitive or a memristive device with or without an additional selector device such as a diode in series, 3-terminal devices, such as a floating-gate transistor, a transistor with an access gate, or 4-terminal devices, such as a transistor with two access gates.
  • the type and configuration of the non-volatile memory unit cells 522 may depend on the specific application requirements, including the speed, power consumption, and reliability of the circuit.
  • the memory unit cell may include or be a single ferroelectric transistor or 6T SRAM cell.
  • the memory unit cell may be a combination of many different devices, including, but not limited to, one or more of a transistor, a memristor, a capacitor, etc.
  • a ferroelectric material can be utilized to form the nonvolatile memory unit cells 522.
  • the ferroelectric material may be implemented as any kind of device, including, but not limited to, a thin-film device, such as a ferroelectric tunnel junction, a capacitor, a single-gate transistor, or dual -gate transistors, etc.
  • the non-volatile memory unit cells522 may be formed from a memristive material, such as a Metal Oxide Memristor (MOM), Conductive-Bridging RAM (CBRAM), or valence change memory (VCM), each of which provides different benefits regarding power consumption, speed, endurance, etc.
  • MOM Metal Oxide Memristor
  • CBRAM Conductive-Bridging RAM
  • VCM valence change memory
  • the non-volatile memory unit cells 522 may be formed from a magnetic material, such as spin-orbit-torque (SOT) devices, spin-transfer- torque (STT) devices, or perpendicular magnetic tunnel junctions (p-MTJ).
  • SOT spin-orbit-torque
  • STT spin-transfer- torque
  • p-MTJ perpendicular magnetic tunnel junctions
  • the modules group may include many modules where each of which can be accessed through dedicated read ports 524, 526 with a dedicate read peripheral 520 while sharing the same write port 512, 516 and shared write peripheral 510.
  • the shared write port 512, 516 can be configured to selectively write to one or more of the plurality of modules within the modules group including the memory bit cells 522.
  • Each of the modules may have the same or different sizes, and different module sizes may be configured to optimize the utilization of the memory array with different operating scenarios, etc.
  • the integrated circuit 500 may be formed utilizing different manufacturing processes and techniques, which include but not limited to, a CMOS or Bipolar- CMOS-DMOS (BCD) process, a silicon-on-insulator (SOI) process, a FinFET process, a silicon germanium (SiGe) process, a gallium arsenide (GaAs) process, etc.
  • BCD Bipolar- CMOS-DMOS
  • SOI silicon-on-insulator
  • FinFET silicon germanium
  • SiGe silicon germanium
  • GaAs gallium arsenide
  • the three-dimensional column array of memory bit cells 522 forms is configured as a microvault. Additionally or alternatively, each of the micvrovaults will have a dedicated read peripheral 520 and a write peripheral 510 that is also a dedicated write peripheral rather than a shared write peripheral.
  • each mircovault includes a dedicate write connection and a dedicated read connection, predetermined number of microvaults (e.g., 2 or 4), may have a dedicated write connection and a dedicated read connection, with or without dedicated respective peripheries, etc.
  • FIG. 6 shows a perspective of an assembly 600 having the integrated circuit of Fig. 1 implemented on a semiconductor device, such as the chiplet 230, that is electrically connected to a system-on-a-chip (“SOC”) 610 in accordance with an embodiment of the present disclosure.
  • the semiconductor device in this embodiment, is the chiplet 230 that is electrically connected to a system-on-a-chip (“SOC”) 610.
  • the SOC 610 includes a silicon substrate 602 on which a plurality of processing elements is formed, including a processing element 606.
  • the processing elements can communicate with each other through a Network-on-Chip (“NOC”) 604, which is a communication fabric that directs data transfer between the processing elements.
  • NOC Network-on-Chip
  • the communication fabric can take various forms, including buses, switches, NOCs, etc.
  • the NOC 604 in the SOC 610 directs data traffic between the various nodes (e.g., the processing element 606) and links, which provide the communication paths between the nodes.
  • the plurality of processing elements including the processing element 606 processing elements can be any suitable type of processors capable of executing instructions, including microprocessors, graphics processing units (GPUs), digital signal processors (DSPs), or application-specific integrated circuits (ASICs).
  • processors capable of executing instructions, including microprocessors, graphics processing units (GPUs), digital signal processors (DSPs), or application-specific integrated circuits (ASICs).
  • GPUs graphics processing units
  • DSPs digital signal processors
  • ASICs application-specific integrated circuits
  • the SOC 610 may comprise various modules, such as module 232, which are grouped together to provide memory functionality to the assembly 600 as described here.
  • the modules in modules group 236 can be coupled to a respective processing element provide it readable memory.
  • the coupling between the module (e.g., module 232) and the processing element (e.g., 606) can be achieved through interconnects on the silicon substrate 602.
  • a second layer 608 can be disposed on top of the substrate.
  • the second layer 608 can be any suitable material, such as an insulating material, a metal, a dielectric, or interconnect layer, and it may be bonded to the chiplet 230.
  • the bonding can be done using any suitable technique, including but not limited to, adhesives, soldering, or welding, etc.
  • the assembly 600 provides a means of integrating the chiplet 230, which can include the integrated circuit of Fig. 1, with the SOC 610. Integrating the chiplet 230 provides various advantages, such as enhanced functionality, higher performance, and lower power consumption. Moreover, the integration of the chiplet 230 with the SOC 610 can be accomplished in various ways, depending on the particular application and design objectives of the system.
  • the assembly 600 can incorporate various variations and modifications, depending on the specific requirements of the system.
  • the processing elements formed on the silicon substrate 602 can vary in their number, type, and arrangement.
  • the modules in modules group 236 can vary in their number, type, and function.
  • the second layer 608 can be modified to include additional functionality.
  • the second layer 608 can include passive components, such as resistors, capacitors, and inductors, or active components, such as transistors or diodes. Incorporating these components in the second layer 608 can further enhance the functionality and performance of the system.
  • the assembly 600 can incorporate a heterogeneous integration approach, where the chiplet 230 is fabricated using a different technology than that used for the SOC 610. This approach allows for the optimal use of different fabrication technologies for different parts of the system, resulting in improved performance and reduced power consumption.
  • FIG. 7 shows a perspective view of an assembly 700 having a semiconductor device 707 with an array of processing elements 706 (on a grid of processing element 706a, a to 706n,n, where the first subscribe is the columns and the second subscript is the row), and a second semiconductor device 709 having an array of microvaults 708.
  • the array of microvaults 708 are on a grid of microvaults 708a, a to 708n,n, where the first subscript is the columns and the second subscript is the row). These subscripts may line up such that a respective subscript of a processing element 706 corresponds to a respective subscript of a microvault 708.
  • the microvaults 708 are a type of module described herein where it is positioned in a vertical direction, e.g., above a respective processing element 706.
  • the semiconductor device 707 may be a chiplet.
  • the semiconductor device 709 may also be a chiplet.
  • the chiplets 707,709 may be bonded together.
  • the different layers 710 e.g., 710a through 710d can correspond
  • the assembly 700 is the overarching structure that houses the various components shown in Fig. 7. It provides mechanical support and integration for the other elements, allowing them to function as a unified system.
  • the assembly 700 includes two semiconductor devices - the semiconductor device 707 and the semiconductor device 709.
  • the semiconductor device 707 contains an array of processing elements labeled 706a, a to 706n,n.
  • the semiconductor device 709 contains an array of microvaults labeled 708a, a to 708n,n.
  • the subscripts a, a to n,n indicate that the processing elements 706 and microvaults 708 are arranged in a grid pattern, with the first subscript referring to the column and the second subscript referring to the row.
  • This grid arrangement allows each processing element 706 to have a corresponding microvault 708 positioned vertically above it.
  • processing element 706a, a has microvault 708a, a above it
  • processing element 706b, b has microvault 708b, b above it, and so on.
  • the alignment of the grid allows tight integration between the processing and storage components.
  • the semiconductor devices 707 and 709 are potentially separate chiplets that are integrated using packaging techniques into the unified assembly 700.
  • the chiplet form factor allows greater flexibility and customization in assembling the system. This arrangement is such that each processing element 706 can access its respective microvault 708 located above it to retrieve relevant data, such as weights for neural networks or Al models. This may provide high bandwidth and low latency access to the data needed for efficient processing.
  • Input data enters the system via the input DRAM memories 702. This data flows into the processing elements 706, where it is operated on locally using weights or parameters from the vertically integrated microvaults 708. The processing results output via the output DRAM memories 704.
  • the input DRAM memories 702 consist of multiple individual DRAM modules labeled 702a, 702b, and 702c.
  • the DRAM memories 702 can be any type of dynamic random access memory, including but not limited to DDR SDRAM, LPDDR SDRAM, GDDR SDRAM, and HBM.
  • the DRAM memories provide high-bandwidth data input capabilities to feed data, such as inference inputs or training data, into the processing pipeline.
  • each individual DRAM module 702a, 702b, and 702c has a dedicated interface and data path to each processing element 706.
  • DRAM module 702a may feed data only to processing element 706a, a
  • DRAM module 702b feeds data only to processing element 706b, b.
  • This provides modular scalability, as additional DRAM modules can be added to feed more processing elements.
  • the number of input DRAM memories 702 and individual modules 702a-702c may vary depending on the application requirements. For instance, there could be 4, 8, 16, or more input DRAM modules.
  • the capacity of each module can range from gigabytes to terabytes depending on factors such as access speed, power, and cost budget.
  • High-speed interfaces like DDR5, GDDR6, or HBM3 may be used to maximize data transfer bandwidth between the input DRAM memories 702 and the processing elements 706 across the semiconductor device 707.
  • Shared data buses, crossbar switches, or on-chip networks may interconnect groups of DRAM modules 702 and processing elements 706.
  • the input DRAM modules 702 may be stacked or arranged in a multi-dimensional configuration to increase overall memory capacity and bandwidth while reducing latency and power consumption.
  • Specialized memory controllers and schedulers may manage parallel data access across multiple input DRAM modules 702.
  • the input DRAM memories 702 supply the high-bandwidth data needs of the parallel processing elements 706, enabling fast and efficient data-intensive computations such as neural network inferencing.
  • Each processing element 706 can directly access the required input data from its dedicated DRAM module 702 without contending with other processors for data access.
  • adjacent accelerator chiplets may be in communication with the semiconductor device 707. That is, there may be a grid-like arrangement of assemblies 700 in communication with each other to perform Al inference and/or Al training (e.g., transformer inference, CNN interference, ANN interference, etc.). In some embodiments, there may be clusters of semiconductor devices 707 that share a bank or portion of DRAM memories 702 and/or 706. In some embodiments, the input DRAM memories 702 and the output DRAM memories 704 may be combined into the same DRAM memory.
  • the assembly 700 includes a semiconductor device 707 that comprises an array of processing elements labeled from 706a, a to 706n,n.
  • Each processing element in the array may be configured to execute specialized computations and data processing operations. For instance, in some embodiments, the processing elements could be optimized for artificial intelligence workloads like neural network inference. In other cases, the processing elements may focus more on general-purpose capabilities. Ultimately, the capabilities of each processing element depend on its specific microarchitecture which can be tailored for certain applications if desired.
  • the processing elements 706 can access nearby memory storage to retrieve data that feeds into their computations. This memory may be physically separate from the processing element arrays 706 as is the case with the microvaults 708 shown in Figure 7.
  • the processing elements 706 and microvaults 708 are aligned so that each microvault is positioned directly above its corresponding processing element in a vertical configuration. This tight coupling provides fast data transfer speeds between each vault-element pair.
  • the array of processing elements 706 resides within the semiconductor device 707.
  • the semiconductor device 707 could potentially be manufactured as a standalone chiplet using advanced packaging techniques.
  • This modular chiplet can then be integrated with other components like the microvault chiplet 709 through high-density interconnections.
  • Some options include bumpless hybrid bonding, interposers, or even monolithic 3D integration.
  • combining chiplets allows creating powerful heterogenous systems with optimized dies.
  • processing elements 706 can vary between implementations of assembly 700. For instance, simpler systems may need only a 2x2 grid of elements whereas a sophisticated Al accelerator could feature a 32x32 array.
  • the processing elements 706 themselves can also have different memory access routes across the assemblies. Point-to-point links, crossbar switches, or shared buses are possible connection structures. Such architectural decisions depend on the performance and area constraints trying to be met.
  • the second semiconductor device 709 is a separate device from the first semiconductor device 707. Like the first semiconductor device 707, the second semiconductor device 709 may also be implemented as a chiplet.
  • the second semiconductor device 709 includes an array of microvaults 708, arranged on a grid spanning from microvault 708a, a to 708n,n.
  • microvaults 708 on the second semiconductor device 709 are positioned vertically above the processing elements 706 on the first semiconductor device 707.
  • Each microvault 708 lines up with and corresponds to the processing element 706 underneath it, based on the subscripts identifying their position in the grid.
  • microvault 708a, a is vertically aligned with and corresponds to processing element 706a, a. This allows each processing element 706 to access the microvault 708 above it.
  • the microvaults 708 act as a memory structure, storing things like Al model weights that can be accessed by the processing elements 706 underneath during operations like neural network inference.
  • the microvaults 708 may be optimized for very fast read times but slower write times. This allows the processing elements 706 to rapidly access the weights and data needed for their computations, while less frequently updated data can still be written at a slower pace.
  • the second semiconductor device 709 containing the array of microvaults 708 is directly bonded to the first semiconductor device 707 with the processing elements 706. This bonding aligns each microvault 708 with its corresponding processing element 706 underneath. Electrically conductive interconnects between the devices allow each processing element 706 to communicate directly upwards with its respective overlying microvault 708.
  • the microvaults 708 may contain multiple memory layers, labeled 710a to 710d, each storing weights or data for a different Al model. For example, layer 710a contains the weights for model A, layer 710b contains the weights for model B, and so on. Stacking these layers vertically contributes to the high density and fast access times of the microvault design.
  • the microvaults 708 can be implemented using various memory technologies, including but not limited to SRAM, FeFET, ReRAM, SOT, and STT, optimized for fast readout times to supply data to the processing elements 706 with minimal latency. Specific embodiments may configure the microvaults 708 to have much faster read speeds compared to their write speeds. The microvaults 708 may be implimented using any FeFET or memory structure described herein.
  • each microvault 708 may have a capacity between 4 kilobytes to 128 kilobytes for storing parameters for machine learning models or other data.
  • the bit density per layer may exceed 0.4 gigabits per square millimeter.
  • the microvaults' 708 compact size between less than 100 micrometers on each side in one embodiment or 12 micrometers by 12 micrometers in another, allows high-density integration of the memory modules.
  • the array-based arrangement of the microvaults 708 may enables concurrent parallel data access by the processing elements 706, supporting high-throughput data processing by the assembly 700.
  • the one-to-one alignment of the microvaults 708 and processing elements 706 also ensures that each processing element 706 has dedicated access to its required data without contention.
  • microvaults 708 share the semiconductor device interface provided by the second semiconductor device 709, which facilitates writing data to the microvaults 708 from the input DRAM memories 702. Reading data from the microvaults 708 to the processing elements 706 and output DRAM memories 704 is handled through dedicated pathways between each vertically aligned microvault 708 and processing element pair.
  • the microvault memory layers 710 refer to multiple layers of microvault memories stacked vertically within the second semiconductor device 709. As illustrated in Fig. 7, there are four separate microvault memory layers labeled as 710a, 710b, 710c, and 710d. Each layer contains an array of microvaults, such as the array of microvaults 708 shown in the diagram.
  • the microvaults 708 may utilize a stacked 3D NAND architecture built from multiple layers of NAND memory arrays using charge trap flash technology. Each microvault 708 may contain a dedicated set of wordline drivers on the bottom layer to facilitate access to the 3D NAND cell arrays above, spaced by alternating dielectric layers.
  • the 3D NAND implementation may be used to maximize density and throughput by leveraging vertical scaling.
  • the microvaults 708 employ a 3D NOR architecture constructed from multiple tiers of NOR flash memory arrays. Each plane features NOR strings with a source line and bit line architecture, stacked on top of each other using vias. The 3D NOR arrangement optimizes random read access times to stored data.
  • the microvaults 708 may also adopt a hybrid configuration with different types of volatile and/or non-volatile memory, such as combining FeRAM and ReRAM cells, organized into vertical sub-arrays. This heterogeneous 3D integration allows optimizing for speed, endurance, and retention within the same vault structure.
  • the microvaults 708 integrate processing logic like analog computing directly into the memory array stack itself. This processing-in-memory approach places basic computational operators within the memory peripheral or bit cells, enabling highly parallel and efficient in-situ data processing.
  • Some implementations may utilize 2.5D or 3D stacking to integrate the microvaults 708 with other components like logic, CPUs, GPUs or application-specific accelerators.
  • This tight packaging integration via techniques like high-bandwidth memory cube architectures reduces data transfer latency and power consumption.
  • the microvaults 708 may also employ a virtualized architecture, with an external memory controller handling translation between the physical array organization and dynamically allocated virtual memory domains. These virtual domains mapped onto the physical array effectively creates separate virtual vaults with flexible capacities tailored to application needs.
  • the microvaults 708 are designed as Computational RAM (CRAM) with integrated processing capabilities within the bit cell peripheral to enable highly parallel in-memory computing architectures. Gateless transistor structures integrated into the CRAM arrays facilitate efficient execution of bulk bitwise operations.
  • CRAM Computational RAM
  • microvaults 708 into modular Memory Processing Unit (MPU) structures containing dedicated processing logic tailored for workloads like Al inferencing.
  • MPU Memory Processing Unit
  • the MPU architecture couples vault arrays to vector processors via highspeed interfaces like HBM2 enabling low-latency data transfers.
  • the microvaults 708 may also implement content-addressable capabilities by integrating comparison logic into the memory peripheral. This facilitates searching or accessing data based on content rather than explicit addresses, enabling powerful pattern matching capabilities.
  • Certain embodiments may stack multiple microvault dies on top of base logic dies featuring things like GPUs or Al accelerators. This creates dense, high-bandwidth heterogeneous systems optimized for data-centric workloads while minimizing data movement.
  • microvault memory layers 710 may be fabricated utilizing three- dimensional integrated circuit manufacturing processes to stack multiple dies or wafers containing microvault 708 arrays on top of each other.
  • Through-silicon vias (TSVs) or other vertical interconnect technologies can be employed to enable communication between the layers.
  • each microvault memory layer 710 corresponds to a different artificial intelligence (Al) model or application.
  • layer 710a could store the weights and parameters for Al model A
  • layer 710b could store the weights and parameters for Al model B, and so on. This allows multiple Al models to be stored efficiently within the same microvault memory 708 structure.
  • the microvaults 708 may possess capacities ranging from 4 kilobytes to 128 kilobytes in some embodiments. In other cases, the capacity could be between 4 kilobytes to 16 kilobytes. Each microvault could have lateral dimensions less than 100 micrometers by less than 100 micrometers, while extending vertically to incorporate potentially over 200 memory cell layers in some implementations.
  • the bit density of per square millimeter per layer within the microvault memory layers 710 may facilitate high-capacity storage with a small footprint.
  • the layers may utilize non-volatile memory technologies, such as FeFET, STT-MRAM, or ReRAM, to retain data when power is removed.
  • the processing elements 706 may access weights or parameters from the microvault memory layers 710 to perform neural network inferencing or other machine learning computations.
  • the inference results of the various Ais may be sent to the output DRAM memories 704. which comprise individual DRAM memory modules labeled 704a, 704b, and 704c.
  • the output DRAM memories 704 are positioned adjacent to the array of microvaults 708 and the second semiconductor device 709.
  • the output DRAM memories 704 may serve as temporary data storage that can buffer output data retrieved from the microvaults 708 before it is transmitted externally.
  • Each DRAM memory module 704a, 704b, and 704c may have similar or different storage capacities, depending on the design requirements. For example, in one embodiment, each module contains 16 megabits of storage.
  • the DRAM storage cells utilize a capacitor to retain data bits in the form of electrical charges. Due to charge leakage, the DRAM memories require periodic refresh cycles to maintain the stored data integrity.
  • each DRAM module 704a, 704b, and 704c can have dedicated internal control circuitry and VO ports.
  • the data outputs from the individual microvaults 708 may get aggregated and buffered in the output DRAM memories 704 before being transmitted to external components via peripheral circuitry. Buffering the data allows the transmission rate to be regulated to match the requirements of the external interfaces. It also enables data processing operations like formatting, encoding, or encryption to be performed by the second semiconductor device 709 prior to output.
  • the output DRAM modules 704a, 704b, and 704c are designed to provide high-density, low-cost temporary data storage to support the high- bandwidth parallel reads from the array of microvaults 708. Optimizing these performance parameters allows efficient extraction of data from the microvaults to feed the computational workflows hosted on external chips or devices. Specific implementations may utilize various types of DRAM, including asynchronous DRAM, synchronous DRAM, graphics DRM, and low-power DRM tailored to the application. Overall, the output DRAM memories 704 facilitate seamless data movement from the integrated microvaults to external execution pipelines.
  • Fig. 8 shows an assembly 800 of a semiconductor devices 802, 804, 806, 808, 810, 812, 814 including several memory types in accordance with an embodiment of the present disclosure.
  • Fig. 8 shows an exemplary assembly 800 of semiconductor devices 802, 804, 806, 808, 810, 812, 814 configured to provide a hierarchical memory structure.
  • the assembly 800 is modular and scalable, allowing for various combinations and numbers of semiconductor devices, which may be implemented as chiplets in certain embodiments, to be stacked to meet specific performance and density requirements.
  • the assembly 800 includes an application semiconductor 802, that may be a plurality of processing elements as described herein.
  • semiconductor device 802 On top of the semiconductor device 802 is semiconductor device 814 that includes an array of microvaults.
  • semiconductor device 812 which may also include an array of microvaults.
  • semiconductor devices 810, 808, On top of the semiconductor device 812, are semiconductor devices 810, 808, which may be SRAM vaulted dies.
  • semiconductor devices 806, 804 may be DRAM vaulted dies.
  • These vaults 816 may be arranged in a grid-like fashion such that 816a, a to 816n,n subscripts the vaults.
  • Each of these vaults may include a respective microvault from semiconductor devices 804, 812, respective SRAM vaults from semiconductor devices 810, 808, and respective DRAM vaults from semiconductor devices 806, 804.
  • the semiconductor device 802 At the base of assembly 800 lies the semiconductor device 802, which comprises a plurality of processing elements. These processing elements execute computational tasks and facilitating data flow within the system.
  • semiconductor device 814 which includes an array of microvaults.
  • These microvaults utilize Field-Effect Transistors (FeFETs) known for their non-volatile characteristics and suitability for high-density memory applications.
  • the FeFET-based microvaults may be designed to enable high-speed read operations essential for rapid data retrieval during processing tasks, such as Al inferencing, while supporting slower write operations that are more tolerant to latency.
  • Stacked on top of semiconductor device 814 is semiconductor device 812, which similarly includes an array of microvaults.
  • the presence of multiple layers of microvaults in semiconductor devices 814 and 812 exemplifies the scalable nature of the assembly, where additional memory capacities and functionalities can be integrated through additional layers.
  • semiconductor devices 810 and 808, positioned above semiconductor device 812 are depicted as SRAM vaulted dies.
  • SRAM provides fast access memory that can serve as a cache or buffer to the slower, but denser, FeFET microvault memory layers beneath.
  • semiconductor devices 806 and 804 At the top of the assembly 800 and hence the memory structure are semiconductor devices 806 and 804, illustrated as DRAM vaulted dies. DRAM is typically used for main memory due to its relatively high speed and low cost per bit compared to SRAM, offering a balance between performance and economy.
  • This vertical stacking and alignment ensure that data and control signals can be directly routed between processing elements and their respective memory stacks, facilitated by interconnect technologies such as through-silicon vias (TSVs) and micro-bumps, which are sued in the assembly's 800 3D integrated circuit architecture.
  • TSVs through-silicon vias
  • micro-bumps micro-bumps
  • assembly 800 allows for various combinations of semiconductor devices or chiplets to be integrated into more extensive systems.
  • the flexibility in the number and combination of stacks provides the adaptability to tailor the assembly to the requirements of different applications and performance demands.
  • Each vault within the vaults 816 within the assembly 800 presents a multi -die structure that contributes to the overall capacity and performance of the system.
  • Fig. 9 shows an assembly of semiconductor devices including a semiconductor device with a system-on-chip 914 and another semiconductor 906 with microvaults disposed on top in accordance with an embodiment of the present disclosure.
  • the assembly 900 integrates a semiconductor device 906 and a semiconductor device 914, which may be implemented as separate chiplets bonded together.
  • the semiconductor device 914 includes various components to facilitate reading data from the microvaults on the semiconductor device 906, such as a read address register input interconnect 924, read data register 922, and read data register output interconnect 950. These components pass the read address to the microvaults on semiconductor device 906 and return the read data back to the semiconductor device 914.
  • the read address enters via interconnect 924 into the read address register 926.
  • the output of this register 962 connects through interconnects and bumpless bonds to another read address register 938 on the semiconductor device 906, which then addresses the target microvault 936.
  • the microvault 936 outputs read data via interconnect 940 to a read data register 942, which passes the data back through bumpless bonds 910, 918 to read data register 922 on semiconductor device 914. This data can then be accessed externally via the read data register output interconnect 950.
  • the semiconductor device 914 and 906 have interconnected Through-Silicon Vias 916 and 944 to allow communication with devices potentially stacked above semiconductor device 906.
  • the semiconductor device 906 features various memory structures to provide data storage capabilities.
  • the microvault 936 resides on the BEOL portion of the chiplet, allowing dense 3D integration of memory layers.
  • the microvault utilizes non-volatile memory technologies like FeFET or STT-MRAM for data retention without power.
  • the semiconductor device 914 comprises processing elements and data routing circuitry to retrieve and manipulate data stored in semiconductor device 906. Components like read address register 926 and read data register 922 handle sending read addresses and receiving data from the microvault 936 respectively.
  • the device 914 also includes interconnects 924, 950 and Through-Silicon Via 916 to communicate externally.
  • the two devices 906 and 914 integrate via fine-pitch interconnects like bumpless hybrid bonds 908, 910, 918, 920, 930 and 932. This allows direct data transfer pathways between processing components in device 914 and memory structures in device 906. Alignment during bonding ensures dedicated access - for instance, read data register output interconnect 950 on 914 links directly to read data register 922 to receive requested data.
  • a read address enters through interconnect 924 into read address register 926 on device 914. This gets communicated via interconnects and bumpless bonds to read address register 938 on device 906, which then addresses microvault 936. Requested data gets passed via interconnect 940 to read data register 942, then transfers through bonds back to read data register 922 on 914, where it becomes available externally via interconnect 950.
  • the assembly 900 exemplifies a modular, high-density architecture optimized for data-centric applications like Al inferencing. Tight integration of processing and storage dies via advanced packaging techniques allows localized data access with minimal latency and power. Scalability is also enabled by incorporating multiple chiplets, in this case devices 906 and 914.
  • the assembly 900 illustrates a potential configuration suited for space-constrained, high-performance computing systems.
  • the Through-Silicon Via (TSV) 916 is an electrical connection that passes vertically through the semiconductor device 914. Its purpose is to provide a pathway for signals to travel between the top and to a processing element within the semiconductor device 914. This allows the device to be stacked and interconnected with other components in a vertical configuration.
  • the TSV 916 interacts with several other components within the system. On the top side of semiconductor device 914, it connects to interconnect 912, which couples it to bumpless bonds 918. These bonds interface with complementary bumpless bonds 910 on the bottom side of semiconductor device 906 when the two devices are stacked. This allows signals to travel from device 914 to device 906 through the TSV 916. The route continues as signals go through interconnect 902 to TSV 944 on device 906. TSV 944 provides a vertical signal pathway to the top surface of device 906 where additional devices could be stacked. In the reverse direction, signals can travel from TSV 944 down through device 906, back up TSV 916, and down into device 914. So the TSV 916 provides bidirectional vertical communication across device boundaries.
  • TSV 916 There are a few possible variations for the TSV 916 implementation.
  • the dimensions and materials of the TSV could be optimized- for example, smaller TSV diameters using denser materials like tungsten could be advantageous.
  • the interface circuitry driving signals into the TSV like interconnects 912 and 902, could employ variable line drivers to support different voltage levels or signal integrity enhancements. Further embodiments may include integrated monitoring circuitry within TSV 916 to track metrics like temperature and link utilization. And alternative signaling schemes besides electrical signals could be employed in future cases. For instance, integrated silicon photonics utilizing modulated light to convey data through the TSVs could enable very high bandwidth and low latency connectivity.
  • TSV-based vertical links like TSV 916 within these complex 3D integrated architectures.
  • interconnect 912 there are several variations and alternatives for the interconnect 912 implementation.
  • different conductive materials such as copper or aluminum may be utilized to fabricate the pathways forming interconnect 912 and optimize for conductivity or thermal dissipation.
  • interconnect 912 may feature redundant signal paths or self-repair capabilities using spare interconnect lines to improve reliability and resilience.
  • the bumpless bonds 918 and 910 connecting devices 906 and 914 could also be replaced with other high-density bonding approaches like hybrid bonding or Through-Silicon Vias.
  • alternate signaling schemes besides simple digital logic could be employed on interconnect 912, such as analog signaling or multi-level digital waveforms to enhance data transmission capabilities.
  • the routing and dimensions of interconnect 912 can also be adapted according to bandwidth requirements or circuit layout considerations. Overall, many structural and functional alternatives exist for crafting interconnect 912 to meet application needs.
  • the bumpless bonds 918 are electrical connections located on the semiconductor device 914 between an interconnect 912 and bumpless bonds 910 of the semiconductor device 906.
  • the bumpless bonds 918 provide an electrical pathway for signals to travel between the semiconductor device 914 and any additional semiconductor devices, such as the semiconductor device 906, stacked on top of the assembly 900.
  • the signals communicated over the bumpless bonds 918 can include data signals, control signals, address signals, or any other signals needed to coordinate operations between the multiple semiconductor devices.
  • the number of individual bond sites can range from just a few to hundreds, depending on signal bandwidth requirements.
  • the bonding method can utilize techniques like direct bonding, plasma-activated bonding, adhesive bonding, or compression bonding. Hybrid bonding approaches are also possible, combining direct wafer bonds with intermediate metal bonds.
  • the size and pitch of each bond site can vary and may use pitches under 10 micrometers to enable high-density connections. Redundant bonds can provide backup pathways. Shielding structures may surround bonds for noise immunity. Overall, many embodiments of bumpless bonds 918 are possible to meet cost, reliability, and performance needs.
  • the bumpless bonds 910 provide an interface for communicating signals between the semiconductor device 906 and semiconductor device 914. Specifically, the bumpless bonds 910 of the semiconductor device 906 are electrically coupled to the complementary bumpless bonds 918 of the semiconductor device 914. This allows signals like read/write data and addresses to be transmitted between the two devices. The bumpless nature of the bonds allows for a low-profile, high-density interconnection.
  • the bumpless bonds 910 interact with other components in the system to facilitate data transfer operations.
  • data enters the semiconductor device 914 via the Through-Silicon Via 916, passes through interconnect 912 and bumpless bonds 918 before reaching bumpless bonds 910 of device 906.
  • addresses flow from the read address register 926 of device 914 through interconnects 928, 930 and bumpless bonds 932 into the read address register 938 on device 906. Read data then returns through bumpless bonds 908 and 920 back to device 914. So the bumpless bonds 910 provide key data and address routing between the devices.
  • bumpless bonds 910 Possible variations of the bumpless bonds 910 include using different bond densities, materials, or electrical contact configurations to optimize performance.
  • the bonds can use alloying or doping techniques to improve conductivity.
  • the routing of signals can be changed, for example by using separate ports for input and output instead of shared ports.
  • More bumpless bonds can be added to increase bandwidth between devices. Shielding may be added around the bonds to reduce interference.
  • many modifications to the bumpless bonds 910 are possible within the scope of electrically interconnecting multiple devices.
  • the Through-Silicon Via (TSV) 944 is an electrical connection that passes vertically through the semiconductor device 906 from the top surface to the bottom surface. Its purpose is to facilitate communication of signals and data between the semiconductor device 906 and any additional semiconductor devices potentially stacked on top of it in a 3D integrated circuit configuration.
  • the TSV 944 enables high-density interconnections between multiple stacked semiconductor layers, providing an efficient means for data routing and signaling.
  • the TSV 944 interfaces with surrounding circuitry within the semiconductor device 906, allowing signals to be transmitted upwards or downwards depending on the system configuration.
  • the TSV 944 couples to the read data register 942 via interconnect 946.
  • the read data register 942 can use the TSV 944 path to transfer read data from the microvault 936 to external semiconductor devices. This enables efficient data offloading from the on-chip memory.
  • the TSV 944 continues through to the top surface of semiconductor device 906, where it may interface with complementary contacts or interconnects on the bonded semiconductor above it. This facilitates the vertical transfer of signals and data along the assembly 900.
  • TSV 944 There can be many variations in the specific implementation of the TSV 944. Its dimensions can range from a few microns to tens of microns to match pitch requirements.
  • the TSV 944 can be tapered, straight, or have non-uniform cross-sections. It may utilize different conductive materials as liners and fills, including metals like copper, tungsten or alloys. Insulating liners made of materials like silicon dioxide can separate the conductive fill from the substrate.
  • the contacts and interconnects coupling into the TSV 944 can also have diverse layouts. Multiple TSVs can be placed adjacent to each other in a high-density array configuration if desired. Overall, many architectural optimizations in the design and fabrication process of the TSV 944 are possible within the scope of the present disclosure.
  • FIG. 10 shows a semiconductor assembly 1000 incorporating a daisy-chained configuration of microvaults 1036, 1058, operatively connected to a multiplexer 1060 and managed by a counter 1062 for coordinated data selection and retrieval, in accordance with an embodiment of the present disclosure.
  • This assembly 1000 is designed to carry out data processing tasks, potentially for applications such as artificial intelligence (Al) and machine learning, where high-speed data access and processing are utilized.
  • Al artificial intelligence
  • machine learning high-speed data access and processing are utilized.
  • the assembly 1000 comprises two primary semiconductor devices: semiconductor device 1006 and semiconductor device 1014.
  • Semiconductor device 1014 is depicted as containing several interfaces and registers for data communication, including a read address register input interconnect 1024.
  • This interconnect 1024 facilitates the delivery of read addresses to a read address register 1026, which temporarily holds these addresses before they are transmitted to corresponding microvaults 1036, 1058 in semiconductor device 1006 for data retrieval operations.
  • interconnect 1028 serves as a pathway for read addresses from the read address register 1026 to transition to bumpless bonds 1030.
  • Bumpless bonds 1030 and 1032 represent high-density, low-profile electrical connections between semiconductor device 1014 and semiconductor device 1006, ensuring the transmission of read addresses with minimal signal loss and physical space requirements.
  • Microvault 1036 a memory storage unit, may encompass a variety of memory technologies, such as FeFETs and/or 3D-NAND structures as described herein, to facilitate the storage and rapid retrieval of data.
  • the multiplexer 1060 selects the appropriate data stream from multiple microvault 1036, 1058 outputs. Controlled by a counter 1062, which may operate according to a predefined sequence or be driven by external control signals, the multiplexer 1060 arbitrates between the outputs of microvault 1036 and another microvault, denoted as microvault 1058. Microvault 1058, similar in function and potential memory technology to microvault 1036, provides an additional source of data for the multiplexer 1060 to select from.
  • a read data register 1042 also located within semiconductor device 1006.
  • This register 1042 acts as a buffer, holding the data for subsequent processing or transmission.
  • the read data is then routed via interconnect 1004 to bumpless bonds 1008, which facilitate the transfer of data to the semiconductor device 1014.
  • bumpless bonds 1010, 1018 facilitate the continued data's journey through the assembly 1000, ensuring data transfer from semiconductor device 1006 to semiconductor device 1014.
  • the read data arrives at semiconductor device 1014, it is channeled via interconnect 1048 to a read data register, specifically read data register 1022, where it can be accessed by external systems, such as an application-specific integrated circuit (ASIC) or a system-on-chip (SoC), via the read data register output interconnect 1050.
  • ASIC application-specific integrated circuit
  • SoC system-on-chip
  • the assembly 1000 encompasses Through-Silicon Vias (TSVs) 1016 and 1044, providing vertical electrical connections through the semiconductor devices 1014 and 1006, respectively.
  • TSVs Through-Silicon Vias
  • Interconnects 1012 and 1046 serve as horizontal pathways for signals to travel to and from the TSVs 1016 and 1044, respectively.
  • the assembly 1000 may be subject to various modifications and alternative embodiments.
  • the number and arrangement of microvaults, the specific types of memory technologies employed within the microvaults, and the configuration of interconnects and bonding areas may be tailored to meet the requirements of different applications.
  • the semiconductor devices 1006 and 1014 may be designed to accommodate additional functionality, such as thermal management layers for heat dissipation, hardware-based encryption modules for data security, or power management circuits to optimize energy consumption.
  • additional functionality such as thermal management layers for heat dissipation, hardware-based encryption modules for data security, or power management circuits to optimize energy consumption.
  • the detailed structure of Fig. 10, therefore, serves as a foundation upon which a variety of sophisticated semiconductor systems can be constructed, each tailored to the specific needs of its intended application.
  • microvaults 1036 and 1058 present a daisy-chaining configuration that allows for an expandable and flexible memory architecture within the semiconductor device 1006. This daisy-chaining is facilitated through a series of interconnected pathways and controlled by the multiplexer 1060 in coordination with the counter 1062.
  • Each microvault such as 1036 and 1058, is designed to hold and provide rapid access to data, which may be in the form of stored charge, magnetic states, ferroelectric material states, or other physical embodiments of binary information.
  • the microvaults are interconnected such that the output of one microvault can be routed to the input of another, creating a chain of memory elements. This is achieved through a series of interconnects, such as interconnect 1034 for microvault 1036 and interconnect 1056 for microvault 1058, which serve as conduits for the read data signals emanating from the microvaults.
  • the multiplexer 1060 manages the flow of data from this daisy chain of microvaults. It is designed with multiple inputs, each connected to the output of a microvault via respective interconnects.
  • interconnect 1040 carries the read data from microvault 1036
  • interconnect 1056 carries the read data from microvault 1058 to the multiplexer 1060.
  • the multiplexer 1060 is capable of selecting which input to connect to its output at any given time, thus controlling which microvault's data is forwarded to the read data register 1042.
  • the counter 1062 orchestrates the operation of the multiplexer 1060. It may be a binary counter or any form of sequential logic circuit that produces a series of output states in response to a clock signal.
  • the counter 1062 progresses through its states with each tick of the clock, which may be provided by an external clock source or generated internally within the semiconductor device 1006. As the counter 1062 advances, it outputs a control signal that instructs the multiplexer 1060 on which input to select.
  • the counter 1062 may instruct the multiplexer 1060 to connect the output from microvault 1036 to the read data register 1042.
  • the counter may switch the connection to microvault 1058's output, and so on, cycling through the available microvaults in a predefined order.
  • the counter's sequence and timing can be configured based on the desired data access patterns and the specific requirements of the processing tasks at hand.
  • This clock-driven coordination allows for an efficient and organized retrieval of data from a potentially large array of microvaults. It ensures that each microvault has an equal opportunity to present its data for processing, and it simplifies the control scheme by reducing it to a predictable, rhythmic progression of states. This is particularly advantageous in systems where a large volume of data must be processed in parallel, as it provides a systematic method for accessing and utilizing the stored information.
  • Fig. 10 illustrates only two microvaults
  • the described daisy-chaining mechanism can be extended to accommodate any arbitrary number of microvaults. Additional microvaults can be added to the chain, with each new microvault connected to the multiplexer via an additional input line.
  • the multiplexer 1060 and counter 1062 would be scaled accordingly to manage the increased number of inputs, maintaining the same clock-driven, sequential data retrieval process across the expanded memory architecture.
  • This daisy-chaining of microvaults in conjunction with the multiplexing and counter-driven control system, exemplifies a modular and scalable approach to memory design in semiconductor devices. It allows for the customization of memory arrays to match the capacity and performance needs of a wide range of applications, from embedded systems to large-scale data centers, providing a versatile solution for modern computing challenges.
  • FIG. 11 shows a semiconductor assembly 1100 incorporating a daisy-chained configuration of microvaults in multiple semiconductor devices 1106, 1116 that are operatively connected to multiplexers and managed by counters for coordinated data selection and retrieval, in accordance with an embodiment of the present disclosure.
  • Fig. 11 of the accompanying drawings illustrates an embodiment of an assembly 1100 as part of an integrated circuit.
  • the assembly 1100 may be seen as a hierarchical structure that includes a bottom semiconductor device 1122, a middle semiconductor device 1116, and a top semiconductor device 1106 (each of these may be chiplets).
  • Each semiconductor device is configured to interface with the others through a series of bumpless bonds, such as bumpless bonds 1128, 1129, 1158, 1159, 1160, 1161, 1162, and 1163, which facilitate electrical connectivity without the added profile of traditional bonding methods, thus enabling a compact and dense stacking of semiconductor layers.
  • the bottom semiconductor device 1122 includes a read address register 1126, which may be configured to store and communicate read addresses to microvaults located across the assembly 1100.
  • the read address register 1126 communicates via an interconnect 1174, which serves as a conduit for signals directed to bumpless bonds 1128. These bonds in turn engage with bumpless bonds 1129 of the middle semiconductor device 1116, thus transferring the read addresses into the middle semiconductor device.
  • the bottom semiconductor device 1122 also comprises a read data register 1124, which may serve as a repository for read data received. Read data is received through an interconnect 1176 that connects to bumpless bonds 1158, which are in communication with bumpless bonds 1159 of the middle semiconductor device 1116.
  • the middle semiconductor device 1116 serves as an intermediary layer within the assembly 1100, housing microvaults such as microvault 1132 and microvault 1118, each of which may be designed to store and rapidly provide access to data. These microvaults are linked to other components within the device via interconnects, such as interconnect 1130 and interconnect 1134, which guide the flow of read addresses and read data, respectively.
  • the middle semiconductor device 1116 also features a read address register 1146, which receives read addresses from interconnect 1130, and a read data register 1154, which collects read data from TSV 1152.
  • the multiplexer 1114 within the middle semiconductor device 1116 selects between various data streams. This multiplexer is controlled by a phase counter 1110, which determines the sequence of data selection based on the input received from the top semiconductor device 1106 via the TSV 1152.
  • the read data register 1112 serves as a holding area for the selected data stream from the multiplexer 1114.
  • the top semiconductor device 1106 features a phase counter 1102 and a read data register 1104, which are used for coordinating data flow within the assembly 1100.
  • the phase counter 1102 in conjunction with multiplexer 1150, dictates the output of read data from microvaults 1138 and 1164 based on the selected phase.
  • the read data register 1104 captures the output from the multiplexer 1150, which is then relayed through interconnect 1108 to bumpless bonds 1162, facilitating communication with the middle semiconductor device 1116.
  • the assembly 1100 illustrates the integration of multiple microvaults across different semiconductor devices. For example, the microvault 1132 on the middle semiconductor device 1116 may receive read addresses from read address register 1146 via an interconnect 1134, path " 1".
  • microvault 1118 may receive read addresses from the same register via an interconnect 1156, path "2".
  • Microvaults 1138 and 1164 on the top semiconductor device 1106 receive read addresses via interconnect 1140 and paths "3" and "4", respectively, from read address register 1142, which is in communication with the middle semiconductor device 1116 via TSV 1136 and bumpless bonds 1160 and 1161.
  • Each microvault such as 1132, 1118, 1138, and 1164, can potentially output read data to the multiplexer 1114 or 1150, where the data is then selected based on the configuration of the respective phase counter, 1110 or 1102.
  • the selected data is temporarily stored in a read data register, either 1112 or 1104, before being transmitted down the assembly 1100 through the respective bumpless bonds and interconnects, ultimately reaching the read data register 1124 of the bottom semiconductor device 1122.
  • This arrangement allows for a synchronized read-out of data from all microvaults, which may be essential in applications requiring parallel processing and high-speed data access.
  • the TSVs provide vertical connectivity across the semiconductor devices, enabling the integration of additional layers or functionalities atop the existing assembly 1100. These TSVs are coupled to various interconnects and bumpless bonds that establish the necessary pathways for signal transmission both within and between the semiconductor devices.
  • the microvaults within the assembly 1100 may include various memory technologies, such as 3D-NAND or 3D-NOR structures, and are arranged to facilitate parallel processing and efficient data retrieval. Each microvault may include additional features, such as thermal management layers for heat dissipation, hardware-based encryption modules for data security, or power management circuits to optimize energy consumption.
  • Datapath 1 within the assembly 1100 exemplifies a route through which read addresses and corresponding read data are transmitted across the assembly, specifically directing operations from the read address register 1126 located on the bottom semiconductor device 1122 to the read data register 1124 within the same device.
  • the process begins with the read address register 1126 holding a specific read address. This address is sent through interconnect 1174, which acts as a channel for the signal. The read address is then transmitted to bumpless bonds 1128, which are meticulously designed to create a reliable electrical connection without the physical protrusion associated with traditional bonding methods. These bonds ensure a low-profile interface that preserves the compactness of the semiconductor stack.
  • the signal continues from bumpless bonds 1128 to engage with bumpless bonds 1129 of the middle semiconductor device 1116.
  • the read address is carried forward by interconnect 1130, which delivers the address to the read address register 1146 of the middle semiconductor device.
  • Read address register 1146 propagates the read address through interconnect 1134, designated as path " 1 " guiding the signal to the microvault 1132.
  • microvault 1132 Upon receiving the read address, microvault 1132 accesses the requested data. This data is then outputted through interconnect 1170 and directed to the multiplexer 1114.
  • multiplexer 1114 functions as a selective switch that chooses between data streams based on the configuration determined by phase counter 1110. This phase counter may be designed to cycle through a sequence that dictates the timing and selection of data streams, ensuring that each microvault is read in a coordinated manner.
  • the selected data from multiplexer 1114 is then captured by read data register 1112, which holds the data momentarily.
  • the data is subsequently sent via interconnect 1120, which carries the signal to bumpless bonds 1159. These bonds are part of a sophisticated electrical interconnection system that, along with bumpless bonds 1158 on the bottom semiconductor device 1122, enables vertical and horizontal integration within the semiconductor stack.
  • the signal now in the form of read data, traverses from bumpless bonds 1159 to bumpless bonds 1158 and is finally introduced into interconnect 1176. This interconnect completes the connection to read data register 1124, which is configured to receive and hold the read data.
  • the read data register 1124 may be equipped to retain the data for subsequent processing or external communication.
  • Datapath 2 within the assembly 1100 delineates a route specifically designed for the transmission of read addresses from the read address register 1126 on the bottom semiconductor device 1122 to the microvault 1118 located on the middle semiconductor device 1116 and the subsequent transfer of read data back to the read data register 1124 on the bottom device.
  • the journey commences at the read address register 1126, where a read address is held in preparation for dispatch.
  • This register is a part of the semiconductor device's control mechanism, orchestrating the retrieval of data by issuing specific addresses to the memory units.
  • the read address is sent through the interconnect 1174, which provides a secure and reliable pathway for electrical signals within the integrated circuit.
  • the read address continues from the interconnect 1174 to bumpless bonds 1128, which offer a seamless and low-profile connection to the middle semiconductor device 1116 via the corresponding bumpless bonds 1129. These bonds maintain the signal's integrity during inter-layer communication and are designed to accommodate the requirements of modern semiconductor architectures.
  • the signal is then channeled via interconnect 1130 to the read address register 1146 within the middle semiconductor device 1116.
  • the read address register 1146 acts as a secondary store and hold register from there, the read address is directed down interconnect 1156, labeled as path "2," which terminates at the microvault 1118.
  • microvault 1118 Upon receipt of the read address, microvault 1118 accesses the corresponding data. This data retrieval process is facilitated by the microvault's internal architecture, which may comprise an array of memory cells optimized for rapid access and data stability. The read data is outputted from microvault 1118 and travels through interconnect 1172, which leads to the multiplexer 1114.
  • Multiplexer 1114 determines which data stream to forward based on input from the phase counter 1110.
  • the phase counter 1110 operates in synchronization with the system clock or an external control signal, cycling through various states to control the selection process of the multiplexer 1114 in a precise and predictable manner.
  • the output of the multiplexer 1114, now carrying the selected read data, is conveyed to read data register 1112. This register temporarily stores the read data, acting as a buffer. The read data is then dispatched via interconnect 1120 towards bumpless bonds 1159.
  • Bumpless bonds 1159 form the interface with bumpless bonds 1158 on the bottom semiconductor device 1122, where the signal is transmitted downward through the assembly.
  • the read data then traverses the interconnect 1176 to reach its final destination, the read data register 1124.
  • the read data register 1124 captures the read data, holding it in readiness for further processing or transmission to external circuits.
  • Datapath 3 within the assembly 1100 is another communication route that illustrates the data transfer sequence from the read address register 1126 on the bottom semiconductor device 1122, through various components, ultimately to the microvault 1138 on the top semiconductor device 1106, and then back to the read data register 1124 on the bottom device.
  • the sequence initiates at the read address register 1126, which serves as the origin point for read addresses.
  • the register 1126 securely holds the address before it is dispatched through the interconnect 1174.
  • Interconnect 1174 acts as a dedicated channel, ensuring that the read address is conveyed with precision to the bumpless bonds 1128.
  • These bumpless bonds 1128 facilitate a streamlined connection to the bumpless bonds 1129 of the middle semiconductor device 1116, preserving the integrity and compactness of the signal pathway.
  • the read address Upon reaching the middle semiconductor device 1116, the read address is relayed through interconnect 1130 to the read address register 1146.
  • the read address register 1146 acts as a juncture that further propagates the address signal through the Through-Silicon Via (TSV) 1136.
  • TSV Through-Silicon Via
  • the TSV 1136 is a vertical interconnect that pierces through the semiconductor substrate, providing a direct link from the middle semiconductor device 1116 to the top semiconductor device 1106, thus exemplifying the 3D integration capabilities of semiconductor design.
  • the read address ascends from TSV 1136 and emerges onto bumpless bonds 1160 on the middle semiconductor device 1116.
  • the bumpless bonds 1160 are connected to the bumpless bonds 1161 of the top semiconductor device 1106.
  • the address signal is conducted through interconnect 1140 to the read address register 1142 on the top device 1106.
  • the read address register 1142 upon receiving the read address, directs the signal along interconnect 1144. This path, denoted as "3,” leads the address to the microvault 1138.
  • Microvault 1138 designed for data storage, retrieves the requested information in response to the read address.
  • the read data is outputted through interconnect 1166, which feeds the data into the multiplexer 1150.
  • the multiplexer 1150 in the top semiconductor device 1106 is governed by the phase counter 1102, which dictates the selection of the data stream to be channeled to the read data register 1104.
  • the chosen data stream is temporarily housed in the read data register 1104, where it awaits downstream transmission.
  • the read data departs from the read data register 1104 via interconnect 1108, which connects to bumpless bonds 1162. These bonds 1162 engage with the corresponding bumpless bonds 1163 on the middle semiconductor device 1116, transferring the read data to TSV 1152.
  • TSV 1152 operates as a vertical conduit, allowing the read data to traverse down into the middle semiconductor device 1116, where it is received by the read data register 1154.
  • the read data register 1154 holds the read data momentarily before it is directed to the multiplexer 1114 through interconnect 1156.
  • the multiplexer 1114 in the middle semiconductor device 1116 coordinated by the phase counter 1110, selects the appropriate data for output.
  • the read data is then channeled to the read data register 1112, where it is briefly stored. Following this, the read data travels via interconnect 1120 to bumpless bonds 1159.
  • the bumpless bonds 1159 form an interface with bumpless bonds 1158 on the bottom semiconductor device 1122.
  • the read data signal is then carried through interconnect 1176, culminating its journey at the read data register 1124 on the bottom device.
  • Datapath 4 within the assembly 1100 is a path that establishes the flow of read addresses from the read address register 1126 on the bottom semiconductor device 1122 to the microvault 1164 located on the top semiconductor device 1106, and subsequently facilitates the movement of read data back down to the read data register 1124 on the bottom device.
  • This datapath begins at the read address register 1126, which is responsible for holding and issuing the read addresses necessary for data retrieval from the microvaults.
  • the read address is sent from the register 1126 through interconnect 1174, a pathway that maintains signal integrity and facilitates electrical communication.
  • the read address is directed to bumpless bonds 1128. These bonding areas create an interconnection between the bottom semiconductor device 1122 and the middle semiconductor device 1116 through bumpless bonds 1129. The design of these bumpless bonds facilitates data transmission.
  • the read address Once the read address reaches the middle semiconductor device 1116, it is carried forward by interconnect 1130 to the read address register 1146. This register acts as an intermediary, preparing the address for its vertical ascent through the device stack. The address is then transmitted via the Through-Silicon Via (TSV) 1136 that facilitates vertical integration by providing a direct electrical link through the semiconductor substrate.
  • TSV Through-Silicon Via
  • the read address After ascending through TSV 1136, the read address emerges onto bumpless bonds 1160, which are aligned to connect with bumpless bonds 1161 on the top semiconductor device 1106. The read address then proceeds along interconnect 1140 to the read address register 1142 located on the top device.
  • the read address register 1142 serves to forward the read address to its final destination, the microvault 1164, through interconnect 1148, labeled as path "4".
  • Microvault 1164 upon receiving the read address, retrieves the requested data, which is then outputted through interconnect 1168. This data is directed to the multiplexer 1150, which is under the control of phase counter 1102.
  • the phase counter 1102 determines which data stream is selected by the multiplexer 1150, which then sends the read data to the read data register 1104.
  • the read data register 1104 acts as a temporary repository, holding the data until it can be sent downwards through the device stack.
  • the data leaves the read data register 1104 and travels via interconnect 1108 to bumpless bonds 1162. These bonds maintain a connection to bumpless bonds 1163 on the middle semiconductor device 1116.
  • the read data is then transferred to TSV 1152, which carries the data vertically down to the read data register 1154 on the middle semiconductor device 1116.
  • the read data register 1154 temporarily holds the read data before it is fed into the multiplexer 1114 via interconnect 1156.
  • the multiplexer 1114 coordinated by the phase counter 1110, channels the appropriate data stream to the read data register 1112. This register serves as a staging area for the read data, which is then sent through interconnect 1120 to bumpless bonds 1159.
  • Bumpless bonds 1159 interface with bumpless bonds 1158 on the bottom semiconductor device 1122 to provide a downward transmission of the read data. Finally, the signal is routed through interconnect 1176 and arrives at read data register 1124, where the data is made available for subsequent processing or external communication.
  • Fig. 12 illustrates a three-dimensional (3D) memory column 1200 configured as a 3D-N0R or 3D-AND structure, featuring a series of ferroelectric field-effect transistors (FeFETs) 1202 with interconnected drain terminals 1204 linked to a common select line 1212 and individual gate terminals 1206 connected to respective read/write enable lines 1214 (e.g., 1214a for FeFET 1202a, all coupled to a common bit line, in accordance with an embodiment of the present disclosure.
  • FeFETs ferroelectric field-effect transistors
  • Fig. 12 depicts a three-dimensional (3D) memory column, designated as element 1200, which can be configured in various embodiments as either a 3D-NOR or 3D- AND structure, providing flexibility in the application and use of the integrated circuit.
  • This memory column is an assembly of multiple ferroelectric field-effect transistors (FeFETs), collectively referred to as fefets 1202, where each FeFET is indicated by elements such as 1202a, 1202b, 1202c, and 1202d, among others potentially present in the array.
  • FeFETs ferroelectric field-effect transistors
  • each FeFET such as 1202a, there is a drain terminal 1204a.
  • This drain terminal is part of the memory cell's output path and is connected to a common select line 1212.
  • the common select line 1212 serves as a control mechanism that enables the selection of a particular FeFET for data read or write operations.
  • each FeFET exemplified by 1206a for FeFET 1202a
  • a respective read/write enable line such as 1214a. This enables control of the FeFET's state, allowing it to be in a conductive (on) state for reading or writing data or in a non-conductive (off) state to prevent data flow.
  • the presence of individual read/write lines for each FeFET may allow for precise control and operation of each memory cell.
  • each FeFET such as 1202a, comprises a source terminal, such as 1208a, which is coupled to a common bit line 1210.
  • the bit line 1210 provides a conduit for data being written to or read from the FeFETs. In some embodiments, this bit line can be shared across multiple memory columns, which can facilitate parallel processing and increased data throughput.
  • the 3D memory column 1200 may incorporate additional elements and configurations to enhance performance and functionality.
  • the 3D memory column 1200 may include insulating materials, conductive pathways, and other structural components not explicitly shown in Fig. 12 but which are inherent to the implementation of such 3D memory structures.
  • the FeFETs 1202 may also exhibit variations in terms of material composition, structural dimensions, and electrical properties, contributing to a range of performance characteristics suitable for different applications.
  • the memory column 1200 may be incorporated into larger memory arrays, forming part of a memory module or system. These arrays can be arranged in various configurations, such as rows and columns, to create a matrix that efficiently addresses the demands of high-density data storage.
  • the memory column 1200 can also be interfaced with other circuit elements and control logic, which may govern the operation of the memory array, including data management protocols, error correction algorithms, and power optimization strategies.
  • the memory column 1200 may be fabricated using advanced semiconductor manufacturing techniques, such as photolithography, etching, deposition, and planarization processes.
  • advanced semiconductor manufacturing techniques such as photolithography, etching, deposition, and planarization processes.
  • the choice of materials for the FeFETs, including the ferroelectric material, the semiconductor channel, and the conductive elements, can be selected based on desired electrical characteristics, such as charge retention, switching speed, and energy efficiency.
  • the 3D memory column 1200 may include FeFETs, such as 1202, fabricated from a variety of materials that provide the necessary electrical and physical properties to achieve the desired functionality.
  • FeFETs such as 1202
  • the channel layer of each FeFET in the FeFETs 1202 could be constructed from materials such as Indium Gallium Zinc Oxide (IGZO) or other Amorphous Oxide Semiconductors (AOS) like Zinc Tin Oxide or Indium Tungsten Oxide (IWO). These materials are selected for their electronic properties, such as carrier mobility and stability.
  • the ferroelectric material rigidly coupled to the channel layer in each FeFET may comprise hafnium zirconium oxide (HfZrO2) or other transition metal oxides, perovskites, etc. These ferroelectric materials are chosen for their ability to maintain a polarization state when an electric field is applied, which is used for the non-volatile memory characteristics of the FeFETs.
  • the thickness, crystalline structure, and stoichiometry of the ferroelectric layer can be controlled to achieve the desired coercive voltage, remanent polarization, and other electrical parameters for reliable data storage and retrieval.
  • the drain 1204 and source 1208 terminals of the FeFETs 1202 are connected to the common select line 1212 and common bit line 1210, respectively.
  • These common lines may be formed from conductive materials such as tungsten, titanium nitride, or other metals and metal alloys that provide low-resistance pathways for electrical signals. The configuration of these terminals and their respective common lines ensures that the FeFETs can be accessed and controlled effectively during operation.
  • Each gate terminal, such as the gate 1206 of the FeFET 1202a is connected to its respective read/write enable line, such as 1214a.
  • the gate terminals are help control the state of the FeFET, and the materials chosen for these terminals may include various conductive materials that can provide a reliable electrical interface with the ferroelectric material.
  • the read/write enable 1214 lines are designed to deliver suitable voltage levels to the gates 1206 of the FeFETs 1202 for switching between states.
  • the memory column 1200 as a whole is designed to support a range of operating parameters.
  • these parameters may include, but are not limited to, an off- state current of less than 10 A -8 amps per centimeter cubed, an on-state current greater than 10 A - 7 amps per centimeter cubed, and a channel mobility that is maintained despite the presence of the ferroelectric layer.
  • the channel layer's thickness can be less than 30 nm to ensure high device density, while the ferroelectric layer's characteristics, such as coercive voltage and remanent polarization, are optimized to provide the necessary memory functionality.
  • the FeFETs 1202 may include additional materials or dopants to enhance their electrical properties.
  • dopants such as gallium (Ga), indium (In), or zinc (Zn) may be introduced into the channel layer to modulate the carrier concentration or to adjust the threshold voltage of the FeFETs.
  • the ferroelectric layer may include dopants like lanthanum (La) or niobium (Nb) to adjust its ferroelectric properties.
  • the 3D memory column 1200 may be integrated with additional semiconductor devices and structures to form complex memory systems. These systems can provide storage capabilities and support various memory architectures.
  • Fig. 13 depicts a three-dimensional (3D) memory column 1300 configured as a 3D-NAND structure, consisting of a vertical stack of ferroelectric field-effect transistors (FeFETs) 1302, each with source 1304 and drain 1308 terminals.
  • the source 1304 of each FeFET such as 1304a for FeFET 1302a, is coupled to the start of a bit line 1310 or connected to the drain of the preceding FeFET, exemplified by source 1304b of FeFET 1302b coupled to drain 1308a of FeFET 1302a.
  • Each FeFET includes a gate 1306, such as 1306a for FeFET 1302a, connected to a respective read/write enable line, illustrated by 1314a for FeFET 1302a, in accordance with an embodiment of the present disclosure.
  • the 3D memory column 1300 is composed of a series of vertically stacked Field-Effect Transistors (FeFETs), identified collectively as FeFETs 1302. These transistors, which include FeFETs 1302a, 1302b, 1302c, 1302d, and so on, are characterized by their incorporation of ferroelectric materials within their gate structure. Each FeFET in the series is of the memory column contributes to the memory storage capabilities of the device. [00527] In the depicted embodiment, each FeFET, such as FeFET 1302a, includes a source terminal 1304, for instance, source 1304a, which is coupled to a bit line 1310.
  • FeFETs Field-Effect Transistors
  • the bit line 1310 serves as a conduit for electrical signals that are used to read from and write to the memory cell associated with FeFET 1302a.
  • its source 1304b may be connected to the drain 1308a of the immediately preceding FeFET, such as FeFET 1302a, facilitating a serial connection that defines the vertical NAND architecture.
  • Each FeFET within the FeFETs 1302 is further equipped with a gate terminal 1306, exemplified by gate 1306a for FeFET 1302a.
  • This gate terminal 1306 is coupled to a respective read/write enable line, exemplified by 1314a for FeFET 1302a.
  • the read/write enable line 1314a is responsible for controlling the state of the FeFET, allowing it to either conduct or prevent the flow of current through the device, thereby enabling the writing or reading of data.
  • each FeFET of the FeFETs 1302 also includes a drain terminal 1308, such as drain 1308a for FeFET 1302a, which is typically connected to the source of the subsequent FeFET in the vertical stack. This arrangement ensures that the charge stored in the ferroelectric material of the gate can modulate the current flowing from the source to the drain, allowing for the storage and retrieval of data.
  • the memory column 1300 within Fig. 13 is indicative of a memory architecture that can be utilized in various applications, from portable electronics to enterprise-level data storage systems.
  • the ferroelectric material used in the FeFETs may include various compositions, such as hafnium oxide, zirconium oxide, or any combination thereof, which can be doped with elements such as lanthanum or yttrium to adjust the ferroelectric properties as required.
  • the 3D memory column 1300 can incorporate additional features that enhance performance, reliability, or manufacturability.
  • the FeFETs 1302 may include protective layers to shield the ferroelectric material from environmental factors or process-induced damage.
  • the column 1300 may also be integrated with other circuit elements, such as capacitors or diodes, to facilitate operations like charge pumping or to provide additional functionality within the memory array.
  • the 3D memory column 1300 may be fabricated from a variety of materials that confer specific electrical properties to enhance device performance.
  • the channel layer of each FeFET may be formed from materials such as Indium Gallium Zinc Oxide (IGZO).
  • IGZO Indium Gallium Zinc Oxide
  • Other materials for the channel layer could include Amorphous Oxide Semiconductors (AOS) like Zinc Tin Oxide or Aluminum Zinc Oxide.
  • AOS Amorphous Oxide Semiconductors
  • the ferroelectric layer within the FeFETs 1302 may comprise materials such as Hafnium Zirconium Oxide (HfZrO2).
  • HfZrO2 Hafnium Zirconium Oxide
  • the ferroelectric layer's thickness and material composition can be controlled through methods like Atomic Layer Deposition (ALD) to achieve the desired coercive voltages, remanent polarizations, and endurance characteristics.
  • ALD Atomic Layer Deposition
  • the coercive voltage of the ferroelectric layer may be tuned to be between -3 Volts to +3 Volts, facilitating low-voltage operation of the memory devices.
  • the source and drain terminals of the FeFETs 1302 may be composed of conductive materials such as Tungsten or Titanium Nitride. These materials may also be selected to optimize the contact resistance with the channel layer, reducing overall power consumption and improving the lon/Ioff ratio of the device.
  • the FeFETs 1302 may be engineered to exhibit specific electrical parameters.
  • the channel layer's thickness may be less than 30 nm in some embodiments.
  • the channel layer may demonstrate a carrier concentration of 10 A l 7 to 10 A 20 per centimeter-cubed, which can be adjusted through doping with elements such as Gallium, Indium, or Zinc to modulate the electrical properties.
  • the memory cells formed by the FeFETs 1302 within the 3D memory column 1300 may also target operational parameters such as read and write latencies, endurance, and energy consumption. For example, read and write operations may be executed with energies less than 10 picojoules and within timeframes less than 20 nanoseconds, contributing to the low power and high-speed attributes of the memory column.
  • the 3D-NAND configuration of the memory column 1300 may be designed to achieve a high off-state resistance to on-state resistance ratio (Roff/Ron), which is critical for distinguishing between different data states and ensuring reliable data retention.
  • This ratio may be about 10 A 3 or greater, which helps to maintain a high signal -to-noise ratio during memory operations.
  • the FeFETs 1302 in the memory column 1300 may also be designed to sustain a high degree of reliability, with endurance ratings greater than or equal to 10 A l 1 cycles, ensuring the longevity and durability of the memory device. This endurance is complemented by the ferroelectric layer's ability to maintain data retention for at least 1 minute at room temperature, which is 25°C.
  • Fig. 14 depicts a three-dimensional (3D) memory column configured as a 3D- NAND with an integrated pass gate, in accordance with an embodiment of the present disclosure.
  • This figure illustrates a series of ferroelectric field-effect transistors (FeFETs) 1402, each including source 1404 and drain 1408 terminals, gated by respective gate terminals 1406 and coupled to read/write enable lines 1414.
  • the FeFETs are interconnected, forming a vertical memory structure with pass gates 1418 linked to a pass gate line 1416.
  • Fig. 14 illustrates a three-dimensional (3D) memory column, designated as element 1400, which can be configured as a 3D-NAND structure with an integrated pass gate. This configuration enables enhanced control over individual memory cells within the 3D structure, potentially improving read/write operations and facilitating efficient memory management.
  • the 3D memory column 1400 comprises multiple ferroelectric fieldeffect transistors (FeFETs), collectively referred to as FeFETs 1402.
  • FeFETs ferroelectric fieldeffect transistors
  • These FeFETs are utilized fortheir ability to retain data in a non-volatile manner due to the ferroelectric properties of their gate material, which allows for data retention without continuous power supply for a time.
  • Each FeFET in the series 1402 includes a source, exemplified by source 1404a for FeFET 1402a.
  • the source 1404 for each FeFET is either coupled to a bit line, illustrated as bit line 1410 for FeFET 1402a, or is connected to the drain of the preceding FeFET in the series.
  • source 1404b of FeFET 1402b is electrically coupled to drain 1408a of FeFET 1402a.
  • This serial connection forms the basis for the daisy-chain configuration, which is used in NAND architectures, allowing for sequential access to the array of FeFETs.
  • each FeFET within the FeFETs 1402 is equipped with a gate terminal, such as gate 1406a for FeFET 1402a.
  • the gates of the FeFETs are connected to their respective read/write enable lines, which are depicted as element 1414 in the figure.
  • gate 1406a of FeFET 1402a is influenced by read/write enable line 1414a. These enable lines control the application of appropriate voltages for the reading and writing of data.
  • each FeFET in the FeFETs 1402 series includes a drain, such as drain 1408a for FeFET 1402a. This drain is connected to the source of the subsequent FeFET in the series, thus establishing the continuity for the columnar structure of the 3D memory stack.
  • each FeFET of the FeFETs 1402 incorporates a pass gate, for example, pass gate 1418a, which is connected to a pass gate line, represented by 1416 in the figure.
  • the pass gate line 1416 is a conductive pathway that provides electrical signals to control the pass gates 1418 of the FeFETs.
  • the inclusion of pass gates in the FeFETs may allow for improved isolation between memory cells during operation, thereby reducing interference and potentially enhancing the reliability of data storage and retrieval.
  • the 3D memory column 1400 as depicted in Fig. 14 also encompasses a diverse range of materials and parameters that could be utilized to optimize its performance in various embodiments.
  • Each FeFET 1402 within the column could be fabricated using a variety of semiconductor materials.
  • the channel layer of the FeFETs could be formed from materials such as Indium Gallium Zinc Oxide (IGZO).
  • the ferroelectric layer which is a defining characteristic of the FeFETs, may be composed of materials like Hafnium Zirconium Oxide (HfZrO2) or other perovskite materials, which are known for their remanent polarization. This property determines the data retention capabilities of the FeFETs.
  • the coercive voltage of this layer which affects the energy required to switch the polarization state, is another critical parameter that can be adjusted according to the requirements of the specific application, with a range in one embodiment being between -3 Volts to 3 Volts.
  • the source and drain terminals of the FeFETs which include elements 1404 and 1408, respectively, could be composed of conductive materials such as Tungsten or Titanium Nitride. These materials provide pathways for current flow, which is for switching.
  • the read/write enable lines 1414, which control the gates 1406 of the FeFETs, could also be fabricated from similar materials, ensuring consistent electrical characteristics throughout the device.
  • the channel layer thickness may be less than
  • the electron mobility within these channel layers may be maintained at a predetermined level even when the layer is less than 30nm in thickness.
  • the pass gates 1418 may be manufactured using low-resistance materials to enable quick switching times, which is beneficial when the memory column is accessed frequently during operation.
  • Fig. 15 illustrates a three-dimensional (3D) memory column 1500, which may be configured as either a 3D-NOR or a 3D- AND structure with independent Read/Write enable capabilities, in accordance with an embodiment of the present disclosure.
  • This memory column encompasses a series of vertically aligned FeFETs 1502, such as FeFETs 1502a, 1502b, 1502c, 1502d, and so forth, each integrated with a source 1504 (e.g., source 1504a for FeFET 1502a) linked to a respective read enable line 1520 (e.g., read enable line 1520a for FeFET 1502a), and a gate 1506 (e.g., gate 1506a for FeFET 1502a) connected to a corresponding write enable line 1522 (e.g., write enable line 1522a for FeFET 1502a). All FeFETs within the column share a common bit line 1510 connected to their drains 1508, enabling the column to perform coordinated memory operations.
  • Fig. 15 presents a detailed depiction of a three-dimensional (3D) memory column 1500, which can be configured as a 3D-NOR or 3D-AND structure with independent Read/Write enable functionalities.
  • This memory column is an assembly of Field-Effect Transistors with ferroelectric gate layers, commonly referred to as FeFETs 1502, which are individually identified, for example, as 1502a, 1502b, 1502c, 1502d, etc., each representing a memory cell within the column.
  • each FeFET 1502 includes a source 1504, such as source 1504a corresponding to FeFET 1502a.
  • the source 1504 is designed to be electrically coupled to a respective read enable line 1520, such as read enable line 1520a which is dedicated to FeFET 1502a.
  • the read enable line 1520 functions to selectively activate the FeFET 1502 for reading operations, allowing the readout of stored data from the memory cell.
  • each FeFET 1502 is equipped with a gate 1506, exemplified by gate 1506a for FeFET 1502a.
  • the gate 1506 is connected to a respective write enable line 1522, such as write enable line 1522a, which is specific to FeFET 1502a.
  • the write enable line 1522 serves to selectively activate the FeFET 1502 for writing operations, enabling the storage of data within the memory cell.
  • each FeFET 1502 includes a drain 1508, for instance, drain 1508a affiliated with FeFET 1502a.
  • the drain 1508 is connected to a common bit line 1510.
  • the bit line 1510 acts as a conduit for transferring data to and from the memory cells during read and write operations.
  • the commonality of the bit line 1510 across multiple FeFETs 1502 signifies that data from any activated memory cell can be routed through this shared path.
  • the configuration of the FeFETs 1502 allows for a high density of memory cells vertically stacked within a compact footprint.
  • the ferroelectric material utilized in the gate 1506 of the FeFETs 1502 may comprise various compositions, such as hafnium oxide-based materials, which can be deposited using atomic layer deposition techniques.
  • the ferroelectric property of the material allows for data retention, enabling the memory cells to maintain stored information even when power is not supplied.
  • the source 1504, gate 1506, and drain 1508 of each FeFET 1502 can be fabricated from materials that provide predetermined electrical performance. These materials may include metals such as tungsten or copper, or metal nitrides such as titanium nitride.
  • the read enable lines 1520 and write enable lines 1522 can be designed to minimize crosstalk and interference between adjacent lines, in some embodiments. In some specific embodiments, shielding layers or insulating materials may be included to further isolate the signal paths.
  • the described memory column 1500 may be integrated within a larger semiconductor device, such as a processor or a storage module. It may form part of a system-on-chip (SoC) or be included in a multi-chip module (MCM), contributing to a data storage and retrieval system.
  • SoC system-on-chip
  • MCM multi-chip module
  • the materials that constitute the FeFETs 1502 within the memory column 1500 are selected to provide specific electrical and physical properties to optimize the performance of the integrated circuit.
  • the channel layer in each FeFET may be formed from advanced semiconductor materials, such as Indium Gallium Zinc Oxide (IGZO) or other Amorphous Oxide Semiconductors (AOS) like Zinc Tin Oxide or Cadmium Oxide. These materials are chosen for their excellent electron mobility characteristics and stability.
  • IGZO Indium Gallium Zinc Oxide
  • AOS Amorphous Oxide Semiconductors
  • the ferroelectric layer integral to the FeFETs 1502, may be fabricated from various ferroelectric materials that exhibit suitable polarization properties. Materials such as Hafnium Zirconium Oxide (HfZrO2) or Lead Zirconate Titanate (PZT) could be utilized. These materials can be doped with elements such as Lanthanum, Yttrium, or other suitable dopants to modify their ferroelectric properties, such as coercive voltage, remanent polarization, and crystallization temperature. The ferroelectric layer's thickness and material composition may be adjusted to achieve desired memory characteristics, such as write endurance and retention time, while ensuring the layer remains compatible with the overall semiconductor manufacturing process, or other considerations, etc.
  • HfZrO2 Hafnium Zirconium Oxide
  • PZT Lead Zirconate Titanate
  • These materials can be doped with elements such as Lanthanum, Yttrium, or other suitable dopants to modify their ferroelectric properties, such as coercive voltage, remanent polar
  • the source 1504, gate 1506, and drain 1508 terminals of the FeFETs 1502 may be composed of conductive materials like Tungsten, Titanium Nitride, Nickel, or Molybdenum. Connections to the read enable lines 1520 and the write enable lines 1522 may be facilitated through conductive vias or contacts.
  • the read enable lines 1520 and write enable lines 1522, along with the common bit line 1510, may be patterned using lithographic techniques to achieve the predetermined precision and alignment for proper functionality. These lines may be insulated from one another using dielectric materials like Silicon Dioxide (SiO2), Silicon Nitride (Si3N4), or low- k dielectrics to reduce parasitic capacitance and crosstalk.
  • dielectric materials like Silicon Dioxide (SiO2), Silicon Nitride (Si3N4), or low- k dielectrics to reduce parasitic capacitance and crosstalk.
  • Each element within the memory column 1500 may consider factors such as line width, spacing, and aspect ratio to ensure manufacturability, functionality, and/or other goals or characteristics.
  • the materials and processes used in the construction of the memory column 1500 are chosen to ensure compatibility with standard semiconductor fabrication techniques, such as photolithography, etching, deposition, and annealing, while also enabling the integration of materials and structures.
  • the fabrication of the FeFETs 1502 within the memory column 1500 may involve deposition techniques such as atomic layer deposition (ALD), chemical vapor deposition (CVD), or physical vapor deposition (PVD) to create uniform and/or non-uniform layers.
  • ALD atomic layer deposition
  • CVD chemical vapor deposition
  • PVD physical vapor deposition
  • Fig. 16 presents a cross-sectional view of a 3D memory structure, designated as 1600, configured as a single-port 3D NAND, in accordance with an embodiment of the present disclosure.
  • the structure includes a first vertical structure 1608a and a second identical vertical structure 1608b, each comprising a dielectric column 1610a, 1610b, a channel column 1612a, 1612b disposed around the dielectric column, and a ferroelectric column 1614a, 1614b disposed around the channel column.
  • a series of horizontal gate-electrode layers 1606a-c are disposed at predetermined distances from each other, adj acent to the ferroelectric column along the length of the vertical structures.
  • the assembly further includes a drain select layer 1602 and a source select layer 1604, with respective end dielectric columns 1618a, 1618b, and 1616a, 1616b positioned at the interfaces with the vertical structures, illustrating a detailed and intricate design for high-density data storage.
  • fig. 16 provides a cross-sectional view of a three-dimensional (3D) memory structure, designated as 1600, which is configured as a single-port 3D NAND architecture.
  • This structure incorporates a pair of vertical structures, 1608a and 1608b, which may be fabricated to be substantially identical, as indicated by their respective subscripts a and b, suggesting the potential for a modular and scalable memory array design.
  • Each vertical structure exemplified by the first vertical structure 1608a, includes a dielectric column 1610a.
  • the dielectric column may adopt various geometric forms — it can be cylindrical, substantially cylindrical, or feature curves. Additionally, it may present a tapered form, having different diameters at each end, implying a design that narrows towards the top. Both solid and hollow configurations of the dielectric column are contemplated within the scope of the disclosure, offering design flexibility for different electrical and structural requirements.
  • a channel column 1612a Surrounding the dielectric column 1610a is a channel column 1612a, which is the locus for charge carriers during device operation.
  • the channel column is also described as potentially cylindrical, substantially cylindrical, or feature curves and/or and may exhibit similar variations in diameter along its length as the dielectric column.
  • Enveloping the channel column 1612a is a ferroelectric column 1614a, which extends along the length of the channel column but may recede at the ends, thereby meaning the ferroelectric column 1614 does not extend the entire length of the channel column 1612a.
  • drain select layer 1602 parallel to the horizontal gate-electrode layers 1606.
  • end dielectric columns, 1618a and 1618b are discernible. These end dielectric columns 1618 interface with the channel column 1612 and the drain select layer 1602, contributing to the isolation and control of the charge carriers within the channel column. They may contact the ferroelectric layer 1614, as they envelop the channel column 1612 at different positions along its length.
  • a source select layer 1604 is situated at the bottom of the structure 1600, again parallel to the horizontal gate-electrode layers 1606.
  • the horizontal gate-electrode 1606 layers could be constructed from a range of conductive materials, including metals and metal compounds, which may offer different work functions, conductivity, and compatibility with other materials in the structure.
  • the ferroelectric column 1614 might incorporate a variety of ferroelectric materials each with its unique polarization characteristics, coercive fields, and dielectric constants, affecting the device's memory retention and switching behaviors.
  • the channel column 1612 materials can be chosen based on their electronic properties, such as carrier mobility and bandgap, to achieve the desired levels of on-state and off-state current.
  • the dielectric column 1610 provides the electrical insulation necessary to prevent leakage currents and ensure the proper functioning of the device.
  • the dielectric column such as 1610a for the first vertical structure, may be constructed from materials that offer insulating properties to mitigate any potential leakage currents.
  • Choices for the dielectric material may be Hafnium Oxide (HfO2) or Silicon Dioxide (SiO2).
  • the channel column (1612a) Surrounding the dielectric column, the channel column (1612a) has channel material can be selected from a wide range of semiconducting materials that offer predetermined carrier mobility. For example, Indium Gallium Zinc Oxide (IGZO) can be used for its electrical properties.
  • IGZO Indium Gallium Zinc Oxide
  • the channel layer's thickness may vary, with some embodiments considering a thickness less than 30 nm. This thickness is chosen to achieve a predetermined electrical performance.
  • the ferroelectric column like 1614a, may include perovskite structures, such as Lead Zirconate Titanate (PZT).
  • the horizontal gate-electrode layers are composed of conductive materials that facilitate the application of an electric field to the ferroelectric column, such as Tungsten or Titanium Nitride, which may be chosen for their electrical behavior.
  • the selection of gate-electrode materials also takes into consideration factors such as work function, thermal stability, and ease of integration with the existing semiconductor manufacturing processes.
  • the drain and source select layers, 1602 and 1604 respectively, are incorporated to enable the addressing of individual memory cells within the array.
  • the materials used for these layers are chosen for their conductive properties and compatibility with the channel and ferroelectric materials.
  • the design of these layers may also incorporate considerations for reducing parasitic capacitance and ensuring swift data access.
  • the end dielectric columns like 1618a and 1616a, provide electrical insulation at the ends of the channel column, where the ferroelectric material does not extend.
  • the disclosed embodiments within the 3D memory structure 1600 outline an assembly capable of providing data storage.
  • the design allows for variations in structural dimensions, such as the diameter of the cylindrical columns, which can be uniform or tapered. Additionally, the option for solid or hollow configurations may be used.
  • Fig. 17 shows a 3D memory structure that is a dual -port 3D NAND arrangement in accordance with an embodiment of the present disclosure.
  • the three-dimensional (3D) memory structure illustrated in Fig. 17, referred to as 3D memory structure 1700 exemplifies a dual-port 3D NAND arrangement to provide a memory functionality.
  • This structure is characterized by two primary vertical formations, designated as the first vertical structure 1708a and the second vertical structure 1708b, which may be identical or near identical, as evidenced by the designating subscripts ‘a’ and ‘b’.
  • the first vertical structure 1708a includes a hollow or solid, tapered pass-gate electrode column 1718a that is substantially cylindrical in shape.
  • the pass-gate electrode column 1718a may be made of titanium nitride and may have a larger diameter at the bottom end compared to the top end.
  • a dielectric column 1710a Surrounding the pass-gate electrode column 1718a is a dielectric column 1710a that may be made of hafnium oxide.
  • the dielectric column 1710a is also substantially cylindrical with a slightly tapered shape, having a marginally larger diameter at the top.
  • the dielectric column 1710a provides electrical isolation between the pass-gate electrode and subsequent layers.
  • a cylindrical channel column 1712a Disposed around the dielectric column 1710a is a cylindrical channel column 1712a that may be made of IGZO semiconductor material.
  • the channel column 1712a features curves along its length and has a uniform diameter throughout.
  • the thickness of the channel column may be less than 30 nm.
  • the channel column 1712a Enclosing the channel column 1712a is a PZT ferroelectric column 1714a that covers most of the length of the channel column 1712a but recedes at the ends, leaving a portion of the channel column 1712a uncovered.
  • the ferroelectric column 1714a is substantially cylindrical and contains lead, zirconium and titanium as key elemental constituents.
  • the vertical structures 1708a and 1708b traverse through several horizontal gate-electrode layers 1706a, 1706b and 1706c that may be made of tungsten, which are positioned at fixed intervals to form an interconnected grid layout. These layers influence the electric field within the ferroelectric column 1714a during memory operations.
  • a drain select layer 1702 (e.g., titanium nitride) runs parallel to the horizontal gate-electrode layers 1706. Where the drain select layer 1702 intersects the vertical structures 1708a and 1708b, end dielectric columns 1718a and 1718b are visible. These end columns (e.g., made of HfO2) touch the ferroelectric column 1714a on one end and surround the uncovered portion of channel column 1712a, providing insulation.
  • a source select layer 1704 (e.g., made of tungsten), also parallel to the electrode layers 1706, interfaces with the vertical structures. End dielectric columns 1716a and 1716b can be observed at these intersection points, enclosing the open ends of the channel columns 1712a and 1712b.
  • a thin dielectric horizontal layers 1720a and 1720b may be placed near the bottom terminals (e.g., HfO2). These layers seal off the bottom open ends of the vertical hollow voids.
  • Fig. 18 illustrates a 3D memory structure 1800 that can be configured as a 3D NOR Vertical Transistor memory array.
  • the 3D memory structure 1800 comprises a first vertical structure 1808a and an identical (or substantially identical) second vertical structure 1808b arranged adjacent to one another.
  • the first vertical structure 1808a includes a vertical plug column 1802a that provides an electrical connection to the lower portions of the 3D memory structure.
  • the vertical plug column 1802a may have a uniform diameter along its entire length or may have a larger diameter on its lower end than on its upper end.
  • the plug column 1802a can be fabricated as a solid column or as a hollow column in various embodiments.
  • a source electrode column 1804a and a drain electrode column 1816a Disposed adjacent to the vertical plug column 1802a is a source electrode column 1804a and a drain electrode column 1816a.
  • the source electrode column 1804a and drain electrode column 1816a provide electrical connections to the source and drain nodes of the vertical transistors formed along the vertical structure 1808a.
  • the source electrode column 1804a and drain electrode column 1816a may be comprised of various conducting materials including, but not limited to, tungsten, titanium nitride, tantalum nitride, nickel, molybdenum, platinum, palladium, cobalt, gold, aluminum, copper, hafnium, hafnium nitride, iridium, iridium oxide, ruthenium, ruthenium oxide, silicides, graphene, carbon nanotubes, doped polysilicon, indium tin oxide, silver, aluminum-doped zinc oxide, gallium, gallium arsenide, indium gallium zinc oxide, metal alloys such as AICu and TiW, and conducting polymers.
  • conducting materials including, but not limited to, tungsten, titanium nitride, tantalum nitride, nickel, molybdenum, platinum, palladium, cobalt, gold, aluminum, copper, hafnium, hafnium nitride, iridium
  • the channel column 1812a Surrounding the vertical plug column 1802a, source electrode column 1804a, and drain electrode column 1816a is a channel column 1812a that provides the semiconductor channel region for the vertical transistors along the first vertical structure 1808a.
  • the channel column 1812a may be formed from materials including, but not limited to, indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), zinc tin oxide (ZTO), aluminum zinc oxide (AZO), indium tungsten oxide (IWO), gallium zinc oxide (GZO), hafnium indium oxide (HIO), cadmium oxide (CdO), polysilicon, polygermanium, cadmium selenide (CdSe), copper indium gallium selenide (CIGS), crystalline silicon, crystalline germanium, gallium arsenide (GaAs), indium phosphide (InP), indium antimonide (InSb), silicon carbide (SiC), gallium nitride (GaN), zinc oxide (Z
  • the ferroelectric column 1814a Surrounding the channel column 1812a is a ferroelectric column 1814a that provides the gate dielectric for the vertical transistors along the first vertical structure 1808a.
  • the ferroelectric column 1814a may be comprised of ferroelectric materials including, but not limited to, perovskite oxides, lead zirconate titanate (PZT), barium titanate (BaTiO3), strontium titanate (SrTiO3), bismuth ferrite (BiFeO3), potassium niobate (KNbO3), lithium niobate (LiNbO3), lithium tantalate (LiTaO3), sodium bismuth titanate (Na0.5Bi0.5TiO3), bismuth titanate (Bi4Ti3O12), bismuth zinc niobate (Bi(Znl/2Ti 1/2)03), bismuth lanthanum titanate (BiLaTiO3), bismuth nickel titanate
  • the 3D memory structure 1800 further comprises multiple horizontal gate electrode layers 1806 including layers 1806a, 1806b, 1806c etc.
  • the horizontal gate electrode layers 1806 are disposed at regular intervals along the vertical structures 1808 and provide the gate electrodes for the vertical transistors.
  • the gate electrode layers 1806 may be formed from materials such as tungsten, titanium nitride, tantalum nitride, nickel, molybdenum, platinum, palladium, cobalt, gold, aluminum, copper, hafnium, hafnium nitride, iridium, iridium oxide, ruthenium, ruthenium oxide, silicides, graphene, carbon nanotubes, doped polysilicon, indium tin oxide, silver, aluminum-doped zinc oxide, gallium, gallium arsenide, indium gallium zinc oxide, metal alloys such as AICu and TiW, and conducting polymers.
  • materials such as tungsten, titanium nitride, tantalum nitride, nickel, molybdenum, platinum, palladium, cobalt, gold, aluminum, copper, hafnium, hafnium nitride, iridium, iridium oxide, ruthenium, ruthenium oxide, silicides
  • Each of the horizontal gate electrode layers 1806 may be surrounded by an oxide/nitride/oxide (ONO) stack 1810, such as 1810a surrounding gate electrode layer 1806a, to provide insulation between the gate electrodes.
  • ONO oxide/nitride/oxide
  • the second vertical structure 1808b in the 3D memory structure 1800 is identically configured as the first vertical structure 1808a.
  • the two vertical structures 1808a and 1808b are arranged horizontally adjacent to each other with a spacing that allows integration of the gate electrode layers 1806 and ONO stacks 1810. Together, the first and second vertical structures 1808a, 1808b along with the horizontal gate electrode layers 1806 can be configured as a 3D NOR memory architecture.
  • Fig. 19 illustrates an embodiment of a planar FeFET 1900.
  • the FeFET 1900 comprises a substrate 1910 upon which various layers and components are formed.
  • the substrate 1910 may be comprised of silicon or other suitable semiconductor materials.
  • Disposed on top of the substrate 1910 is a layer of TiN 1912.
  • the TiN layer 1912 may act as an electrode and can be deposited by sputtering or other suitable deposition techniques.
  • HZO 1908 comprises hafnium, zirconium, and oxygen and can exhibit ferroelectric properties.
  • the HZO 1908 may be deposited by ALD, CVD, PVD or other suitable deposition methods and can have a thickness in the range of 5-50 nm. Acting as a ferroelectric layer, the HZO 1908 enables the non-volatile storage of data in the FeFET 1900.
  • IWO 1906 comprises indium, tungsten, and oxygen. It can be deposited by sputtering or other suitable techniques and may have a thickness in various ranges.
  • the IWO 1906 layer serves as a control oxide layer in the FeFET 1900.
  • drain contact 1904 and source contact 1914 are formed on top of the IWO 1906 layer.
  • the drain contact 1904 and source contact 1914 may comprise metals such as copper, aluminum, or alloys thereof and can be deposited by PVD, CVD or other suitable methods.
  • the drain contact 1904 and source contact 1914 allow electrical connection to the FeFET 1900. They may have thicknesses in the range of 50-500 nm.
  • a voltage applied to the drain 1904, source 1914, and TiN gate contact 1912 can control the ferroelectric polarization of the HZO 1908 layer.
  • the polarization state can be used to store information in a non-volatile manner, enabling memory storage capabilities.
  • the IWO 1906 layer helps improve the switching speed and endurance of the FeFET 1900. Overall, the layered structure shown in Fig. 19 enables a FeFET 1900 suitable for non-volatile memory applications.
  • Fig. 20 presents the transfer characteristics of a Ferroelectric FET (FeFET) device, illustrating the relationship between the gate voltage (V_GS) on the x-axis and the resulting drain current (I D) on the y-axis.
  • Fig. 20 may show the characteristics of a FeFET as disclosed herein.
  • the x-axis spans from -IV to IV, while the y-axis, on a logarithmic scale, displays current values from 10 A -12A/pm to 10 A -4A/pm
  • the red curve starts at approximately 10 A -l lA/pm at -IV and increases more gradually as it approaches 0V. At around IV, it then follows closely with the blue curve past IV. This demonstrates comparable drain current behavior under reverse bias conditions regardless of the polarization state.
  • the separation between the red and blue curves spans several orders of magnitude in the negative voltage range near -IV.
  • This substantial difference in off-state current highlights the non-volatile memory effect achievable with the FeFET depending on its polarization direction.
  • This large memory window is explicitly called out in the green box labeled “Large Memory Window” at the top left.
  • Additional key details provided include the FeFET device dimensions, with a width/length ratio of lpm/50nm specified.
  • Fig. 20 comprehensively depicts the bidirectional transfer characteristics of the FeFET device, highlighting the large memory window achievable through polarization switching and providing detailed voltage, current, and dimensional specifications to fully convey the measurement conditions and transistor performance.
  • the paired curves effectively compare the clockwise and counterclockwise operation modes over the full gate voltage range.
  • An integrated circuit comprising: a first transistor comprising: a channel layer formed using a semiconductor material; and a ferroelectric rigidly coupled to the channel layer; a source terminal fixed to the channel layer; a drain terminal fixed to the channel layer; and a gate terminal fixed to the ferroelectric layer.
  • Oxide Semiconductor includes at least one of Indium Oxide, Indium Gallium Zinc Oxide, Zinc Tin Oxide, Indium Zinc Oxide, Gallium Zinc Oxide, Aluminum Zinc Oxide, Cadmium Oxide, Hafnium Indium Zinc Oxide, Tin Oxide, stannous Tin Oxide, stannic Tin Oxide, Indium-Tin- Zinc Oxide, Indium-Tungsten Oxide, Indium-Gallium-Zinc-Tin Oxide, Indium-Gallium-Zinc- Ozynitride, Aluminum-Indium-Gallium-Zinc Oxide, and Zinc-Indium Oxide.
  • Semiconductor is doped with at least one of Gallium (Ga), Indium (In), Zinc (Zn), Tin (Sn), Hafnium (Hf), Silicon (Si), Aluminum (Al), Magnesium (Mg), Calcium (Ca), Strontium (Sr), Barium (Ba), Titanium (Ti), Zirconium (Zr), Molybdenum (Mo), Tantalum (Ta), Niobium (Nb), Chromium (Cr), Iron (Fe), Cobalt (Co), Nickel (Ni), Copper (Cu), Silver (Ag), Gold (Au), Cerium (Ce), Lanthanum (La), Neodymium (Nd), Samarium (Sm), Europium (Eu), Gadolinium (Gd), Terbium (Tb), Dysprosium (Dy), Holmium (Ho), Erbium (Er), Thulium (Tm), Ytterbium (Yb), Lutetium (Lu), Yttrium (Y
  • IWO Indium Tungsten Oxide
  • IGZO indium galium zinc oxide
  • hafnium zirconium oxide is HfD.5Zr0.5O2.
  • the integrated circuit is disposed on a back-end-of-the-line portion of a semiconductor device fabrication flow.
  • ferroelectric layer is made of transition metal oxides, a perovskite, or a two-dimensional material.
  • ferroelectric layer is formed using vapor deposition.
  • ferroelectric layer is formed by adding a dopant comprising at least one of Lanthanum, Niobium, Manganese, Zirconium, Tin, Strontium, Calcium, Yttrium, Magnesium.
  • ferroelectric layer is Hafnium Zirconium Oxide.
  • the first transistor is configured to have 3 or more states each state corresponding to a stored value of the memory cell.
  • ferroelectric layer is configured for a substantially uniform electric field distribution across the ferroelectric layer.
  • microvault is formed via a column in one of a 3D-NOR, a 3D-AND, a 3D-NAND, or a 3D-NAND-PG configuration.
  • IGZO Indium Gallium Zinc Oxide
  • the source terminal comprises at least one of Tungsten, Titanium Nitride, Nickel, and Molybdenum.
  • the drain terminal comprises at least one of Tungsten, Titanium Nitride, Nickel, and Molybdenum.
  • the gate terminal comprises at least one of Tungsten, Titanium Nitride, Nickel, and Molybdenum.
  • microvault column is configured as a 3D-NOR.
  • microvault column is configured as a 3D-AND.
  • microvault column is configured as a 3D-NAND.
  • microvault column is configured as a 3D-NAND with pass gate.
  • microvault column is configured as a 3D-NOR with an independent read enable and an independent write enable.
  • the microvault column is configured as a 3D-AND with an independent read/write enable.
  • the ferroelectric layer is formed from at least one of Perovskites, Lead Zirconate Titanate (PZT), Barium Titanate (BaTiO3), Strontium Titanate (SrTiO3), Bismuth Ferrite (BiFeO3), Potassium Niobate (KNbO3), Lithium Niobate (LiNbO3), Lithium Tantalate (LiTaO3), Sodium Bismuth Titanate (Na0.5Bi0.5TiO3), Bismuth Titanate (Bi4Ti3O12), Bismuth Zinc Niobate (Bi(Znl/2Ti 1/2)03), Bismuth Lanthanum Titanate (BiLaTiO3), Bismuth Nickel Titanate (BiN
  • An integrated circuit comprising: a first vertical structure, comprising: a dielectric column; a channel column disposed around the dielectric column; and a ferroelectric column disposed around the channel along a length of the channel column; and a plurality of horizontal gate-electrode layers, each of the plurality of horizontal gate-electrode layers disposed a predetermined distance between each other, each of the plurality of horizontal gate-electrode layers disposed adjacent to the ferroelectric column along the length of the ferroelectric column.
  • the integrated circuit according to aspect 96 further comprising a dielectric end column disposed around an end of the channel column and adjacent to an end of the length of the channel column and adjacent to the ferroelectric column.
  • ferroelectric column is formed from at least one of Perovskites, Lead Zirconate Titanate (PZT), Barium Titanate (BaTiO3), Strontium Titanate (SrTiO3), Bismuth Ferrite (BiFeO3), Potassium Niobate (KNbO3), Lithium Niobate (LiNbO3), Lithium Tantalate (LiTaO3), Sodium Bismuth Titanate (Na0.5Bi0.5TiO3), Bismuth Titanate (Bi4Ti3O12), Bismuth Zinc Niobate (Bi(Znl/2Ti 1/2)03), Bismuth Lanthanum Titanate (BiLaTiO3), Bismuth Nickel Titanate (BiNiTiO3), Lead Magnesium Niobate-Lead Titanate (PMN-PT), Lead Lanthanum Zirconate Titanate (PLZT), Lead Zirconate Titanate (PZT), Barium Titanate (Ba
  • the channel column is formed from at least one of Indium Gallium Zinc Oxide (IGZO), Indium Zinc Oxide (IZO), Zinc Tin Oxide (ZTO), Aluminum Zinc Oxide (AZO), Indium Tungsten Oxide (IWO), Gallium Zinc Oxide (GZO), Hafnium Indium Oxide (HIO), and Cadmium Oxide (CdO), Polysilicon, Polygermanium Cadmium Selenide (CdSe), Copper Indium Gallium Selenide (CIGS), Crystalline Silicon (c-Silicon), Crystalline Germanium (c-Germanium), Gallium Arsenide (GaAs), Indium Phosphide (InP), Indium Antimonide (InSb), Silicon Carbide (SiC), Gallium Nitride (GaN), Zinc Oxide (ZnO), Pentacene, P3HT (Poly(3 -hexylthiophen
  • the dielectric column is formed from at least one of Hafnium Oxide (HfO2), Zirconium Oxide (ZrO2), Aluminum Oxide (A12O3), Silicon Dioxide (SiO2), Titanium Dioxide (TiO2), Tantalum Oxide (Ta2O5), Lanthanum Oxide (La2O3), Yttrium Oxide (Y2O3), Silicon Nitride (Si3N4), Aluminum Nitride (AIN), Silicon Carbide (SiC), Strontium Titanate (SrTiO3), Barium Strontium Titanate (BST), Lead Zirconate Titanate (PZT), Bismuth Ferrite (BiFeO3), Magnesium Oxide (MgO), Cerium Oxide (CeO2), Nickel Oxide (NiO), Cobalt Oxide (CoO), Copper Oxide (CuO), Manganese Oxide (MnO), Zinc Oxide (A12O3), Silicon Dioxide (SiO2), Titanium
  • An integrated circuit comprising: a first vertical structure, comprising: a pass-gate electrode column; a dielectric column disposed around the pass-gate electrode column; a channel column disposed around the dielectric column; and a ferroelectric column disposed around the channel along a length of the channel column; and a plurality of horizontal gate-electrode layers, each of the plurality of horizontal gate-electrode layers disposed a predetermined distance between each other, each of the plurality of horizontal gate-electrode layers disposed adjacent to the ferroelectric column along the length of the ferroelectric column.
  • the integrated circuit according to aspect 124 further comprising a dielectric end column disposed around an end of the channel column and adjacent to an end of the length of the channel column and adjacent to the ferroelectric column.
  • the passgate electrode column is formed from at least one of Tungsten, Titanium Nitride, Tantalum Nitride, Nickel, Molybdenum, Platinum, Palladium, Cobalt, Gold, Aluminum, Copper, Hafnium, Hafnium Nitride, Iridium, Iridium Oxide, Ruthenium, Ruthenium Oxide, Silicides, TiSi2, CoSi2, NiSi, Graphene, Carbon Nanotubes, Doped Poly silicon, Indium Tin Oxide, Silver, Aluminum-doped Zinc Oxide, Gallium, Gallium Arsenide, Indium Gallium Zinc Oxide, Metal Alloys, AICu, TiW, and Conducting Polymers.
  • ferroelectric column is formed from at least one of Perovskites, Lead Zirconate Titanate (PZT), Barium Titanate (BaTiO3), Strontium Titanate (SrTiO3), Bismuth Ferrite (BiFeO3), Potassium Niobate (KNbO3), Lithium Niobate (LiNbO3), Lithium Tantalate (LiTaO3), Sodium Bismuth Titanate (Na0.5Bi0.5TiO3), Bismuth Titanate (Bi4Ti3O12), Bismuth Zinc Niobate (Bi(Znl/2Ti 1/2)03), Bismuth Lanthanum Titanate (BiLaTiO3), Bismuth Nickel Titanate (BiNiTiO3), Lead Magnesium Niobate-Lead Titanate (PMN-PT), Lead Lanthanum Zirconate Titanate (PMN-PT), Lead Lanthanum Zirconate Titanate (PMN-PT), Lead Lan
  • the channel column is formed from at least one of Indium Gallium Zinc Oxide (IGZO), Indium Zinc Oxide (IZO), Zinc Tin Oxide (ZTO), Aluminum Zinc Oxide (AZO), Indium Tungsten Oxide (IWO), Gallium Zinc Oxide (GZO), Hafnium Indium Oxide (HIO), and Cadmium Oxide (CdO), Polysilicon, Polygermanium Cadmium Selenide (CdSe), Copper Indium Gallium Selenide (CIGS), Crystalline Silicon (c-Silicon), Crystalline Germanium (c-Germanium), Gallium Arsenide (GaAs), Indium Phosphide (InP), Indium Antimonide (InSb), Silicon Carbide (SiC), Gallium Nitride (GaN), Zinc Oxide (ZnO), Pentacene, P3HT (Poly(3 -hexylthiophen
  • the dielectric column is formed from at least one of Hafnium Oxide (HfO2), Zirconium Oxide (ZrO2), Aluminum Oxide (A12O3), Silicon Dioxide (SiO2), Titanium Dioxide (TiO2), Tantalum Oxide (Ta2O5), Lanthanum Oxide (La2O3), Yttrium Oxide (Y2O3), Silicon Nitride (Si3N4), Aluminum Nitride (AIN), Silicon Carbide (SiC), Strontium Titanate (SrTiO3), Barium Strontium Titanate (BST), Lead Zirconate Titanate (PZT), Bismuth Ferrite (BiFeO3), Magnesium Oxide (MgO), Cerium Oxide (CeO2), Nickel Oxide (NiO), Cobalt Oxide (CoO), Copper Oxide (CuO), Manganese Oxide (MnO), Zinc Oxide (A12O3), Silicon Dioxide (SiO2), Titanium
  • An integrated circuit comprising: a first vertical structure, comprising: a vertical plug column; a source electrode column disposed adjacent to the vertical plug column; a drain electrode column disposed adjacent to the vertical plug column; a channel column disposed around the vertical plug column, the source electrode column, and the drain electrode column; and a ferroelectric column disposed around the channel column; and a plurality of horizontal gate-electrode layers, each of the plurality of horizontal gate-electrode layers disposed a predetermined distance between each other, each of the plurality of horizontal gate-electrode layers disposed adjacent to the ferroelectric column along the length of the ferroelectric column.
  • each of the horizontal gate-electrode layers includes an Oxide/Nitride/Oxide disposed adjacent thereto.
  • source electrode column is formed from at least one of Tungsten, Titanium Nitride, Tantalum Nitride, Nickel, Molybdenum, Platinum, Palladium, Cobalt, Gold, Aluminum, Copper, Hafnium, Hafnium Nitride, Iridium, Iridium Oxide, Ruthenium, Ruthenium Oxide, Silicides, TiSi2, CoSi2, NiSi, Graphene, Carbon Nanotubes, Doped Poly silicon, Indium Tin Oxide, Silver, Aluminum-doped Zinc Oxide, Gallium, Gallium Arsenide, Indium Gallium Zinc Oxide, Metal Alloys, AICu, TiW, and Conducting Polymers.
  • the gate electrode column is formed from at least one of Tungsten, Titanium Nitride, Tantalum Nitride, Nickel, Molybdenum, Platinum, Palladium, Cobalt, Gold, Aluminum, Copper, Hafnium, Hafnium Nitride, Iridium, Iridium Oxide, Ruthenium, Ruthenium Oxide, Silicides, TiSi2, CoSi2, NiSi, Graphene, Carbon Nanotubes, Doped Poly silicon, Indium Tin Oxide, Silver, Aluminum-doped Zinc Oxide, Gallium, Gallium Arsenide, Indium Gallium Zinc Oxide, Metal Alloys, AICu, TiW, and Conducting Polymers.
  • ferroelectric column is formed from at least one of Perovskites, Lead Zirconate Titanate (PZT), Barium Titanate (BaTiO3), Strontium Titanate (SrTiO3), Bismuth Ferrite (BiFeO3), Potassium Niobate (KNbO3), Lithium Niobate (LiNbO3), Lithium Tantalate (LiTaO3), Sodium Bismuth Titanate (Na0.5Bi0.5TiO3), Bismuth Titanate (Bi4Ti3O12), Bismuth Zinc Niobate (Bi(Znl/2Ti 1/2)03), Bismuth Lanthanum Titanate (BiLaTiO3), Bismuth Nickel Titanate (BiNiTiO3), Lead Magnesium Niobate-Lead Titanate (PMN-PT), Lead Lanthanum Zirconate Titanate (PLZT), Lead Zirconate Titanate (PZT), Barium Titanate (Ba
  • the channel column is formed from at least one of Indium Gallium Zinc Oxide (IGZO), Indium Zinc Oxide (IZO), Zinc Tin Oxide (ZTO), Aluminum Zinc Oxide (AZO), Indium Tungsten Oxide (IWO), Gallium Zinc Oxide (GZO), Hafnium Indium Oxide (HIO), and Cadmium Oxide (CdO), Polysilicon, Polygermanium Cadmium Selenide (CdSe), Copper Indium Gallium Selenide (CIGS), Crystalline Silicon (c-Silicon), Crystalline Germanium (c-Germanium), Gallium Arsenide (GaAs), Indium Phosphide (InP), Indium Antimonide (InSb), Silicon Carbide (SiC), Gallium Nitride (GaN), Zinc Oxide (ZnO), Pentacene, P3HT (Poly(3 -hexylthiophene), Zinc Tin Oxide (ZTO), Aluminum Zinc Oxide (AZO), Indium
  • the vertical plug column is formed from at least one of Hafnium Oxide (HfO2), Zirconium Oxide (ZrO2), Aluminum Oxide (A12O3), Silicon Dioxide (SiO2), Titanium Dioxide (TiO2), Tantalum Oxide (Ta2O5), Lanthanum Oxide (La2O3), Yttrium Oxide (Y2O3), Silicon Nitride (Si3N4), Aluminum Nitride (AIN), Silicon Carbide (SiC), Strontium Titanate (SrTiO3), Barium Strontium Titanate (BST), Lead Zirconate Titanate (PZT), Bismuth Ferrite (BiFeO3), Magnesium Oxide (MgO), Cerium Oxide (CeO2), Nickel Oxide (NiO), Cobalt Oxide (CoO), Copper Oxide (CuO), Manganese Oxide (MnO), Zinc Oxide (HfO2), Zirconium Oxide (ZrO2),
  • transition metal di chalcogenide (TMD) may be written as MX2, wherein M refers to transition metal atom, and X is the chalcogen atom.
  • TMD is selected from the group consisting of molybdenum disulfide (MoS2), molybdenum diselenide (MoSe2), tungsten disulfide (WS2), tungsten diselenide (WSe2), molybdenum ditelluride (MoTe2), tungsten ditelluride (WTe2), titanium diselenide (TiSe2), niobium disulfide (NbS2), titanium disulfide (TiS2), nickel disulfide (NiS2), and vanadium diselenide (VSe2), niobium diselenide (NbSe2), and tantalum sulfide (TaS2).
  • MoS2 molybdenum disulfide
  • MoSe2 molybdenum diselenide
  • WS2 tungsten disulfide
  • WSe2 tungsten diselenide
  • MoTe2 molybdenum ditelluride

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Abstract

L'invention divulgue un transistor FeFET et des circuits intégrés associés. La couche de canal du transistor (1612a) peut être formée à partir d'un semi-conducteur d'oxyde amorphe. Des exemples de semi-conducteurs d'oxyde amorphe qui pourraient être utilisés comprennent de l'oxyde d'indium, de l'oxyde d'indium-gallium-zinc (IGZO), de l'oxyde de zinc-étain (ZTO), de l'oxyde d'indium-zinc (IZO), de l'oxyde de gallium-zinc (GZO), de l'oxyde d'aluminium-zinc (AZO), de l'oxyde de cadmium, de l'oxyde d'hafnium-indium-zinc (HIZO), de l'oxyde d'étain et de l'oxyde d'indium-étain-zinc (ITZO), entre autres. La couche de canal semi-conducteur d'oxyde amorphe peut également être dopée avec des éléments tels que le gallium, l'indium, le zinc, l'étain, l'hafnium, le silicium, l'aluminium et d'autres pour optimiser la concentration et la mobilité du support.
PCT/US2024/041400 2023-08-11 2024-08-08 Structures fefet utilisant des canaux semi-conducteurs d'oxyde amorphe sur des circuits intégrés Pending WO2025038369A1 (fr)

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