[go: up one dir, main page]

WO2025013484A1 - Conductive member - Google Patents

Conductive member Download PDF

Info

Publication number
WO2025013484A1
WO2025013484A1 PCT/JP2024/020775 JP2024020775W WO2025013484A1 WO 2025013484 A1 WO2025013484 A1 WO 2025013484A1 JP 2024020775 W JP2024020775 W JP 2024020775W WO 2025013484 A1 WO2025013484 A1 WO 2025013484A1
Authority
WO
WIPO (PCT)
Prior art keywords
conductive
layer
recess
thickness
angle
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
PCT/JP2024/020775
Other languages
French (fr)
Japanese (ja)
Inventor
佳子郎 村田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Intellectual Property Management Co Ltd
Original Assignee
Panasonic Intellectual Property Management Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Panasonic Intellectual Property Management Co Ltd filed Critical Panasonic Intellectual Property Management Co Ltd
Publication of WO2025013484A1 publication Critical patent/WO2025013484A1/en
Pending legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01B—CABLES; CONDUCTORS; INSULATORS; SELECTION OF MATERIALS FOR THEIR CONDUCTIVE, INSULATING OR DIELECTRIC PROPERTIES
    • H01B5/00—Non-insulated conductors or conductive bodies characterised by their form
    • H01B5/14—Non-insulated conductors or conductive bodies characterised by their form comprising conductive layers or films on insulating-supports
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details

Definitions

  • This disclosure relates to a conductive member having a multilayer wiring structure.
  • Conductive materials used in touch panels and the like have been known for some time. Some conductive materials have a multilayer wiring structure in which multiple wiring layers are stacked.
  • the conductive substrate of Patent Document 1 includes a first conductive substrate and a second conductive substrate.
  • a plurality of electrode portions (wiring) are formed on each of the first conductive substrate and the second conductive substrate.
  • the first conductive substrate and the second conductive substrate are bonded together by an adhesive layer with the electrode portions formed on the first conductive substrate and the second conductive substrate facing each other.
  • peeling of the electrode portions is prevented by interposing an adhesion improving layer made of a metal oxide between each conductive substrate and the electrode portions.
  • Patent Document 1 an adhesion improvement layer made of a metal oxide is formed between the conductive substrate and the electrode part. That is, an adhesion improvement layer is formed on the side surface of the electrode part.
  • Patent Document 1 in order to further prevent the electrode part from peeling off, it is conceivable to further form an adhesion improvement layer on the side surface of the electrode part. In this way, by forming an adhesion improvement layer on the bottom surface and side surface of the electrode part, it is possible to prevent the electrode part from peeling off and to make the electrode part less visible.
  • the cross-sectional shape of the electrode part is approximately rectangular, so the thickness of the adhesion improvement layer formed on the side of the electrode part is thin.
  • the adhesion improvement layer is formed by a method such as sputtering, if the thickness of the adhesion improvement layer formed on the side of the electrode part is thin, the thickness of the adhesion improvement layer formed on the bottom surface of the electrode part is also thin. As a result, the overall thickness of the adhesion improvement layer is thin, making the electrode part easier to see.
  • the wiring width of the electrode part is widened to reduce the wiring resistance of the electrode part, the wider wiring width of the electrode part makes the electrode part easier to see.
  • a conductive member includes a substrate having transparency and light transmissivity, a first conductive wire disposed in a recess provided in the substrate, and a second conductive wire located on the first conductive wire and disposed in the recess of the substrate, the first conductive wire includes a first metal compound layer made of a metal compound, and a first conductive layer formed on the first metal compound layer and made of a conductive metal, the first metal compound layer contacting a first side surface which is a side surface of the recess in the first layer, the second conductive wire includes a second metal compound layer made of a metal compound, and a second conductive layer formed on the second metal compound layer.
  • the second metal compound layer being in contact with a second side surface that is a side surface of the recess in the second layer, the second groove width that is the groove width of the recess in the second layer being wider than the first groove width that is the groove width of the recess in the first layer, the second angle that is the angle between the second side surface and the bottom surface of the first layer being larger than the first angle that is the angle between the first side surface and the bottom surface of the first layer, and the second thickness that is the thickness of the second metal compound layer at the portion in contact with the lower end of the second conductive layer being thicker than the first thickness that is the thickness of the first metal compound layer at the portion in contact with the lower end of the first conductive layer.
  • the conductive member having the multilayer wiring structure disclosed herein can reduce wiring resistance while making the wiring less visible.
  • FIG. 1 is a perspective view showing an entire multilayer wiring board according to an embodiment of the present disclosure.
  • FIG. 2 is a plan view showing the entire multilayer wiring board according to the embodiment of the present disclosure.
  • FIG. 3 is a partially enlarged plan view showing a portion III in FIG.
  • FIG. 4 is a partially enlarged plan view showing a portion IV in FIG.
  • FIG. 5 is a partially enlarged plan view showing the connection region and its periphery shown in FIG.
  • FIG. 6 is a cross-sectional view taken along line VI-VI in FIG.
  • FIG. 7 is a schematic cross-sectional view of a first conductive wire and a second conductive wire arranged to overlap each other.
  • FIG. 8 is a cross-sectional view that illustrates a schematic cross-sectional state of the first recess and the second recess in FIG.
  • FIG. 9 is a schematic cross-sectional view of a modification of the embodiment in which a first conductive wire and a second conductive wire are arranged to overlap each other.
  • FIG. 10 is a cross-sectional view that illustrates a schematic cross-sectional state of the first recess and the second recess in FIG.
  • FIGS. 1 and 2 show the overall configuration of a multilayer wiring board 1 (conductive member) according to an embodiment of the present disclosure.
  • a multilayer wiring board 1 formed by an imprinting method is illustrated.
  • the multilayer wiring board 1 is provided with a plurality of mounting elements 2. Examples of the mounting elements 2 include LED elements or diodes.
  • the plurality of mounting elements 2 are disposed on the upper side of a substrate 3 (the upper surface side of a first layer 5 (described later)).
  • the direction from the left side to the right side of the paper in FIG. 2 is defined as the "X direction,” while the direction from the bottom to the top of the paper in FIG. 2 is defined as the "Y direction.”
  • the multilayer wiring board 1 includes a substrate 3.
  • the substrate 3 is transparent and light-transmitting.
  • the side on which a film base 4 (described later) is located is defined as the "lower side” of the substrate 3
  • the side on which a second layer 6 (described later) is located is defined as the "upper side” of the substrate 3.
  • the substrate 3 includes a film substrate 4.
  • the film substrate 4 is made of a resin material that is at least flexible and light-transmitting. Preferably, the film substrate 4 has a light transmittance of 80% or more.
  • the film substrate 4 is, for example, 25 ⁇ m to 200 ⁇ m.
  • the film substrate 4 may also be transparent.
  • the resin material examples include PET (polyethylene terephthalate), polycarbonate, COP (cycloolefin polymer), and COC (cycloolefin copolymer).
  • the substrate 3 includes a first layer 5 and a second layer 6.
  • Each of the first layer 5 and the second layer 6 is made of a resin material that is insulating and optically transparent.
  • This resin material is, for example, a thermosetting resin or an ultraviolet-curing resin material.
  • the thickness of each of the first layer 5 and the second layer 6 is, for example, 1 ⁇ m to 6 ⁇ m.
  • the first layer 5 is a layer for arranging the first conductor pattern 10 described below.
  • the first layer 5 is laminated on the upper side of the film substrate 4.
  • the upper surface of the first layer 5 is formed so as to be flat or have a slightly recessed central portion, with the conductive metal constituting each of the first conductive lines 13 described below embedded in the first recesses 7 described below.
  • the first layer 5 has a plurality of bottomed first recesses 7 that are recessed downward from the top surface of the first layer 5.
  • the first recesses 7 extend linearly on the top surface of the first layer 5 to form a predetermined pattern, which will be described later.
  • the groove depth of the first recess 7 is set to, for example, 0.5 ⁇ m or more and 5 ⁇ m or less.
  • the second layer 6 has a plurality of second recesses 8 that are recessed downward from the upper surface of the second layer 6.
  • the second recesses 8 extend linearly to form a predetermined pattern, which will be described later, on the upper surface of the second layer 6.
  • the second recesses 8 are configured so that only the portions where the via portions 22, which will be described later, are formed penetrate the substrate 3 in the thickness direction.
  • the groove depth of the second recess 8 is set to, for example, 0.5 ⁇ m or more and 5 ⁇ m or less.
  • the first conductor pattern 10 is composed of a plurality of first conductive wires 13.
  • Each of the first conductive wires 13 is thinned.
  • the line width of each of the first conductive wires 13 is configured to be 15 ⁇ m or less.
  • the mesh pattern (first conductor pattern 10) consisting of a plurality of first conductive wires 13 is configured so that the plurality of first conductive wires 13 cross each other and are arranged at a predetermined interval (equally spaced intervals in the illustrated example).
  • Each of the first conductive wires 13 constituting the mesh pattern extends diagonally with respect to both the X direction and the Y direction.
  • the multilayer wiring board 1 includes a plurality of second conductor patterns 14.
  • the plurality of second conductor patterns 14 are arranged at intervals (equally spaced in the illustrated example) from one another in the Y direction in a plan view. Note that, for convenience of illustration, the second conductor patterns 14 are simply illustrated by dot hatching in FIGS. 1 to 3.
  • Each second conductive line 17 (described later) constituting the second conductor pattern 14 is disposed on the second layer 6 (see FIG. 6).
  • the second conductor pattern 14 is disposed at a different position from the first conductor pattern 10 in the thickness direction of the substrate 3.
  • Each second conductor pattern 14 has a second main body 15 and multiple (four in the illustrated example) second branch portions 16.
  • the second main body 15 and each second branch portion 16 are formed in a generally strip-like shape in a plan view.
  • the second main body 15 extends in a generally strip-like shape along the X direction in a plan view.
  • Each second branch portion 16 branches off from a midway point of the second main body 15. Specifically, each second branch portion 16 extends from a midway point of the second main body 15 in a direction opposite to the Y direction (toward the bottom of the paper in FIG. 2).
  • the second conductive wires 17 are arranged in a predetermined pattern on the surface of the second layer 6.
  • Figure 4 shows a mesh pattern in which the second conductive wires 17 are arranged in a mesh shape as an example of the predetermined pattern.
  • the mesh pattern (second conductor pattern 14) consisting of a plurality of second conductive wires 17 is configured so that the plurality of second conductive wires 17 cross each other and are arranged at a predetermined interval (equally spaced in the illustrated example).
  • Each of the second conductive wires 17 constituting the mesh pattern extends diagonally with respect to both the X direction and the Y direction.
  • the mesh pattern consisting of a plurality of second conductive wires 17 has the same aperture ratio as the mesh pattern (first conductor pattern 10) consisting of a plurality of first conductive wires 13.
  • the first conductor pattern 10 and the second conductor pattern 14 are provided with an overlapping pattern 20.
  • the overlapping pattern 20 is configured so that a part of the first conductor pattern 10 and a part of the second conductor pattern 14 overlap in the thickness direction of the substrate 3.
  • the overlapping pattern 20 in this embodiment is configured so that a part of the first branch portion 12 and a part of the second branch portion 16 overlap in the thickness direction of the substrate 3.
  • the spacing between the first conductive wires 13, 13 is greater than the spacing between the first conductive wires 13, 13 in the first conductor pattern 10 other than the overlapping pattern 20.
  • the spacing between the first conductive wires 13, 13 constituting the overlapping pattern 20 is approximately twice the spacing between the first conductive wires 13, 13 in the first conductor pattern 10 other than the overlapping pattern 20.
  • the spacing between the second conductive wires 17, 17 constituting the overlapping pattern 20 is approximately twice the spacing between the second conductive wires 17, 17 in the second conductor pattern 14 other than the overlapping pattern 20.
  • a plurality of first conductive wires 13 and a plurality of second conductive wires 17 cross each other in a planar view.
  • the overlapping pattern 20 is configured such that, in a planar view, each of the first conductive wires 13 and each of the second conductive wires 17 are arranged at a predetermined interval (equally spaced in the illustrated example).
  • the aperture ratio of the overlapping pattern 20 is preferably configured so that the difference with the aperture ratio of the first conductor pattern 10 (or the aperture ratio of the second conductor pattern 14) located in an area other than the connection area 21 described below is 30% or less. More preferably, the difference between the aperture ratios is 10% or less.
  • the overlapping pattern 20 in this embodiment has the same aperture ratio as the first conductor pattern 10 (or the aperture ratio of the second conductor pattern 14) other than the overlapping pattern 20.
  • the overlapping pattern 20 includes a connection region 21.
  • the first conductive line 13 and the second conductive line 17 are electrically connected.
  • the overlapping pattern 20 of this embodiment includes one connection region 21.
  • connection region 21 has an area smaller than the area of the overlapping pattern 20.
  • connection region 21 multiple (four in the illustrated example) first conductive lines 13 and multiple (two in the illustrated example) second conductive lines 17 are located.
  • first conductive lines 13 intersect with one second conductive line 17 (see intersection point P shown in Figure 5).
  • intersection points P are located in the connection region 21 shown in Figure 5.
  • each second conductive line 17 located in the connection region 21 is provided with one via portion 22.
  • the via portion 22 is disposed in the connection region 21.
  • the via portion 22 is made of the same material as the conductive metal of the conductive layer 172 that constitutes each second conductive line 17.
  • the via portion 22 is integrally formed with the second conductive line 17 (conductive layer 172) located in the connection region 21.
  • the via portion 22 protrudes from the lower portion of the second conductive line 17 (conductive layer 172) toward a position corresponding to the upper surface of the first layer 5.
  • the via portion 22 is configured so that its line width is equal to or less than the line width of the second conductive line 17.
  • the via portion 22 has the same line width as the second conductive line 17 (see FIG. 8).
  • the via portion 22 is configured so that the angle between the side surface of the via portion 22 and the bottom surface of the second conductive wire 17 in a cross-sectional view is approximately a right angle (see FIG. 6). Furthermore, the angle between the side surface of the via portion 22 and the bottom surface of the second conductive wire 17 is not limited to a right angle, but may be an obtuse angle that is slightly larger than a right angle (specifically, an angle equivalent to the draft angle that occurs when the second recess 8 is formed by the imprinting method).
  • the via portion 22 is configured to be electrically connected to the first conductive wire 13.
  • the lower surface of the via portion 22 contacts the upper surface of the first conductive wire 13 located in the connection region 21.
  • the via portion 22 is electrically connected to the two first conductive wires 13, 13 at two intersections P, P where the two first conductive wires 13, 13 and one second conductive wire 17 intersect.
  • the via portion 22 is configured so that the length along the extension direction of the second conductive wire 17 (dimension L shown in FIG. 6) is equal to or greater than the sum of the pitch interval (dimension A shown in FIG. 6) between the first conductive wires 13, 13 adjacent to each other in the extension direction and the line width (dimension W shown in FIG. 6) of one first conductive wire 13.
  • one via portion 22 overlaps two first conductive wires 13, 13 adjacent to each other in the extension direction of the second conductive wire 17 in the thickness direction of the substrate 3 (see FIG. 6).
  • a second layer 6 is interposed between the first conductive wires 13 that do not overlap with the via portion 22 and each second conductive wire 17 (see FIG. 6).
  • the multilayer wiring board 1 includes a plurality of dummy patterns 30.
  • each dummy pattern 30 is simply shown by dot hatching. Note that in Figures 1 and 2, the illustration of each dummy pattern 30 is omitted.
  • the dummy pattern 30 is composed of multiple dummy conductive lines 31.
  • Each dummy conductive line 31 is thinned.
  • the line width of each dummy conductive line 31 is configured to be 15 ⁇ m or less.
  • Each dummy conductive line 31 includes a conductive metal embedded in a recess (not shown) in the first layer 5.
  • Suitable conductive metals include, for example, copper, silver, gold, or an alloy containing at least one of these metals.
  • the recess is formed on the upper surface side of the first layer 5 in an area where the first conductor pattern 10 is not located.
  • the recess has a configuration similar to that of the first recess 7.
  • the upper surface of each dummy conductive line 31 may be formed to be flush with the upper surface of the first layer 5.
  • the multiple dummy conductive lines 31 are formed in a mesh pattern in which the multiple dummy conductive lines 31 are arranged in a mesh shape.
  • the mesh pattern formed of the multiple dummy conductive lines 31 has the same configuration as the mesh pattern formed of the multiple first conductive lines 13.
  • Each dummy pattern 30 has the same aperture ratio as the first conductor pattern 10.
  • the multiple dummy conductive lines 31 are arranged at intervals from the multiple first conductive lines 13 constituting the first conductor pattern 10 adjacent to each dummy pattern 30 in a plan view. In other words, each dummy pattern 30 is not electrically conductive with the first conductor pattern 10. Although not shown, each dummy pattern 30 is insulated from each second conductor pattern 14 via the second layer 6.
  • the first conductive line 13 includes a conductive material embedded in a first recess 7 formed in the first layer 5.
  • the first recess 7 is composed of a bottom surface 7a (first bottom surface) extending in the width direction (left-right direction in the drawing), a side surface 7b (first side surface) connecting the bottom surface 7a and the opening of the first recess 7, and a corner portion 7c connecting the bottom surface 7a and the side surface 7b.
  • the first conductive wire 13 includes an adhesion layer 131 (first metal compound layer) and a conductive layer 132 (first conductive layer).
  • the adhesion layer 131 is an element for ensuring the adhesion of the conductive layer 132 to the first recess 7.
  • the adhesion layer 131 also has low reflectivity. In other words, the adhesion layer 131 has the function of making the conductive layer 132 less visible when the multilayer wiring board 1 is viewed from the side where the first layer 5 is located (the lower side of the paper in FIG. 7).
  • the adhesion layer 131 is a metal layer composed of, for example, a metal nitride containing at least one metal selected from the group consisting of Ti, Al, V, W, Ta, Si, Cr, Ag, Mo, Cu, Zn, and Ni, a metal oxide, or a metal oxynitride containing both a metal nitride and a metal oxide.
  • the adhesion layer 131 may be a single layer or a laminate of multiple layers having different compositions.
  • the adhesion layer 131 is laminated in the form of a thin film on the first recess 7 by, for example, vapor deposition or sputtering. In this embodiment, the adhesion layer 131 is formed so that the thickness L1 is approximately constant.
  • the adhesion layer 131 includes a bottom portion 131a formed on the bottom surface 7a of the first recess 7 and a side portion 131b formed on the side surface 7b of the first recess 7.
  • the bottom portion 131a and the side portion 131b are connected via a connection portion 131c formed along the corner portion 7c of the first recess 7.
  • the first recess 7 has a curved fillet formed at the corner portion 7c.
  • the corner portion 7c is formed so that the curvature gradually changes from the bottom surface 7a to the side surface 7b. That is, the bottom surface 7a and the side surface 7b are connected at the corner portion 7c so that the angle changes continuously.
  • connection portion 131c is formed along the corner portion 7c of the first recess 7, the bottom surface 131a and the side surface portion 131b are smoothly connected by the connection portion 131c.
  • the corner portion 7c may be formed so that its curvature is constant.
  • the conductive layer 132 is an element for ensuring the conductivity of the first conductive wire 13.
  • the conductive layer 132 is embedded in the first recess 7 while being layered on the adhesive layer 131.
  • the conductive layer 132 is made of a conductive metal. Suitable conductive metals include, for example, copper, silver, gold, and alloys containing at least one of these metals.
  • the conductive layer 132 is formed by, for example, deposition, sputtering, electroless plating, or electroplating.
  • the upper surface of the conductive layer 132 is formed to be flush with the upper surface of the first layer 5.
  • a blackening layer may be formed on the upper surface of the conductive layer 132.
  • the blackening layer has low reflectivity. In other words, the blackening layer has the function of making the conductive layer 132 less visible when the multilayer wiring board 1 is viewed from the side where the second layer 6 is located.
  • the second conductive wire 17 includes a conductive material embedded in a second recess 8 formed in the second layer 6.
  • the second recess 8 is composed of a bottom surface 8a (second bottom surface) extending in the width direction (left-right direction in the drawing), a side surface 8b (second side surface) connecting the bottom surface 8a and the opening of the second recess 8, and a corner portion 8c connecting the bottom surface 8a and the side surface 8b.
  • Fig. 8 illustrates the bottom surface 8a, side surface 8b, and corner portion 8c of the second recess 8.
  • the second conductive wire 17 includes an adhesion layer 171 (second metal compound layer) and a conductive layer 172 (second conductive layer).
  • the adhesion layer 171 is an element for ensuring the adhesion of the conductive layer 172 to the second recess 8.
  • the adhesion layer 171 also has low reflectivity. In other words, the adhesion layer 171 has the function of making the conductive layer 172 less visible when the multilayer wiring board 1 is viewed from the side where the first layer 5 is located (the lower side of the paper in FIG. 7).
  • the adhesion layer 171 is a metal layer composed of, for example, a metal nitride containing at least one metal selected from the group consisting of Ti, Al, V, W, Ta, Si, Cr, Ag, Mo, Cu, Zn, and Ni, a metal oxide, or a metal oxynitride containing both a metal nitride and a metal oxide.
  • the adhesion layer 171 may be a single layer or a laminate of multiple layers having different compositions.
  • the adhesion layer 171 is laminated in the form of a thin film on the second recess 8 by, for example, vapor deposition or sputtering. In this embodiment, the adhesion layer 171 is formed so that the thickness L2 is approximately constant.
  • the adhesive layer 171 includes a bottom portion 171a formed on the bottom surface 8a of the second recess 8 and a side portion 171b formed on the side surface 8b of the second recess 8.
  • the bottom portion 171a and the side portion 171b are connected via a connection portion 171c formed along the corner portion 8c of the second recess 8.
  • the second recess 8 has a curved fillet formed at the corner portion 8c.
  • the corner portion 8c is formed so that the curvature gradually changes from the bottom surface 8a to the side surface 8b. That is, the bottom surface 8a and the side surface 8b are connected so that the angle changes continuously at the corner portion 8c. Therefore, the bottom surface 8a and the side surface 8b are smoothly connected by the corner portion 8c.
  • the connection portion 171c is formed along the corner portion 8c of the second recess 8, the bottom surface portion 171a and the side surface portion 171b are smoothly connected by the connection portion 171c.
  • the conductive layer 172 is an element for ensuring the conductivity of the second conductive wire 17.
  • the conductive layer 172 is embedded in the second recess 8 while being layered on the adhesive layer 171.
  • the conductive layer 172 is made of a conductive metal. Suitable conductive metals include, for example, copper, silver, gold, and alloys containing at least one of these metals.
  • the conductive layer 172 is formed, for example, by vapor deposition, sputtering, electroless plating, or electroplating.
  • the upper surface of the conductive layer 172 is formed to be flush with the upper surface of the second layer 6.
  • a blackening layer may be formed on the upper surface of the conductive layer 172.
  • the blackening layer has low reflectivity. In other words, the blackening layer has the function of making the conductive layer 172 less visible when the multilayer wiring board 1 is viewed from the side where the second layer 6 is located.
  • groove width W1 first groove width
  • groove width W2 second groove width
  • groove width W2 is wider than groove width W1.
  • angle D1 first angle
  • angle D2 second angle
  • angle D1 first angle
  • angle D2 second angle
  • angle D2 (second angle) is the same as the angle between the bottom surface and the side surface 8b of the first layer 5. Therefore, angle D1 (first angle) may be expressed as the angle between the bottom surface and the side surface 7b of the first layer 5. Additionally, angle D2 (second angle) may be expressed as the angle between the bottom surface of the first layer 5 and the side surface 8b.
  • side 8b and side 7b may be gently curved, but as shown in FIG. 8, angles D1 and D2 may be measured using the tangents of side 8b and side 7b, respectively. Products in which angle D2 measured using this method is greater than angle D1 are also included in the present disclosure.
  • thickness L1 first thickness
  • thickness L2 second thickness
  • the recess 100 will be described with reference to Fig. 10.
  • the first recess 7 and the second recess 8 are used for the description.
  • the first recess 7 and the second recess 8 may be collectively referred to as the recess 100.
  • the area of the recess 100 located in the first layer 5 may be referred to as the "recess in the first layer.”
  • the area below the boundary line 100A shown by the dotted line in Figure 10 corresponds to the "recess in the first layer.”
  • the area of the recess 100 located in the second layer 6 may be referred to as the "recess in the second layer.”
  • the area above the boundary line 100A shown by the dotted line in FIG. 10 corresponds to the "recess in the second layer.”
  • the multilayer wiring board 1 includes the first conductive wire 13 and the second conductive wire 17. If the groove width of the first recess 7 in which the first conductive wire 13 is embedded is defined as groove width W1, and the groove width of the second recess 8 in which the second conductive wire 17 is embedded is defined as groove width W2, the groove width W2 is wider than the groove width W1. If the angle between the bottom surface 7a and the side surface 7b of the first recess 7 is defined as angle D1, and the angle between the bottom surface 8a and the side surface 8b of the second recess 8 is defined as angle D2, the angle D2 is larger than the angle D1.
  • angle D1 The angle between the bottom surface of the first layer 5 and the side surface 7b may be described as angle D1
  • the angle between the bottom surface of the first layer 5 and the side surface 8b may be described as angle D2.
  • the angle D2 is larger than the angle D1.
  • the cross-sectional area of the second conductive wire 13 is larger than that of the first conductive wire 17. Therefore, due to the general relationship between electrical resistance and cross-sectional area (i.e., a relationship based on the general formula that the electrical resistance of a conductor is inversely proportional to the cross-sectional area of the conductor), the wiring resistance of the second conductive wire 17 can be suppressed. Furthermore, by making the angle D2 larger than the angle D1, the thickness L2 of the adhesion layer 171 in the second conductive wire 17 can be made thicker than the thickness L1 of the adhesion layer 131 in the first conductive wire 13. By making the thickness L2 thicker, the second conductive wire 17 can be made less visible. Therefore, in a conductive member having a multilayer wiring structure, the wiring can be made less visible while reducing the wiring resistance.
  • the thickness L1 of the adhesive layer 131 of the first conductive wire 13 is formed to be substantially constant, but this is not limited to the embodiment.
  • the thickness L2 of the adhesive layer 171 of the second conductive wire 17 is also not limited to the embodiment.
  • the thickness L11 of the bottom surface portion 131a of the adhesive layer 131 and the thickness L12 of the bottom surface portion 131b of the adhesive layer 131 may be different.
  • the thickness L11 is thicker than the thickness L12.
  • the corner portion 8c is formed so that the thickness gradually changes from the bottom surface 8a to the side surface 8b.
  • the bottom surface 7a and the side surface 7b of the first recess 7 are connected at the corner portion 7c so that the angle changes continuously.
  • the adhesive layer 131 of the first conductive wire 13 is formed to be curved so as to protrude downward. With this configuration, it is possible to suppress a sudden change in light reflection at the connection portion 131c that connects the bottom surface portion 131a and the side surface portion 131b of the adhesive layer 131, making it possible to make the first conductive wire 13 less visible.
  • the thickness L21 of the bottom surface 171a of the adhesion layer 171 is different from the thickness L22 of the bottom surface 171b of the adhesion layer 171.
  • the thickness L21 is thicker than the thickness L22.
  • the corner portion 8c is formed so that the thickness gradually changes from the bottom surface 8a to the side surface 8b.
  • the bottom surface 8a and the side surface 8b of the second recess 8 are connected at the corner portion 8c so that the angle changes continuously.
  • the adhesion layer 171 of the second conductive wire 17 is formed to be curved so as to protrude downward. With this configuration, it is possible to suppress a sudden change in light reflection at the connection portion 171c that connects the bottom surface portion 171a and the side surface portion 171b of the adhesion layer 171, making it possible to make the second conductive wire 17 less visible.
  • the first conductor patterns 10 are formed in a mesh pattern in which a plurality of first conductive wires 13 are arranged in a mesh shape, but the present invention is not limited to this configuration.
  • the second conductor patterns 14 are not limited to a mesh pattern in which a plurality of second conductive wires 17 are arranged in a mesh shape.
  • the multiple first recesses 7 may be configured so that the groove widths W1 of each recess are different from each other.
  • the multiple first recesses 7 include a first recess 71 belonging to a first group and a first recess 72 belonging to a second group.
  • the groove width W1a of the first recess 71 and the groove width W1b of the first recess 72 are 0.3 ⁇ m or more and 50 ⁇ m or less.
  • the groove width W1b is wider than the groove width W1a.
  • the multiple second recesses 8 may be configured so that the groove widths W2 of each recess are different from each other.
  • the multiple second recesses 8 include a second recess 81 belonging to a third group and a second recess 82 belonging to a fourth group.
  • the groove width W2a of the second recess 81 and the groove width W2b of the second recess 82 are 0.8 ⁇ m or more and 52.0 ⁇ m or less.
  • the groove width W2b is wider than the groove width W2a.
  • the groove width W2b is wider than the groove width W1b.
  • the groove width W2 is wider than the groove width W1, so the second conductive wire 17 can have a wider wiring width than the first conductive wire 13. This allows the cross-sectional area of the second conductive wire 17 to be increased, thereby reducing the wiring resistance of the second conductive wire 17.
  • the multiple first recesses 7 may be configured so that each angle D1 (the angle between the bottom surface 7a and the side surface 7b of the first recess 7) is different from the others.
  • the multiple first recesses 7 include a first recess 73 belonging to the fifth group and a first recess 74 belonging to the sixth group.
  • the angle D1a of the first recess 73 and the angle D1b of the first recess 74 are greater than 90° and less than 135°.
  • the angle D1b is greater than the angle D1a.
  • the multiple second recesses 8 may be configured so that each angle D2 (the angle between the bottom surface 8a and the side surface 8b of the second recess 8) is different from the others.
  • the multiple second recesses 8 include a second recess 83 belonging to the seventh group and a second recess 84 belonging to the eighth group.
  • the angle D2a of the second recess 83 and the angle D2b of the second recess 84 are greater than 90° and less than 135°.
  • the angle D2b is greater than the angle D2a.
  • the angles D2a and D2b are greater than the angles D1a and D1b.
  • the angle D1 is smaller than the angle D2
  • the cross-sectional area of the first conductive wire 13 can be increased, and the wiring resistance of the first conductive wire 13 can be reduced.
  • the wiring width of the first conductive wire 13 is narrower than that of the second conductive wire 17, it is difficult to see. Therefore, even if the thickness of the adhesion layer 131 is reduced by reducing the angle D2, the first conductive wire 13 is difficult to see.
  • the angle D2 of the second conductive wire 17 is greater than the angle D1 of the first conductive wire 13, the thickness of the adhesion layer 171 of the second conductive wire 17 can be increased, and the visibility of the second conductive wire 17, which has a wide wiring width, can be reduced.
  • the multiple first conductive wires 13 may be configured so that the thickness L1 of each adhesion layer 131 is different from each other.
  • the multiple first conductive wires 13 include a first conductive wire 13e belonging to a ninth group and a first conductive wire 13f belonging to a tenth group.
  • the thickness L1a of the adhesion layer 171 of the first conductive wire 13e and the thickness L1b of the adhesion layer 171 of the first conductive wire 13f are greater than 3 nm and less than 150 nm.
  • the thickness L1b is greater than the thickness L1a.
  • the second conductive wires 17 may be configured so that the thickness L2 of each adhesive layer 171 is different from each other.
  • the second conductive wires 17 include a second conductive wire 17e belonging to the 11th group and a second conductive wire 17f belonging to the 12th group.
  • the thickness L2a of the adhesive layer 171 of the second conductive wire 17e and the thickness L2b of the adhesive layer 171 of the second conductive wire 17f are greater than 3 nm and smaller than 150 nm.
  • the thickness L2b is thicker than the thickness L2a.
  • the thicknesses L2a and L2b are thicker than the thicknesses L1a and L1b.
  • the thickness L1 is smaller than the thickness L2
  • the cross-sectional area of the first conductive wire 13 can be increased, and the wiring resistance of the first conductive wire 13 can be reduced.
  • the wiring width of the first conductive wire 13 is narrower than that of the second conductive wire 17, the visibility is low. Therefore, even if the thickness of the adhesion layer 131 is reduced, the first conductive line 13 is less visible.
  • the thickness of the adhesion layer 171 of the second conductive line 17 can be increased, so the visibility of the second conductive line 17, which has a wide wiring width, can be reduced.
  • the dummy patterns 30 are arranged on the first layer 5, but this is not limited to the above. In other words, the dummy patterns 30 may be arranged on the second layer 6.
  • the multilayer wiring substrate 1 according to the embodiment of the present disclosure can be widely applied to various technical fields such as touch sensors, liquid crystal display devices, organic electroluminescence display devices (OLEDs), micro LED display devices, solar cell devices, heater devices, antenna devices, and electromagnetic wave shielding sheets.
  • OLEDs organic electroluminescence display devices
  • micro LED display devices solar cell devices
  • heater devices heater devices
  • antenna devices electromagnetic wave shielding sheets.
  • the conductive member (multilayer wiring board 1) of the first aspect of the present disclosure comprises a substrate (3) having transparency and light transmissivity, which includes a first layer (5) and a second layer (6) provided above the first layer (5), a first conductive wire (13) arranged in a recess (100) provided in the substrate (3), and a second conductive wire (17) located above the first conductive wire (13) and arranged in the recess (100) of the substrate (3).
  • the first conductive wire (13) includes a first metal compound layer (adhesion layer 131) made of a metal compound, and a first conductive layer (132) made of a conductive metal formed on the first metal compound layer (adhesion layer 131), and the first metal compound layer (adhesion layer 131) contacts a first side surface (7b) which is the side surface of the recess (100) in the first layer (5).
  • the second conductive wire (17) includes a second metal compound layer (adhesion layer 171) made of a metal compound, and a second conductive layer (172) made of a conductive metal formed on the second metal compound layer (adhesion layer 171), and the second metal compound layer (adhesion layer 171) contacts the second side surface (8b), which is the side surface of the recess (100) in the second layer (6).
  • the second groove width (W2) which is the groove width of the recess (100) in the second layer (6), is wider than the first groove width (W1), which is the groove width of the recess (100) in the first layer (5).
  • the second angle (D2) between the second side (8b) and the bottom surface of the first layer (5) is greater than the first angle (D1) between the first side (7b) and the bottom surface of the first layer (5), and the second thickness (L2) of the second metal compound layer (adhesion layer 171) at the portion in contact with the lower end of the second conductive layer (172) is greater than the first thickness (L1) of the first metal compound layer (adhesion layer 131) at the portion in contact with the lower end of the first conductive layer (132).
  • the thickness of a portion of the second metal compound layer (adhesion layer 171) changes continuously as it moves upward.
  • the first groove width (W1) is 0.3 ⁇ m or more and 50 ⁇ m or less.
  • a plurality of recesses (100) are provided in the board (3), and the first groove width (W1) of one of the plurality of recesses (100) and the first groove width (W1) of another of the plurality of recesses (100) may be different in width.
  • the second groove width (W2) is preferably 0.8 ⁇ m or more and 52.0 ⁇ m or less.
  • the first angle (D1) is greater than 90° and less than 135°.
  • a substrate (3) is provided with a plurality of recesses (100), and the first angle (D1) of one of the plurality of recesses (100) and the first angle (D1) of another of the plurality of recesses (100) are different in size.
  • the second angle (D2) is greater than 90° and less than 135°.
  • the first thickness (L1) is greater than 3 nm and less than 150 nm.
  • the conductive member (multilayer wiring board 1) of the tenth aspect of the present disclosure includes a plurality of first conductive wires (13), and the thickness (L1) of one of the plurality of first conductive wires (13) is different from the thickness (L1) of another of the plurality of first conductive wires (13).
  • the second thickness (L2) is preferably greater than 3 nm and less than 150 nm.
  • the conductive member (multilayer wiring board 1) of the twelfth aspect of the present disclosure includes a plurality of second conductive wires (17), and the thickness (L2) of one of the plurality of second conductive wires (17) is different from the thickness (L2) of another of the plurality of second conductive wires (17).
  • the substrate (3) further includes a film substrate (4) disposed under the first layer (5).
  • the film base material (4) of the board (3) is formed from a resin material that is flexible and optically transparent.
  • the first layer (5) of the substrate (3) and the second layer (6) of the substrate (3) are formed of a resin material that is insulating and optically transparent.
  • the first metal compound layer (adhesion layer 131) of the first conductive line (13) is curved and formed so as to protrude downward.
  • the second metal compound layer (adhesion layer 171) of the second conductive line (17) is curved and formed so as to protrude downward.
  • This disclosure can be used industrially as a conductive material.

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Human Computer Interaction (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Structure Of Printed Boards (AREA)

Abstract

In the present invention, a substrate (3) is provided with a first conductive wire (13) and a second conductive wire (17). The first conductive wire (13) is provided with a close-contact layer (131) and a conductive layer (132) embedded in a recess (100). The second conductive wire (17) is provided with a close-contact layer (171) and a conductive layer (172) embedded in a second recess (8). The groove width (W2) of the second recess (8) is wider than the groove width (W1) of a first recess (7). The angle (D2) formed by the bottom surface of the first layer (5) and a lateral surface (8b) thereof is greater than the angle (D1) formed by the bottom surface of the first layer (5) and a lateral surface (7b) thereof. The thickness (L2) of the close-contact layer (171) is greater than the thickness (L1) of the close-contact layer (131).

Description

導電部材Conductive material

　本開示は、多層配線構造を有する導電部材に関する。 This disclosure relates to a conductive member having a multilayer wiring structure.

　従来から、タッチパネル等に使用される導電部材が知られている。導電部材には、複数の配線層が積層された多層配線構造を有するものがある。 Conductive materials used in touch panels and the like have been known for some time. Some conductive materials have a multilayer wiring structure in which multiple wiring layers are stacked.

　例えば、特許文献１の導電性基板は、第１の導電性基板および第２の導電性基板を備える。第１の導電性基板上および第２の導電性基板上には、それぞれ、複数の電極部（配線）が形成されている。第１の導電性基板および第２の導電性基板のそれぞれに形成された電極部が互いに対向する状態で、第１の導電性基板および第２の導電性基板は、接着層により貼り合わされている。特許文献１では、各導電性基板と電極部との間に、金属酸化物で構成される密着性改善層を介在させることで、電極部の剥離が防止される。 For example, the conductive substrate of Patent Document 1 includes a first conductive substrate and a second conductive substrate. A plurality of electrode portions (wiring) are formed on each of the first conductive substrate and the second conductive substrate. The first conductive substrate and the second conductive substrate are bonded together by an adhesive layer with the electrode portions formed on the first conductive substrate and the second conductive substrate facing each other. In Patent Document 1, peeling of the electrode portions is prevented by interposing an adhesion improving layer made of a metal oxide between each conductive substrate and the electrode portions.

特開２０１３－２２８７８２号公報JP 2013-228782 A

　上述したように、特許文献１では、導電性基板と電極部との間に、金属酸化物で構成される密着性改善層が形成されている。すなわち、電極部の側面に密着性改善層が形成されている。特許文献１において、電極部の剥離をさらに防止するために、電極部の側面に更に密着性改善層を形成することが考えられる。このように、電極部の底面および側面に密着性改善層を形成することで、電極部の剥離を防止するとともに、電極部を視認されにくくすることができる。 As described above, in Patent Document 1, an adhesion improvement layer made of a metal oxide is formed between the conductive substrate and the electrode part. That is, an adhesion improvement layer is formed on the side surface of the electrode part. In Patent Document 1, in order to further prevent the electrode part from peeling off, it is conceivable to further form an adhesion improvement layer on the side surface of the electrode part. In this way, by forming an adhesion improvement layer on the bottom surface and side surface of the electrode part, it is possible to prevent the electrode part from peeling off and to make the electrode part less visible.

　特許文献１では、電極部の断面形状が、略方形であるため、電極部の側面に形成される密着性改善層の厚みが薄くなる。密着性改善層がスパッタリング法等で形成されると、電極部の側面に形成される密着性改善層の厚みが薄くなれば、電極部の底面に形成される密着性改善層の厚みも薄くなる。このため、密着性改善層の全体の厚みが薄くなり、電極部が視認されやすくなる。特に、電極部の配線抵抗を低減させるため、当該電極部の配線幅を広げた場合、当該電極部の配線幅が広くなることから、当該電極部が視認されやすくなる。 In Patent Document 1, the cross-sectional shape of the electrode part is approximately rectangular, so the thickness of the adhesion improvement layer formed on the side of the electrode part is thin. When the adhesion improvement layer is formed by a method such as sputtering, if the thickness of the adhesion improvement layer formed on the side of the electrode part is thin, the thickness of the adhesion improvement layer formed on the bottom surface of the electrode part is also thin. As a result, the overall thickness of the adhesion improvement layer is thin, making the electrode part easier to see. In particular, if the wiring width of the electrode part is widened to reduce the wiring resistance of the electrode part, the wider wiring width of the electrode part makes the electrode part easier to see.

　本開示の一態様の導電部材は、第１層と前記第１層の上方に設けられた第２層とを含み、透明性および光透過性を有する基板と、前記基板に設けられた凹部に配置された第１導電線と、前記第１導電線の上に位置し、前記基板の前記凹部に配置された第２導電線と、を備え、前記第１導電線は、金属化合物からなる第１金属化合物層と、前記第１金属化合物層の上に形成され、導電性の金属からなる第１導電層と、を含み、前記第１金属化合物層は、前記第１層における前記凹部の側面である第１側面に接し、前記第２導電線は、金属化合物からなる第２金属化合物層と、前記第２金属化合物層の上に形成され、導電性の金属からなる第２導電層と、を含み、前記第２金属化合物層は、前記第２層における前記凹部の側面である第２側面に接し、前記第２層における前記凹部の溝幅である第２溝幅は、前記第１層における前記凹部の溝幅である第１溝幅よりも広く、前記第２側面と前記第１層の底面とのなす角度である第２角度は、前記第１側面と前記第１層の前記底面とのなす角度である第１角度よりも大きく、前記第２導電層の下端に接する部分における前記第２金属化合物層の厚みである第２厚みは、前記第１導電層の下端に接する部分における前記第１金属化合物層の厚みである第１厚みよりも厚い。 A conductive member according to one embodiment of the present disclosure includes a substrate having transparency and light transmissivity, a first conductive wire disposed in a recess provided in the substrate, and a second conductive wire located on the first conductive wire and disposed in the recess of the substrate, the first conductive wire includes a first metal compound layer made of a metal compound, and a first conductive layer formed on the first metal compound layer and made of a conductive metal, the first metal compound layer contacting a first side surface which is a side surface of the recess in the first layer, the second conductive wire includes a second metal compound layer made of a metal compound, and a second conductive layer formed on the second metal compound layer. and a second conductive layer made of a conductive metal, the second metal compound layer being in contact with a second side surface that is a side surface of the recess in the second layer, the second groove width that is the groove width of the recess in the second layer being wider than the first groove width that is the groove width of the recess in the first layer, the second angle that is the angle between the second side surface and the bottom surface of the first layer being larger than the first angle that is the angle between the first side surface and the bottom surface of the first layer, and the second thickness that is the thickness of the second metal compound layer at the portion in contact with the lower end of the second conductive layer being thicker than the first thickness that is the thickness of the first metal compound layer at the portion in contact with the lower end of the first conductive layer.

　本開示の多層配線構造を有する導電部材では、配線抵抗を低減しつつ、配線を視認されにくくすることができる。 The conductive member having the multilayer wiring structure disclosed herein can reduce wiring resistance while making the wiring less visible.

図１は、本開示の実施形態に係る多層配線基板の全体を示した斜視図である。FIG. 1 is a perspective view showing an entire multilayer wiring board according to an embodiment of the present disclosure. 図２は、本開示の実施形態に係る多層配線基板の全体を示した平面図である。FIG. 2 is a plan view showing the entire multilayer wiring board according to the embodiment of the present disclosure. 図３は、図２のIII部を拡大して示した部分拡大平面図である。FIG. 3 is a partially enlarged plan view showing a portion III in FIG. 図４は、図３のIV部を拡大して示した部分拡大平面図である。FIG. 4 is a partially enlarged plan view showing a portion IV in FIG. 図５は、図４に示した接続領域およびその周辺を拡大して示した部分拡大平面図である。FIG. 5 is a partially enlarged plan view showing the connection region and its periphery shown in FIG. 図６は、図５のVI－VI線断面図である。FIG. 6 is a cross-sectional view taken along line VI-VI in FIG. 図７は、第１導電線および第２導電線を重ねて配置したときの概略断面図である。FIG. 7 is a schematic cross-sectional view of a first conductive wire and a second conductive wire arranged to overlap each other. 図８は、図７における第１凹部および第２凹部の断面状態を概略的に示す断面図である。FIG. 8 is a cross-sectional view that illustrates a schematic cross-sectional state of the first recess and the second recess in FIG. 図９は、実施形態の変形例における第１導電線および第２導電線を重ねて配置したときの概略断面図である。FIG. 9 is a schematic cross-sectional view of a modification of the embodiment in which a first conductive wire and a second conductive wire are arranged to overlap each other. 図１０は、図７における第１凹部および第２凹部の断面状態を概略的に示す断面図である。FIG. 10 is a cross-sectional view that illustrates a schematic cross-sectional state of the first recess and the second recess in FIG.

　以下、本開示の実施形態を図面に基づいて詳細に説明する。以下の実施形態の説明は、本質的に例示に過ぎず、本開示、その適用物或いはその用途を制限することを意図するものではない。 Below, embodiments of the present disclosure are described in detail with reference to the drawings. The following description of the embodiments is merely exemplary in nature and is not intended to limit the present disclosure, its applications, or its uses.

　図１および図２は、本開示の実施形態に係る多層配線基板１（導電部材）の全体構成を示している。この実施形態では、インプリント工法により形成された多層配線基板１を例示している。多層配線基板１には、複数の実装素子２が設けられている。実装素子２としては、例えばＬＥＤ素子またはダイオードが挙げられる。複数の実装素子２は、後述する基板３の上側（後述する第１層５の上面側）に配置されている。 FIGS. 1 and 2 show the overall configuration of a multilayer wiring board 1 (conductive member) according to an embodiment of the present disclosure. In this embodiment, a multilayer wiring board 1 formed by an imprinting method is illustrated. The multilayer wiring board 1 is provided with a plurality of mounting elements 2. Examples of the mounting elements 2 include LED elements or diodes. The plurality of mounting elements 2 are disposed on the upper side of a substrate 3 (the upper surface side of a first layer 5 (described later)).

　なお、この実施形態では、説明の便宜上、図２における紙面の左側から右側に向かう方向を「Ｘ方向」とする一方、図２における紙面の下側から上側に向かう方向を「Ｙ方向」として定めるものとする。 In this embodiment, for ease of explanation, the direction from the left side to the right side of the paper in FIG. 2 is defined as the "X direction," while the direction from the bottom to the top of the paper in FIG. 2 is defined as the "Y direction."

　（基板）
　図１および図２に示すように、多層配線基板１は、基板３を備えている。基板３は、透明性および光透過性を有している。なお、この実施形態では、基板３の厚み方向において、後述するフィルム基材４が位置する側を基板３の「下側」と定める一方、後述する第２層６が位置する側を基板３の「上側」と定めるものとする。 (substrate)
1 and 2, the multilayer wiring board 1 includes a substrate 3. The substrate 3 is transparent and light-transmitting. In this embodiment, in the thickness direction of the substrate 3, the side on which a film base 4 (described later) is located is defined as the "lower side" of the substrate 3, while the side on which a second layer 6 (described later) is located is defined as the "upper side" of the substrate 3.

　基板３は、フィルム基材４を含む。フィルム基材４は、少なくとも可撓性および光透過性を有する樹脂材料からなる。好ましくは、フィルム基材４は、８０％以上の光透過率を有する。フィルム基材４は、例えば２５μｍ～２００μｍである。また、フィルム基材４は、透明性を有していてもよい。 The substrate 3 includes a film substrate 4. The film substrate 4 is made of a resin material that is at least flexible and light-transmitting. Preferably, the film substrate 4 has a light transmittance of 80% or more. The film substrate 4 is, for example, 25 μm to 200 μm. The film substrate 4 may also be transparent.

　上記樹脂材料としては、例えば、ＰＥＴ（ポリエチレンテレフタレート）、ポリカーボネート、ＣＯＰ（シクロオレフィンポリマー）、ＣＯＣ（シクロオレフィンコポリマー）のような樹脂材料が挙げられる。 Examples of the resin material include PET (polyethylene terephthalate), polycarbonate, COP (cycloolefin polymer), and COC (cycloolefin copolymer).

　図６に示すように、基板３は、第１層５および第２層６を含む。第１層５および第２層６の各々は、絶縁性および光透過性を有する樹脂材料により構成されている。この樹脂材料は、例えば熱硬化性樹脂または紫外線硬化性樹脂材料である。第１層５および第２層６の各々の厚みは、例えば１μｍ～６μｍである。 As shown in FIG. 6, the substrate 3 includes a first layer 5 and a second layer 6. Each of the first layer 5 and the second layer 6 is made of a resin material that is insulating and optically transparent. This resin material is, for example, a thermosetting resin or an ultraviolet-curing resin material. The thickness of each of the first layer 5 and the second layer 6 is, for example, 1 μm to 6 μm.

　第１層５は、後述する第１導体パターン１０を配置するための層である。第１層５は、フィルム基材４の上側に積層配置されている。第１層５の上面は、後述の各第１導電線１３を構成する導電性金属が後述の第１凹部７に埋設された状態で、平坦状または中央部分が少し凹んだ形状になるように形成されている。 The first layer 5 is a layer for arranging the first conductor pattern 10 described below. The first layer 5 is laminated on the upper side of the film substrate 4. The upper surface of the first layer 5 is formed so as to be flat or have a slightly recessed central portion, with the conductive metal constituting each of the first conductive lines 13 described below embedded in the first recesses 7 described below.

　第２層６は、後述する第２導体パターン１４を配置するための層である。第２層６は、第１層５の上側に積層配置されている。第２層６の上面は、後述の各第２導電線１７を構成する導電性金属が後述の第２凹部８に埋設された状態で、平坦状または中央部分が少し凹んだ形状になるように形成されている。 The second layer 6 is a layer for arranging the second conductor pattern 14 described below. The second layer 6 is arranged on the upper side of the first layer 5. The upper surface of the second layer 6 is formed so as to be flat or have a slightly recessed shape in the center, with the conductive metal constituting each second conductive line 17 described below embedded in the second recess 8 described below.

　図６に示すように、第１層５には、第１層５の上面から下方に向かって凹陥した有底状の第１凹部７が複数設けられている。複数の第１凹部７は、第１層５の上面において後述する所定パターンを形成するように線状に延びている。 As shown in FIG. 6, the first layer 5 has a plurality of bottomed first recesses 7 that are recessed downward from the top surface of the first layer 5. The first recesses 7 extend linearly on the top surface of the first layer 5 to form a predetermined pattern, which will be described later.

　第１凹部７の溝深さは、例えば０．５μｍ以上５μｍ以下に設定される。 The groove depth of the first recess 7 is set to, for example, 0.5 μm or more and 5 μm or less.

　第２層６には、第１層５と同様に、第２層６の上面から下方に向かって凹陥した第２凹部８が複数設けられている。複数の第２凹部８は、第２層６の上面において後述する所定パターンを形成するように線状に延びている。なお、第２凹部８は、後述のビア部２２が形成される部分のみが、基板３の厚み方向において貫通した状態となるように構成されている。 Similar to the first layer 5, the second layer 6 has a plurality of second recesses 8 that are recessed downward from the upper surface of the second layer 6. The second recesses 8 extend linearly to form a predetermined pattern, which will be described later, on the upper surface of the second layer 6. The second recesses 8 are configured so that only the portions where the via portions 22, which will be described later, are formed penetrate the substrate 3 in the thickness direction.

　第２凹部８の溝深さは、例えば０．５μｍ以上５μｍ以下に設定される。 The groove depth of the second recess 8 is set to, for example, 0.5 μm or more and 5 μm or less.

　（第１導体パターン）
　図１～図３に示すように、多層配線基板１は、複数の第１導体パターン１０を備えている。複数の第１導体パターン１０は、平面視においてＸ方向に互いに間隔（図示例では等間隔）をあけて配置されている。第１導体パターン１０を構成する後述の各第１導電線１３は、第１層５に配置されている（図６参照）。なお、図１～図３では、図示の便宜上、各第１導体パターン１０をドットハッチングにより簡略的に図示している。 (First Conductive Pattern)
As shown in Figures 1 to 3, the multilayer wiring board 1 includes a plurality of first conductor patterns 10. The plurality of first conductor patterns 10 are arranged at intervals (equally spaced apart in the illustrated example) in the X direction in a plan view. Each of the first conductive lines 13 (described below) constituting the first conductor pattern 10 is arranged on the first layer 5 (see Figure 6). Note that, for convenience of illustration, each of the first conductor patterns 10 is simply illustrated by dot hatching in Figures 1 to 3.

　各第１導体パターン１０は、第１本体部１１と、複数（図示例では４つ）の第１分岐部１２と、を有する。第１本体部１１および各第１分岐部１２は、平面視において略帯状に形成されている。第１本体部１１は、平面視においてＹ方向に沿って略帯状に延びている。各第１分岐部１２は、第１本体部１１の中途部から分岐している。具体的に、各第１分岐部１２は、第１本体部１１の中途部からＸ方向と反対方向（図２および図３の紙面左側に向かう方向）に向かって延びるように構成されている。 Each first conductor pattern 10 has a first main body 11 and multiple (four in the illustrated example) first branch portions 12. The first main body 11 and each first branch portion 12 are formed in a generally strip-like shape in a plan view. The first main body 11 extends in a generally strip-like shape along the Y direction in a plan view. Each first branch portion 12 branches off from a midway point of the first main body 11. Specifically, each first branch portion 12 is configured to extend from a midway point of the first main body 11 in a direction opposite to the X direction (towards the left side of the paper in Figures 2 and 3).

　図４に示すように、第１導体パターン１０は、複数の第１導電線１３により構成されている。各第１導電線１３は、細線化されている。具体的に、各第１導電線１３の線幅は、１５μｍ以下となるように構成されている。 As shown in FIG. 4, the first conductor pattern 10 is composed of a plurality of first conductive wires 13. Each of the first conductive wires 13 is thinned. Specifically, the line width of each of the first conductive wires 13 is configured to be 15 μm or less.

　複数の第１導電線１３は、第１層５の表面において所定パターンとなるように配置されている。図４では、上記所定パターンの一例として、複数の第１導電線１３をメッシュ状に配置したメッシュパターンを示している。 The multiple first conductive wires 13 are arranged in a predetermined pattern on the surface of the first layer 5. Figure 4 shows a mesh pattern in which the multiple first conductive wires 13 are arranged in a mesh shape as an example of the predetermined pattern.

　複数の第１導電線１３からなるメッシュパターン（第１導体パターン１０）は、複数の第１導電線１３が互いに交差しかつ複数の第１導電線１３が所定の間隔（図示例では等間隔）に配置された状態となるように構成されている。メッシュパターンを構成する各第１導電線１３は、Ｘ方向およびＹ方向の双方に対して斜め方向に延びている。 The mesh pattern (first conductor pattern 10) consisting of a plurality of first conductive wires 13 is configured so that the plurality of first conductive wires 13 cross each other and are arranged at a predetermined interval (equally spaced intervals in the illustrated example). Each of the first conductive wires 13 constituting the mesh pattern extends diagonally with respect to both the X direction and the Y direction.

　（第２導体パターン）
　図１～図３に示すように、多層配線基板１は、複数の第２導体パターン１４を備えている。複数の第２導体パターン１４は、平面視においてＹ方向に互いに間隔（図示例では等間隔）をあけて配置されている。なお、図１～図３では、図示の便宜上、第２導体パターン１４をドットハッチングにより簡略的に図示している。 (Second Conductive Pattern)
1 to 3, the multilayer wiring board 1 includes a plurality of second conductor patterns 14. The plurality of second conductor patterns 14 are arranged at intervals (equally spaced in the illustrated example) from one another in the Y direction in a plan view. Note that, for convenience of illustration, the second conductor patterns 14 are simply illustrated by dot hatching in FIGS. 1 to 3.

　第２導体パターン１４を構成する後述の各第２導電線１７は、第２層６に配置されている（図６参照）。すなわち、第２導体パターン１４は、基板３の厚み方向において第１導体パターン１０と異なる位置に配置されている。 Each second conductive line 17 (described later) constituting the second conductor pattern 14 is disposed on the second layer 6 (see FIG. 6). In other words, the second conductor pattern 14 is disposed at a different position from the first conductor pattern 10 in the thickness direction of the substrate 3.

　各第２導体パターン１４は、第２本体部１５と、複数（図示例では４つ）の第２分岐部１６と、を有している。第２本体部１５および各第２分岐部１６は、平面視において略帯状に形成されている。第２本体部１５は、平面視においてＸ方向に沿って略帯状に延びている。各第２分岐部１６は、第２本体部１５の中途部から分岐している。具体的に、各第２分岐部１６は、第２本体部１５の中途部からＹ方向と反対方向（図２の紙面下側）に向かって延びている。 Each second conductor pattern 14 has a second main body 15 and multiple (four in the illustrated example) second branch portions 16. The second main body 15 and each second branch portion 16 are formed in a generally strip-like shape in a plan view. The second main body 15 extends in a generally strip-like shape along the X direction in a plan view. Each second branch portion 16 branches off from a midway point of the second main body 15. Specifically, each second branch portion 16 extends from a midway point of the second main body 15 in a direction opposite to the Y direction (toward the bottom of the paper in FIG. 2).

　図４に示すように、第２導体パターン１４は、複数の第２導電線１７により構成されている。各第２導電線１７は、細線化されている。具体的に、各第２導電線１７の線幅は、１５μｍ以下となるように構成されている。なお、図４では、第１導電線１３と第２導電線１７と区別して示すために、第２導電線１７を、第１導電線１３よりも太い線を用いて図示している。 As shown in FIG. 4, the second conductor pattern 14 is composed of a plurality of second conductive wires 17. Each second conductive wire 17 is thinned. Specifically, each second conductive wire 17 is configured to have a line width of 15 μm or less. Note that in FIG. 4, in order to distinguish between the first conductive wires 13 and the second conductive wires 17, the second conductive wires 17 are illustrated using lines thicker than the first conductive wires 13.

　図４および図６に示すように、複数の第２導電線１７は、第２層６の表面において所定パターンとなるように配置されている。なお、図４では、上記所定パターンの一例として、複数の第２導電線１７をメッシュ状に配置したメッシュパターンを示している。 As shown in Figures 4 and 6, the second conductive wires 17 are arranged in a predetermined pattern on the surface of the second layer 6. Note that Figure 4 shows a mesh pattern in which the second conductive wires 17 are arranged in a mesh shape as an example of the predetermined pattern.

　図４に示すように、複数の第２導電線１７からなるメッシュパターン（第２導体パターン１４）は、複数の第２導電線１７が互いに交差しかつ複数の第２導電線１７が所定の間隔（図示例では等間隔）に配置された状態となるように構成されている。メッシュパターンを構成する各第２導電線１７は、Ｘ方向およびＹ方向の双方に対して斜め方向に延びている。なお、この実施形態において、複数の第２導電線１７からなるメッシュパターンは、複数の第１導電線１３からなるメッシュパターン（第１導体パターン１０）と同じ開口率を有している。 As shown in FIG. 4, the mesh pattern (second conductor pattern 14) consisting of a plurality of second conductive wires 17 is configured so that the plurality of second conductive wires 17 cross each other and are arranged at a predetermined interval (equally spaced in the illustrated example). Each of the second conductive wires 17 constituting the mesh pattern extends diagonally with respect to both the X direction and the Y direction. In this embodiment, the mesh pattern consisting of a plurality of second conductive wires 17 has the same aperture ratio as the mesh pattern (first conductor pattern 10) consisting of a plurality of first conductive wires 13.

　ここで、複数の第１導電線１３が第１導体パターン１０に占める比率、あるいは、複数の第２導電線１７が第２導体パターン１４に占める比率を「影率」という。そして、第１導体パターン１０の全体面積（１００％）から上記影率を差し引いた割合が、第１導体パターン１０の開口率に相当する。これと同様に、第２導体パターン１４の全体面積（１００％）から上記影率を差し引いた割合が、第２導体パターン１４の開口率に相当する。 Here, the ratio of the multiple first conductive wires 13 to the first conductor pattern 10, or the ratio of the multiple second conductive wires 17 to the second conductor pattern 14, is called the "shadow ratio." The ratio obtained by subtracting the above shadow ratio from the total area (100%) of the first conductor pattern 10 corresponds to the aperture ratio of the first conductor pattern 10. Similarly, the ratio obtained by subtracting the above shadow ratio from the total area (100%) of the second conductor pattern 14 corresponds to the aperture ratio of the second conductor pattern 14.

　（重なりパターン）
　図３および図４に示すように、第１導体パターン１０および第２導体パターン１４には、重なりパターン２０が設けられている。重なりパターン２０は、第１導体パターン１０の一部と第２導体パターン１４の一部とが基板３の厚み方向に重なるように構成されている。この実施形態の重なりパターン２０は、第１分岐部１２の一部と、第２分岐部１６の一部とが基板３の厚み方向に重なるように構成されている。 (Overlapping pattern)
3 and 4 , the first conductor pattern 10 and the second conductor pattern 14 are provided with an overlapping pattern 20. The overlapping pattern 20 is configured so that a part of the first conductor pattern 10 and a part of the second conductor pattern 14 overlap in the thickness direction of the substrate 3. The overlapping pattern 20 in this embodiment is configured so that a part of the first branch portion 12 and a part of the second branch portion 16 overlap in the thickness direction of the substrate 3.

　図４および図５に示すように、重なりパターン２０（図３参照）では、第１導電線１３，１３同士の間隔が、重なりパターン２０以外の、第１導体パターン１０における第１導電線１３，１３同士の間隔よりも大きくなっている。この実施形態において、重なりパターン２０を構成する第１導電線１３，１３同士の間隔は、重なりパターン２０以外の、第１導体パターン１０における第１導電線１３，１３同士の間隔の約２倍となっている。これと同様に、重なりパターン２０を構成する第２導電線１７，１７同士の間隔は、重なりパターン２０以外の、第２導体パターン１４における第２導電線１７，１７同士の間隔の約２倍となっている。 As shown in Figures 4 and 5, in the overlapping pattern 20 (see Figure 3), the spacing between the first conductive wires 13, 13 is greater than the spacing between the first conductive wires 13, 13 in the first conductor pattern 10 other than the overlapping pattern 20. In this embodiment, the spacing between the first conductive wires 13, 13 constituting the overlapping pattern 20 is approximately twice the spacing between the first conductive wires 13, 13 in the first conductor pattern 10 other than the overlapping pattern 20. Similarly, the spacing between the second conductive wires 17, 17 constituting the overlapping pattern 20 is approximately twice the spacing between the second conductive wires 17, 17 in the second conductor pattern 14 other than the overlapping pattern 20.

　重なりパターン２０では、平面視において、複数の第１導電線１３と複数の第２導電線１７とが互いに交差している。そして、重なりパターン２０は、平面視において、各第１導電線１３と各第２導電線１７とが所定の間隔（図示例では等間隔）に配置された状態となるように構成されている。 In the overlapping pattern 20, a plurality of first conductive wires 13 and a plurality of second conductive wires 17 cross each other in a planar view. The overlapping pattern 20 is configured such that, in a planar view, each of the first conductive wires 13 and each of the second conductive wires 17 are arranged at a predetermined interval (equally spaced in the illustrated example).

　重なりパターン２０の開口率は、後述する接続領域２１以外の領域に位置する第１導体パターン１０の開口率（または第２導体パターン１４の開口率）との差が３０％以下となるように構成されるのが好ましい。より好ましくは、両者の開口率の差は１０％以下である。この実施形態の重なりパターン２０は、重なりパターン２０以外の、第１導体パターン１０が有する開口率（または第２導体パターン１４が有する開口率）と同じ開口率を有する。 The aperture ratio of the overlapping pattern 20 is preferably configured so that the difference with the aperture ratio of the first conductor pattern 10 (or the aperture ratio of the second conductor pattern 14) located in an area other than the connection area 21 described below is 30% or less. More preferably, the difference between the aperture ratios is 10% or less. The overlapping pattern 20 in this embodiment has the same aperture ratio as the first conductor pattern 10 (or the aperture ratio of the second conductor pattern 14) other than the overlapping pattern 20.

　（接続領域）
　図４および図５に示すように、重なりパターン２０は、接続領域２１を含む。接続領域２１では、第１導電線１３と第２導電線１７とが電気的に接続されている。なお、この実施形態の重なりパターン２０は、１つの接続領域２１を含む。 (Connection Area)
4 and 5 , the overlapping pattern 20 includes a connection region 21. In the connection region 21, the first conductive line 13 and the second conductive line 17 are electrically connected. Note that the overlapping pattern 20 of this embodiment includes one connection region 21.

　この実施形態において、接続領域２１は、重なりパターン２０が有する領域よりも小さい領域を有する。接続領域２１には、複数（図示例では４つ）の第１導電線１３と、複数（図示例では２つ）の第２導電線１７とが位置している。接続領域２１では、１つの第２導電線１７に対して複数の第１導電線１３が交差している（図５に示した交点Ｐを参照）。図５に示した接続領域２１には、４箇所の交点Ｐが位置している。 In this embodiment, the connection region 21 has an area smaller than the area of the overlapping pattern 20. In the connection region 21, multiple (four in the illustrated example) first conductive lines 13 and multiple (two in the illustrated example) second conductive lines 17 are located. In the connection region 21, multiple first conductive lines 13 intersect with one second conductive line 17 (see intersection point P shown in Figure 5). Four intersection points P are located in the connection region 21 shown in Figure 5.

　（ビア部）
　図６に示すように、接続領域２１に位置する各第２導電線１７には、１つのビア部２２が設けられている。ビア部２２は、接続領域２１に配置されている。ビア部２２は、各第２導電線１７を構成する導電層１７２の導電性金属と同じ材料からなる。 (Via section)
6 , each second conductive line 17 located in the connection region 21 is provided with one via portion 22. The via portion 22 is disposed in the connection region 21. The via portion 22 is made of the same material as the conductive metal of the conductive layer 172 that constitutes each second conductive line 17.

　ビア部２２は、接続領域２１に位置する第２導電線１７（導電層１７２）と一体に形成されている。この実施形態のビア部２２は、第２導電線１７（導電層１７２）の下部から第１層５の上面に対応する位置に向かって突出している。 The via portion 22 is integrally formed with the second conductive line 17 (conductive layer 172) located in the connection region 21. In this embodiment, the via portion 22 protrudes from the lower portion of the second conductive line 17 (conductive layer 172) toward a position corresponding to the upper surface of the first layer 5.

　ビア部２２は、その線幅が第２導電線１７の線幅以下の線幅となるように構成されている。この実施形態のビア部２２は、第２導電線１７の線幅と同じ線幅を有している（図８参照）。 The via portion 22 is configured so that its line width is equal to or less than the line width of the second conductive line 17. In this embodiment, the via portion 22 has the same line width as the second conductive line 17 (see FIG. 8).

　この実施形態において、ビア部２２は、断面視においてビア部２２の側面と第２導電線１７の下面とのなす角度が略直角となるように構成されている（図６参照）。また、ビア部２２の側面と第２導電線１７の下面とのなす角度は、直角に限られず、直角よりもやや大きい鈍角（具体的には、インプリント工法により第２凹部８を形成した際に生じる抜き勾配に相当する角度）であってもよい。 In this embodiment, the via portion 22 is configured so that the angle between the side surface of the via portion 22 and the bottom surface of the second conductive wire 17 in a cross-sectional view is approximately a right angle (see FIG. 6). Furthermore, the angle between the side surface of the via portion 22 and the bottom surface of the second conductive wire 17 is not limited to a right angle, but may be an obtuse angle that is slightly larger than a right angle (specifically, an angle equivalent to the draft angle that occurs when the second recess 8 is formed by the imprinting method).

　接続領域２１において第１導電線１３と第２導電線１７とが交差する交点（図５に示した交点Ｐ）では、ビア部２２が第１導電線１３と電気的に接続されるように構成されている。この実施形態において、交点Ｐでは、ビア部２２の下面が、接続領域２１に位置する第１導電線１３の上面と接している。 At the intersection (intersection P shown in FIG. 5) where the first conductive wire 13 and the second conductive wire 17 intersect in the connection region 21, the via portion 22 is configured to be electrically connected to the first conductive wire 13. In this embodiment, at the intersection P, the lower surface of the via portion 22 contacts the upper surface of the first conductive wire 13 located in the connection region 21.

　この実施形態において、ビア部２２は、２つの第１導電線１３，１３と１つの第２導電線１７とが交差する２箇所の交点Ｐ，Ｐで、２つの第１導電線１３，１３と電気的に接続されている。ビア部２２は、第２導電線１７の延伸方向に沿う長さ（図６に示した寸法Ｌ）が、当該延伸方向において互いに隣り合う第１導電線１３，１３のピッチ間隔（図６に示した寸法Ａ）と、１つの第１導電線１３の線幅（図６に示した寸法Ｗ）との合計値以上の長さとなるように構成されている。この実施形態では、１つのビア部２２が、第２導電線１７の延伸方向において互いに隣り合う２つの第１導電線１３，１３と基板３の厚み方向に重なった状態となっている（図６参照）。なお、ビア部２２と重なり合わない第１導電線１３と、各第２導電線１７との間には、第２層６が介在している（図６参照）。 In this embodiment, the via portion 22 is electrically connected to the two first conductive wires 13, 13 at two intersections P, P where the two first conductive wires 13, 13 and one second conductive wire 17 intersect. The via portion 22 is configured so that the length along the extension direction of the second conductive wire 17 (dimension L shown in FIG. 6) is equal to or greater than the sum of the pitch interval (dimension A shown in FIG. 6) between the first conductive wires 13, 13 adjacent to each other in the extension direction and the line width (dimension W shown in FIG. 6) of one first conductive wire 13. In this embodiment, one via portion 22 overlaps two first conductive wires 13, 13 adjacent to each other in the extension direction of the second conductive wire 17 in the thickness direction of the substrate 3 (see FIG. 6). Note that a second layer 6 is interposed between the first conductive wires 13 that do not overlap with the via portion 22 and each second conductive wire 17 (see FIG. 6).

　（ダミーパターン）
　図３および図４に示すように、多層配線基板１は、複数のダミーパターン３０を備えている。図３では、各ダミーパターン３０をドットハッチングにより簡略的に示している。なお、図１および図２では、各ダミーパターン３０の図示を省略している。 (Dummy pattern)
As shown in Figures 3 and 4, the multilayer wiring board 1 includes a plurality of dummy patterns 30. In Figure 3, each dummy pattern 30 is simply shown by dot hatching. Note that in Figures 1 and 2, the illustration of each dummy pattern 30 is omitted.

　この実施形態において、複数のダミーパターン３０は、第１層５に配置されている。具体的に、複数のダミーパターン３０は、平面視において、第１層５の、第１導体パターン１０および第２導体パターン１４が位置しない領域（図１および図２参照）に配置されている。 In this embodiment, the multiple dummy patterns 30 are arranged on the first layer 5. Specifically, the multiple dummy patterns 30 are arranged in an area of the first layer 5 where the first conductor pattern 10 and the second conductor pattern 14 are not located in a plan view (see Figures 1 and 2).

　図４に示すように、ダミーパターン３０は、複数のダミー導電線３１により構成されている。各ダミー導電線３１は、細線化されている。具体的に、各ダミー導電線３１の線幅は、１５μｍ以下となるように構成されている。 As shown in FIG. 4, the dummy pattern 30 is composed of multiple dummy conductive lines 31. Each dummy conductive line 31 is thinned. Specifically, the line width of each dummy conductive line 31 is configured to be 15 μm or less.

　各ダミー導電線３１は、第１層５の凹部（図示せず）に埋設された導電性金属を含む。この導電性金属としては、例えば、銅、銀、金、またはこれらの金属の少なくとも１つを含む合金が適している。また、上記凹部は、第１層５の、第１導体パターン１０が位置しない領域の上面側に形成されている。上記凹部は、第１凹部７と同様の構成を有する。図示しないが、各ダミー導電線３１の上面は、第１層５の上面と面一となるように形成されていてもよい。 Each dummy conductive line 31 includes a conductive metal embedded in a recess (not shown) in the first layer 5. Suitable conductive metals include, for example, copper, silver, gold, or an alloy containing at least one of these metals. The recess is formed on the upper surface side of the first layer 5 in an area where the first conductor pattern 10 is not located. The recess has a configuration similar to that of the first recess 7. Although not shown, the upper surface of each dummy conductive line 31 may be formed to be flush with the upper surface of the first layer 5.

　複数のダミー導電線３１は、複数のダミー導電線３１をメッシュ状に配置したメッシュパターンからなる。複数のダミー導電線３１からなるメッシュパターンは、複数の第１導電線１３からなるメッシュパターンと同じ構成を有している。各ダミーパターン３０は、第１導体パターン１０が有する開口率と同じ開口率を有する。 The multiple dummy conductive lines 31 are formed in a mesh pattern in which the multiple dummy conductive lines 31 are arranged in a mesh shape. The mesh pattern formed of the multiple dummy conductive lines 31 has the same configuration as the mesh pattern formed of the multiple first conductive lines 13. Each dummy pattern 30 has the same aperture ratio as the first conductor pattern 10.

　複数のダミー導電線３１は、平面視において、各ダミーパターン３０と隣り合う第１導体パターン１０を構成する複数の第１導電線１３と間隔をあけて配置されている。すなわち、各ダミーパターン３０は、第１導体パターン１０と電気的に非導通状態となっている。また、図示しないが、各ダミーパターン３０は、第２層６を介して各第２導体パターン１４と絶縁されている。 The multiple dummy conductive lines 31 are arranged at intervals from the multiple first conductive lines 13 constituting the first conductor pattern 10 adjacent to each dummy pattern 30 in a plan view. In other words, each dummy pattern 30 is not electrically conductive with the first conductor pattern 10. Although not shown, each dummy pattern 30 is insulated from each second conductor pattern 14 via the second layer 6.

　（第１導電線）
　図７および図８に示すように、第１導電線１３は、第１層５に形成された第１凹部７に埋設された導電材料を含む。第１凹部７は、幅方向（図面左右方向）に延びる底面７ａ（第１底面）と、底面７ａと第１凹部７の開口とを接続する側面７ｂ（第１側面）と、底面７ａおよび側面７ｂを接続する隅角部７ｃとで構成されている。 (First conductive wire)
7 and 8, the first conductive line 13 includes a conductive material embedded in a first recess 7 formed in the first layer 5. The first recess 7 is composed of a bottom surface 7a (first bottom surface) extending in the width direction (left-right direction in the drawing), a side surface 7b (first side surface) connecting the bottom surface 7a and the opening of the first recess 7, and a corner portion 7c connecting the bottom surface 7a and the side surface 7b.

　第１導電線１３は、密着層１３１（第１金属化合物層）および導電層１３２（第１導電層）を含む。 The first conductive wire 13 includes an adhesion layer 131 (first metal compound layer) and a conductive layer 132 (first conductive layer).

　密着層１３１は、第１凹部７に対する導電層１３２の密着性を担保するための要素である。また、密着層１３１は低反射性を有する。すなわち、密着層１３１は、第１層５が位置する側（図７の紙面下側）から多層配線基板１を見たときに、導電層１３２が視認されにくくなるという機能を有する。 The adhesion layer 131 is an element for ensuring the adhesion of the conductive layer 132 to the first recess 7. The adhesion layer 131 also has low reflectivity. In other words, the adhesion layer 131 has the function of making the conductive layer 132 less visible when the multilayer wiring board 1 is viewed from the side where the first layer 5 is located (the lower side of the paper in FIG. 7).

　密着層１３１は、例えば、Ｔｉ、Ａｌ、Ｖ、Ｗ、Ｔａ、Ｓｉ、Ｃｒ、Ａｇ、Ｍｏ、Ｃｕ、ＺｎおよびＮｉからなる群より選ばれる少なくとも１種以上の金属を含む金属窒化物、金属酸化物、または、金属窒化物と金属酸化物とをいずれも含む金属酸窒化物により構成される金属層である。なお、密着層１３１は、１層もしくは組成の異なる複数の層を積層した積層体であってもよい。密着層１３１は、例えば蒸着やスパッタリングにより第１凹部７に対して薄膜状に積層配置される。なお、本実施形態では、密着層１３１は、厚みＬ１が略一定となるように形成されている。 The adhesion layer 131 is a metal layer composed of, for example, a metal nitride containing at least one metal selected from the group consisting of Ti, Al, V, W, Ta, Si, Cr, Ag, Mo, Cu, Zn, and Ni, a metal oxide, or a metal oxynitride containing both a metal nitride and a metal oxide. The adhesion layer 131 may be a single layer or a laminate of multiple layers having different compositions. The adhesion layer 131 is laminated in the form of a thin film on the first recess 7 by, for example, vapor deposition or sputtering. In this embodiment, the adhesion layer 131 is formed so that the thickness L1 is approximately constant.

　密着層１３１は、第１凹部７の底面７ａに形成された底面部１３１ａと、第１凹部７の側面７ｂに形成された側面部１３１ｂとを含む。底面部１３１ａおよび側面部１３１ｂは、第１凹部７の隅角部７ｃに沿って形成された接続部１３１ｃを介して接続されている。第１凹部７は、隅角部７ｃに、湾曲状のフィレットが形成されている。具体的に、隅角部７ｃは、底面７ａから側面７ｂに掛けて曲率が徐々に変化するように形成されている。すなわち、底面７ａおよび側面７ｂは、隅角部７ｃにおいて、連続的に角度変化するように接続されている。このため、底面７ａおよび側面７ｂは、隅角部７ｃにより、滑らかに接続されている。そして、接続部１３１ｃが第１凹部７の隅角部７ｃに沿って形成されることから、底面部１３１ａおよび側面部１３１ｂは、接続部１３１ｃにより、滑らかに接続されている。なお、隅角部７ｃは、曲率が一定となるように形成してもよい。 The adhesion layer 131 includes a bottom portion 131a formed on the bottom surface 7a of the first recess 7 and a side portion 131b formed on the side surface 7b of the first recess 7. The bottom portion 131a and the side portion 131b are connected via a connection portion 131c formed along the corner portion 7c of the first recess 7. The first recess 7 has a curved fillet formed at the corner portion 7c. Specifically, the corner portion 7c is formed so that the curvature gradually changes from the bottom surface 7a to the side surface 7b. That is, the bottom surface 7a and the side surface 7b are connected at the corner portion 7c so that the angle changes continuously. Therefore, the bottom surface 7a and the side surface 7b are smoothly connected by the corner portion 7c. And, since the connection portion 131c is formed along the corner portion 7c of the first recess 7, the bottom surface 131a and the side surface portion 131b are smoothly connected by the connection portion 131c. The corner portion 7c may be formed so that its curvature is constant.

　導電層１３２は、第１導電線１３の導電性を担保するための要素である。導電層１３２は、密着層１３１に積層配置された状態で第１凹部７に埋設されている。導電層１３２は、導電性金属により構成されている。この導電性金属としては、例えば、銅、銀、金、またはこれらの金属の少なくとも１つを含む合金が適している。導電層１３２は、例えば、蒸着、スパッタリング、無電解めっき処理、または、電気めっき処理により形成される。なお、好ましくは、導電層１３２の上面は、第１層５の上面と面一となるように形成される。 The conductive layer 132 is an element for ensuring the conductivity of the first conductive wire 13. The conductive layer 132 is embedded in the first recess 7 while being layered on the adhesive layer 131. The conductive layer 132 is made of a conductive metal. Suitable conductive metals include, for example, copper, silver, gold, and alloys containing at least one of these metals. The conductive layer 132 is formed by, for example, deposition, sputtering, electroless plating, or electroplating. Preferably, the upper surface of the conductive layer 132 is formed to be flush with the upper surface of the first layer 5.

　なお、導電層１３２の上面に、黒化層を形成してもよい。黒化層は、低反射性を有する。すなわち、黒化層は、第２層６が位置する側から多層配線基板１を見たときに、導電層１３２が視認されにくくなるという機能を有する。 A blackening layer may be formed on the upper surface of the conductive layer 132. The blackening layer has low reflectivity. In other words, the blackening layer has the function of making the conductive layer 132 less visible when the multilayer wiring board 1 is viewed from the side where the second layer 6 is located.

　（第２導電線）
　図７および図８に示すように、第２導電線１７は、第２層６に形成された第２凹部８に埋設された導電材料を含む。第２凹部８は、幅方向（図面左右方向）に延びる底面８ａ（第２底面）と、底面８ａと第２凹部８の開口とを接続する側面８ｂ（第２側面）と、底面８ａおよび側面８ｂを接続する隅角部８ｃとで構成されている。なお、実際の製品には、第１凹部７と第２凹部８との境界線は存在しないが、本開示では、第１導電線１８と第２導電線１７との境界線を、第１凹部７と第２凹部８の境界線と見なすことができる。図８に、第２凹部８の、底面８ａ、側面８ｂ、隅角部８ｃを図示している。 (Second conductive wire)
As shown in Fig. 7 and Fig. 8, the second conductive wire 17 includes a conductive material embedded in a second recess 8 formed in the second layer 6. The second recess 8 is composed of a bottom surface 8a (second bottom surface) extending in the width direction (left-right direction in the drawing), a side surface 8b (second side surface) connecting the bottom surface 8a and the opening of the second recess 8, and a corner portion 8c connecting the bottom surface 8a and the side surface 8b. Note that, although there is no boundary line between the first recess 7 and the second recess 8 in an actual product, in this disclosure, the boundary line between the first conductive wire 18 and the second conductive wire 17 can be regarded as the boundary line between the first recess 7 and the second recess 8. Fig. 8 illustrates the bottom surface 8a, side surface 8b, and corner portion 8c of the second recess 8.

　第２導電線１７は、密着層１７１（第２金属化合物層）および導電層１７２（第２導電層）を含む。 The second conductive wire 17 includes an adhesion layer 171 (second metal compound layer) and a conductive layer 172 (second conductive layer).

　密着層１７１は、第２凹部８に対する導電層１７２の密着性を担保するための要素である。また、密着層１７１は低反射性を有する。すなわち、密着層１７１は、第１層５が位置する側（図７の紙面下側）から多層配線基板１を見たときに、導電層１７２が視認されにくくなるという機能を有する。 The adhesion layer 171 is an element for ensuring the adhesion of the conductive layer 172 to the second recess 8. The adhesion layer 171 also has low reflectivity. In other words, the adhesion layer 171 has the function of making the conductive layer 172 less visible when the multilayer wiring board 1 is viewed from the side where the first layer 5 is located (the lower side of the paper in FIG. 7).

　密着層１７１は、例えば、Ｔｉ、Ａｌ、Ｖ、Ｗ、Ｔａ、Ｓｉ、Ｃｒ、Ａｇ、Ｍｏ、Ｃｕ、ＺｎおよびＮｉからなる群より選ばれる少なくとも１種以上の金属を含む金属窒化物、金属酸化物、または、金属窒化物と金属酸化物とをいずれも含む金属酸窒化物により構成される金属層である。なお、密着層１７１は、１層もしくは組成の異なる複数の層を積層した積層体であってもよい。密着層１７１は、例えば蒸着やスパッタリングにより第２凹部８に対して薄膜状に積層配置される。なお、本実施形態では、密着層１７１は、厚みＬ２が略一定となるように形成されている。 The adhesion layer 171 is a metal layer composed of, for example, a metal nitride containing at least one metal selected from the group consisting of Ti, Al, V, W, Ta, Si, Cr, Ag, Mo, Cu, Zn, and Ni, a metal oxide, or a metal oxynitride containing both a metal nitride and a metal oxide. The adhesion layer 171 may be a single layer or a laminate of multiple layers having different compositions. The adhesion layer 171 is laminated in the form of a thin film on the second recess 8 by, for example, vapor deposition or sputtering. In this embodiment, the adhesion layer 171 is formed so that the thickness L2 is approximately constant.

　密着層１７１は、第２凹部８の底面８ａに形成された底面部１７１ａと、第２凹部８の側面８ｂに形成された側面部１７１ｂとを含む。底面部１７１ａおよび側面部１７１ｂは、第２凹部８の隅角部８ｃに沿って形成された接続部１７１ｃを介して接続されている。第２凹部８は、隅角部８ｃに、湾曲状のフィレットが形成されている。具体的に、隅角部８ｃは、底面８ａから側面８ｂに掛けて曲率が徐々に変化するように形成されている。すなわち、底面８ａおよび側面８ｂは、隅角部８ｃにおいて、連続的に角度変化するように接続されている。このため、底面８ａおよび側面８ｂは、隅角部８ｃにより、滑らかに接続されている。そして、接続部１７１ｃが第２凹部８の隅角部８ｃに沿って形成されることから、底面部１７１ａおよび側面部１７１ｂは、接続部１７１ｃにより、滑らかに接続されている。 The adhesive layer 171 includes a bottom portion 171a formed on the bottom surface 8a of the second recess 8 and a side portion 171b formed on the side surface 8b of the second recess 8. The bottom portion 171a and the side portion 171b are connected via a connection portion 171c formed along the corner portion 8c of the second recess 8. The second recess 8 has a curved fillet formed at the corner portion 8c. Specifically, the corner portion 8c is formed so that the curvature gradually changes from the bottom surface 8a to the side surface 8b. That is, the bottom surface 8a and the side surface 8b are connected so that the angle changes continuously at the corner portion 8c. Therefore, the bottom surface 8a and the side surface 8b are smoothly connected by the corner portion 8c. And, since the connection portion 171c is formed along the corner portion 8c of the second recess 8, the bottom surface portion 171a and the side surface portion 171b are smoothly connected by the connection portion 171c.

　導電層１７２は、第２導電線１７の導電性を担保するための要素である。導電層１７２は、密着層１７１に積層配置された状態で第２凹部８に埋設されている。導電層１７２は、導電性金属により構成されている。この導電性金属としては、例えば、銅、銀、金、またはこれらの金属の少なくとも１つを含む合金が適している。導電層１７２は、例えば、蒸着、スパッタリング、無電解めっき処理、または、電気めっき処理により形成される。なお、好ましくは、導電層１７２の上面は、第２層６の上面と面一となるように形成される。 The conductive layer 172 is an element for ensuring the conductivity of the second conductive wire 17. The conductive layer 172 is embedded in the second recess 8 while being layered on the adhesive layer 171. The conductive layer 172 is made of a conductive metal. Suitable conductive metals include, for example, copper, silver, gold, and alloys containing at least one of these metals. The conductive layer 172 is formed, for example, by vapor deposition, sputtering, electroless plating, or electroplating. Preferably, the upper surface of the conductive layer 172 is formed to be flush with the upper surface of the second layer 6.

　なお、導電層１７２の上面に、黒化層を形成してもよい。黒化層は、低反射性を有する。すなわち、黒化層は、第２層６が位置する側から多層配線基板１を見たときに、導電層１７２が視認されにくくなるという機能を有する。 A blackening layer may be formed on the upper surface of the conductive layer 172. The blackening layer has low reflectivity. In other words, the blackening layer has the function of making the conductive layer 172 less visible when the multilayer wiring board 1 is viewed from the side where the second layer 6 is located.

　ここで、第１導電線１３が埋設された第１凹部７の溝幅を溝幅Ｗ１（第１溝幅）とし、第２導電線１７が埋設された第２凹部８の溝幅を溝幅Ｗ２（第２溝幅）とすると、溝幅Ｗ２は溝幅Ｗ１よりも広い。第１凹部７の底面７ａと側面７ｂとのなす角度を角度Ｄ１（第１角度）とし、第２凹部８の底面８ａと側面８ｂとのなす角度を角度Ｄ２（第２角度）とすると、角度Ｄ２は角度Ｄ１よりも大きい。なお、角度Ｄ１（第１角度）は、第１層５の底面と側面７ｂとのなす角度と同じである。また角度Ｄ２（第２角度）は、第１層５の底面と側面８ｂとのなす角度と同じである。よって、角度Ｄ１（第１角度）を、第１層５の底面と側面７ｂとのなす角度と表す場合がある。また角度Ｄ２（第２角度）を、第１層５の底面と側面８ｂとのなす角度と表す場合がある。 Here, if the groove width of the first recess 7 in which the first conductive wire 13 is embedded is defined as groove width W1 (first groove width), and the groove width of the second recess 8 in which the second conductive wire 17 is embedded is defined as groove width W2 (second groove width), then groove width W2 is wider than groove width W1. If the angle between the bottom surface 7a and the side surface 7b of the first recess 7 is defined as angle D1 (first angle), and the angle between the bottom surface 8a and the side surface 8b of the second recess 8 is defined as angle D2 (second angle), then angle D2 is larger than angle D1. Note that angle D1 (first angle) is the same as the angle between the bottom surface and the side surface 7b of the first layer 5. Also, angle D2 (second angle) is the same as the angle between the bottom surface and the side surface 8b of the first layer 5. Therefore, angle D1 (first angle) may be expressed as the angle between the bottom surface and the side surface 7b of the first layer 5. Additionally, angle D2 (second angle) may be expressed as the angle between the bottom surface of the first layer 5 and the side surface 8b.

　また、側面８ｂおよび側面７ｂは実際の製品では、緩やかに湾曲している場合があるが、図８に示すように、側面８ｂおよび側面７ｂのそれぞれの接線を用いて、角度Ｄ１、角度Ｄ２を測る場合がある。このような測定方法で計測した角度Ｄ２が角度Ｄ１よりも大きい製品についても本開示に含まれる。 Furthermore, in an actual product, side 8b and side 7b may be gently curved, but as shown in FIG. 8, angles D1 and D2 may be measured using the tangents of side 8b and side 7b, respectively. Products in which angle D2 measured using this method is greater than angle D1 are also included in the present disclosure.

　第１導電線１３における密着層１３１の厚みを厚みＬ１（第１厚み）とし、第２導電線１７における密着層１７１の厚みを厚みＬ２（第２厚み）とすると、厚みＬ２は厚みＬ１よりも厚い。 If the thickness of the adhesive layer 131 in the first conductive wire 13 is thickness L1 (first thickness) and the thickness of the adhesive layer 171 in the second conductive wire 17 is thickness L2 (second thickness), thickness L2 is thicker than thickness L1.

　（凹部１００の構成）
　凹部１００について、図１０を参照しながら説明する。上述した実施形態では、第１凹部７と第２凹部８を用いて説明したが、第１凹部７と第２凹部８とをまとめて凹部１００と表してもよい。 (Configuration of the recess 100)
The recess 100 will be described with reference to Fig. 10. In the above embodiment, the first recess 7 and the second recess 8 are used for the description. However, the first recess 7 and the second recess 8 may be collectively referred to as the recess 100.

　凹部１００のうち第１層５に位置する領域を『第１層における凹部』と、表すことがある。図１０に点線で示す境界線１００Ａより下の領域が、『第１層における凹部』に相当する。 The area of the recess 100 located in the first layer 5 may be referred to as the "recess in the first layer." The area below the boundary line 100A shown by the dotted line in Figure 10 corresponds to the "recess in the first layer."

　また、凹部１００のうち第２層６に位置する領域を『第２層における凹部』と、表すことがある。図１０に点線で示す境界線１００Ａより上の領域が、『第２層における凹部』に相当する。 The area of the recess 100 located in the second layer 6 may be referred to as the "recess in the second layer." The area above the boundary line 100A shown by the dotted line in FIG. 10 corresponds to the "recess in the second layer."

　［実施形態の作用効果］
　上述したように、本開示の実施形態に係る多層配線基板１は、第１導電線１３と、第２導電線１７とを備える。第１導電線１３が埋設された第１凹部７の溝幅を溝幅Ｗ１とし、第２導電線１７が埋設された第２凹部８の溝幅を溝幅Ｗ２とすると、溝幅Ｗ２は溝幅Ｗ１よりも広い。第１凹部７の底面７ａと側面７ｂとのなす角度を角度Ｄ１とし、第２凹部８の底面８ａと側面８ｂとのなす角度を角度Ｄ２とすると、角度Ｄ２は角度Ｄ１よりも大きい。第１層５の底面と側面７ｂとのなす角度を角度Ｄ１とし、第１層５の底面と側面８ｂとのなす角度を角度Ｄ２として説明する場合がある。この場合であっても、角度Ｄ２は角度Ｄ１よりも大きい。 [Effects of the embodiment]
As described above, the multilayer wiring board 1 according to the embodiment of the present disclosure includes the first conductive wire 13 and the second conductive wire 17. If the groove width of the first recess 7 in which the first conductive wire 13 is embedded is defined as groove width W1, and the groove width of the second recess 8 in which the second conductive wire 17 is embedded is defined as groove width W2, the groove width W2 is wider than the groove width W1. If the angle between the bottom surface 7a and the side surface 7b of the first recess 7 is defined as angle D1, and the angle between the bottom surface 8a and the side surface 8b of the second recess 8 is defined as angle D2, the angle D2 is larger than the angle D1. The angle between the bottom surface of the first layer 5 and the side surface 7b may be described as angle D1, and the angle between the bottom surface of the first layer 5 and the side surface 8b may be described as angle D2. Even in this case, the angle D2 is larger than the angle D1.

　この構成により、第１導電線１７よりも第２導電線１３の断面積が大きくなる。このため、電気抵抗と断面積との一般的な関係性（すなわち、導体の電気抵抗は該導体の断面積に反比例するという一般的な公式に基づく関係）により、第２導電線１７の配線抵抗を抑えることができる。また、角度Ｄ２を角度Ｄ１よりも大きくすることで、第２導電線１７における密着層１７１の厚みＬ２を、第１導電線１３における密着層１３１の厚みＬ１よりも厚くすることができる。厚みＬ２を厚くすることで、第２導電線１７を視認されにくくすることができる。したがって、多層配線構造を有する導電部材において、配線抵抗を低減しつつ、配線を視認されにくくすることができる。 With this configuration, the cross-sectional area of the second conductive wire 13 is larger than that of the first conductive wire 17. Therefore, due to the general relationship between electrical resistance and cross-sectional area (i.e., a relationship based on the general formula that the electrical resistance of a conductor is inversely proportional to the cross-sectional area of the conductor), the wiring resistance of the second conductive wire 17 can be suppressed. Furthermore, by making the angle D2 larger than the angle D1, the thickness L2 of the adhesion layer 171 in the second conductive wire 17 can be made thicker than the thickness L1 of the adhesion layer 131 in the first conductive wire 13. By making the thickness L2 thicker, the second conductive wire 17 can be made less visible. Therefore, in a conductive member having a multilayer wiring structure, the wiring can be made less visible while reducing the wiring resistance.

　［実施形態の変形例］
　上記実施形態では、第１導電線１３の密着層１３１の厚みＬ１が略一定となるように形成されている形態を示したが、この形態に限られない。第２導電線１７の密着層１７１についても、厚みＬ２が略一定となるように形成されている形態に限られない。 [Modification of the embodiment]
In the above embodiment, the thickness L1 of the adhesive layer 131 of the first conductive wire 13 is formed to be substantially constant, but this is not limited to the embodiment. The thickness L2 of the adhesive layer 171 of the second conductive wire 17 is also not limited to the embodiment.

　例えば、図９に示した変形例のように、密着層１３１の底面部１３１ａの厚みＬ１１と密着層１３１の底面部１３１ｂの厚みＬ１２とが異なってもよい。図９では、厚みＬ１１が厚みＬ１２よりも厚い。この場合、隅角部８ｃは、底面８ａから側面８ｂに掛けて厚みが徐々に変化するように形成されている。そして、上述したように、第１凹部７の底面７ａおよび側面７ｂは、隅角部７ｃにおいて、連続的に角度変化するように接続されている。別の言い方をすれば、第１導電線１３の密着層１３１は下方に向かって突出するように湾曲して形成されている。この構成により、密着層１３１の底面部１３１ａおよび側面部１３１ｂを接続する接続部１３１ｃにおいて、光反射の急変を抑えることができるため、第１導電線１３をより視認されにくくすることができる。 For example, as in the modified example shown in FIG. 9, the thickness L11 of the bottom surface portion 131a of the adhesive layer 131 and the thickness L12 of the bottom surface portion 131b of the adhesive layer 131 may be different. In FIG. 9, the thickness L11 is thicker than the thickness L12. In this case, the corner portion 8c is formed so that the thickness gradually changes from the bottom surface 8a to the side surface 8b. As described above, the bottom surface 7a and the side surface 7b of the first recess 7 are connected at the corner portion 7c so that the angle changes continuously. In other words, the adhesive layer 131 of the first conductive wire 13 is formed to be curved so as to protrude downward. With this configuration, it is possible to suppress a sudden change in light reflection at the connection portion 131c that connects the bottom surface portion 131a and the side surface portion 131b of the adhesive layer 131, making it possible to make the first conductive wire 13 less visible.

　また、図９では、密着層１７１の底面部１７１ａの厚みＬ２１と密着層１７１の底面部１７１ｂの厚みＬ２２とが異なる。図９では、厚みＬ２１が厚みＬ２２よりも厚い。この場合、隅角部８ｃは、底面８ａから側面８ｂに掛けて厚みが徐々に変化するように形成されている。そして、上述したように、第２凹部８の底面８ａおよび側面８ｂは、隅角部８ｃにおいて、連続的に角度変化するように接続されている。別の言い方をすれば、第２導電線１７の密着層１７１は下方に向かって突出するように湾曲して形成されている。この構成により、密着層１７１の底面部１７１ａおよび側面部１７１ｂを接続する接続部１７１ｃにおいて、光反射の急変を抑えることができるため、第２導電線１７をより視認されにくくすることができる。 9, the thickness L21 of the bottom surface 171a of the adhesion layer 171 is different from the thickness L22 of the bottom surface 171b of the adhesion layer 171. In FIG. 9, the thickness L21 is thicker than the thickness L22. In this case, the corner portion 8c is formed so that the thickness gradually changes from the bottom surface 8a to the side surface 8b. As described above, the bottom surface 8a and the side surface 8b of the second recess 8 are connected at the corner portion 8c so that the angle changes continuously. In other words, the adhesion layer 171 of the second conductive wire 17 is formed to be curved so as to protrude downward. With this configuration, it is possible to suppress a sudden change in light reflection at the connection portion 171c that connects the bottom surface portion 171a and the side surface portion 171b of the adhesion layer 171, making it possible to make the second conductive wire 17 less visible.

　［その他の実施形態］
　上記実施形態では、各第１導体パターン１０として、複数の第１導電線１３をメッシュ状に配置したメッシュパターンからなる形態を示したが、この形態に限られない。各第２導体パターン１４についても、複数の第２導電線１７をメッシュ状に配置したメッシュパターンからなる形態に限られない。 [Other embodiments]
In the above embodiment, the first conductor patterns 10 are formed in a mesh pattern in which a plurality of first conductive wires 13 are arranged in a mesh shape, but the present invention is not limited to this configuration. Similarly, the second conductor patterns 14 are not limited to a mesh pattern in which a plurality of second conductive wires 17 are arranged in a mesh shape.

　上記実施形態において、複数の第１凹部７は、各々の溝幅Ｗ１が互いに異なる大きさとなるように構成されていてもよい。例えば、複数の第１凹部７は、第１グループに属する第１凹部７１と、第２グループに属する第１凹部７２とを含む。第１凹部７１の溝幅Ｗ１ａおよび第１凹部７２の溝幅Ｗ１ｂは、０．３μｍ以上５０μｍ以下である。溝幅Ｗ１ｂは、溝幅Ｗ１ａよりも広い。 In the above embodiment, the multiple first recesses 7 may be configured so that the groove widths W1 of each recess are different from each other. For example, the multiple first recesses 7 include a first recess 71 belonging to a first group and a first recess 72 belonging to a second group. The groove width W1a of the first recess 71 and the groove width W1b of the first recess 72 are 0.3 μm or more and 50 μm or less. The groove width W1b is wider than the groove width W1a.

　上記実施形態において、複数の第２凹部８は、各々の溝幅Ｗ２が互いに異なる大きさとなるように構成されていてもよい。例えば、複数の第２凹部８は、第３グループに属する第２凹部８１と、第４グループに属する第２凹部８２とを含む。第２凹部８１の溝幅Ｗ２ａおよび第２凹部８２の溝幅Ｗ２ｂは、０．８μｍ以上５２．０μｍ以下である。溝幅Ｗ２ｂは、溝幅Ｗ２ａよりも広い。また、溝幅Ｗ２ｂは、溝幅Ｗ１ｂよりも広い。 In the above embodiment, the multiple second recesses 8 may be configured so that the groove widths W2 of each recess are different from each other. For example, the multiple second recesses 8 include a second recess 81 belonging to a third group and a second recess 82 belonging to a fourth group. The groove width W2a of the second recess 81 and the groove width W2b of the second recess 82 are 0.8 μm or more and 52.0 μm or less. The groove width W2b is wider than the groove width W2a. Also, the groove width W2b is wider than the groove width W1b.

　この構成により、溝幅Ｗ２が溝幅Ｗ１よりも広くなるため、第２導電線１７は第１導電線１３よりも配線幅が広くすることができる。これにより、第２導電線１７の断面積を大きくすることができるため、第２導電線１７の配線抵抗を低減することができる。 With this configuration, the groove width W2 is wider than the groove width W1, so the second conductive wire 17 can have a wider wiring width than the first conductive wire 13. This allows the cross-sectional area of the second conductive wire 17 to be increased, thereby reducing the wiring resistance of the second conductive wire 17.

　上記実施形態において、複数の第１凹部７は、各々の角度Ｄ１（第１凹部７の底面７ａと側面７ｂとのなす角度）が互いに異なる大きさとなるように構成されていてもよい。例えば、複数の第１凹部７は、第５グループに属する第１凹部７３と、第６グループに属する第１凹部７４とを含む。第１凹部７３の角度Ｄ１ａおよび第１凹部７４の角度Ｄ１ｂは、９０°より大きく１３５°より小さい。角度Ｄ１ｂは、角度Ｄ１ａよりも大きい。 In the above embodiment, the multiple first recesses 7 may be configured so that each angle D1 (the angle between the bottom surface 7a and the side surface 7b of the first recess 7) is different from the others. For example, the multiple first recesses 7 include a first recess 73 belonging to the fifth group and a first recess 74 belonging to the sixth group. The angle D1a of the first recess 73 and the angle D1b of the first recess 74 are greater than 90° and less than 135°. The angle D1b is greater than the angle D1a.

　上記実施形態において、複数の第２凹部８は、各々の角度Ｄ２（第２凹部８の底面８ａと側面８ｂとのなす角度）が互いに異なる大きさとなるように構成されていてもよい。例えば、複数の第２凹部８は、第７グループに属する第２凹部８３と、第８グループに属する第２凹部８４とを含む。第２凹部８３の角度Ｄ２ａおよび第２凹部８４の角度Ｄ２ｂは、９０°より大きく１３５°より小さい。角度Ｄ２ｂは、角度Ｄ２ａよりも大きい。また、角度Ｄ２ａ，Ｄ２ｂは、角度Ｄ１ａ，Ｄ１ｂよりも大きい。この構成により、角度Ｄ１が角度Ｄ２よりも小さいため、第１導電線１３の断面積を大きくすることができ、第１導電線１３の配線抵抗を低減することができる。また、第１導電線１３は第２導電線１７よりも配線幅が狭いため、視認性されにくい。このため、角度Ｄ２が小さくなることによって、密着層１３１の厚みが薄くなったとしても、第１導電線１３は視認されにくい。一方、第２導電線１７の角度Ｄ２が第１導電線１３の角度Ｄ１よりも大きいため、第２導電線１７の密着層１７１の厚みを厚くすることができ、配線幅が広い第２導電線１７の視認性を低くすることができる。 In the above embodiment, the multiple second recesses 8 may be configured so that each angle D2 (the angle between the bottom surface 8a and the side surface 8b of the second recess 8) is different from the others. For example, the multiple second recesses 8 include a second recess 83 belonging to the seventh group and a second recess 84 belonging to the eighth group. The angle D2a of the second recess 83 and the angle D2b of the second recess 84 are greater than 90° and less than 135°. The angle D2b is greater than the angle D2a. In addition, the angles D2a and D2b are greater than the angles D1a and D1b. With this configuration, since the angle D1 is smaller than the angle D2, the cross-sectional area of the first conductive wire 13 can be increased, and the wiring resistance of the first conductive wire 13 can be reduced. In addition, since the wiring width of the first conductive wire 13 is narrower than that of the second conductive wire 17, it is difficult to see. Therefore, even if the thickness of the adhesion layer 131 is reduced by reducing the angle D2, the first conductive wire 13 is difficult to see. On the other hand, because the angle D2 of the second conductive wire 17 is greater than the angle D1 of the first conductive wire 13, the thickness of the adhesion layer 171 of the second conductive wire 17 can be increased, and the visibility of the second conductive wire 17, which has a wide wiring width, can be reduced.

　上記実施形態において、複数の第１導電線１３は、各々の密着層１３１の厚みＬ１が互いに異なる厚みとなるように構成されていてもよい。例えば、複数の第１導電線１３は、第９グループに属する第１導電線１３ｅと、第１０グループに属する第１導電線１３ｆとを含む。第１導電線１３ｅの密着層１７１の厚みＬ１ａおよび第１導電線１３ｆの密着層１７１の厚みＬ１ｂは、３ｎｍより大きく１５０ｎｍより小さい。厚みＬ１ｂは、厚みＬ１ａよりも大きい。 In the above embodiment, the multiple first conductive wires 13 may be configured so that the thickness L1 of each adhesion layer 131 is different from each other. For example, the multiple first conductive wires 13 include a first conductive wire 13e belonging to a ninth group and a first conductive wire 13f belonging to a tenth group. The thickness L1a of the adhesion layer 171 of the first conductive wire 13e and the thickness L1b of the adhesion layer 171 of the first conductive wire 13f are greater than 3 nm and less than 150 nm. The thickness L1b is greater than the thickness L1a.

　上記実施形態において、複数の第２導電線１７は、各々の密着層１７１の厚みＬ２が互いに異なる厚みとなるように構成されていてもよい。例えば、複数の第２導電線１７は、第１１グループに属する第２導電線１７ｅと、第１２グループに属する第２導電線１７ｆとを含む。第２導電線１７ｅの密着層１７１の厚みＬ２ａおよび第２導電線１７ｆの密着層１７１の厚みＬ２ｂは、３ｎｍより大きく１５０ｎｍより小さい。厚みＬ２ｂは、厚みＬ２ａよりも厚い。また、厚みＬ２ａ，Ｌ２ｂは、厚みＬ１ａ，Ｌ１ｂよりも厚い。この構成により、厚みＬ１が厚みＬ２よりも小さいため、第１導電線１３の断面積を大きくすることができ、第１導電線１３の配線抵抗を低減することができる。また、第１導電線１３は第２導電線１７よりも配線幅が狭いため、視認性が低い。このため、密着層１３１の厚みが薄くなったとしても、第１導電線１３は視認性されにくい。一方、第２導電線１７の密着層１７１の厚みを厚くすることができるため、配線幅が広い第２導電線１７の視認性を低くすることができる。 In the above embodiment, the second conductive wires 17 may be configured so that the thickness L2 of each adhesive layer 171 is different from each other. For example, the second conductive wires 17 include a second conductive wire 17e belonging to the 11th group and a second conductive wire 17f belonging to the 12th group. The thickness L2a of the adhesive layer 171 of the second conductive wire 17e and the thickness L2b of the adhesive layer 171 of the second conductive wire 17f are greater than 3 nm and smaller than 150 nm. The thickness L2b is thicker than the thickness L2a. Furthermore, the thicknesses L2a and L2b are thicker than the thicknesses L1a and L1b. With this configuration, since the thickness L1 is smaller than the thickness L2, the cross-sectional area of the first conductive wire 13 can be increased, and the wiring resistance of the first conductive wire 13 can be reduced. Furthermore, since the wiring width of the first conductive wire 13 is narrower than that of the second conductive wire 17, the visibility is low. Therefore, even if the thickness of the adhesion layer 131 is reduced, the first conductive line 13 is less visible. On the other hand, the thickness of the adhesion layer 171 of the second conductive line 17 can be increased, so the visibility of the second conductive line 17, which has a wide wiring width, can be reduced.

　上記実施形態では、各ダミーパターン３０を第１層５に配置した形態を示したが、この形態に限られない。すなわち、各ダミーパターン３０は、第２層６に配置されていてもよい。 In the above embodiment, the dummy patterns 30 are arranged on the first layer 5, but this is not limited to the above. In other words, the dummy patterns 30 may be arranged on the second layer 6.

　上記実施形態では、本開示の実施形態に係る多層配線基板１は、タッチセンサ、液晶表示装置、有機エレクトロルミネッセンス表示装置（ＯＬＥＤ）、マイクロＬＥＤ表示装置、太陽電池装置、ヒータ装置、アンテナ装置、電磁波遮蔽シートなどの様々な技術分野）に広く適用することが可能である。 In the above embodiment, the multilayer wiring substrate 1 according to the embodiment of the present disclosure can be widely applied to various technical fields such as touch sensors, liquid crystal display devices, organic electroluminescence display devices (OLEDs), micro LED display devices, solar cell devices, heater devices, antenna devices, and electromagnetic wave shielding sheets.

　以上、本開示についての実施形態を説明したが、本開示は上述の実施形態のみに限定されず、本開示の範囲内で種々の変更が可能である。 　Although the embodiments of the present disclosure have been described above, the present disclosure is not limited to the above-described embodiments, and various modifications are possible within the scope of the present disclosure.

　（態様）
　本開示の第１の態様の導電部材（多層配線基板１）は、第１層（５）と第１層（５）の上方に設けられた第２層（６）とを含み、透明性および光透過性を有する基板（３）と、基板（３）に設けられた凹部（１００）に配置された第１導電線（１３）と、第１導電線（１３）の上に位置し、基板（３）の凹部（１００）に配置された第２導電線（１７）と、を備える。 (Aspects)
The conductive member (multilayer wiring board 1) of the first aspect of the present disclosure comprises a substrate (3) having transparency and light transmissivity, which includes a first layer (5) and a second layer (6) provided above the first layer (5), a first conductive wire (13) arranged in a recess (100) provided in the substrate (3), and a second conductive wire (17) located above the first conductive wire (13) and arranged in the recess (100) of the substrate (3).

　第１導電線（１３）は、金属化合物からなる第１金属化合物層（密着層１３１）と、第１金属化合物層（密着層１３１）の上に形成され、導電性の金属からなる第１導電層（１３２）と、を含み、第１金属化合物層（密着層１３１）は、第１層（５）における凹部（１００）の側面である第１側面（７ｂ）に接する。 The first conductive wire (13) includes a first metal compound layer (adhesion layer 131) made of a metal compound, and a first conductive layer (132) made of a conductive metal formed on the first metal compound layer (adhesion layer 131), and the first metal compound layer (adhesion layer 131) contacts a first side surface (7b) which is the side surface of the recess (100) in the first layer (5).

　第２導電線（１７）は、金属化合物からなる第２金属化合物層（密着層１７１）と、第２金属化合物層（密着層１７１）の上に形成され、導電性の金属からなる第２導電層（１７２）と、を含み、第２金属化合物層（密着層１７１）は、第２層（６）における凹部（１００）の側面である第２側面（８ｂ）に接する。 The second conductive wire (17) includes a second metal compound layer (adhesion layer 171) made of a metal compound, and a second conductive layer (172) made of a conductive metal formed on the second metal compound layer (adhesion layer 171), and the second metal compound layer (adhesion layer 171) contacts the second side surface (8b), which is the side surface of the recess (100) in the second layer (6).

　第２層（６）における凹部（１００）の溝幅である第２溝幅（Ｗ２）は、第１層（５）における凹部（１００）の溝幅である第１溝幅（Ｗ１）よりも広い。 The second groove width (W2), which is the groove width of the recess (100) in the second layer (6), is wider than the first groove width (W1), which is the groove width of the recess (100) in the first layer (5).

　第２側面（８ｂ）と第１層（５）の底面とのなす角度である第２角度（Ｄ２）は、第１側面（７ｂ）と第１層（５）の底面とのなす角度である第１角度（Ｄ１）よりも大きく、第２導電層（１７２）の下端に接する部分における第２金属化合物層（密着層１７１）の厚みである第２厚み（Ｌ２）は、第１導電層（１３２）の下端に接する部分における第１金属化合物層（密着層１３１）の厚みである第１厚み（Ｌ１）よりも厚い。 The second angle (D2) between the second side (8b) and the bottom surface of the first layer (5) is greater than the first angle (D1) between the first side (7b) and the bottom surface of the first layer (5), and the second thickness (L2) of the second metal compound layer (adhesion layer 171) at the portion in contact with the lower end of the second conductive layer (172) is greater than the first thickness (L1) of the first metal compound layer (adhesion layer 131) at the portion in contact with the lower end of the first conductive layer (132).

　本開示の第２の態様の導電部材（多層配線基板１）では、第２金属化合物層（密着層１７１）の一部の厚みが、上方に向かうにつれて連続的に変化していている。 In the conductive member (multilayer wiring board 1) of the second aspect of the present disclosure, the thickness of a portion of the second metal compound layer (adhesion layer 171) changes continuously as it moves upward.

　本開示の第３の態様の導電部材（多層配線基板１）では、第１溝幅（Ｗ１）が、０．３μｍ以上５０μｍ以下であると好ましい。 In the conductive member (multilayer wiring board 1) of the third aspect of the present disclosure, it is preferable that the first groove width (W1) is 0.3 μm or more and 50 μm or less.

　本開示の第４の態様の導電部材（多層配線基板１）では、基板（３）に複数の凹部（１００）が設けられ、複数の凹部（１００）のうちの１つの第１溝幅（Ｗ１）と、複数の凹部（１００）のうちの他の１つの第１溝幅（Ｗ１）とは、互いに幅が異なっていてもよい。 In the conductive member (multilayer wiring board 1) of the fourth aspect of the present disclosure, a plurality of recesses (100) are provided in the board (3), and the first groove width (W1) of one of the plurality of recesses (100) and the first groove width (W1) of another of the plurality of recesses (100) may be different in width.

　本開示の第５の態様の導電部材（多層配線基板１）では、第２溝幅（Ｗ２）が、０．８μｍ以上５２．０μｍ以下であると好ましい。 In the conductive member (multilayer wiring board 1) of the fifth aspect of the present disclosure, the second groove width (W2) is preferably 0.8 μm or more and 52.0 μm or less.

　本開示の第６の態様の導電部材（多層配線基板１）では、第１角度（Ｄ１）が、９０°より大きく１３５°より小さいと好ましい。 In the conductive member (multilayer wiring board 1) of the sixth aspect of the present disclosure, it is preferable that the first angle (D1) is greater than 90° and less than 135°.

　本開示の第７の態様の導電部材（多層配線基板１）では、基板（３）に、複数の凹部（１００）が設けられ、複数の凹部（１００）のうちの1つの第１角度（Ｄ１）と、複数の凹部（１００）のうちの他の1つの第１角度（Ｄ１）とは、互いに大きさが異なる。 In the seventh aspect of the conductive member (multilayer wiring board 1) of the present disclosure, a substrate (3) is provided with a plurality of recesses (100), and the first angle (D1) of one of the plurality of recesses (100) and the first angle (D1) of another of the plurality of recesses (100) are different in size.

　本開示の第８の態様の導電部材（多層配線基板１）では、第２角度（Ｄ２）が、９０°より大きく１３５°より小さいと好ましい。 In the conductive member (multilayer wiring board 1) of the eighth aspect of the present disclosure, it is preferable that the second angle (D2) is greater than 90° and less than 135°.

　本開示の第９の態様の導電部材（多層配線基板１）では、第１厚み（Ｌ１）が、３ｎｍより大きく１５０ｎｍより小さいと好ましい。 In the conductive member (multilayer wiring board 1) of the ninth aspect of the present disclosure, it is preferable that the first thickness (L1) is greater than 3 nm and less than 150 nm.

　本開示の第１０の態様の導電部材（多層配線基板１）は、複数の第１導電線（１３）を備え、複数の第１導電線（１３）のうちの１つの厚み（Ｌ１）と、複数の第１導電線（１３）のうちの他の１つの厚み（Ｌ１）とは、互いに厚みが異なる。 The conductive member (multilayer wiring board 1) of the tenth aspect of the present disclosure includes a plurality of first conductive wires (13), and the thickness (L1) of one of the plurality of first conductive wires (13) is different from the thickness (L1) of another of the plurality of first conductive wires (13).

　本開示の第１１の態様の導電部材（多層配線基板１）では、第２厚み（Ｌ２）が、３ｎｍより大きく１５０ｎｍより小さいと好ましい。 In the conductive member (multilayer wiring board 1) of the eleventh aspect of the present disclosure, the second thickness (L2) is preferably greater than 3 nm and less than 150 nm.

　本開示の第１２の態様の導電部材（多層配線基板１）は、複数の第２導電線（１７）を備え、複数の第２導電線（１７）のうちの１つの厚み（Ｌ２）と、複数の第２導電線（１７）のうちの他の１つの厚み（Ｌ２）とは、互いに厚みが異なる。 The conductive member (multilayer wiring board 1) of the twelfth aspect of the present disclosure includes a plurality of second conductive wires (17), and the thickness (L2) of one of the plurality of second conductive wires (17) is different from the thickness (L2) of another of the plurality of second conductive wires (17).

　本開示の第１３の態様の導電部材（多層配線基板１）では、基板（３）が、第１層（５）の下に設けられたフィルム基材（４）を更に含む。 In the conductive member (multilayer wiring board 1) of the thirteenth aspect of the present disclosure, the substrate (3) further includes a film substrate (4) disposed under the first layer (5).

　本開示の第１４の態様の導電部材（多層配線基板１）では、基板（３）のフィルム基材（４）が、可撓性および光透過性を有する樹脂材料で形成されている。 In the conductive member (multilayer wiring board 1) of the fourteenth aspect of the present disclosure, the film base material (4) of the board (3) is formed from a resin material that is flexible and optically transparent.

　本開示の第１５の態様の導電部材（多層配線基板１）では、基板（３）の第１層（５）および基板（３）の第２層（６）が、絶縁性および光透過性を有する樹脂材料で形成されている。 In the conductive member (multilayer wiring board 1) of the fifteenth aspect of the present disclosure, the first layer (5) of the substrate (3) and the second layer (6) of the substrate (3) are formed of a resin material that is insulating and optically transparent.

　本開示の第１６の態様の導電部材（多層配線基板１）では、第１導電線（１３）の第１金属化合物層（密着層１３１）が、下方に向かって突出するように湾曲して形成されている。 In the conductive member (multilayer wiring board 1) of the sixteenth aspect of the present disclosure, the first metal compound layer (adhesion layer 131) of the first conductive line (13) is curved and formed so as to protrude downward.

　本開示の第１７の態様の導電部材（多層配線基板１）では、第２導電線（１７）の第２金属化合物層（密着層１７１）が、下方に向かって突出するように湾曲して形成されている。 In the conductive member (multilayer wiring board 1) of the seventeenth aspect of the present disclosure, the second metal compound layer (adhesion layer 171) of the second conductive line (17) is curved and formed so as to protrude downward.

　これらの態様によると、多層配線構造を有する導電部材において、配線抵抗を低減しつつ、配線を視認されにくくすることができる。 These aspects make it possible to reduce the wiring resistance in a conductive member having a multi-layer wiring structure while making the wiring less visible.

　本開示は、導電部材として産業上の利用が可能である。 This disclosure can be used industrially as a conductive material.

１：多層配線基板（導電部材）
２：実装素子
３：基板
４：フィルム基材
５：第１層
６：第２層
７：第１凹部
７ａ：底面（第１底面）
７ｂ：側面（第１側面）
７ｃ：隅角部
８：第２凹部
８ａ：底面（第２底面）
８ｂ：側面（第２側面）
８ｃ：隅角部
１０：第１導体パターン
１３：第１導電線
１３１：密着層（第１金属化合物層）
１３２：導電層（第１導電層）
１４：第２導体パターン
１７：第２導電線
１７１：密着層（第２金属化合物層）
１７２：導電層（第２導電層）
２０：重なりパターン
２１：接続領域
２２：ビア部
３０：ダミーパターン
３１：ダミー導電線
１００：凹部
１００Ａ：境界線
Ｐ：交点
Ｄ１：角度（第１角度）
Ｄ２：角度（第２角度）
Ｌ１：厚み（第１厚み）
Ｌ２：厚み（第２厚み）
Ｗ１：溝幅（第１溝幅）
Ｗ２：溝幅（第２溝幅） 1: Multilayer wiring board (conductive material)
2: Mounting element 3: Substrate 4: Film base material 5: First layer 6: Second layer 7: First recess 7a: Bottom surface (first bottom surface)
7b: Side (first side)
7c: Corner portion 8: Second recess 8a: Bottom surface (second bottom surface)
8b: Side (second side)
8c: Corner portion 10: First conductor pattern 13: First conductive line 131: Adhesion layer (first metal compound layer)
132: Conductive layer (first conductive layer)
14: second conductor pattern 17: second conductive line 171: adhesion layer (second metal compound layer)
172: Conductive layer (second conductive layer)
20: overlapping pattern 21: connection region 22: via portion 30: dummy pattern 31: dummy conductive line 100: recess 100A: boundary line P: intersection point D1: angle (first angle)
D2: Angle (second angle)
L1: Thickness (first thickness)
L2: Thickness (second thickness)
W1: Groove width (first groove width)
W2: Groove width (second groove width)

Claims (17)

　第１層と前記第１層の上方に設けられた第２層とを含み、透明性および光透過性を有する基板と、
　前記基板に設けられた凹部に配置された第１導電線と、
　前記第１導電線の上に位置し、前記基板の前記凹部に配置された第２導電線と、
を備え、
　前記第１導電線は、
　　　金属化合物からなる第１金属化合物層と、
　　　前記第１金属化合物層の上に形成され、導電性の金属からなる第１導電層と、
を含み、
　前記第１金属化合物層は、前記第１層における前記凹部の側面である第１側面に接し、
　前記第２導電線は、
　　　金属化合物からなる第２金属化合物層と、
　　　前記第２金属化合物層の上に形成され、導電性の金属からなる第２導電層と、
を含み、
　前記第２金属化合物層は、前記第２層における前記凹部の側面である第２側面に接し、
　前記第２層における前記凹部の溝幅である第２溝幅は、前記第１層における前記凹部の溝幅である第１溝幅よりも広く、
　前記第２側面と前記第１層の底面とのなす角度である第２角度は、前記第１側面と前記第１層の前記底面とのなす角度である第１角度よりも大きく、
　前記第２導電層の下端に接する部分における前記第２金属化合物層の厚みである第２厚みは、前記第１導電層の下端に接する部分における前記第１金属化合物層の厚みである第１厚みよりも厚い、
導電部材。 a substrate including a first layer and a second layer provided above the first layer, the substrate having transparency and light transmissibility;
A first conductive line disposed in a recess provided in the substrate;
a second conductive line overlying the first conductive line and disposed in the recess of the substrate;
Equipped with
The first conductive line is
a first metal compound layer made of a metal compound;
a first conductive layer formed on the first metal compound layer and made of a conductive metal;
Including,
the first metal compound layer is in contact with a first side surface that is a side surface of the recess in the first layer,
The second conductive line is
a second metal compound layer made of a metal compound;
a second conductive layer formed on the second metal compound layer and made of a conductive metal;
Including,
the second metal compound layer is in contact with a second side surface that is a side surface of the recess in the second layer,
a second groove width that is a groove width of the recess in the second layer is wider than a first groove width that is a groove width of the recess in the first layer;
a second angle between the second side surface and a bottom surface of the first layer is larger than a first angle between the first side surface and the bottom surface of the first layer;
a second thickness, which is a thickness of the second metal compound layer at a portion in contact with a lower end of the second conductive layer, is greater than a first thickness, which is a thickness of the first metal compound layer at a portion in contact with a lower end of the first conductive layer;
Conductive material. 　前記第２金属化合物層の一部の厚みは、上方に向かうにつれて連続的に変化する
導電部材。 A conductive member, wherein a thickness of a portion of the second metal compound layer changes continuously upward. 　請求項１に記載の導電部材において、
　前記第１溝幅は、０．３μｍ以上５０μｍ以下である、
導電部材。 The conductive member according to claim 1 ,
The first groove width is 0.3 μm or more and 50 μm or less.
Conductive material. 　請求項１に記載の導電部材において、
　前記基板には、複数の凹部が設けられ、
　前記複数の前記凹部のそれぞれは、前記凹部であり、
　前記複数の前記凹部のうちの１つの前記第１溝幅と、前記複数の前記凹部のうちの他の１つの前記第１溝幅とは、互いに幅が異なる、
導電部材。 The conductive member according to claim 1 ,
The substrate is provided with a plurality of recesses;
Each of the plurality of recesses is a recess,
The first groove width of one of the plurality of recesses and the first groove width of the other of the plurality of recesses are different from each other.
Conductive material. 　請求項１に記載の導電部材において、
　前記第２溝幅は、０．８μｍ以上５２．０μｍ以下である、
導電部材。 The conductive member according to claim 1 ,
The second groove width is 0.8 μm or more and 52.0 μm or less.
Conductive material. 　請求項１に記載の導電部材において、
　前記第１角度は、９０°より大きく１３５°より小さい、
導電部材。 The conductive member according to claim 1 ,
the first angle is greater than 90° and less than 135°;
Conductive material. 　請求項１に記載の導電部材において、
　前記基板には、複数の凹部が設けられ、
　前記複数の前記凹部のそれぞれは、前記凹部であり、
　前記複数の前記凹部うちの1つの前記第１角度と、前記複数の前記凹部のうちの他の1つの前記第１角度とは、互いに大きさが異なる、
導電部材。 The conductive member according to claim 1 ,
The substrate is provided with a plurality of recesses;
Each of the plurality of recesses is a recess,
The first angle of one of the plurality of recesses and the first angle of the other of the plurality of recesses are different in magnitude from each other.
Conductive material. 　請求項１に記載の導電部材において、
　前記第２角度は、９０°より大きく１３５°より小さい、
導電部材。 The conductive member according to claim 1 ,
The second angle is greater than 90° and less than 135°.
Conductive material. 　請求項１に記載の導電部材において、
　前記第１厚みは、３ｎｍより大きく１５０ｎｍより小さい、
導電部材。 The conductive member according to claim 1 ,
The first thickness is greater than 3 nm and less than 150 nm;
Conductive material. 　請求項１に記載の導電部材において、
　複数の第１導電線を備え、
　前記複数の前記第１導電線のそれぞれは、前記第１導電線であり、
　前記複数の前記第１導電線のうちの１つの厚みと、前記複数の前記第１導電線のうちの他の１つの厚みとは、互いに厚みが異なる、
導電部材。 The conductive member according to claim 1 ,
A plurality of first conductive lines;
each of the plurality of first conductive lines is a first conductive line,
a thickness of one of the plurality of first conductive wires and a thickness of another of the plurality of first conductive wires are different from each other;
Conductive material. 　請求項１に記載の導電部材において、
　前記第２厚みは、３ｎｍより大きく１５０ｎｍより小さい、
導電部材。 The conductive member according to claim 1 ,
The second thickness is greater than 3 nm and less than 150 nm;
Conductive material. 　請求項１に記載の導電部材において、
　複数の第２導電線を備え、
　前記複数の前記第２導電線のそれぞれは、前記第２導電線であり、
　前記複数の前記第２導電線のうちの１つの厚みと、前記複数の前記第２導電線のうちの他の１つの厚みとは、互いに厚みが異なる、
導電部材。 The conductive member according to claim 1 ,
a plurality of second conductive lines;
Each of the plurality of second conductive lines is a second conductive line,
a thickness of one of the plurality of second conductive wires and a thickness of another of the plurality of second conductive wires are different from each other;
Conductive material. 　請求項１～１２に記載の導電部材において、
　前記基板は、前記第１層の下に設けられたフィルム基材を更に含む、
導電部材。 The conductive member according to any one of claims 1 to 12,
The substrate further includes a film base provided under the first layer.
Conductive material. 　請求項１３に記載の導電部材において、
　前記基板の前記フィルム基材は、可撓性および光透過性を有する樹脂材料で形成されている、
導電部材。 The conductive member according to claim 13,
The film base material of the substrate is formed of a resin material having flexibility and optical transparency.
Conductive material. 　請求項１～１２に記載の導電部材において、
　前記基板の前記第１層および前記基板の前記第２層は、絶縁性および光透過性を有する樹脂材料で形成されている、
導電部材。 The conductive member according to any one of claims 1 to 12,
the first layer of the substrate and the second layer of the substrate are formed of a resin material having insulating properties and optical transparency;
Conductive material. 　請求項１～１２に記載の導電部材において、
　前記第１導電線の前記第１金属化合物層は、下方に向かって突出するように湾曲して形成されている、
導電部材。 The conductive member according to any one of claims 1 to 12,
the first metal compound layer of the first conductive wire is curved so as to protrude downward;
Conductive material. 　請求項１～１２に記載の導電部材において、
　前記第２導電線の前記第２金属化合物層は、下方に向かって突出するように湾曲して形成されている、
導電部材。 The conductive member according to any one of claims 1 to 12,
the second metal compound layer of the second conductive wire is curved so as to protrude downward;
Conductive material.
PCT/JP2024/020775 2023-07-10 2024-06-06 Conductive member Pending WO2025013484A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2023-112969 2023-07-10
JP2023112969 2023-07-10

Publications (1)

Publication Number Publication Date
WO2025013484A1 true WO2025013484A1 (en) 2025-01-16

Family

ID=94215467

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2024/020775 Pending WO2025013484A1 (en) 2023-07-10 2024-06-06 Conductive member

Country Status (1)

Country Link
WO (1) WO2025013484A1 (en)

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011141652A (en) * 2010-01-06 2011-07-21 Hitachi Chem Co Ltd Touch panel display device
US20110180309A1 (en) * 2010-01-26 2011-07-28 International Business Machines Corporation INTERCONNECT STRUCTURE EMPLOYING A Mn-GROUP VIIIB ALLOY LINER
JP2014519663A (en) * 2011-06-10 2014-08-14 ミレナノテク シーオー．，エルティーディー． Touch screen sensor substrate, touch screen sensor and panel including the same
US20140239504A1 (en) * 2013-02-28 2014-08-28 Hwei-Ling Yau Multi-layer micro-wire structure
WO2020149113A1 (en) * 2019-01-17 2020-07-23 Ｊｘｔｇエネルギー株式会社 Transparent electroconductive film
WO2021131319A1 (en) * 2019-12-25 2021-07-01 パナソニックＩｐマネジメント株式会社 Touch sensor
JP2023092093A (en) * 2021-12-21 2023-07-03 パナソニックＩｐマネジメント株式会社 Thin wire structure and touch sensor using it

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011141652A (en) * 2010-01-06 2011-07-21 Hitachi Chem Co Ltd Touch panel display device
US20110180309A1 (en) * 2010-01-26 2011-07-28 International Business Machines Corporation INTERCONNECT STRUCTURE EMPLOYING A Mn-GROUP VIIIB ALLOY LINER
JP2014519663A (en) * 2011-06-10 2014-08-14 ミレナノテク シーオー．，エルティーディー． Touch screen sensor substrate, touch screen sensor and panel including the same
US20140239504A1 (en) * 2013-02-28 2014-08-28 Hwei-Ling Yau Multi-layer micro-wire structure
WO2020149113A1 (en) * 2019-01-17 2020-07-23 Ｊｘｔｇエネルギー株式会社 Transparent electroconductive film
WO2021131319A1 (en) * 2019-12-25 2021-07-01 パナソニックＩｐマネジメント株式会社 Touch sensor
JP2023092093A (en) * 2021-12-21 2023-07-03 パナソニックＩｐマネジメント株式会社 Thin wire structure and touch sensor using it

Similar Documents

Publication Publication Date Title
KR101936939B1 (en) Touch sensor and image display device including the same
KR102453234B1 (en) Touch sensor and image display device including the same
JP7523030B2 (en) Touch Sensor
US12119531B2 (en) Signal transmission line comprising stacked insulating layers having a signal line and a ground conductor respectively spaced apart by a spacer with a hollow portion
KR101946721B1 (en) Display device
KR102539364B1 (en) Electronic device
CN118542091A (en) Display panel and display device
TWI842972B (en) Light emitting display device and method of manufacturing the same
WO2025013484A1 (en) Conductive member
KR20200091313A (en) Touch sensor and image display device including the same
TW201602879A (en) Touch panel
KR102819881B1 (en) Touch sensor and image display device including the same
TW201610773A (en) Touch panel
WO2025013485A1 (en) Conductive member
EP3933924A1 (en) Electronic device
US20170090108A1 (en) Planar illumination device
WO2025074895A1 (en) Electroconductive member
EP4601419A1 (en) Multilayer wiring substrate
TWM434987U (en) Single substrate flexible touch control sensor
CN219960931U (en) Copper circuit structure based on transparent substrate
JP2025163483A (en) Connection wiring board
JP2024122401A (en) Conductive Film
US11556215B2 (en) Touch sensor
CN120153432A (en) Conductive film
EP4554006A1 (en) Frequency selective surface

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 24839381

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 2025532442

Country of ref document: JP

Kind code of ref document: A

WWE Wipo information: entry into national phase

Ref document number: 2025532442

Country of ref document: JP