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WO2025004582A1 - Dispositif de détection de défaillance, dispositif d'imagerie à semi-conducteurs et procédé de détection de défaillance - Google Patents

Dispositif de détection de défaillance, dispositif d'imagerie à semi-conducteurs et procédé de détection de défaillance Download PDF

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Publication number
WO2025004582A1
WO2025004582A1 PCT/JP2024/017899 JP2024017899W WO2025004582A1 WO 2025004582 A1 WO2025004582 A1 WO 2025004582A1 JP 2024017899 W JP2024017899 W JP 2024017899W WO 2025004582 A1 WO2025004582 A1 WO 2025004582A1
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WIPO (PCT)
Prior art keywords
circuit
control lines
pixel
voltage
voltage divider
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English (en)
Japanese (ja)
Inventor
雄貴 樋口
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Sony Semiconductor Solutions Corp
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Sony Semiconductor Solutions Corp
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith

Definitions

  • This disclosure relates to a fault detection device, a solid-state imaging device, and a fault detection method.
  • driver failure detection in a solid-state imaging device is disclosed, for example, in Patent Document 1.
  • the failure detection device is a failure detection device in an imaging device including a plurality of pixels, a plurality of pixel control lines, and a drive circuit electrically connected to one end of each pixel control line and driving the plurality of pixels via the plurality of pixel control lines.
  • the failure detection device is electrically connected to the other end of each pixel control line.
  • the failure detection device includes a first resistive voltage divider circuit, a second resistive voltage divider circuit, a comparator, and a determination unit.
  • the first resistive voltage divider circuit is configured to be capable of dividing a Hi voltage applied to a first pixel control line among the plurality of pixel control lines.
  • the second resistive voltage divider circuit is configured to be capable of dividing a Lo voltage applied to the first pixel control line.
  • the comparator is capable of comparing either one of the first voltage generated by the first resistive voltage divider circuit and the second voltage generated by the second resistive voltage divider circuit with a reference voltage.
  • the determination unit is capable of determining a failure in the drive circuit and each pixel control line based on the result of the comparator.
  • the fault detection device is a fault detection device in an imaging device including a plurality of pixels, a plurality of control lines, and a control circuit electrically connected to each control line, the control circuit processing pixel signals output from the plurality of pixels, the control circuit controlling the control circuit via the plurality of control lines.
  • the fault detection device is electrically connected to each control line.
  • the fault detection device includes a first resistive voltage divider circuit, a second resistive voltage divider circuit, a comparator, and a determination unit.
  • the first resistive voltage divider circuit is capable of dividing a Hi voltage applied to a first control line of the plurality of control lines.
  • the second resistive voltage divider circuit is capable of dividing a Lo voltage applied to the first control line.
  • the comparator is capable of comparing either the first voltage generated by the first resistive voltage divider circuit or the second voltage generated by the second resistive voltage divider circuit with a reference voltage.
  • the determination unit is capable of determining faults in the control circuit and each control line based on the result of the comparator.
  • the imaging device includes a plurality of pixels, a plurality of pixel control lines, a drive circuit electrically connected to one end of each pixel control line and driving the plurality of pixels via the plurality of pixel control lines, and a fault detection circuit electrically connected to the other end of each pixel control line.
  • the fault detection circuit includes a first resistive voltage divider circuit, a second resistive voltage divider circuit, a comparator, and a determination unit.
  • the first resistive voltage divider circuit is configured to be capable of dividing a Hi voltage applied to a first pixel control line of the plurality of pixel control lines.
  • the second resistive voltage divider circuit is configured to be capable of dividing a Lo voltage applied to the first pixel control line.
  • the comparator is capable of comparing either one of the first voltage generated by the first resistive voltage divider circuit and the second voltage generated by the second resistive voltage divider circuit with a reference voltage.
  • the determination unit is capable of determining faults in the drive circuit and each pixel control line based on the result of the comparator.
  • the imaging device includes a plurality of pixels, a plurality of control lines, a control circuit connected to each control line, a control circuit that processes pixel signals output from the plurality of pixels, and a fault detection circuit electrically connected to each control line.
  • the fault detection circuit includes a first resistive voltage divider circuit, a second resistive voltage divider circuit, a comparator, and a determination unit.
  • the first resistive voltage divider circuit is capable of dividing a Hi voltage applied to a first control line of the plurality of control lines.
  • the second resistive voltage divider circuit is capable of dividing a Lo voltage applied to the first control line.
  • the comparator is capable of comparing either the first voltage generated by the first resistive voltage divider circuit or the second voltage generated by the second resistive voltage divider circuit with a reference voltage.
  • the determination unit is capable of determining faults in the control circuit and each control line based on the result of the comparator.
  • a failure detection method is a method executed by a failure detection device electrically connected to one end of each of the pixel control lines in an imaging device including a plurality of pixels, a plurality of pixel control lines, and a drive circuit electrically connected to the other end of each of the pixel control lines and driving the plurality of pixels via the plurality of pixel control lines.
  • a failure detection method is a method executed by a failure detection device electrically connected to each control line in an imaging device including a plurality of pixels, a plurality of control lines, and a control circuit electrically connected to each control line and controlling a control circuit via the plurality of control lines, the control circuit processing pixel signals output from the plurality of pixels.
  • This failure detection method includes the following four features.
  • FIG. 1 is a diagram illustrating an example of a schematic configuration of a solid-state imaging device according to a first embodiment of the present disclosure.
  • FIG. 2 is a diagram illustrating an example of a circuit configuration of the sensor pixel in FIG.
  • FIG. 3 is a diagram showing an example of a wiring layout of the pixel array unit in FIG. 1 and an example of a schematic configuration of the failure detection circuit in FIG.
  • FIG. 4 is a diagram showing an example of a schematic configuration of the failure detection circuit of FIG.
  • FIG. 5 is a diagram illustrating an example of the operation of the solid-state imaging device of FIG.
  • FIG. 6 is a diagram showing an example of the batch transfer of all rows in FIG.
  • FIG. 7 is a diagram showing an example of the row-by-row read operation in FIG. FIG.
  • FIG. 8 is a diagram showing an example of a fault detection target in the operation of FIG.
  • FIG. 9 is a diagram showing an example of fault detection during normal operation.
  • FIG. 10 is a diagram showing an example of failure detection when a high level abnormality occurs.
  • FIG. 11 is a diagram showing an example of failure detection when an abnormality occurs at Lo level.
  • FIG. 12 is a diagram showing a modified example of the circuit configuration of the vertical drive circuit in FIG.
  • FIG. 13 is a diagram showing a modification of the schematic configuration of the failure detection circuit of FIG.
  • FIG. 14 is a diagram showing a modification of the schematic configuration of the failure detection circuit of FIG.
  • FIG. 15 is a diagram illustrating an example of a schematic configuration of a solid-state imaging device according to the second embodiment of the present disclosure.
  • FIG. 16 is a diagram illustrating an example of a schematic configuration of the column signal processing circuit of FIG.
  • FIG. 17 is a diagram illustrating an example of a schematic configuration of the failure detection circuit of FIG.
  • FIG. 18 is a diagram showing a modification of the schematic configuration of the failure detection circuit of FIG.
  • FIG. 19 is a diagram showing a modification of the schematic configuration of the failure detection circuit of FIG.
  • FIG. 20 is a block diagram showing an example of a schematic configuration of a vehicle control system.
  • FIG. 21 is an explanatory diagram showing an example of the installation positions of the outside-of-vehicle information detection unit and the imaging unit.
  • a solid-state imaging device 1 according to a first embodiment of the present disclosure will be described.
  • the solid-state imaging device 1 is, for example, a global shutter type image sensor including a CMOS (Complementary Metal Oxide Semiconductor) image sensor or the like.
  • the solid-state imaging device 1 is capable of capturing an image by receiving light from a subject, photoelectrically converting the light, and generating an image signal.
  • the solid-state imaging device 1 is capable of outputting a pixel signal according to the incident light.
  • the global shutter method is a method of performing global exposure in which exposure basically starts and ends for all pixels at the same time.
  • all pixels means all pixels that appear in the image, excluding dummy pixels and the like.
  • the global shutter method also includes a method in which global exposure is performed in units of multiple rows (for example, several tens of rows) while moving the area in which global exposure is performed, rather than for all pixels at the same time.
  • the global shutter method also includes a method in which global exposure is performed on pixels in a specified area, rather than on all pixels that appear in the image.
  • the image sensor is, for example, a back-illuminated image sensor in which a photoelectric conversion unit such as a photodiode that receives light from the subject and converts it into an electrical signal is provided between a light receiving surface on which light from the subject is incident and a wiring layer on which wiring connected to transistors that drive each pixel is provided.
  • a photoelectric conversion unit such as a photodiode that receives light from the subject and converts it into an electrical signal is provided between a light receiving surface on which light from the subject is incident and a wiring layer on which wiring connected to transistors that drive each pixel is provided.
  • FIG. 1 shows an example of a schematic configuration of a solid-state imaging device 1 according to a first embodiment of the present disclosure.
  • the solid-state imaging device 1 is a stacked chip in which a first chip 100 having a pixel array section 10 and a second chip 200 having a logic circuit 20 are stacked.
  • the top surface of the first chip 100 is the light receiving surface.
  • the above-mentioned wiring layer is in contact with the top surface of the second chip 200.
  • the first chip 100 has a pixel array section 10 in which a plurality of sensor pixels 11 that perform photoelectric conversion are arranged in a matrix.
  • the sensor pixels 11 correspond to a specific example of a "pixel" according to an embodiment of the present disclosure.
  • FIG. 2 shows an example of a circuit configuration of the sensor pixels 11 and a readout circuit 12 (described later).
  • the sensor pixels 11 are arranged in a matrix on a semiconductor substrate (e.g., a silicon substrate).
  • the readout circuit 12 is arranged on the semiconductor substrate (e.g., a silicon substrate). Each readout circuit 12 is capable of outputting a pixel signal based on the charge output from the sensor pixel 11.
  • multiple readout circuits 12 are provided for every four sensor pixels 11.
  • the four sensor pixels 11 share one readout circuit 12.
  • “shared” means that the outputs of the four sensor pixels 11 are input to a common readout circuit 12.
  • the readout circuit 12 has, for example, a reset transistor Tr6, a selection transistor Tr7, and an amplification transistor Tr5.
  • the first chip 100 has a number of pixel control lines extending in the row direction and a number of data output lines VSL extending in the column direction.
  • the pixel control lines are wiring to which control signals that control the output of electric charges accumulated in the sensor pixels 11 are applied, and extend, for example, in the row direction.
  • the data output lines VSL are wiring that outputs pixel signals output from each readout circuit 12 to the logic circuit 20, and extend, for example, in the column direction.
  • the second chip 200 has a logic circuit 20 that processes pixel signals on a semiconductor substrate (e.g., a silicon substrate).
  • the logic circuit 20 has, for example, a vertical drive circuit 21, a column signal processing circuit 22, a horizontal drive circuit 23, a system control circuit 24, and a fault detection circuit 25, as shown in FIG. 1.
  • the logic circuit 20 (specifically, the horizontal drive circuit 23) is capable of outputting the output voltage of each sensor pixel 11 to the outside.
  • the fault detection circuit 25 is capable of outputting the fault detection results of the vertical drive circuit 21 and each pixel control line connected to the vertical drive circuit 21 to the outside.
  • the first chip 100 and the second chip 200 are provided with TCVs (Through Chip Vias) 26, 27, and 28, as shown in FIG. 1, for example, and the first chip 100 and the second chip 200 are electrically connected to each other via the TCVs 26, 27, and 28.
  • the TCV 26 is connected to a plurality of output terminals of the vertical drive circuit 21 provided in the second chip 200 and one end of a plurality of pixel control lines provided in the first chip 100.
  • the TCV 27 is connected to a plurality of input terminals of the column signal processing circuit 22 provided in the second chip 200 and a plurality of data output lines VSL provided in the first chip 100.
  • the TCV 28 is connected to a plurality of input terminals of the failure detection circuit 25 provided in the second chip 200 and the other end of a plurality of pixel control lines provided in the first chip 100. That is, one end of each of the pixel control lines is electrically connected to the vertical drive circuit 21, and the other end of each of the pixel control lines is electrically connected to the failure detection circuit 25.
  • the vertical drive circuit 21 is capable of, for example, sequentially selecting a plurality of sensor pixels 11 for each predetermined unit pixel row.
  • a "predetermined unit pixel row” refers to a pixel row for which pixels can be selected at the same address.
  • the layout of the plurality of sensor pixels 11 that share the readout circuit 12 is assumed to be 2 pixel rows by n pixel columns (n is an integer equal to or greater than 1).
  • the "predetermined unit pixel row” refers to two pixel rows.
  • the layout of the plurality of sensor pixels 11 that share the readout circuit 12 is 4 pixel rows by n pixel columns (n is an integer equal to or greater than 1)
  • the "predetermined unit pixel row” refers to four pixel rows.
  • the column signal processing circuit 22 can perform, for example, correlated double sampling (CDS) processing on the pixel signals output from each sensor pixel 11 of the row selected by the vertical drive circuit 21.
  • the column signal processing circuit 22 can extract the signal level of the pixel signal by performing, for example, CDS processing, and hold pixel data according to the amount of light received by each sensor pixel 11.
  • the column signal processing circuit 22 has, for example, a column signal processing section for each data output line VSL.
  • the column signal processing section includes, for example, a single-slope A/D converter.
  • the single-slope A/D converter includes, for example, a comparator and a counter circuit.
  • the horizontal drive circuit 23 sequentially outputs, for example, the pixel data held in the column signal processing circuit 22 to the outside.
  • the system control circuit 24 can, for example, control the driving of each block (the vertical drive circuit 21, the column signal processing circuit 22, the horizontal drive circuit 23, and the failure detection circuit 25) in the logic circuit 20.
  • Each sensor pixel 11 has components in common with the others.
  • each sensor pixel 11 has a photodiode PD, transfer transistors Tr1, Tr2, Tr3, charge holding units MEM1, MEM2, floating diffusion FD, and a discharge transistor Tr4.
  • the transfer transistors Tr1, Tr2, Tr3 and the discharge transistor Tr4 are, for example, NMOS (Metal Oxide Semiconductor) transistors.
  • the photodiode PD is capable of photoelectrically converting light incident through its light receiving surface.
  • the photodiode PD is capable of generating an electric charge according to the amount of light received by performing photoelectric conversion.
  • the photodiode PD is a PN junction photoelectric conversion element composed of an N-type semiconductor region and a P-type semiconductor region provided in a semiconductor substrate (e.g., a silicon substrate).
  • the cathode of the photodiode PD is electrically connected to the source of the transfer transistor Tr1, and the anode of the photodiode PD is electrically connected to a reference potential line (e.g., ground GND).
  • the transfer transistor Tr1 is connected between the photodiode PD and the transfer transistor Tr2, and is capable of transferring the charge stored in the photodiode PD to the transfer transistor Tr2 in response to a control signal applied to the gate electrode.
  • the transfer transistor Tr1 is capable of transferring charge from the photodiode PD to the charge holding unit MEM1.
  • the transfer transistor Tr1 has, for example, a vertical gate electrode.
  • the drain of the transfer transistor Tr1 is electrically connected to the source of the transfer transistor Tr2, and the gate of the transfer transistor Tr1 is connected to a pixel control line TRY (for example, TRY0 or TRY1).
  • the transfer transistor Tr2 is connected between the transfer transistors Tr1 and Tr3, and controls the potential of the charge holding unit MEM1 in response to a control signal applied to the gate electrode. For example, when the transfer transistor Tr2 is turned on, the potential of the charge holding unit MEM becomes deeper, and when the transfer transistor Tr2 is turned off, the potential of the charge holding unit MEM becomes shallower. Then, for example, when the transfer transistor Tr1 is turned on, the charge stored in the charge holding unit MEM1 is transferred to the charge holding unit MEM2 via the transfer transistor Tr2.
  • the drain of the transfer transistor Tr2 is electrically connected to the source of the transfer transistor Tr3, and the gate of the transfer transistor Tr2 is connected to a pixel control line TRX (for example, TRX0, TRX1, TRX2, or TRX3).
  • the charge holding units MEM1 and MEM2 are regions that temporarily hold the charge accumulated in the photodiode PD in order to realize the global shutter function.
  • the charge holding units MEM1 and MEM2 are capable of holding the charge transferred from the photodiode PD.
  • the transfer transistor Tr3 is connected between the transfer transistor Tr2 and the floating diffusion FD, and is capable of transferring the charge held in the charge holding unit MEM2 to the floating diffusion FD in response to a control signal applied to the gate electrode. For example, when the transfer transistor Tr2 is turned off and the transfer transistor Tr3 is turned on, the charge held in the charge holding unit MEM is transferred to the floating diffusion FD via the transfer transistors Tr2 and Tr3.
  • the drain of the transfer transistor Tr3 is electrically connected to the floating diffusion FD, and the gate of the transfer transistor Tr3 is connected to a pixel control line TRG (for example, TRG0, TRG1, TRG2, or TRG3).
  • the floating diffusion FD is a floating diffusion region that temporarily holds the charge output from the photodiode PD via the transfer transistor Tr3.
  • the reset transistor Tr6 is connected to the floating diffusion FD
  • the vertical signal line VSL is connected to the floating diffusion FD via the amplification transistor Tr5 and the selection transistor Tr7.
  • the drain of the discharge transistor Tr4 is connected to the power supply line VDD, and the source is connected between the photodiode PD and the transfer transistor Tr1.
  • the gate of the discharge transistor Tr4 is connected to the pixel control line OFG.
  • the discharge transistor Tr4 initializes (resets) the photodiode PD in response to a control signal applied to the gate electrode. For example, when the discharge transistor Tr4 is turned on, the potential of the photodiode PD is reset to the potential level of the power supply line VDD. In other words, the photodiode PD is initialized.
  • the drain of the reset transistor Tr6 is connected to the power supply line VDD, and the source is connected to the floating diffusion FD.
  • the gate of the reset transistor Tr6 is connected to a pixel control line RST.
  • the reset transistor RST initializes (resets) each area from the charge holding unit MEM1 to the floating diffusion FD in response to a control signal applied to the gate electrode. For example, when the transfer transistor Tr3 and the reset transistor Tr6 are turned on, the potentials of the charge holding units MEM1, MEM2, and the floating diffusion FD are reset to the potential level of the power supply line VDD. That is, the charge holding units MEM1, MEM2, and the floating diffusion FD are initialized.
  • the amplifier transistor Tr5 has a gate electrode connected to the floating diffusion FD and a drain connected to the power supply line VDD, and serves as the input of a source follower circuit that reads out the charge obtained by photoelectric conversion in the photodiode PD.
  • the amplifier transistor AMP has a source connected to the vertical signal line VSL via the selection transistor SEL, and thus forms a source follower circuit with a constant current source connected to one end of the vertical signal line VSL.
  • the selection transistor Tr7 is connected between the source of the amplification transistor Tr5 and the vertical signal line VSL, and a control signal is supplied as a selection signal to the gate electrode of the selection transistor Tr7.
  • the gate of the selection transistor Tr7 is connected to the pixel control line SEL.
  • the control signal is turned on, the selection transistor Tr7 becomes conductive, and the sensor pixel 11 connected to the selection transistor Tr7 becomes selected.
  • the sensor pixel 11 becomes selected, the pixel signal output from the amplification transistor Tr5 is read out to the column signal processing circuit 22 via the vertical signal line VSL.
  • FIG. 3 shows an example of the wiring layout of the pixel array section 10.
  • FIG. 3 illustrates pixel control lines OFG, TRY0, TRY1, TRX0, TRX1, TRX2, TRX3, TRG0, TRG1, TRG2, and TRG3 as examples of multiple pixel control lines connected to four sensor pixels 11 that share a floating diffusion FD.
  • FIG. 3 also illustrates RST and SEL as examples of multiple pixel control lines connected to a readout circuit 12 shared by the four sensor pixels 11.
  • Figure 4 shows an example of the circuit configuration of the failure detection circuit 25.
  • the failure detection circuit 25 has, for example, a selector 25A, a comparison unit 25B, and a determination unit 25C.
  • the multiple input terminals of the selector 25A are connected to one end of the multiple pixel control lines (OFG, TRY0, TRY1, TRX0, TRX1, TRX2, TRX3, TRG0, TRG1, TRG2, TRG3, RST, SEL).
  • One output terminal of the selector 25A is connected to one input terminal of the comparison unit 25B.
  • the selector 25A is capable of connecting any one of the multiple pixel control lines selected in accordance with the control signal ctl1 from the system control circuit 24 to the comparison unit 25B.
  • the comparison unit 25B has, for example, a selector 251, a resistive voltage divider circuit 252 for the Hi level, a resistive voltage divider circuit 253 for the Lo level, a selector 254, and a comparator 255.
  • a resistor voltage divider circuit 252 for a Hi level is connected to one of the two output terminals of the selector 251, and a resistor voltage divider circuit 253 for a Lo level is connected to the other output terminal.
  • the selector 251 is capable of connecting one of the two output terminals selected according to a control signal ctl2 from the system control circuit 24 to the input terminal.
  • the voltage of the Hi-level output terminal is the voltage VH (Hi voltage) of the pixel control line selected by the selector 25A.
  • the voltage of the Lo-level output terminal is the voltage VL (Lo voltage) of the pixel control line selected by the selector 25A.
  • the high-level resistive voltage divider circuit 252 is composed of two resistive elements R1 and R2 connected in series to one output terminal of the selector 251, as shown in FIG. 4, for example.
  • the connection node between the resistive elements R1 and R2 is connected to one of the two input terminals of the selector 254.
  • the end of the resistive element R2 that is not connected to the resistive element R1 is electrically connected to, for example, a reference potential line (e.g., ground GND).
  • the Lo level resistive voltage divider circuit 253 is composed of two resistive elements R3 and R4 connected in series to the other output terminal of the selector 251, as shown in FIG. 4, for example.
  • the connection node between the resistive elements R3 and R4 is connected to the other of the two input terminals of the selector 254.
  • the end of the resistive element R3 that is not connected to the resistive element R4 is electrically connected to the power supply line VDD, for example.
  • One of the two input terminals of the selector 254 is connected to a connection node between the resistor elements R1 and R2, and the other input terminal is connected to a connection node between the resistor elements R3 and R4.
  • One of the input terminals of the comparator 255 is connected to one output terminal of the selector 254.
  • the selector 254 can connect one of the two input terminals selected according to the control signal ctl3 from the system control circuit 24 to the output terminal.
  • the voltage of the output terminal of the selector 254 is VH ⁇ (R2/(R1+R2)).
  • the voltage of the output terminal of the selector 254 is (VDD-VL) ⁇ (R4/(R3+R4)).
  • comparator 255 One input end of comparator 255 is connected to the output end of selector 254, and the other input end of comparator 255 is connected to a resistive voltage divider circuit.
  • the output voltage (voltage Vin) of selector 254 is input to one input end of comparator 255.
  • the resistive voltage divider circuit connected to the other input end of comparator 255 is composed of two resistive elements R5 and R6 connected in series between the power supply line VDD and a reference potential line (e.g., ground GND). The connection node between resistive elements R5 and R6 is connected to the other input end of comparator 255.
  • V_GND indicates, for example, the potential of ground GND.
  • the comparator 255 is capable of outputting a Hi-level voltage when the difference (Vin-Vref) between the voltage at one input terminal (voltage Vin) and the voltage at the other input terminal (reference voltage Vref) is 0 or positive.
  • the comparator 255 is capable of outputting a Lo-level voltage when the difference (Vin-Vref) is negative.
  • the determination unit 25C is capable of determining whether there is a fault in the vertical drive circuit 21 and in a plurality of pixel control lines connected to the vertical drive circuit 21, based on the output of the comparator 255.
  • the determination unit 25C is configured to include, for example, a CPU (central processing unit).
  • the judgment unit 25C is capable of judging that the vertical drive circuit 21 and the pixel control line selected by the selector 25A are normal at the Hi level.
  • the judgment unit 25C is capable of judging that the vertical drive circuit 21 and the pixel control line selected by the selector 25A are normal at the Lo level.
  • the judgment unit 25C is capable of judging that at least one of the vertical drive circuit 21 and the pixel control line selected by the selector 25A is abnormal at the Hi level.
  • the judgment unit 25C is capable of judging that at least one of the vertical drive circuit 21 and the pixel control line selected by the selector 25A is abnormal at the Lo level.
  • FIG. 5 shows an example of the operation of the solid-state imaging device 1.
  • Fig. 6 shows an example of the batch transfer of all rows in Fig. 5.
  • Fig. 7 shows an example of the row-by-row readout operation in Fig. 5.
  • the solid-state imaging device 1 performs a batch transfer of all rows, a row-by-row readout operation, and blanking in that order.
  • the solid-state imaging device 1 resets the charge holding units MEM1, MEM2 and the floating diffusion FD in each sensor pixel 11, and then transfers charge from the photodiode PD to the charge holding units MEM1, MEM2 in each sensor pixel 11.
  • the solid-state imaging device 1 sequentially transfers the charges stored in the charge holding units MEM1 and MEM2 of the four sensor pixels 11 that share the floating diffusion FD to the floating diffusion FD. At this time, as shown in FIG. 7, for example, the solid-state imaging device 1 outputs the charges transferred to the floating diffusion FD to the data output line VSL every time it transfers charges to the floating diffusion FD. Then, as shown in FIG. 7, for example, the solid-state imaging device 1 resets the floating diffusion FD before the next charge transfer.
  • the failure detection circuit 25 detects failures in the vertical drive circuit 21 and all pixel control lines, for example, during a period when all-row batch transfer is being performed.
  • the failure detection circuit 25, for example, divides all pixel control lines into multiple groups and detects failures in multiple pixel control lines for each group. For example, as shown in FIG. 8, the failure detection circuit 25 divides all pixel control lines into three groups and detects failures in multiple pixel control lines L(1) to L(N/3) belonging to the first group during a certain frame period. Then, the failure detection circuit 25 detects failures in multiple pixel control lines L(N/3+1) to L(2N/3) belonging to the second group during the next frame period, for example, as shown in FIG. 8.
  • the failure detection circuit 25 detects failures in multiple pixel control lines L(2N/3+1) to L(N) belonging to the third group during the next frame period, for example, as shown in FIG. 8.
  • G in FIG. 8 represents the period during which all rows are transferred at once
  • R in FIG. 8 represents the period during which row-by-row readout is performed
  • B represents the blanking period.
  • the failure detection circuit 25 detects failures in the vertical drive circuit 21 and all pixel control lines, for example, during the period when the row-by-row readout operation is being performed. For example, as shown in FIG. 8, the failure detection circuit 25 detects failures in the pixel control line selected by the row-by-row readout operation each time the pixel control line is selected by the row-by-row readout operation.
  • the judgment unit 25C judges that it is the timing to detect the Lo level during the all-row batch transfer.
  • the judgment unit 25C judges that the vertical drive circuit 21 and the pixel control line selected by the selector 25A are normal at the Lo level.
  • the judgment unit 25C judges that it is the timing to detect the Hi level in the row-by-row readout operation.
  • the judgment unit 25C judges that the vertical drive circuit 21 and the pixel control line selected by the selector 25A are normal at the Hi level.
  • the judgment unit 25C judges that it is the timing to detect the Lo level in the row-by-row readout operation.
  • the judgment unit 25C judges that the vertical drive circuit 21 and the pixel control line selected by the selector 25A are normal at the Lo level.
  • the judgment unit 25C judges that it is the Hi-level detection timing for the all-row batch transfer.
  • the judgment unit 25C judges that at least one of the vertical drive circuit 21 and the pixel control line selected by the selector 25A is abnormal at the Hi level.
  • the judgment unit 25C judges that it is the timing to detect the Lo level in the all-row batch transfer.
  • the judgment unit 25C judges that the vertical drive circuit 21 and the pixel control line selected by the selector 25A are normal at the Lo level.
  • the judgment unit 25C judges that it is the timing to detect the Hi level in the row-by-row readout operation.
  • the judgment unit 25C judges that at least one of the vertical drive circuit 21 and the pixel control line selected by the selector 25A is abnormal at the Hi level.
  • the judgment unit 25C judges that it is the timing to detect the Lo level in the row-by-row readout operation.
  • the judgment unit 25C judges that the vertical drive circuit 21 and the pixel control line selected by the selector 25A are normal at the Lo level.
  • the judgment unit 25C judges that it is the timing to detect the Hi level in the all-row batch transfer.
  • the judgment unit 25C judges that the vertical drive circuit 21 and the pixel control line selected by the selector 25A are normal at the Hi level.
  • the judgment unit 25C judges that it is the timing to detect the Lo level in the all-row batch transfer.
  • the judgment unit 25C judges that at least one of the vertical drive circuit 21 and the pixel control line selected by the selector 25A is abnormal at the Lo level.
  • the judgment unit 25C judges that it is the Hi-level detection timing for the row-by-row readout operation.
  • the judgment unit 25C judges that the vertical drive circuit 21 and the pixel control line selected by the selector 25A are normal at the Hi level.
  • the judgment unit 25C judges that it is the timing to detect the Lo level in the row-by-row readout operation.
  • the judgment unit 25C judges that at least one of the vertical drive circuit 21 and the pixel control line selected by the selector 25A is abnormal at the Lo level.
  • the failure detection device 25 is electrically connected to the other end of each pixel control line.
  • the Hi voltage (VH) applied to the selected pixel control line is divided by the resistive voltage divider circuit 252, and the Lo voltage (VL) applied to the selected pixel control line is divided by the resistive voltage divider circuit 253.
  • Either the voltage Vin generated by the resistive voltage divider circuit 252 or the voltage generated by the resistive voltage divider circuit 253 is compared with the reference voltage Vref by the comparator 255. Then, the failure detection circuit 25 judges the failure of the vertical drive circuit 21 based on the result of the comparator 255. This allows Hi-level failure detection and Lo-level failure detection to be performed for the vertical drive circuit 21. Also, Hi-level failure detection and Lo-level failure detection can be performed for the selected pixel control line.
  • selectors 251 and 254 are provided in the failure detection device 25. This allows either the voltage Vin generated by the resistive voltage divider circuit 252 or the voltage generated by the resistive voltage divider circuit 253 to be input to the comparator 255. This allows for Hi-level failure detection and Lo-level failure detection for the vertical drive circuit 21. In addition, Hi-level failure detection and Lo-level failure detection can be performed for the selected pixel control line.
  • a selector 25A is provided in the failure detection device 25. This allows one pixel control line to be selected from multiple pixel control lines when transferring all rows at once, making it possible to perform failure detection for each pixel control line when transferring all rows at once.
  • Fig. 12 shows a modified example of the circuit configuration of the vertical drive circuit 21.
  • the vertical drive circuit 21 may have, for example, a drive circuit 21a for batch transfer of all rows and a drive circuit 21b for row-by-row readout operation, as shown in Fig. 12.
  • the drive circuit 21a for example, has one driver DRa(k) for each pixel row 12(k) (1 ⁇ k ⁇ N; N is the number of unit pixel rows in the pixel array section 10). In the drive circuit 21a, each driver DRa(k) is driven simultaneously by a common control line.
  • the drive circuit 21b for example, has one driver DRb(k) for each pixel row 12(k). In the drive circuit 21b, each driver DRb(k) is driven independently by a control line assigned to each driver DRb(k).
  • Fig. 13 shows a modified circuit configuration of the failure detection circuit 25.
  • the resistance elements R5 and R6 may each be a variable resistor, for example, as shown in Fig. 13.
  • the system control circuit 24 may be able to set the resistance values of the resistance elements R5 and R6 to predetermined resistance values, for example, by inputting a control signal ctl4 that sets the resistance value of the resistance elements R5 and R6.
  • the resistance element R5 can be changed to a resistance value, for example, 10% smaller than the normal resistance value.
  • the resistance element R6 can be changed to a resistance value, for example, 10% smaller than the normal resistance value.
  • the system control circuit 24 inputs a control signal to the resistance element R5 to set the resistance value to a value, for example, 10% smaller than the normal resistance value, and inputs a control signal to the resistance element R6 to set the resistance value to the normal resistance value.
  • the reference voltage Vref becomes a voltage value that is slightly larger than when both the resistance elements R5 and R6 are at their normal resistance values.
  • the system control circuit 24 inputs a control signal to the resistance element R5 to set the resistance value to the normal resistance value, and inputs a control signal to the resistance element R6 to set the resistance value to a value, for example, 10% smaller than the normal resistance value.
  • the reference voltage Vref becomes a voltage value that is slightly smaller than when both the resistance elements R5 and R6 are at their normal resistance values.
  • variable resistors for the resistive elements R5 and R6 it is possible to set the reference voltage Vref to a slightly larger or smaller value. This makes it possible to detect slight fluctuations in the value of the voltage Vin, and therefore to detect whether there is a defect in at least one of the vertical drive circuit 21 and the pixel control line that causes slight fluctuations in the value of the voltage Vin.
  • the failure detection circuit 25 may have a selector 256 and a resistor tap 257 instead of the resistor elements R5 and R6, as shown in FIG. 14, for example.
  • the resistor tap 257 is a resistor tap in which a plurality of resistor elements are connected in series.
  • a plurality of wirings are connected to the plurality of input terminals of the selector 256, one for each connection point of two resistor elements in the resistor tap 257.
  • the output terminal of the selector 256 is connected to one input terminal of the comparator 255.
  • the system control circuit 24 may input a control signal ctl4 to the selector 256, thereby making it possible to cause the selector 256 to select one of the plurality of input terminals.
  • the reference voltage Vref can be set to a slightly larger value or a slightly smaller value. This makes it possible to detect a slight fluctuation in the value of the voltage Vin, and therefore it is possible to detect whether or not there is a defect that causes a slight fluctuation in the value of the voltage Vin in at least one of the vertical drive circuit 21 and the pixel control line.
  • the solid-state imaging device 2 is, for example, a global shutter type image sensor including a CMOS image sensor or the like.
  • the solid-state imaging device 2 is capable of capturing an image by receiving light from a subject, photoelectrically converting the light, and generating an image signal.
  • the solid-state imaging device 2 is capable of outputting a pixel signal according to the incident light.
  • FIG. 15 shows an example of a schematic configuration of a solid-state imaging device 2 according to a second embodiment of the present disclosure.
  • the solid-state imaging device 2 is a stacked chip in which a first chip 100 having a pixel array section 10 and a second chip 300 having a logic circuit 30 are stacked.
  • the upper surface of the first chip 100 is the light receiving surface.
  • the data output line VSL is a wiring that outputs pixel signals output from each readout circuit 12 to the logic circuit 30, and extends, for example, in the column direction.
  • the second chip 300 has a logic circuit 30 for processing pixel signals on a semiconductor substrate (e.g., a silicon substrate).
  • the logic circuit 30 has, for example, a vertical drive circuit 21, a column signal processing circuit 22, a horizontal drive circuit 23, a system control circuit 24, and a fault detection circuit 29, as shown in FIG. 15.
  • the logic circuit 30 (specifically, the horizontal drive circuit 23) is capable of outputting the output voltage of each sensor pixel 11 to the outside.
  • the fault detection circuit 29 is capable of outputting the fault detection results of the column signal processing circuit 22 and each control line connected to the column signal processing circuit 22 to the outside.
  • the first chip 100 and the second chip 300 are provided with TCVs 26 and 27, as shown in FIG. 15, for example, and the first chip 100 and the second chip 300 are electrically connected to each other via the TCVs 26 and 27.
  • the TCV 26 is connected to a plurality of output terminals of the vertical drive circuit 21 provided in the second chip 300 and one end of a plurality of pixel control lines provided in the first chip 100.
  • the TCV 27 is connected to a plurality of input terminals of the column signal processing circuit 22 provided in the second chip 300 and a plurality of data output lines VSL provided in the first chip 100.
  • the column signal processing circuit 22 has a DAC 221, for example, as shown in FIG. 16, and has a column signal processing section 22A for each data output line VSL.
  • the column signal processing section 22A includes, for example, a single-slope A/D converter.
  • the column signal processing section 22A includes, for example, a comparator 222, a counter 223, and a buffer 224.
  • the comparator 222 is capable of comparing the pixel signal obtained from the sensor pixel 11 via the data output line VSL with the ramp voltage supplied from the DAC 221 based on the comparison control signal supplied from the system control circuit 24.
  • the comparator 222 is further capable of outputting the comparison result as binary data to the counter 223.
  • the comparison control signal is input to the comparator 222 by a control line CTL1 connected to the system control circuit 24.
  • the counter 223 is capable of performing a counting operation based on a count control signal supplied from the system control circuit 24.
  • the counter 223 performs a counting operation, for example, until the comparison result (binary data) is inverted, and is capable of outputting a digital signal indicating the count value obtained as a result to the buffer 224.
  • the count control signal is input to the counter 223 by a control line CTL2 connected to the system control circuit 24.
  • the buffer 224 is used to control the output to the horizontal drive circuit 23, and includes, for example, a latch circuit, and is capable of outputting the digital signal input from the counter 223 to the horizontal drive circuit 23 based on a selection signal from the horizontal drive circuit 23.
  • the system control circuit 24 may be connected to a control line other than the above-mentioned control lines CTL1 and CTL2, for example. If the column signal processing unit 22A has a selector connected to multiple data output lines VSL, for example, the system control circuit 24 may be connected to a control line to which a selection signal for this selector is applied. Also, the system control circuit 24 may be connected to a control line to which a control signal that controls the auto-zero of the comparator 222 is applied, for example.
  • control lines other than the above-mentioned control lines CTL1 and CTL2 are connected to the system control circuit 24, these control lines may be connected to the selector 29A in the same way as the above-mentioned control lines CTL1 and CTL2.
  • FIG. 17 shows an example of the circuit configuration of the failure detection circuit 29.
  • the failure detection circuit 29 has, for example, a selector 29A, a comparison unit 29B, and a determination unit 29C.
  • One end of a plurality of control lines (CTL1, CTL2, etc.) is connected to the multiple input terminals of the selector 29A.
  • One input terminal of the comparator 29B is connected to one output terminal of the selector 29A.
  • the selector 29A is capable of connecting any one of the multiple control lines selected according to the control signal ctl1 from the system control circuit 24 to the comparator 29B.
  • the comparison unit 29B has, for example, a selector 291, a resistive voltage divider circuit 292 for the Hi level, a resistive voltage divider circuit 293 for the Lo level, a selector 294, and a comparator 295.
  • a resistor voltage divider circuit 292 for a Hi level is connected to one of the two output terminals of the selector 291, and a resistor voltage divider circuit 293 for a Lo level is connected to the other output terminal.
  • the selector 291 is capable of connecting one of the two output terminals selected according to a control signal ctl2 from the system control circuit 24 to the input terminal.
  • the Hi-level output terminal of the two output terminals of the selector 291 is selected by the selector 291
  • the voltage of the Hi-level output terminal is the voltage VH of the control line selected by the selector 29A.
  • the voltage of the Lo-level output terminal is the voltage VL of the control line selected by the selector 29A.
  • the high-level resistive voltage divider circuit 292 is composed of two resistive elements R1 and R2 connected in series to one output terminal of the selector 291, as shown in FIG. 17, for example.
  • the connection node between the resistive elements R1 and R2 is connected to one of the two input terminals of the selector 294.
  • the end of the resistive element R2 that is not connected to the resistive element R1 is electrically connected to, for example, a reference potential line (for example, ground GND).
  • the Lo level resistive voltage divider circuit 293 is composed of two resistive elements R3 and R4 connected in series to the other output terminal of the selector 291, as shown in FIG. 17, for example.
  • the connection node between the resistive elements R3 and R4 is connected to the other of the two input terminals of the selector 294.
  • the end of the resistive element R3 that is not connected to the resistive element R4 is electrically connected to the power supply line VDD, for example.
  • One of the two input terminals of the selector 294 is connected to a connection node between the resistor elements R1 and R2, and the other input terminal is connected to a connection node between the resistor elements R3 and R4.
  • One of the input terminals of the comparator 295 is connected to one output terminal of the selector 294.
  • the selector 294 can connect one of the two input terminals selected according to the control signal ctl3 from the system control circuit 24 to the output terminal.
  • the voltage of the output terminal of the selector 294 is VH ⁇ (R2/(R1+R2)).
  • the voltage of the output terminal of the selector 294 is (VDD-VL) ⁇ (R4/(R3+R4)).
  • the output terminal of selector 294 is connected to one input terminal of comparator 295, and a resistive voltage divider circuit is connected to the other input terminal of comparator 295.
  • the output voltage (voltage Vin) of selector 294 is input to one input terminal of comparator 295.
  • the resistive voltage divider circuit connected to the other input terminal of comparator 295 is composed of two resistive elements R5 and R6 connected in series between the power supply line VDD and a reference potential line (e.g., ground GND).
  • the connection node between resistive elements R5 and R6 is connected to the other input terminal of comparator 295.
  • V_GND indicates, for example, the potential of ground GND.
  • the comparator 295 is capable of outputting a Hi-level voltage when the difference (Vin-Vref) between the voltage at one input terminal (voltage Vin) and the voltage at the other input terminal (reference voltage Vref) is 0 or positive.
  • the comparator 295 is capable of outputting a Lo-level voltage when the difference (Vin-Vref) is negative.
  • the determination unit 29C is capable of determining whether or not there is a fault in the system control circuit 24 and in a plurality of control lines (e.g., CTL1, CTL2) connected to the system control circuit 24 based on the output of the comparator 295.
  • the determination unit 29C is configured to include, for example, a CPU.
  • the judgment unit 29C is capable of judging that the system control circuit 24 and the control line selected by the selector 29A are normal at the Hi level.
  • the judgment unit 29C is capable of judging that the system control circuit 24 and the control line selected by the selector 29A are normal at the Lo level.
  • the judgment unit 29C is capable of judging that at least one of the system control circuit 24 and the control line selected by the selector 29A is abnormal at the Hi level.
  • the judgment unit 29C is capable of judging that at least one of the system control circuit 24 and the control line selected by the selector 29A is abnormal at the Lo level.
  • the determination unit 29C has the same functions as the determination unit 25C in the above embodiment.
  • the operation of the solid-state imaging device 2 is the same as the operation of the solid-state imaging device 1 in the above embodiment, except for the fact that the object of failure detection is different.
  • the fault detection device 29 is electrically connected to each control line.
  • the Hi voltage (VH) applied to the selected control line is divided by the resistive voltage divider circuit 292, and the Lo voltage (VL) applied to the selected control line is divided by the resistive voltage divider circuit 293.
  • Either the voltage Vin generated by the resistive voltage divider circuit 292 or the voltage generated by the resistive voltage divider circuit 293 is compared with the reference voltage Vref by the comparator 295. Then, based on the result of the comparator 295, the fault detection circuit 29 judges whether the system control circuit 24 and the multiple control lines connected to the system control circuit 24 have a fault. This allows for Hi-level fault detection and Lo-level fault detection for the system control circuit 24. Also, for the selected control line, Hi-level fault detection and Lo-level fault detection can be performed.
  • selectors 291 and 294 are provided in the fault detection device 29. This allows either the voltage Vin generated by the resistive voltage divider circuit 292 or the voltage generated by the resistive voltage divider circuit 293 to be input to the comparator 295. This allows Hi-level fault detection and Lo-level fault detection for the system control circuit 24. In addition, Hi-level fault detection and Lo-level fault detection can be performed for the selected control line.
  • a selector 29A is provided in the failure detection device 29. This makes it possible to select one pixel control line from among the multiple control lines when all the control lines are used simultaneously, so that failure detection can be performed for each control line when all the control lines are used simultaneously.
  • Fig. 18 shows a modified circuit configuration of the failure detection circuit 29.
  • the resistive elements R5 and R6 may each be a variable resistor, for example, as shown in Fig. 18.
  • the system control circuit 24 may be able to set the resistance values of the resistive elements R5 and R6 to predetermined resistance values, for example, by inputting a control signal that sets the resistance value to the resistive elements R5 and R6.
  • the resistance element R5 can be changed to a resistance value, for example, 10% smaller than the normal resistance value.
  • the resistance element R6 can be changed to a resistance value, for example, 10% smaller than the normal resistance value.
  • the system control circuit 24 inputs a control signal to the resistance element R5 to set the resistance value to a value, for example, 10% smaller than the normal resistance value, and inputs a control signal to the resistance element R6 to set the resistance value to the normal resistance value.
  • the reference voltage Vref becomes a voltage value that is slightly larger than when both the resistance elements R5 and R6 are at their normal resistance values.
  • the system control circuit 24 inputs a control signal to the resistance element R5 to set the resistance value to the normal resistance value, and inputs a control signal to the resistance element R6 to set the resistance value to a value, for example, 10% smaller than the normal resistance value.
  • the reference voltage Vref becomes a voltage value that is slightly smaller than when both the resistance elements R5 and R6 are at their normal resistance values.
  • variable resistors for the resistive elements R5 and R6 it is possible to set the reference voltage Vref to a slightly larger value or a slightly smaller value. This makes it possible to detect slight fluctuations in the value of the voltage Vin, and therefore to detect whether there is a defect in at least one of the system control circuit 24 and the control line that causes slight fluctuations in the value of the voltage Vin.
  • the failure detection circuit 25 may have a selector 296 and a resistor tap 297 instead of the resistor elements R5 and R6, as shown in FIG. 19.
  • the resistor tap 297 is a resistor tap in which a plurality of resistor elements are connected in series.
  • a plurality of wirings are connected to the plurality of input terminals of the selector 296, one for each connection point of two resistor elements in the resistor tap 297.
  • the output terminal of the selector 296 is connected to one input terminal of the comparator 295.
  • the system control circuit 24 may input a control signal ctl4 to the selector 296, thereby making it possible to cause the selector 296 to select one of the plurality of input terminals.
  • the reference voltage Vref can be set to a slightly larger value or a slightly smaller value. This makes it possible to detect a slight fluctuation in the value of the voltage Vin, and therefore it is possible to detect whether or not there is a defect that causes a slight fluctuation in the value of the voltage Vin in at least one of the vertical drive circuit 21 and the pixel control line.
  • the technology according to the present disclosure can be applied to various products.
  • the technology according to the present disclosure may be realized as a device mounted on any type of moving body, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, a personal mobility device, an airplane, a drone, a ship, a robot, a construction machine, or an agricultural machine (tractor).
  • FIG. 20 is a block diagram showing a schematic configuration example of a vehicle control system 7000, which is an example of a mobile control system to which the technology disclosed herein can be applied.
  • the vehicle control system 7000 includes a plurality of electronic control units connected via a communication network 7010.
  • the vehicle control system 7000 includes a drive system control unit 7100, a body system control unit 7200, a battery control unit 7300, an outside vehicle information detection unit 7400, an inside vehicle information detection unit 7500, and an integrated control unit 7600.
  • the communication network 7010 connecting these multiple control units may be, for example, an in-vehicle communication network conforming to any standard such as CAN (Controller Area Network), LIN (Local Interconnect Network), LAN (Local Area Network), or FlexRay (registered trademark).
  • CAN Controller Area Network
  • LIN Local Interconnect Network
  • LAN Local Area Network
  • FlexRay registered trademark
  • Each control unit includes a microcomputer that performs arithmetic processing according to various programs, a storage unit that stores the programs executed by the microcomputer or parameters used in various calculations, and a drive circuit that drives various devices to be controlled.
  • Each control unit includes a network I/F for communicating with other control units via a communication network 7010, and a communication I/F for communicating with devices or sensors inside and outside the vehicle by wired or wireless communication.
  • the functional configuration of the integrated control unit 7600 includes a microcomputer 7610, a general-purpose communication I/F 7620, a dedicated communication I/F 7630, a positioning unit 7640, a beacon receiving unit 7650, an in-vehicle device I/F 7660, an audio/image output unit 7670, an in-vehicle network I/F 7680, and a storage unit 7690.
  • Other control units also include a microcomputer, a communication I/F, a storage unit, and the like.
  • the drive system control unit 7100 controls the operation of devices related to the drive system of the vehicle according to various programs.
  • the drive system control unit 7100 functions as a control device for a drive force generating device for generating a drive force for the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a braking force for the vehicle.
  • the drive system control unit 7100 may also function as a control device such as an ABS (Antilock Brake System) or ESC (Electronic Stability Control).
  • the drive system control unit 7100 is connected to a vehicle state detection unit 7110.
  • the vehicle state detection unit 7110 includes at least one of a gyro sensor that detects the angular velocity of the axial rotational motion of the vehicle body, an acceleration sensor that detects the acceleration of the vehicle, or a sensor for detecting the amount of operation of the accelerator pedal, the amount of operation of the brake pedal, the steering angle of the steering wheel, the engine speed, or the rotation speed of the wheels, etc.
  • the drive system control unit 7100 performs arithmetic processing using the signal input from the vehicle state detection unit 7110, and controls the internal combustion engine, the drive motor, the electric power steering device, the brake device, etc.
  • the body system control unit 7200 controls the operation of various devices installed in the vehicle body according to various programs.
  • the body system control unit 7200 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as headlamps, tail lamps, brake lamps, turn signals, and fog lamps.
  • radio waves or signals from various switches transmitted from a portable device that replaces a key can be input to the body system control unit 7200.
  • the body system control unit 7200 accepts the input of these radio waves or signals and controls the vehicle's door lock device, power window device, lamps, etc.
  • the battery control unit 7300 controls the secondary battery 7310, which is the power supply source for the drive motor, according to various programs. For example, information such as the battery temperature, battery output voltage, or remaining capacity of the battery is input to the battery control unit 7300 from a battery device equipped with the secondary battery 7310. The battery control unit 7300 performs calculations using these signals, and controls the temperature regulation of the secondary battery 7310 or a cooling device or the like equipped in the battery device.
  • the outside vehicle information detection unit 7400 detects information outside the vehicle equipped with the vehicle control system 7000.
  • the imaging unit 7410 and the outside vehicle information detection unit 7420 is connected to the outside vehicle information detection unit 7400.
  • the imaging unit 7410 includes at least one of a ToF (Time Of Flight) camera, a stereo camera, a monocular camera, an infrared camera, and other cameras.
  • the outside vehicle information detection unit 7420 includes at least one of an environmental sensor for detecting the current weather or climate, or a surrounding information detection sensor for detecting other vehicles, obstacles, pedestrians, etc., around the vehicle equipped with the vehicle control system 7000.
  • the environmental sensor may be, for example, at least one of a raindrop sensor that detects rain, a fog sensor that detects fog, a sunshine sensor that detects the level of sunlight, and a snow sensor that detects snowfall.
  • the surrounding information detection sensor may be at least one of an ultrasonic sensor, a radar device, and a LIDAR (Light Detection and Ranging, Laser Imaging Detection and Ranging) device.
  • the imaging unit 7410 and the outside vehicle information detection unit 7420 may each be provided as an independent sensor or device, or may be provided as a device in which multiple sensors or devices are integrated.
  • FIG. 21 shows an example of the installation positions of the imaging unit 7410 and the outside vehicle information detection unit 7420.
  • the imaging units 7910, 7912, 7914, 7916, and 7918 are provided, for example, at least one of the front nose, side mirrors, rear bumper, back door, and the upper part of the windshield inside the vehicle cabin of the vehicle 7900.
  • the imaging unit 7910 provided on the front nose and the imaging unit 7918 provided on the upper part of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 7900.
  • the imaging units 7912 and 7914 provided on the side mirrors mainly acquire images of the sides of the vehicle 7900.
  • the imaging unit 7916 provided on the rear bumper or back door mainly acquires images of the rear of the vehicle 7900.
  • the imaging unit 7918, which is installed on the top of the windshield inside the vehicle is primarily used to detect preceding vehicles, pedestrians, obstacles, traffic signals, traffic signs, lanes, etc.
  • FIG. 21 shows an example of the imaging ranges of the imaging units 7910, 7912, 7914, and 7916.
  • Imaging range a indicates the imaging range of the imaging unit 7910 provided on the front nose
  • imaging ranges b and c indicate the imaging ranges of the imaging units 7912 and 7914 provided on the side mirrors
  • imaging range d indicates the imaging range of the imaging unit 7916 provided on the rear bumper or back door.
  • image data captured by the imaging units 7910, 7912, 7914, and 7916 are superimposed to obtain an overhead image of the vehicle 7900.
  • External information detection units 7920, 7922, 7924, 7926, 7928, and 7930 provided on the front, rear, sides, corners, and upper part of the windshield inside the vehicle 7900 may be, for example, ultrasonic sensors or radar devices.
  • External information detection units 7920, 7926, and 7930 provided on the front nose, rear bumper, back door, and upper part of the windshield inside the vehicle 7900 may be, for example, LIDAR devices. These external information detection units 7920 to 7930 are primarily used to detect preceding vehicles, pedestrians, obstacles, etc.
  • the outside-vehicle information detection unit 7400 causes the imaging unit 7410 to capture an image outside the vehicle, and receives the captured image data.
  • the outside-vehicle information detection unit 7400 also receives detection information from the connected outside-vehicle information detection unit 7420. If the outside-vehicle information detection unit 7420 is an ultrasonic sensor, a radar device, or a LIDAR device, the outside-vehicle information detection unit 7400 transmits ultrasonic waves or electromagnetic waves, and receives information on the received reflected waves.
  • the outside-vehicle information detection unit 7400 may perform object detection processing or distance detection processing for people, cars, obstacles, signs, or characters on the road surface, based on the received information.
  • the outside-vehicle information detection unit 7400 may perform environmental recognition processing for recognizing rainfall, fog, road surface conditions, etc., based on the received information.
  • the outside-vehicle information detection unit 7400 may calculate the distance to an object outside the vehicle based on the received information.
  • the outside vehicle information detection unit 7400 may also perform image recognition processing or distance detection processing to recognize people, cars, obstacles, signs, or characters on the road surface based on the received image data.
  • the outside vehicle information detection unit 7400 may perform processing such as distortion correction or alignment on the received image data, and may also generate an overhead image or a panoramic image by synthesizing image data captured by different imaging units 7410.
  • the outside vehicle information detection unit 7400 may also perform viewpoint conversion processing using image data captured by different imaging units 7410.
  • the in-vehicle information detection unit 7500 detects information inside the vehicle.
  • the in-vehicle information detection unit 7500 is connected to, for example, a driver state detection unit 7510 that detects the state of the driver.
  • the driver state detection unit 7510 may include a camera that captures an image of the driver, a biosensor that detects the driver's biometric information, or a microphone that collects sound inside the vehicle.
  • the biosensor is provided, for example, on the seat or steering wheel, and detects the biometric information of a passenger sitting in the seat or a driver gripping the steering wheel.
  • the in-vehicle information detection unit 7500 may calculate the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 7510, or may determine whether the driver is dozing off.
  • the in-vehicle information detection unit 7500 may perform processing such as noise canceling on the collected sound signal.
  • the integrated control unit 7600 controls the overall operation of the vehicle control system 7000 according to various programs.
  • the input unit 7800 is connected to the integrated control unit 7600.
  • the input unit 7800 is realized by a device that can be operated by the passenger, such as a touch panel, a button, a microphone, a switch, or a lever. Data obtained by voice recognition of a voice input by a microphone may be input to the integrated control unit 7600.
  • the input unit 7800 may be, for example, a remote control device using infrared or other radio waves, or an externally connected device such as a mobile phone or a PDA (Personal Digital Assistant) that supports the operation of the vehicle control system 7000.
  • PDA Personal Digital Assistant
  • the input unit 7800 may be, for example, a camera, in which case the passenger can input information by gestures. Alternatively, data obtained by detecting the movement of a wearable device worn by the passenger may be input. Furthermore, the input unit 7800 may include, for example, an input control circuit that generates an input signal based on information input by a passenger or the like using the input unit 7800 and outputs the signal to the integrated control unit 7600. The passenger or the like operates the input unit 7800 to input various data to the vehicle control system 7000 and to instruct processing operations.
  • the memory unit 7690 may include a ROM (Read Only Memory) that stores various programs executed by the microcomputer, and a RAM (Random Access Memory) that stores various parameters, calculation results, sensor values, etc.
  • the memory unit 7690 may also be realized by a magnetic memory device such as a HDD (Hard Disc Drive), a semiconductor memory device, an optical memory device, or a magneto-optical memory device, etc.
  • the general-purpose communication I/F 7620 is a general-purpose communication I/F that mediates communication between various devices present in the external environment 7750.
  • the general-purpose communication I/F 7620 may implement cellular communication protocols such as GSM (registered trademark) (Global System of Mobile communications), WiMAX (registered trademark), LTE (registered trademark) (Long Term Evolution) or LTE-A (LTE-Advanced), or other wireless communication protocols such as wireless LAN (also called Wi-Fi (registered trademark)) and Bluetooth (registered trademark).
  • GSM Global System of Mobile communications
  • WiMAX registered trademark
  • LTE registered trademark
  • LTE-A Long Term Evolution
  • Bluetooth registered trademark
  • the general-purpose communication I/F 7620 may connect to devices (e.g., application servers or control servers) present on an external network (e.g., the Internet, a cloud network, or an operator-specific network) via, for example, a base station or an access point.
  • the general-purpose communication I/F 7620 may connect to a terminal located near the vehicle (e.g., a driver's, pedestrian's, or store's terminal, or an MTC (Machine Type Communication) terminal) using, for example, P2P (Peer To Peer) technology.
  • P2P Peer To Peer
  • the dedicated communication I/F 7630 is a communication I/F that supports a communication protocol developed for use in vehicles.
  • the dedicated communication I/F 7630 may implement a standard protocol such as WAVE (Wireless Access in Vehicle Environment), DSRC (Dedicated Short Range Communications), or a cellular communication protocol, which is a combination of the lower layer IEEE 802.11p and the higher layer IEEE 1609.
  • the dedicated communication I/F 7630 typically performs V2X communication, which is a concept that includes one or more of vehicle-to-vehicle communication, vehicle-to-infrastructure communication, vehicle-to-home communication, and vehicle-to-pedestrian communication.
  • the positioning unit 7640 performs positioning by receiving, for example, GNSS signals from GNSS (Global Navigation Satellite System) satellites (for example, GPS signals from GPS (Global Positioning System) satellites), and generates position information including the latitude, longitude, and altitude of the vehicle.
  • GNSS Global Navigation Satellite System
  • GPS Global Positioning System
  • the positioning unit 7640 may determine the current position by exchanging signals with a wireless access point, or may obtain position information from a terminal such as a mobile phone, PHS, or smartphone that has a positioning function.
  • the beacon receiver 7650 receives, for example, radio waves or electromagnetic waves transmitted from radio stations installed on the road, and acquires information such as the current location, congestion, road closures, and travel time.
  • the functions of the beacon receiver 7650 may be included in the dedicated communication I/F 7630 described above.
  • the in-vehicle device I/F 7660 is a communication interface that mediates the connection between the microcomputer 7610 and various in-vehicle devices 7760 present in the vehicle.
  • the in-vehicle device I/F 7660 may establish a wireless connection using a wireless communication protocol such as wireless LAN, Bluetooth (registered trademark), NFC (Near Field Communication), or WUSB (Wireless USB).
  • the in-vehicle device I/F 7660 may also establish a wired connection such as USB (Universal Serial Bus), HDMI (High-Definition Multimedia Interface), or MHL (Mobile High-definition Link) via a connection terminal (and a cable, if necessary) not shown.
  • USB Universal Serial Bus
  • HDMI High-Definition Multimedia Interface
  • MHL Mobile High-definition Link
  • the in-vehicle device 7760 may include, for example, at least one of a mobile device or wearable device owned by a passenger, or an information device carried into or attached to the vehicle.
  • the in-vehicle device 7760 may also include a navigation device that searches for a route to an arbitrary destination.
  • the in-vehicle device I/F 7660 exchanges control signals or data signals with these in-vehicle devices 7760.
  • the in-vehicle network I/F 7680 is an interface that mediates communication between the microcomputer 7610 and the communication network 7010.
  • the in-vehicle network I/F 7680 transmits and receives signals in accordance with a specific protocol supported by the communication network 7010.
  • the microcomputer 7610 of the integrated control unit 7600 controls the vehicle control system 7000 according to various programs based on information acquired through at least one of the general-purpose communication I/F 7620, the dedicated communication I/F 7630, the positioning unit 7640, the beacon receiving unit 7650, the in-vehicle device I/F 7660, and the in-vehicle network I/F 7680.
  • the microcomputer 7610 may calculate the control target value of the driving force generating device, the steering mechanism, or the braking device based on the acquired information inside and outside the vehicle, and output a control command to the drive system control unit 7100.
  • the microcomputer 7610 may perform cooperative control for the purpose of realizing the functions of an ADAS (Advanced Driver Assistance System), including vehicle collision avoidance or impact mitigation, following driving based on the distance between vehicles, vehicle speed maintenance driving, vehicle collision warning, vehicle lane departure warning, etc.
  • ADAS Advanced Driver Assistance System
  • the microcomputer 7610 may control the driving force generating device, steering mechanism, braking device, etc. based on the acquired information about the surroundings of the vehicle, thereby performing cooperative control for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on the driver's operation.
  • the microcomputer 7610 may generate three-dimensional distance information between the vehicle and objects such as surrounding structures and people based on information acquired via at least one of the general-purpose communication I/F 7620, the dedicated communication I/F 7630, the positioning unit 7640, the beacon receiving unit 7650, the in-vehicle equipment I/F 7660, and the in-vehicle network I/F 7680, and may create local map information including information about the surroundings of the vehicle's current position.
  • the microcomputer 7610 may also predict dangers such as vehicle collisions, the approach of pedestrians, or entry into closed roads based on the acquired information, and generate warning signals.
  • the warning signals may be, for example, signals for generating warning sounds or turning on warning lights.
  • the audio/image output unit 7670 transmits at least one of audio and image output signals to an output device capable of visually or audibly notifying the vehicle occupants or the outside of the vehicle of information.
  • an audio speaker 7710, a display unit 7720, and an instrument panel 7730 are illustrated as output devices.
  • the display unit 7720 may include, for example, at least one of an on-board display and a head-up display.
  • the display unit 7720 may have an AR (Augmented Reality) display function.
  • the output device may be other devices such as headphones, wearable devices such as glasses-type displays worn by the occupants, projectors, or lamps other than these devices.
  • the display device visually displays the results obtained by various processes performed by the microcomputer 7610 or information received from other control units in various formats such as text, images, tables, graphs, etc. Also, if the output device is an audio output device, the audio output device converts an audio signal consisting of reproduced voice data or acoustic data, etc., into an analog signal and outputs it audibly.
  • At least two control units connected via the communication network 7010 may be integrated into one control unit.
  • each control unit may be composed of multiple control units.
  • the vehicle control system 7000 may include another control unit not shown.
  • some or all of the functions performed by any control unit may be provided by another control unit.
  • a predetermined calculation process may be performed by any control unit.
  • a sensor or device connected to any control unit may be connected to another control unit, and multiple control units may transmit and receive detection information to each other via the communication network 7010.
  • An imaging device including a plurality of pixels, a plurality of pixel control lines, and a drive circuit electrically connected to one end of each of the pixel control lines and configured to drive the plurality of pixels via the plurality of pixel control lines, comprising: a failure detection device electrically connected to the other end of each of the pixel control lines, a first resistive voltage dividing circuit capable of dividing a high voltage applied to a first pixel control line among the plurality of pixel control lines; a second resistive voltage divider circuit capable of dividing the Lo voltage applied to the first pixel control line; a comparator capable of comparing either a first voltage generated by the first resistive voltage divider circuit or a second voltage generated by the second resistive voltage divider circuit with a reference voltage; a determination unit capable of determining whether or not a failure has occurred in the drive circuit and each of the pixel control lines based on a result of the comparator.
  • a first selector having two input terminals electrically connected to the first resistive voltage divider circuit and the second resistive voltage divider circuit, and having one output terminal electrically connected to one input terminal of the comparator; and a second selector having one input terminal electrically connected to the first pixel control line and two output terminals electrically connected to the first resistive voltage divider circuit and the second resistive voltage divider circuit.
  • a failure detection device electrically connected to each of the control lines in an imaging device including a plurality of pixels, a plurality of control lines, and a control circuit connected to each of the control lines and controlling a control circuit that processes pixel signals output from the plurality of pixels via the plurality of control lines, a first resistive voltage dividing circuit capable of dividing a high voltage applied to a first control line of the plurality of control lines; a second resistive voltage divider circuit capable of dividing the Lo voltage applied to the first control line; a comparator capable of comparing either a first voltage generated by the first resistive voltage divider circuit or a second voltage generated by the second resistive voltage divider circuit with a reference voltage; a determination unit capable of determining whether or not a fault has occurred in the control circuit and each of the control lines
  • a first selector having two input terminals electrically connected to the first resistive voltage divider circuit and the second resistive voltage divider circuit, and having one output terminal electrically connected to one input terminal of the comparator; and a second selector having one input terminal electrically connected to the first control line and two output terminals electrically connected to the first resistive voltage divider circuit and the second resistive voltage divider circuit.
  • the fault detection device according to (6) further comprising a third selector having a plurality of input terminals electrically connected to the other ends of the plurality of control lines and having one output terminal electrically connected to an input terminal of the second selector.
  • a third resistor voltage divider circuit capable of generating the reference voltage;
  • the fault detection device according to any one of (5) to (7), wherein the third resistive voltage divider circuit includes a plurality of variable resistors connected in series.
  • the failure detection circuit includes: a first resistive voltage dividing circuit capable of dividing a high voltage applied to a first pixel control line among the plurality of pixel control lines; a second resistive voltage divider circuit capable of dividing the Lo voltage applied to the first pixel control line; a comparator capable of comparing either a first voltage generated by the first resistive voltage divider circuit or a second voltage generated by the second resistive voltage divider circuit with a reference voltage; and a determination unit capable of determining whether or not the drive circuit
  • the failure detection circuit includes: a first resistive voltage dividing circuit capable of dividing a high voltage applied to a first control line of the plurality of control lines; a second resistive voltage divider circuit capable of dividing the Lo voltage applied to the first control line; a comparator capable of comparing either a first voltage generated by the first resistive voltage divider circuit or a second voltage generated by the second resistive voltage divider circuit with a reference voltage; and a determination unit capable of determining whether or not the control circuit and each of the control lines have a fault based on a result of the comparator.
  • An imaging device including a plurality of pixels, a plurality of pixel control lines, and a drive circuit electrically connected to one end of each of the pixel control lines and driving the plurality of pixels via the plurality of pixel control lines, comprising: Dividing a high voltage applied to a first pixel control line of the plurality of pixel control lines; Dividing a Lo voltage applied to the first pixel control line; comparing one of a first voltage generated by the first resistive voltage divider circuit and a second voltage generated by the second resistive voltage divider circuit with a reference voltage; and determining whether or not a failure has occurred in the drive circuit and each of the pixel control lines based on a result of the comparison. (12) 1.
  • a failure detection method for an imaging device including a plurality of pixels, a plurality of control lines, and a control circuit connected to each of the control lines, the control circuit processing pixel signals output from the plurality of pixels, the failure detection method being executed by a failure detection device electrically connected to each of the control lines, the method comprising: Dividing a high voltage applied to a first control line of the plurality of control lines; Dividing a Lo voltage applied to the first control line; comparing one of a first voltage generated by the first resistive voltage divider circuit and a second voltage generated by the second resistive voltage divider circuit with a reference voltage; and determining whether or not a fault occurs in said control circuit and each of said control lines based on a result of the comparison.

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Solid State Image Pick-Up Elements (AREA)

Abstract

Selon un mode de réalisation de la présente divulgation, un dispositif de détection de défaillance comprend un premier circuit de division de tension de résistance, un second circuit de division de tension de résistance, un comparateur et une unité de détermination. Le premier circuit de division de tension de résistance est configuré pour pouvoir diviser une tension Hi appliquée à une première ligne de commande de pixel parmi la pluralité de lignes de commande de pixel. Le second circuit de division de tension de résistance est configuré pour pouvoir diviser une tension Lo appliquée à la première ligne de commande de pixel. Le comparateur est capable de comparer une première tension générée par le premier circuit de division de tension de résistance ou une seconde tension générée par le second circuit de division de tension de résistance avec une tension de référence. L'unité de détermination est capable de déterminer, d'après un résultat provenant du comparateur, s'il existe une défaillance dans le circuit d'attaque ou les lignes de commande de pixel.
PCT/JP2024/017899 2023-06-28 2024-05-15 Dispositif de détection de défaillance, dispositif d'imagerie à semi-conducteurs et procédé de détection de défaillance Pending WO2025004582A1 (fr)

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JP2023106350 2023-06-28

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007208322A (ja) * 2006-01-30 2007-08-16 Matsushita Electric Ind Co Ltd 固体撮像装置
US20130093910A1 (en) * 2011-10-14 2013-04-18 Samsung Electronics Co., Ltd. Image sensor and image processing apparatus including the same
WO2017209221A1 (fr) * 2016-05-31 2017-12-07 ソニーセミコンダクタソリューションズ株式会社 Dispositif de capture d'image, procédé de capture d'image, module de caméra et dispositif électronique
WO2019171839A1 (fr) * 2018-03-07 2019-09-12 Sony Semiconductor Solutions Corporation Dispositif d'imagerie, système d'imagerie et procédé d'imagerie
WO2022210152A1 (fr) * 2021-03-30 2022-10-06 パナソニックＩｐマネジメント株式会社 Dispositif de formation d'images à semi-conducteurs et système de formation d'images à semi-conducteurs

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007208322A (ja) * 2006-01-30 2007-08-16 Matsushita Electric Ind Co Ltd 固体撮像装置
US20130093910A1 (en) * 2011-10-14 2013-04-18 Samsung Electronics Co., Ltd. Image sensor and image processing apparatus including the same
WO2017209221A1 (fr) * 2016-05-31 2017-12-07 ソニーセミコンダクタソリューションズ株式会社 Dispositif de capture d'image, procédé de capture d'image, module de caméra et dispositif électronique
WO2019171839A1 (fr) * 2018-03-07 2019-09-12 Sony Semiconductor Solutions Corporation Dispositif d'imagerie, système d'imagerie et procédé d'imagerie
WO2022210152A1 (fr) * 2021-03-30 2022-10-06 パナソニックＩｐマネジメント株式会社 Dispositif de formation d'images à semi-conducteurs et système de formation d'images à semi-conducteurs

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