WO2025088439A1 - Information processing system and information processing method - Google Patents

Abstract

The present invention provides a novel information processing system. First, an image corresponding to a processing range which is at least a part of a layout of a semiconductor device is received. Next, by using a detection model, a shape based on a design rule prepared in advance is extracted from the image, and a tag indicating a type of the design rule and a bounding box indicating a position of the shape are assigned to the shape. Next, a position of a correction target area in the layout corresponding to the position of the bounding box in the image is calculated. Next, vertex information of a pattern element included in the correction target area and layer information to which the pattern element belongs are acquired. Next, an instruction sentence is created using the tag, the vertex information, and the layer information. Next, a response sentence including a layout correction proposal based on the instruction sentence is generated using a language model. Finally, the response sentence is output.

Description

Information processing system and information processing method

One aspect of the present invention relates to an information processing system and an information processing method.

Note that one aspect of the present invention is not limited to the above technical field. The technical field of one aspect of the invention disclosed in this specification relates to an object, a method, a driving method, or a manufacturing method. Alternatively, one aspect of the present invention relates to a process, a machine, a manufacture, or a composition of matter. More specifically, examples of the technical field of one aspect of the present invention disclosed in this specification include semiconductor devices, display devices, light-emitting devices, power storage devices, optical devices, imaging devices, lighting devices, arithmetic devices, control devices, storage devices, input devices, output devices, input/output devices, signal processing devices, arithmetic processing devices, electronic computers, electronic devices, driving methods thereof, or manufacturing methods thereof.

In recent years, there has been an increasing demand for higher integration, more functionality, and higher performance of integrated circuits. This has resulted in an increase in the complexity of circuit patterns, creating a demand for more efficient, optimized, and automated layout design. For example, Patent Document 1 discloses a layout design method for keeping the parasitic capacitance and parasitic resistance of wiring below an allowable value. Also, for example, Patent Document 2 discloses a layout design method for suppressing the characteristic variation of transistors.

In addition, the use of artificial intelligence (AI) is being considered for various applications. Types of AI include discriminative AI, such as image recognition and voice recognition, and generative AI, such as text generation and image generation, and are used according to the application.

In particular, the development of language models using artificial neural networks (ANN, hereinafter sometimes simply referred to as neural networks) has been actively pursued, and for example, large-scale language models (LLMs) have attracted attention. Large-scale language models are natural language processing models trained using large amounts of data. Large-scale language models can realize dialogue models that respond to user instructions, for example. For example, Non-Patent Document 1 discloses GPT-4 (registered trademark) (Generative Pre-trained Transformer 4) as a large-scale language model, and ChatGPT as a dialogue model.

JP 2003-50835 A JP 2009-65056 A

Summary of ChatGPT/GPT-4 Research and Perspective Tower ds the Future of Large Language Models, Yiheng Liu et al. (Submitted on 4 April 2023, [online], Internet <URL: https://arxiv.org/abs/2304.01852>

In layout design for semiconductor devices such as integrated circuits, it is necessary to draw circuit patterns that comply with design rules. For example, it is necessary to draw circuit patterns according to rules that are restricted by the processing accuracy of manufacturing equipment. Furthermore, as semiconductor devices become more miniaturized, layout design based on manufacturability-conscious design technology is becoming important in order to improve yield and quality.

Generally, manufacturability-aware design techniques require layout designers to have advanced skills based on knowledge and experience. Therefore, there is a demand for reducing the dependency on the skills of layout designers as much as possible in the layout design of semiconductor devices.

An object of one embodiment of the present invention is to provide a novel information processing system that assists in the layout design of a semiconductor device, or a semiconductor device designed using the system. Alternatively, an object of one embodiment of the present invention is to provide a novel information processing method that assists in the layout design of a semiconductor device, or a semiconductor device designed using the method.

An object of one embodiment of the present invention is to provide an information processing system that helps improve the yield of a semiconductor device, or a semiconductor device designed using the system. Alternatively, an object of one embodiment of the present invention is to provide an information processing method that helps improve the yield of a semiconductor device, or a semiconductor device designed using the method.

An object of one embodiment of the present invention is to provide an information processing system that helps improve the quality of a semiconductor device, or a semiconductor device designed using the system. Alternatively, an object of one embodiment of the present invention is to provide an information processing method that helps improve the quality of a semiconductor device, or a semiconductor device designed using the method.

An object of one embodiment of the present invention is to provide an information processing system that assists in reducing the manufacturing cost of a semiconductor device, or a semiconductor device designed using the system. Alternatively, an object of one embodiment of the present invention is to provide an information processing method that assists in reducing the manufacturing cost of a semiconductor device, or a semiconductor device designed using the method.

An object of one aspect of the present invention is to provide an information processing system that assists in responding to changes in the manufacturing process of a semiconductor device, or a semiconductor device designed using the system. Alternatively, an object of one aspect of the present invention is to provide an information processing method that assists in responding to changes in the manufacturing process of a semiconductor device, or a semiconductor device designed using the method.

An object of one embodiment of the present invention is to provide an information processing system that assists in reducing the design costs of a semiconductor device, or a semiconductor device designed using the system. Alternatively, an object of one embodiment of the present invention is to provide an information processing method that assists in reducing the design costs of a semiconductor device, or a semiconductor device designed using the method.

An object of one embodiment of the present invention is to provide an information processing system that assists in shortening the design period of a semiconductor device, or a semiconductor device designed using the system. Alternatively, an object of one embodiment of the present invention is to provide an information processing method that assists in shortening the design period of a semiconductor device, or a semiconductor device designed using the method.

An object of one embodiment of the present invention is to provide an information processing system that helps improve the skills of a designer of a semiconductor device, or a semiconductor device designed using the system. Alternatively, an object of one embodiment of the present invention is to provide an information processing method that helps improve the skills of a designer of a semiconductor device, or a semiconductor device designed using the method.

An object of one embodiment of the present invention is to provide a novel information processing system or a semiconductor device designed using the system. Alternatively, an object of one embodiment of the present invention is to provide a novel information processing method or a semiconductor device designed using the method.

One aspect of the present invention is to provide a program for executing the above information processing method on one or more computers, or a computer-readable recording medium on which the program is recorded.

Note that the above-mentioned problems do not preclude the existence of other problems. Note that problems other than the above-mentioned problems will become apparent from the description in this specification, drawings, claims, etc., and it is possible to extract problems other than the above-mentioned problems from the description in this specification, drawings, claims, etc. Note that one embodiment of the present invention does not need to solve all of these problems (the above-mentioned problems and other problems).

(1)
One aspect of the present invention is an information processing system for designing a layout of a semiconductor device, the information processing system having an input unit, a first processing unit, a second processing unit, a third processing unit, and an output unit, wherein the input unit has a function of accepting an image corresponding to a processing range which is at least a part of the layout of the semiconductor device, the first processing unit has a function of using a detection model to extract a shape based on a pre-prepared design rule from the image, a function of using the detection model to assign a tag indicating a type of design rule and a bounding box indicating a position of the shape to the shape, and a function of acquiring the tag and the bounding box, the second processing unit has a function of acquiring vertex information of a pattern element included in a correction target area which is part of the layout, and layer information to which the pattern element belongs, the position of the correction target area corresponds to the position of the bounding box in the image, the third processing unit has a function of creating a directive statement using the tag, vertex information, and layer information, a function of using a language model to generate a response statement including a layout revision proposal based on the directive statement, and a function of acquiring the response statement, and the output unit has a function of outputting the response statement.

(2)
In addition, in the above (1), the device may further include a fourth processing unit, the fourth processing unit having a function of obtaining an explanatory diagram associated with the tag, and the output unit may further have a function of outputting the explanatory diagram.

(3)
In the above (1) or (2), the design rules may include rules determined based on a manufacturability-aware design technique.

(4)
One aspect of the present invention is an information processing method for layout design of a semiconductor device, the information processing method having first to seventh steps, in which in the first step, an image corresponding to a processing range that is at least a part of the layout of the semiconductor device is accepted, in the second step, a shape based on a pre-prepared design rule is extracted from the image by using a detection model, and a tag indicating a type of the design rule and a bounding box indicating a position of the shape are assigned to the shape, in the third step, a position of a correction target area in the layout that corresponds to the position of the bounding box in the image is calculated, in the fourth step, vertex information of a pattern element included in the correction target area and layer information to which the pattern element belongs are obtained, in the fifth step, an instruction statement is created using the tag, vertex information, and layer information, in the sixth step, a response statement including a layout modification proposal based on the instruction statement is generated by using a language model, and in the seventh step, the response statement is output.

(5)
In addition, in the above (4), an eighth step may be included before the seventh step, in which an explanatory diagram associated with the tag is obtained in the eighth step, and further in which the explanatory diagram is output in the seventh step.

(6)
In the above (4) or (5), the design rules may include rules determined based on a manufacturability-aware design technique.

One aspect of the present invention can provide a novel information processing system that supports the layout design of a semiconductor device, or a semiconductor device designed using the system. Alternatively, one aspect of the present invention can provide a novel information processing method that supports the layout design of a semiconductor device, or a semiconductor device designed using the method.

One aspect of the present invention can provide an information processing system that helps improve the yield of semiconductor devices, or a semiconductor device designed using the system. Alternatively, one aspect of the present invention can provide an information processing method that helps improve the yield of semiconductor devices, or a semiconductor device designed using the method.

One aspect of the present invention can provide an information processing system that supports the improvement of the quality of a semiconductor device, or a semiconductor device designed using the system. Alternatively, one aspect of the present invention can provide an information processing method that supports the improvement of the quality of a semiconductor device, or a semiconductor device designed using the method.

One aspect of the present invention can provide an information processing system that helps reduce the manufacturing costs of semiconductor devices, or a semiconductor device designed using the system. Alternatively, one aspect of the present invention can provide an information processing method that helps reduce the manufacturing costs of semiconductor devices, or a semiconductor device designed using the method.

One aspect of the present invention can provide an information processing system that assists in responding to changes in the manufacturing process of a semiconductor device, or a semiconductor device designed using the system. Alternatively, one aspect of the present invention can provide an information processing method that assists in responding to changes in the manufacturing process of a semiconductor device, or a semiconductor device designed using the method.

One aspect of the present invention can provide an information processing system that helps reduce the design costs of a semiconductor device, or a semiconductor device designed using the system. Alternatively, one aspect of the present invention can provide an information processing method that helps reduce the design costs of a semiconductor device, or a semiconductor device designed using the method.

One aspect of the present invention can provide an information processing system that assists in shortening the design period of a semiconductor device, or a semiconductor device designed using the system. Alternatively, one aspect of the present invention can provide an information processing method that assists in shortening the design period of a semiconductor device, or a semiconductor device designed using the method.

One aspect of the present invention can provide an information processing system that helps improve the skills of semiconductor device designers, or a semiconductor device designed using the system. Alternatively, one aspect of the present invention can provide an information processing method that helps improve the skills of semiconductor device designers, or a semiconductor device designed using the method.

One aspect of the present invention can provide a novel information processing system or a semiconductor device designed using the system. Alternatively, one aspect of the present invention can provide a novel information processing method or a semiconductor device designed using the method.

One aspect of the present invention provides a program for executing the above information processing method on one or more computers, or a computer-readable recording medium on which the program is recorded.

Note that the above effects do not preclude the existence of other effects. Note that effects other than the above effects will become apparent from the description in this specification, drawings, claims, etc., and it is possible to extract effects other than the above effects from the description in this specification, drawings, claims, etc. Note that one embodiment of the present invention does not need to have all of these effects (the above effects and other effects).

FIG. 1 is a block diagram illustrating an example of an information processing system.
FIG. 2 is a schematic diagram illustrating an example of an information processing system.
FIG. 3 is a schematic diagram illustrating an example of an information processing system.
FIG. 4 is a block diagram illustrating an example of an information processing system.
5A and 5B are schematic diagrams illustrating an example of an information processing system.
6A and 6B are schematic diagrams illustrating an example of an information processing system.
7A to 7C are schematic diagrams illustrating an example of an information processing system.
8A to 8D are schematic diagrams illustrating an example of an information processing system.
FIG. 9 is a schematic diagram illustrating an example of an information processing system.
10A and 10B are schematic diagrams illustrating an example of an information processing system.
FIG. 11 is a schematic diagram illustrating an example of an information processing system.
FIG. 12 is a schematic diagram illustrating an example of an information processing system.
FIG. 13 is a flowchart showing an example of an information processing method.

In this specification, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to, for example, a circuit including a semiconductor element (e.g., a transistor or a diode) or a device having such a circuit. It also refers to any device that can function by utilizing semiconductor characteristics. For example, an integrated circuit including a semiconductor element, a chip equipped with an integrated circuit, an electronic component in which a chip is housed in a package, or an electronic device equipped with an electronic component are examples of semiconductor devices. Also, for example, a display device, a light-emitting device, a power storage device, an optical device, an imaging device, a lighting device, an arithmetic device, a control device, a memory device, an input device, an output device, an input/output device, a signal processing device, an electronic computer, or an electronic device may be a semiconductor device itself and may have a semiconductor device.

The following describes the embodiments with reference to the drawings. However, the embodiments can be implemented in many different ways. Therefore, it will be easily understood by those skilled in the art that the form and details can be modified in various ways without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments.

Furthermore, in this specification and the like, the configurations shown in each embodiment can be appropriately combined with the configurations shown in other embodiments to form one aspect of the present invention. Furthermore, when multiple configurations are shown in one embodiment, those configurations can be appropriately combined to form one aspect of the present invention.

In addition, in this specification, the ordinal numbers "first," "second," and "third" are used to avoid confusion between components. Therefore, they do not limit the number of components. Furthermore, they do not limit the order of the components. For example, a component referred to as "first" in one embodiment of this specification may be a component referred to as "second" in another embodiment or in the claims. Also, for example, a component referred to as "first" in one embodiment of this specification may be omitted in another embodiment or in the claims.

Note that in drawings explaining embodiments, the same reference numerals may be used in common between different drawings for identical parts or parts having similar functions in the configuration of the invention, thereby omitting repeated description of such parts. Furthermore, when the drawings indicate similar functions, they may use the same hatching patterns, for example, and not be given specific reference numerals. Furthermore, in drawings, for example, in perspective views or top views (also called "plan views"), the illustration of some components may be omitted in order to make them easier to understand. Furthermore, in drawings, for example, the illustration of some hidden lines may be omitted. Furthermore, in drawings, for example, the illustration of hatching patterns may be omitted.

In addition, in the drawings, the size, layer thickness, or area may be exaggerated for clarity. Therefore, the drawings are not limited to, for example, their size or aspect ratio. Note that the drawings are schematic illustrations of ideal examples, and are not limited to, for example, the shapes or values shown in the drawings.

Furthermore, in this specification and drawings, components may be classified by function and shown as independent elements. However, there are cases where it is difficult to separate components by function, and one element is involved in multiple functions, or one function is involved across multiple elements. For this reason, the elements shown in this specification and drawings are not limited to the explanations given, and may be rephrased appropriately.

In addition, in this specification and drawings, when the same reference numeral is used for multiple elements, and particularly when it is necessary to distinguish between them, the reference numeral may be accompanied by an identifying symbol such as "A", "b", "_1", "[n]", or "[m, n]". In addition, when explaining matters common to multiple elements accompanied by identifying symbols, or when it is not necessary to distinguish between them, the reference numeral may be omitted.

(Embodiment 1)
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A data processing system according to one embodiment of the present invention will be described with reference to the drawings. The data processing system according to one embodiment of the present invention can be used for, for example, layout design of a semiconductor device.

In this specification, layout design of a semiconductor device refers to, for example, designing a photomask pattern used when fabricating an integrated circuit including semiconductor elements (e.g., transistors and diodes). Note that it may also refer to, for example, designing a pattern when directly drawing with an electron beam drawing device. It may also refer to, for example, designing a pattern for a printed circuit board (PCB) and a flexible printed circuit (FPC) pattern.

In other words, in this specification, the term "layout" refers to a pattern (circuit pattern) in which multiple circuit elements (e.g., semiconductor elements, resistive elements, and capacitive elements) and wiring that connects the circuit elements to each other are arranged in a semiconductor device such as an integrated circuit. Examples of such patterns include photomask patterns, patterns used when directly drawing with an electron beam drawing device, PCB patterns, and FPC patterns.

Furthermore, examples of the transistor include a Si transistor (a transistor containing silicon in a channel formation region) and an OS transistor (a transistor containing metal oxide in a channel formation region). That is, the integrated circuit may have, for example, a Si transistor. Also, for example, the integrated circuit may have an OS transistor. Also, for example, the integrated circuit may have both a Si transistor and an OS transistor. When the integrated circuit has both a Si transistor and an OS transistor, for example, the integrated circuit may have a configuration in which the OS transistor is provided on the Si transistor.

<Example of information processing system configuration>
[0023] Fig. 1 is a block diagram illustrating an example of an information processing system according to one embodiment of the present invention. Fig. 2 is a schematic diagram illustrating an example of an information processing system according to one embodiment of the present invention.

FIG. 1 illustrates components 110, 120, 130, 140, 150, and 190. Component 110 can exchange information with each of components 120, 130, 140, 150, and 190.

The component 110 has an input unit 111, a processing unit 112, a processing unit 113, a processing unit 114, an output unit 116, and a transmission path 119. It may further have a processing unit 115. Each of the input unit 111, the processing unit 112, the processing unit 113, the processing unit 114, the processing unit 115, and the output unit 116 can exchange information with each other via the transmission path 119. The component 110 has a function of controlling the operation of the information processing system. Details of the component 110 will be described later.

The component 120 has layout data 121. The layout data 121 represents a circuit pattern in a semiconductor device such as an integrated circuit in a vector format (e.g., GDSII (Graphic Data System II) and DXF (Drawing Exchange Format)), and includes information such as the types (points, lines, rectangles, polygons, etc.) of the elements (also called pattern elements) that make up the pattern, vertices, and layers.

Component 130 has detection model 131. Detection model 131 has the following functions: when an image is input, it extracts a shape based on a pre-prepared design rule from the image; it assigns a tag indicating the type of the design rule and a bounding box indicating the position of the shape (also called the area in which the shape is located) to the shape; and it outputs the tag and the bounding box.

For example, an object detection model using a classification AI can be used as the detection model 131. In particular, it is preferable to use a neural network model.

In this specification, a neural network refers to a general model that imitates the neural circuit network of an organism, determines the connection strength between neurons through learning, and has problem-solving capabilities. A neural network has an input layer, an intermediate layer (hidden layer), and an output layer. In a neural network, determining the connection strength (also called weight coefficient) between neurons from existing information (also called a data set) is sometimes called "learning". In other words, a neural network model is created by learning. Learning methods include "supervised learning", "unsupervised learning", and "reinforcement learning". Also, constructing a neural network using the connection strength obtained by learning and deriving a new conclusion from it is sometimes called "inference". A neural network is realized by a circuit (hardware) or a program (software).

As a neural network detection model, for example, R-CNN (Regions with Convolutional Neural Networks), YOLO (You Only Look Once), SSD (Single Shot MultiBox Detector), DCN (Deformed Convolutional Networks), DETR (End-to-End Object Detection with Transformers), and HOG (Histogram of Oriented Gradient) can be used.

Furthermore, examples of pre-prepared design rules include rules that are constrained by the processing accuracy of manufacturing equipment (sometimes called DRC (Design Rule Check) rules), rules established based on Optical Proximity Correction (OPC) technology (sometimes called OPC rules), and rules established based on Design For Manufacturability (DFM) technology (sometimes called DFM rules).

Here, DFM technology refers to incorporating countermeasures at the design stage in advance to deal with reduced yields and performance caused by constraints on the manufacturing process of semiconductor devices. In other words, by designing the layout in accordance with DFM rules, it is possible to improve the yield and performance of semiconductor devices, as well as reduce manufacturing costs and improve quality.

DFM rules include, for example, "Double Via" and "Bridging."

Double via is a technology that aims to improve yield by providing redundancy against electrical continuity defects by driving two vias into the same node. Therefore, the DFM rule recommends that if there is one via (single via) at the same node, it should be two vias (double via).

Bridging is one of the hot spots in lithography, and is a phenomenon that leads to a decrease in yield when the spacing between contour patterns becomes narrower compared to the spacing between circuit patterns. Therefore, the DFM rule recommends increasing the spacing between circuit patterns to prevent hot spots from occurring.

Component 140 has a language model 141. Language model 141 has a function of generating a response sentence including a layout modification proposal based on an instruction sentence when the instruction sentence is input, and a function of outputting the response sentence.

For example, a natural language processing model using generative AI can be used as the language model 141. In particular, it is preferable to use a neural network model.

As language models of neural networks, for example, BERT (Bidirectional Encoder Representations from Transformers), T5 (Text-to-Text Transformer Transformer), GPT-3, GPT-3.5, GPT-4 (registered trademark), LaMDA (Language Model for Dialogue Applications), PaLM (Pathways Language Model), and PaLM2 can be used.

Component 150 has database 151. In database 151, types of design rules prepared in advance and explanatory diagrams of the design rules are stored in association with each other. For example, the above-mentioned types of DFM rules and explanatory diagrams of the DFM rules are stored in association with each other. Database 151 has a function of returning an explanatory diagram of the design rule in response to an inquiry specifying the type of design rule.

The component 190 has a monitor 191 (sometimes called a display device) and a mouse 192 (sometimes called an input device). The monitor 191 has a function of displaying at least a part of the layout data 121. It also has a function of displaying a response sentence including a layout revision proposal generated by the language model 141. It may also have a function of displaying an explanatory diagram of a design rule obtained from the database 151. The mouse 192 has a function of operating a mouse pointer displayed on the monitor 191.

Figure 2 illustrates an information processing device 10, an information processing device 20, an information terminal 30, and a network 90.

The information processing device 10, for example, has a component 110 and a component 120. The information processing device 20, for example, has a component 130 and a component 140. It may further have a component 150. The information terminal 30 has a component 190. Each of the information processing device 10, the information processing device 20, and the information terminal 30 is connected to a network 90. As a result, each of the information processing device 10, the information processing device 20, and the information terminal 30 can exchange information with each other via the network 90.

In this way, by configuring the information processing device 10, the information processing device 20, and the information terminal 30 to be connected via the network 90, the load related to information processing can be distributed.

For example, a workstation, a server computer, or a supercomputer can be used as the information processing device 10. It is preferable that the information processing device 10 has a function as a parallel computer. This makes it possible to perform large-scale calculations required for processing such as AI learning and inference.

The information processing device 20 can be, for example, a large computer such as a server computer or a supercomputer. It is preferable that the information processing device 20 has a function as a parallel computer. This makes it possible to perform large-scale calculations required for processing such as AI learning and inference.

Note that the information processing device 20 may perform calculations on a larger scale than the information processing device 10 in order to process the learning and inference of the detection model 131 and the learning and inference of the language model 141. Therefore, it is preferable that the information processing device 20 has a higher computing power than the information processing device 10, and in particular a higher parallel computing power.

For example, a desktop computer can be used as the information terminal 30. The information terminal 30 can also be called a client computer.

For example, a local network or a global network can be used as the network 90. Also, for example, an intranet or an extranet can be used. Also, for example, a PAN (Personal Area Network), a LAN (Local Area Network), a CAN (Campus Area Network), a MAN (Metropolitan Area Network), a WAN (Wide Area Network), or a GAN (Global Area Network) can be used. Also, for example, the Internet, which is the foundation of the World Wide Web (WWW), can be used.

When performing wireless communication, the communication protocol or technology that can be used may be, for example, a communication standard such as the fourth generation mobile communication system (4G), the fifth generation mobile communication system (5G), or the sixth generation mobile communication system (6G), or a specification standardized by the IEEE such as Wi-Fi (registered trademark) or Bluetooth (registered trademark).

Here, a person who provides a service using an information processing system according to an embodiment of the present invention can provide the service using an information processing method according to an embodiment of the present invention, for example, via a network 90. The information processing method according to an embodiment of the present invention will be described in the second embodiment described below.

When a provider of a service using an information processing method according to an embodiment of the present invention and a user of the service belong to the same organization (such as a company), it is preferable to use a local network such as an intranet established within the organization as the network 90. This allows information to be exchanged more securely than when a global network such as the Internet is used. It also makes it possible to prevent confidential information within the organization from leaking to the outside.

Note that one aspect of the present invention is not limited to the example configuration of the information processing system shown in FIG. 2. Other example configurations different from the example configuration shown in FIG. 2 will be described later.

Here, a user (e.g., a layout designer of a semiconductor device, etc.) can access the information processing system of one embodiment of the present invention via, for example, dedicated application software or a web browser running on an information terminal 30. This allows the user to enjoy services using the information processing system.

Figure 3 is a schematic diagram showing an example of a display on a monitor 191 of a component 190 in an information terminal 30.

Displayed on the monitor 191 are a window wnd1, a window wnd2, and a mouse pointer mpt. The window wnd1 has a layout work area wrkara. The window wnd2 has a text display area txtara. It may also have an image display area figara. The position of the mouse pointer mpt can be moved by the mouse 192.

At least a part of the layout data 121 is displayed in the layout work area wrkara. For example, the layout lyot is displayed in the layout work area wrkara (see FIG. 5A described later). In addition, the text display area txtara displays a response sentence including a layout revision proposal generated by the language model 141, and the image display area figara displays an explanatory diagram of the design rule obtained from the database 151. For example, the text display area txtara displays the response sentence rspn, and the image display area figara displays an explanatory diagram dgrm (see FIG. 10A and FIG. 10B described later).

Component 110
Next, a description will be given of the component 110. In the information processing system according to one aspect of the present invention, the component 110 has a function of controlling the operation of the information processing system.

Figure 4 is a block diagram explaining component 110. In Figure 4, a part of the block diagram shown in Figure 1 is excerpted, and arrows are used to indicate how information is exchanged between each component.

Below, we will explain each of the components of component 110, taking into account their relationships with other components.

[Input unit 111]
5A and 5B are schematic diagrams for explaining functions of the input unit 111. The input unit 111 has a function of receiving an image img corresponding to a processing range rng which is at least a part of a layout lyot of a semiconductor device.

Figure 5A shows a circuit pattern having a wiring layer M1, a wiring layer M2, and a via layer VIA as an example of a layout lyot.

Here, for example, it is assumed that the layout lyot shown in FIG. 5A is displayed in the layout work area wrkara of the monitor 191 of the information terminal 30 operated by the user. At this time, by operating the mouse pointer mpt with the mouse 192 to select the processing range rng (e.g., by dragging and dropping), an image img corresponding to the processing range rng can be created as shown in FIG. 5B. Note that an image img corresponding to the entire layout lyot may also be created.

At this time, for example, the image img may be created by performing a screen capture of the processing range rng on the information terminal 30. In this case, the image img is transferred to the input unit 111 in the information processing device 10 via the network 90, so that the input unit 111 can accept the image img.

For example, information on the processing range rng may be transferred to the processing unit 112 in the information processing device 10 via the network 90, and the processing unit 112 may create an image img using the layout lyot and the processing range rng. In this case, the image img may be transferred from the processing unit 112 to the input unit 111, so that the input unit 111 can accept the image img.

Here, the image img can be, for example, a raster format image (e.g., PNG (Portable Network Graphics) and GIF (Graphics Interchange Format)).

[Processing section 113]
6A and 6B are schematic diagrams for explaining functions of the processing unit 113. The processing unit 113 has a function of extracting a shape based on a previously prepared design rule from the image img using the detection model 131, a function of assigning a tag indicating the type of the design rule and a bounding box bbox indicating the position of the shape to the shape using the detection model 131, and a function of acquiring the tag and the bounding box bbox.

In FIG. 6A, as an example, in the image img, three shapes based on the double via DFM rule and three shapes based on the bridging DFM rule are extracted, and bounding boxes indicating the positions of the shapes are attached, enclosed in dashed rectangles. Each of the dashed rectangles indicating the positions of the shapes extracted based on the double via DFM rule is assigned a code of one of the bounding boxes bbox[1] to bbox[3] and a code of one of the tags tag[1] to tag[3]. Each of the dashed rectangles indicating the positions of the shapes extracted based on the bridging DFM rule is assigned a code of one of the bounding boxes bbox[4] to bbox[6] and a code of one of the tags tag[4] to tag[6].

Here, the bounding box can be represented, for example, by the lower left coordinates and the upper right coordinates in the coordinate system of the image img. It may also be represented by the upper left coordinates and the lower right coordinates. It may also be represented by the center coordinates, width, and height. For example, in the bounding box bbox[1] shown in FIG. 6B, [x1a, y1a] can be the lower left coordinates and [x1b, y1b] can be the upper right coordinates. The same applies to the bounding boxes bbox[2] to bbox[6].

Also, for example, as shown in FIG. 6B, each of tags tag[1] through tag[3] can be given "Double Via" to indicate that the shape is extracted based on the double via DFM rule, and each of tags tag[4] through tag[6] can be given "Bridging" to indicate that the shape is extracted based on the bridging DFM rule.

[Processing section 112]
7A and 7B are schematic diagrams for explaining functions of the processing unit 112. The processing unit 112 has a function of acquiring vertex information of a pattern element elm included in a correction target area zon that is a part of the layout lyot, and layer information to which the pattern element elm belongs.

Here, the position of the correction target area zon in the layout lyot corresponds to the position of the bounding box bbox in the image img. Therefore, the processing unit 112 has a function of calculating the position of the correction target area zon in the layout lyot, which corresponds to the position of the bounding box bbox in the image img.

The position of the area zon to be modified can be calculated, for example, using a coordinate transformation matrix. The coordinate transformation matrix can be found, for example, using the position of the processing range rng in the coordinate system of the layout lyot and the size (width and height) of the image img. By using the coordinate transformation matrix, the position of the area zon to be modified in the coordinate system of the layout lyot can be calculated from the position of the bounding box bbox in the coordinate system of the image img.

In FIG. 7A, the position of the correction target area zon in the layout lyot, which corresponds to the position of the bounding box bbox in the image img, is shown enclosed in a dotted rectangle. In addition, the correction target area zon[1] corresponding to the bounding box bbox[1] and the correction target area zon[4] corresponding to the bounding box bbox[4] are respectively given reference numbers.

Figure 7B shows pattern element elm[1] included in the correction target area zon[1]. Figure 7C shows pattern element elm[4] included in the correction target area zon[4]. Here, pattern element elm is a set of one or more pattern elements included in the correction target area zon, and is represented by a "BOUNDARY" row indicating the boundary of the pattern elements, a "LAYER" row indicating layer information to which the pattern element belongs, and an "XY" row indicating vertex information of the pattern element. In other words, pattern element elm[1] is represented as a set of three pattern elements, and pattern element elm[4] is represented as a set of two pattern elements.

In this case, the "LAYER" row displays layer information such as "M1" indicating wiring layer M1, "M2" indicating wiring layer M2, or "VIA" indicating via layer VIA. Also, the "XY" row displays vertex information such as a set of vertex coordinates as "X11a Y11a X11b Y11b X11c Y11c X11d Y11d X11a Y11a". In this case, it displays a rectangle surrounded by the coordinates of the four vertices: [X11a, Y11a], [X11b, Y11b], [X11c, Y11c], and [X11d, Y11d].

[Processing section 114]
8A to 8D are schematic diagrams for explaining the functions of the processing unit 114. The processing unit 114 has a function of creating an instruction statement prpt using a tag tag, vertex information of a pattern element elm, and layer information to which the pattern element elm belongs. The processing unit 114 also has a function of generating a response statement rspn including a layout revision proposal based on the instruction statement prpt using a language model 141, and a function of acquiring the response statement rspn.

The instruction statement prpt is created, for example, as follows: "Please suggest a correction for 'character string based on the information of tag tag' from the following graphic coordinates: 'character string based on the information of pattern element elm'."

Figure 8A shows an example of an instruction prpt created using the pattern element elm[1] shown in Figure 7B and the tag tag[1] shown in Figure 6B. In this case, the "character string based on the information of the tag tag" is, for example, "Double Via". In other words, an instruction prpt such as "Please suggest a correction for Double Via from the following geometric coordinates. Graphic coordinates: "character string based on the information of the pattern element elm[1]"" is created.

FIG. 8C shows an example of an instruction prpt created using the pattern element elm[4] shown in FIG. 7C and the tag tag[4] shown in FIG. 6B. In this case, the "character string based on the information of the tag tag" is, for example, "Bridging." That is, an instruction prpt such as "Please suggest a correction for Bridging from the following geometric coordinates. Graphic coordinates: "Character string based on the information of the pattern element elm[4]"" is created.

Here, the "character string based on the information of the pattern element elm" is expressed as, for example, "M1: RECTANGLE (X1a, Y1a), (X1b, Y1b)." Note that here, as an example, it is expressed as "RECTANGLE" indicating a rectangle, "(X1a, Y1a)" indicating the coordinates of the lower left corner of the rectangle, and "(X1b, Y1b)" indicating the coordinates of the upper right corner of the rectangle.

Note that, in this example, when a "BOUNDARY" that represents a quadrangle bounded by the coordinates of four vertices is a rectangle, it is converted into a "RECTANGLE" that represents a rectangle using the lower left coordinate and the upper right coordinate, thereby reducing the amount of data (here also referred to as the number of characters) of the instruction prpt.

The response sentence rspn is obtained by providing the instruction sentence prpt to the language model 141.

Figure 8B shows an example of a response statement rspn to the instruction statement prpt shown in Figure 8A. That is, for example, a response statement rspn such as "By widening the width of M1 or M2 wiring to P μm, two VIAs can be placed." Note that "P" is replaced with a specific numerical value generated by the language model 141.

Figure 8D shows an example of a response statement rspn to the instruction statement prpt shown in Figure 8C. That is, for example, a response statement rspn such as "The problem will be resolved by widening the width of the M1 wiring by Q μm" is obtained. Note that "Q" is replaced with a specific numerical value generated by the language model 141.

[Processing section 115]
Fig. 9 is a schematic diagram for explaining the functions of the processing unit 115. Fig. 9 is also a schematic diagram showing data stored in the database 151. The processing unit 115 has a function of acquiring an explanatory diagram (dgrm) associated with a tag (tag).

The diagram dgrm is obtained by providing a tag to the database 151. In the database 151, as shown in FIG. 9, the tag "Double Via" is associated with the diagram dgrm "Example of double via". Also, the tag "Bridging" is associated with the diagram dgrm "Example of bridging".

As a result, for example, by providing "Double Via" as the tag in database 151, it is possible to obtain "Example of Double Via" as the explanatory diagram dgrm.

Also, for example, by providing the tag "Bridging" to database 151, it is possible to obtain "Example of Bridging" as the explanatory diagram dgrm.

[Output unit 116]
10A and 10B are schematic diagrams for explaining the functions of the output unit 116. Note that, in the information terminal 30, Fig. 10A and 10B are also schematic diagrams showing a state in which a response sentence rspn is displayed in a text display area txtara and an explanatory diagram dgrm is displayed in an image display area figara of the monitor 191. The output unit 116 has a function of outputting the response sentence rspn. It may further have a function of outputting an explanatory diagram dgrm.

Figure 10A shows how the response statement rspn shown in Figure 8B and the acquired explanatory diagram dgrm are output and displayed on the monitor 191. In other words, it shows how a layout modification proposal based on the double via DFM rule is displayed.

Figure 10B shows how the response statement rspn shown in Figure 8C and the acquired explanatory diagram dgrm are output and displayed on the monitor 191. In other words, it shows how a layout modification proposal based on the bridging DFM rules is displayed.

The user can learn the layout modification proposal proposed by the information processing system of one embodiment of the present invention by viewing the response statement rspn and the explanatory diagram dgrm displayed on the monitor 191. The user can efficiently perform layout design by modifying the circuit pattern in accordance with the proposed layout modification proposal. In other words, it is possible to reduce the design cost and shorten the design period in the layout design of a semiconductor device.

Here, in an information processing system according to one aspect of the present invention, multiple response statements rspn and explanatory diagrams dgrm may be output. For example, as shown in FIG. 6, when six shapes based on previously prepared design rules are extracted, six response statements rspn and explanatory diagrams dgrm are output. At this time, multiple response statements rspn and explanatory diagrams dgrm may be displayed on the monitor 191. In other words, the window wnd2 of the monitor 191 may have multiple text display areas txtara and image display areas figara.

Note that the output unit 116 may output, as the response sentence rspn, a part of the response sentence rspn, or may add an arbitrary character string to the response sentence rspn and output it, or may add an arbitrary character string to a part of the response sentence and output it. In other words, it can be said that the output unit 116 has a function of outputting, as the response sentence rspn, text including at least a part of the response sentence rspn.

In addition, the output unit 116 does not need to output the explanatory diagram dgrm. In this case, the information processing system of one embodiment of the present invention does not need to have the database 151. That is, for example, by outputting the explanatory diagram dgrm, the user can easily know the layout revision proposal. Also, for example, by not outputting the explanatory diagram dgrm, it is not necessary to have the database 151, and therefore it is possible to reduce the introduction cost and operation cost of the information processing system of one embodiment of the present invention.

[Detection model 131, language model 141]
Next, the detection model 131 and the language model 141 will be described.

The detection model 131 can be created, for example, rule-based or by machine learning. In particular, it may be created by machine learning.

For example, when creating a detection model 131 using machine learning, a data set can be prepared that is annotated with images of patterns that require modification in accordance with design rules and tags that indicate the type of design rule.

The language model 141 can be created, for example, rule-based or by machine learning. In particular, it may be created by machine learning.

For example, when creating language model 141 using machine learning, a data set can be prepared in which instruction statements corresponding to patterns that require modification in accordance with design rules are associated with response statements including layout modification suggestions for those patterns.

Here, in the layout design of semiconductor devices, DRC rules are required rules that must be followed, while OPC rules and DFM rules are recommended rules determined through experiments and simulations. Furthermore, OPC rules and DFM rules are a trade-off between the yield and integration level of semiconductor devices, so they depend heavily on the skills of the layout designer.

Therefore, it is preferable that the data set is created using a revision proposal by a highly skilled layout designer. As a result, the information processing system of one embodiment of the present invention can output a layout revision proposal based on the knowledge and experience of a highly skilled layout designer. Therefore, the user can know the layout revision proposal based on the knowledge and experience of a highly skilled layout designer. In other words, even a layout designer with low skills can perform a layout design comparable to that of a highly skilled layout designer. As a result, for example, it is possible to improve the yield of semiconductor devices, improve quality, reduce manufacturing costs, reduce design costs, and shorten the design period. In addition, it is also possible to improve the skills of the layout designer.

Furthermore, for example, due to changes in the manufacturing process of a semiconductor device, the OPC rules and DFM rules may also change. Even in such cases, by creating a data set based on the knowledge and experience of a highly skilled layout designer and fine-tuning the detection model 131 and the language model 141, it is possible to immediately respond to the changes in the manufacturing process.

Note that the detection model 131 and the language model 141 may be created by a person who provides a service using an information processing system of one embodiment of the present invention, or by a person who receives the service.

[Storage unit MEM, calculation unit PRC]
1 and 2, an information processing system according to an aspect of the present invention may have, for example, a memory unit MEM and a calculation unit PRC in each of the information processing device 10, the information processing device 20, and the information terminal 30. For example, each of the component 110, the component 120, the component 130, the component 140, the component 150, and the component 190 may have a memory unit MEM and a calculation unit PRC. The memory unit MEM has, for example, a function of storing information exchanged in the information processing system. The calculation unit PRC has, for example, a function of controlling the exchange of information in the information processing system.

The memory unit MEM has a function of storing the program executed by the calculation unit PRC. The memory unit MEM may also have a function of storing data generated by the calculation unit PRC (e.g., calculation results, analysis results, inference results, etc.).

The storage unit MEM may have a database. Note that an information processing device of one embodiment of the present invention may have a database separate from the storage unit MEM. The information processing device may have a function of retrieving data from a database that exists outside the storage unit MEM, outside the information processing device, or outside the information processing system of one embodiment of the present invention. In addition, the information processing device may have a function of retrieving data from both its own database and an external database.

One or both of the storage and the file server can be used as the memory unit MEM. Also, a database that records the paths of files stored in the file server can be used as the memory unit MEM.

The memory unit MEM has at least one of a volatile memory and a non-volatile memory. Examples of volatile memory include computer-readable recording media such as DRAM (Dynamic Random Access Memory) and SRAM (Static Random Access Memory). Non-volatile memory includes computer-readable recording media such as ReRAM (Resistive Random Access Memory, also known as resistive memory), PRAM (Phase change Random Access Memory), FeRAM (Ferroelectric Random Access Memory), MRAM (Magnetoresistive Random Access Memory, also known as magnetoresistive memory), and flash memory.

The memory unit MEM may also have a recording medium. As the recording medium, a computer-readable recording medium such as a hard disk drive (HDD) and a solid state drive (SSD) may be used. Note that a HDD, SSD, etc. that is detachable from a computer may also be used. Also, a HDD, SSD, etc. that can exchange information via a network may also be used. As the recording medium, a computer-readable recording medium such as a CD (Compact Disc), a DVD (Digital Versatile Disc), a USB memory (Universal Serial Bus Memory), and a SD card (Secure Digital Card) may also be used. In addition, IC (Integrated Circuit) chips, magnetic tapes, and media having at least one of these (cards, tags, etc.) can also be considered to be computer-readable recording media. In addition, media (paper, plastic, metal, etc.) to which codes (sequences of numbers, letters, symbols, etc.), one-dimensional codes (bar codes, etc.), two-dimensional codes (QR Code (registered trademark), etc.) are added can also be considered to be computer-readable recording media.

The memory unit MEM can store, for example, a program for implementing at least a portion of the functions of the above-mentioned component 110 (functions for controlling the operation of an information processing system according to one embodiment of the present invention) on one or more computers (e.g., information processing device 10). It can also store, for example, a program for executing at least a portion of an information processing method according to one embodiment of the present invention described below on one or more computers (e.g., information processing device 10 and information processing device 20).

Here, the program is, for example, for causing one or more computers to realize at least a portion of the functions of the component 110 described above (functions for controlling the operation of an information processing system according to one embodiment of the present invention). Also, the program is, for example, for causing one or more computers to execute at least a portion of an information processing method according to one embodiment of the present invention, which will be described later.

Therefore, one aspect of the present invention can be said to be a program for executing the information processing method of one aspect of the present invention on one or more computers. Also, one aspect of the present invention can be said to be a computer-readable recording medium on which the program is recorded.

The memory unit MEM may also have at least one of NOSRAM (registered trademark) and DOSRAM (registered trademark).

NOSRAM is an abbreviation for "Nonvolatile Oxide Semiconductor Random Access Memory (RAM)". NOSRAM refers to a memory in which the memory cell is a two-transistor (2T) gain cell or a three-transistor (3T) gain cell, and the transistor is an OS transistor. The current that flows between the source and drain in the off state, that is, the off current, of an OS transistor is extremely small. NOSRAM can be used as a nonvolatile memory by retaining a charge according to data in the memory cell using the characteristic of an extremely small off current. In particular, NOSRAM can read the retained data without destroying it (nondestructive read), so it is suitable for arithmetic processing in which only data read operations are repeated in large quantities. Since NOSRAM can increase the data capacity by stacking, it can be used as a large-scale cache memory, main memory, or storage memory to improve the performance of semiconductor devices.

DOSRAM is an abbreviation for "Dynamic Oxide Semiconductor RAM" and refers to a RAM that has 1T (transistor) 1C (capacitor) type memory cells. DOSRAM is a DRAM formed using OS transistors, and is a memory that temporarily stores information sent from the outside. DOSRAM is a memory that takes advantage of the small off-current of OS transistors.

In this specification, metal oxide is a metal oxide in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also called oxide semiconductors or simply OS), and the like. For example, when a metal oxide is used in the semiconductor layer of a transistor, the metal oxide may be called an oxide semiconductor.

The metal oxide in the channel formation region preferably contains indium (In). When the metal oxide in the channel formation region contains indium, the carrier mobility (electron mobility) of the OS transistor is increased. In addition, the metal oxide in the channel formation region is preferably an oxide semiconductor containing element M. The element M is preferably at least one of aluminum (Al), gallium (Ga), and tin (Sn). Other elements that can be used for element M include boron (B), silicon (Si), titanium (Ti), iron (Fe), nickel (Ni), germanium (Ge), yttrium (Y), zirconium (Zr), molybdenum (Mo), lanthanum (La), cerium (Ce), neodymium (Nd), hafnium (Hf), tantalum (Ta), and tungsten (W). However, as element M, a combination of multiple elements described above may be used. The element M is, for example, an element that has a high binding energy with oxygen. For example, it is an element that has a higher bond energy with oxygen than indium. In addition, it is preferable that the metal oxide in the channel formation region is a metal oxide that contains zinc (Zn). Metal oxides that contain zinc may be more likely to crystallize.

The metal oxide of the channel formation region is not limited to a metal oxide containing indium. The metal oxide of the channel formation region may be, for example, a metal oxide containing zinc, a metal oxide containing gallium, or a metal oxide containing tin, which does not contain indium, such as zinc tin oxide or gallium tin oxide.

The calculation unit PRC has a function of performing processes such as calculation, analysis, and inference using data supplied from the memory unit MEM, etc. The calculation unit PRC can supply the generated data (e.g., calculation results, analysis results, inference results) to one or both of the memory unit MEM and the output unit 116.

The calculation unit PRC has a function of acquiring data from the memory unit MEM. The calculation unit PRC may also have a function of recording or registering data in the memory unit MEM.

The calculation unit PRC may have, for example, a calculation circuit. The calculation unit PRC may have, for example, a central processing unit (CPU). The calculation unit PRC may also have a graphics processing unit (GPU).

The calculation unit PRC may have a microprocessor such as a DSP (Digital Signal Processor). The microprocessor may be realized by a PLD (Programmable Logic Device) such as an FPGA (Field Programmable Gate Array) or an FPAA (Field Programmable Analog Array). The calculation unit PRC may also have a quantum processor. The calculation unit PRC can perform various data processing and program control by interpreting and executing instructions from various programs using the processor. Programs that can be executed by the processor are stored in at least one of the memory area and the storage unit MEM of the processor.

The calculation unit PRC may have a main memory. The main memory may have at least one of a volatile memory such as a RAM (Random Access Memory) and a non-volatile memory such as a ROM (Read Only Memory). The main memory may also have at least one of the above-mentioned NOSRAM and DOSRAM.

As the RAM, for example, DRAM, SRAM, etc. are used, and a virtual memory space is allocated and used as a working space for the calculation unit PRC. The operating system, application programs, program modules, program data, lookup tables, etc. stored in the memory unit MEM are loaded into the RAM for execution. These data, programs, and program modules loaded into the RAM are each directly accessed and operated by the calculation unit PRC.

ROM can store BIOS (Basic Input/Output System) and firmware that do not require rewriting. Examples of ROM include mask ROM, OTPROM (One Time Programmable Read Only Memory), and EPROM (Erasable Programmable Read Only Memory). Examples of EPROM include UV-EPROM (Ultra-Violet Erasable Programmable Read Only Memory), which allows stored data to be erased by exposure to ultraviolet light, EEPROM (Electrically Erasable Programmable Read Only Memory), and flash memory.

The calculation unit PRC can have either or both of an OS transistor and a Si transistor.

The computing unit PRC preferably includes an OS transistor. Since the off-state current of an OS transistor is extremely small, by using the OS transistor as a switch for retaining charge (data) flowing into a capacitor functioning as a memory element, the data retention period can be secured for a long period of time. By using this characteristic in at least one of the register and the cache memory of the computing unit PRC, the computing unit PRC can be operated only when necessary, and in other cases, the computing unit PRC can be turned off by saving the information of the immediately previous processing to the memory element. In other words, normally-off computing is possible, and the power consumption of an information processing system according to one embodiment of the present invention can be reduced.

<Other configuration examples of information processing system>
The information processing system according to one embodiment of the present invention is not limited to the above-described configuration example.

Figure 11 is a schematic diagram showing a modified example of the information processing system shown in Figure 2 etc. The information processing system shown in Figure 11 differs from the information processing system shown in Figure 2 etc. in that it does not have an information processing device 20 and that the information processing device 10 has components 110, 120, 130, 140, and 150.

The information processing system shown in FIG. 11 is composed of one information processing device. Therefore, it is possible to reduce the introduction cost and operation cost of the information processing system.

Figure 12 is a schematic diagram showing a modified example of the information processing system shown in Figure 2 etc. The information processing system shown in Figure 12 differs from the information processing system shown in Figure 2 etc. in that the information processing device 20 is not connected to the network 90, the information processing device 10 and the information processing device 20 are each connected to the network 80, and the information processing device 11 is connected to both the network 80 and the network 91. Note that Figure 12 also shows an information terminal 31 connected to the network 91.

The information processing device 10 and the information terminal 30 can exchange information with each other via a network 90. The information processing device 10 and the information processing device 20 can exchange information with each other via a network 80. The information processing device 11 and the information terminal 31 can exchange information with each other via a network 91. The information processing device 11 and the information processing device 20 can exchange information with each other via a network 80.

Since the information processing device 11 is similar to the information processing device 10, and the information terminal 31 is similar to the information terminal 30, detailed explanations will be omitted here.

The information processing system shown in FIG. 12 is suitable, for example, for the case where two different organizations receive a service using an information processing method according to one embodiment of the present invention. That is, for example, network 90 can be a local network constructed in one organization, network 91 can be a local network constructed in the other organization, and network 80 can be a global network. That is, for example, a configuration can be used in which a person providing a service using an information processing method according to one embodiment of the present invention owns information processing device 20, one organization owns information processing device 10, and the other organization owns information processing device 11.

Here, the detection model 131 and the language model 141 possessed by the information processing device 20 are preferably created using a revision proposal by a highly skilled layout designer, and therefore can be said to be highly confidential information. Therefore, when a person who provides a service using an information processing method of one embodiment of the present invention provides the service using a detection model 131 and a language model 141 that they have created themselves, for example, an information processing system as shown in FIG. 12 may be constructed. This can prevent confidential information owned by the person who provides the service from leaking to the outside. Also, when a person who receives a service using an information processing method of one embodiment of the present invention receives the service using a detection model 131 and a language model 141 that they have created themselves, for example, an information processing system as shown in FIG. 2 may be constructed. This can prevent confidential information owned by the person who receives the service from leaking to the outside.

Note that, as an example, a case has been described here in which a service using an information processing method according to one aspect of the present invention is enjoyed by two different organizations, but the present invention can also be applied to cases in which a single organization enjoys the service, and cases in which three or more organizations enjoy the service.

The information processing system according to one embodiment of the present invention is not limited to the above-described configuration example, and can have various configurations.

For example, in the information processing system shown in FIG. 2 etc., the component 120 may be included in the information processing device 20. Also, for example, one or two of the components 130, 140, and 150 may be included in the information processing device 10.

Furthermore, for example, a configuration having three or more information processing devices may be used. In this case, each of the three or more information processing devices may have component 120, component 130, component 140, and component 150 as appropriate. In this way, by increasing the number of information processing devices, the load related to information processing can be distributed.

Note that one aspect of the present invention is not limited to the information processing system and information processing device described in this embodiment. At least a part of the information processing system and information processing device exemplified in this embodiment, and the corresponding drawings, etc., can be appropriately combined.

(Embodiment 2)
An information processing method according to one embodiment of the present invention will be described with reference to the drawings. The information processing method according to one embodiment of the present invention can be used for, for example, layout design of a semiconductor device.

Figure 13 is a flowchart illustrating an example of an information processing method according to one aspect of the present invention.

Figure 13 illustrates steps S11 to S18.

In step S11, an image img corresponding to a processing range rng, which is at least a part of the layout lyot of the semiconductor device, is received (see Figures 5A and 5B, etc.).

For example, when a layout lyot is displayed in a layout work area wrkara on a monitor 191 of an information terminal 30 operated by a user (e.g., a layout designer of a semiconductor device), the user may operate the mouse pointer mpt with the mouse 192 to select a processing range rng (e.g., drag and drop), and create and accept an image img corresponding to the processing range rng (e.g., a screen capture of the processing range rng) (see Figures 3, 5A, 5B, etc.).

In step S12, a detection model 131 is used to extract a shape based on a previously prepared design rule from the image img, and a tag indicating the type of the design rule and a bounding box bbox indicating the position of the shape are assigned to the shape (see Figures 6A and 6B, etc.).

In step S13, the position of the area zon to be modified in the layout lyot, which corresponds to the position of the bounding box bbox in the image img, is calculated (see Figure 7A, etc.).

In step S14, vertex information of the pattern element elm contained in the correction target area zon and layer information to which the pattern element belongs are obtained (see Figures 7B and 7C, etc.).

In step S15, the instruction statement prpt is created using the tag tag, the vertex information of the pattern element elm, and the layer information to which the pattern element elm belongs (see Figures 8A and 8C, etc.).

In step S16, the language model 141 is used to generate a response sentence rspn including a layout revision proposal based on the instruction sentence prpt (see Figures 8B and 8D, etc.).

In step S17, the explanatory diagram dgrm associated with the tag tag is obtained (see Figure 9, etc.).

In step S18, the response text rspn and the explanatory diagram dgrm are output (see Figures 10A and 10B, etc.).

For example, on the information terminal 30 operated by the user, the response sentence rspn can be displayed in the text display area txtara of the monitor 191, and the explanatory diagram dgrm can be displayed in the image display area figara (see Figures 3, 10A, and 10B, etc.).

Through steps S11 to S18, the user can learn about layout modification proposals based on pre-prepared design rules for the processing range rng, which is part of the layout lyot.

Here, as the pre-prepared design rules, design rules based on the knowledge and experience of a highly skilled layout designer may be prepared. As a result, a layout modification proposal based on the knowledge and experience of the highly skilled layout designer is output. Therefore, by modifying the circuit pattern in accordance with the layout modification proposal, even a layout designer with low skills can create a layout design comparable to that of a highly skilled layout designer.

Therefore, the information processing method according to one embodiment of the present invention can improve the yield of semiconductor devices, improve quality, reduce manufacturing costs, reduce design costs, and shorten design time. For example, even if a change occurs in the manufacturing process, the change can be immediately addressed by updating the design rules. For example, the skills of layout designers can be improved.

The information processing method shown in this embodiment can be implemented, for example, by the information processing system shown in the above-mentioned embodiment 1. For example, step S11 can be implemented by the input unit 111 or the like. Step S12 can be implemented by the processing unit 113 and the detection model 131 or the like. Step S13 and step S14 can be implemented by the processing unit 112 or the like. Step S15 can be implemented by the processing unit 114 or the like. Step S16 can be implemented by the processing unit 114 and the language model 141 or the like. Step S17 can be implemented by the processing unit 115 or the like. Step S18 can be implemented by the output unit 116 or the like.

Therefore, the explanation of the above-mentioned first embodiment can be referred to for each step as appropriate.

Note that, in one aspect of the present invention, some of the steps described above may not be performed. For example, step S17 may not be performed. In that case, in step S18, only the response sentence rspn may be output.

Note that one aspect of the present invention is not limited to the information processing method described in this embodiment. The information processing method exemplified in this embodiment and the corresponding drawings and the like can be combined at least in part as appropriate.

10: Information processing device, 11: Information processing device, 20: Information processing device, 30: Information terminal, 31: Information terminal, 80: Network, 90: Network, 91: Network, 110: Component, 111: Input unit, 112: Processing unit, 113: Processing unit, 114: Processing unit, 115: Processing unit, 116: Output unit, 119: Transmission path, 120: Component, 121: Layout data, 130: Component, 131: Detection model, 140: Component, 141: Language model, 150: Component, 151: Database, 190: Component, 191: Monitor, 192: Mouse, wnd1: window, wnd2: window, mpt: mouse pointer, wrkara: layout work area, txtara: text display area, figara: image display area, lyot: layout, rng: processing range, img: image, bbox: bounding box, tag: tag, zon: area to be modified, elm: pattern element, prpt: instruction statement, rspn: response statement, dgrm: explanatory diagram, S11: step, S12: step, S13: step, S14: step, S15: step, S16: step, S17: step, S18: step

Claims (6)

An information processing system for layout design of a semiconductor device, comprising:
An input unit, a first processing unit, a second processing unit, a third processing unit, and an output unit,
the input unit has a function of receiving an image corresponding to a processing range which is at least a part of a layout of the semiconductor device;
the first processing unit has a function of extracting a shape based on a previously prepared design rule from the image by using a detection model, a function of assigning a tag indicating a type of the design rule and a bounding box indicating a position of the shape to the shape by using the detection model, and a function of acquiring the tag and the bounding box;
the second processing unit has a function of acquiring vertex information of a pattern element included in a correction target area that is a part of the layout, and layer information to which the pattern element belongs;
the location of the modification area corresponds to the location of the bounding box in the image;
the third processing unit has a function of creating an instruction sentence by using the tag, the vertex information, and the layer information, a function of generating a response sentence including a layout modification proposal based on the instruction sentence by using a language model, and a function of acquiring the response sentence;
The output unit has a function of outputting the response sentence.
Information processing system. In claim 1,
Further, a fourth processing unit is provided,
The fourth processing unit has a function of acquiring an explanatory diagram associated with the tag,
The output unit further has a function of outputting the explanatory diagram.
Information processing system. In claim 1 or 2,
The design rule is:
Including rules established based on manufacturable design technology,
Information processing system. An information processing method relating to layout design of a semiconductor device, comprising:
The method includes steps 1 to 7,
In the first step, an image corresponding to a processing range that is at least a part of a layout of the semiconductor device is received;
In the second step, a shape based on a design rule prepared in advance is extracted from the image by using a detection model, and a tag indicating a type of the design rule and a bounding box indicating a position of the shape are assigned to the shape;
In the third step, a position of a modification target area in the layout is calculated, the position corresponding to the position of the bounding box in the image;
In the fourth step, vertex information of the pattern element included in the correction target area and layer information to which the pattern element belongs are obtained;
In the fifth step, a directive is generated using the tag, the vertex information, and the layer information;
In the sixth step, a response sentence including a layout modification proposal based on the instruction sentence is generated by using a language model;
In the seventh step, the response sentence is output.
Information processing methods. In claim 4,
an eighth step before the seventh step,
In the eighth step, an explanatory diagram associated with the tag is obtained;
In the seventh step, the explanatory diagram is further output.
Information processing methods. In claim 4 or claim 5,
The design rule is:
Including rules established based on manufacturable design technology,
Information processing methods.

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