WO2025083530A1 - Semiconductor device - Google Patents

Abstract

Provided is a semiconductor device having a small footprint. This semiconductor device includes a first transistor, a second transistor, and a first insulating layer. The first transistor includes a first conductive layer, a first metal oxide layer, a gate insulating layer, and a first gate electrode. The second transistor includes a second conductive layer, a third conductive layer, a second metal oxide layer, a gate insulating layer, and a second gate electrode. The first insulating layer is located above the first conductive layer and the second conductive layer and includes a first opening reaching the first conductive layer. The first insulating layer and the third conductive layer include a second opening reaching the second conductive layer. The first metal oxide layer includes: a first region in contact with the upper surface of the first conductive layer; a second region in contact with a lateral surface of the first insulating layer; and a third region in contact with the upper surface of the first insulating layer. The third region is in contact with the second region. The second metal oxide layer is in contact with the upper surface of the second conductive layer, the lateral surface of the first insulating layer, and a lateral surface of the third conductive layer.

Description

Semiconductor Device

One aspect of the present invention relates to a semiconductor device and a manufacturing method thereof. One aspect of the present invention relates to a transistor and a manufacturing method thereof. One aspect of the present invention relates to a display device having a semiconductor device.

Note that one embodiment of the present invention is not limited to the above technical field. Examples of technical fields of one embodiment of the present invention include semiconductor devices, display devices, light-emitting devices, power storage devices, memory devices, electronic devices, lighting devices, input devices (e.g., touch sensors), input/output devices (e.g., touch panels), driving methods thereof, or manufacturing methods thereof.

In this specification and the like, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (transistor, diode, photodiode, etc.), a device having such a circuit, etc. Also, it refers to any device that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip including an integrated circuit, and an electronic component that houses a chip in a package are examples of semiconductor devices. Also, memory devices, display devices, light-emitting devices, lighting devices, and electronic devices may themselves be semiconductor devices and each may have a semiconductor device.

Semiconductor devices having transistors are widely used in electronic devices. For example, in display devices, pixel size can be reduced and resolution can be increased by reducing the area occupied by transistors. For this reason, there is a demand for miniaturized transistors.

Devices requiring high-definition display devices, such as those for virtual reality (VR), augmented reality (AR), substitute reality (SR), and mixed reality (MR), are being actively developed.

As display devices, for example, light-emitting devices having organic EL (Electro Luminescence) elements or light-emitting diodes (LEDs: Light Emitting Diodes) have been developed.

Patent document 1 discloses a high-definition display device that uses organic EL elements.

International Publication No. 2016/038508

An object of one embodiment of the present invention is to provide a semiconductor device having a fine-sized transistor. Alternatively, an object of the present invention is to provide a semiconductor device having a transistor with a short channel length. Alternatively, an object of the present invention is to provide a semiconductor device having a transistor with high on-state current. Alternatively, an object of the present invention is to provide a semiconductor device having a transistor with high field-effect mobility. Alternatively, an object of the present invention is to provide a transistor with a small occupancy area. Alternatively, an object of the present invention is to provide a semiconductor device having a transistor with high saturation. Alternatively, an object of the present invention is to provide a semiconductor device having a transistor with good electrical characteristics. Alternatively, an object of the present invention is to provide a semiconductor device that operates at high speed. Alternatively, an object of the present invention is to provide a semiconductor device with a small occupancy area. Alternatively, an object of the present invention is to provide a semiconductor device with low wiring resistance. Alternatively, an object of the present invention is to provide a semiconductor device or display device with low power consumption. Alternatively, an object of the present invention is to provide a highly reliable transistor, semiconductor device, or display device. Alternatively, an object of the present invention is to provide a high-definition display device. Alternatively, an object of the present invention is to provide a method for manufacturing a semiconductor device or display device with high productivity. Alternatively, an object of the present invention is to provide a new transistor, semiconductor device, or display device, or a manufacturing method thereof.

Note that the description of these problems does not preclude the existence of other problems. One embodiment of the present invention does not necessarily have to solve all of these problems. Problems other than these can be extracted from the description in the specification, drawings, and claims.

One aspect of the present invention is a semiconductor device having a first transistor, a second transistor, and a first insulating layer. The first transistor has a first conductive layer, a first metal oxide layer, a gate insulating layer, and a first gate electrode. The second transistor has a second conductive layer, a third conductive layer, a second metal oxide layer, a gate insulating layer, and a second gate electrode. The first insulating layer is located on the first conductive layer and the second conductive layer. The third conductive layer has a region that overlaps with the second conductive layer via the first insulating layer. The first insulating layer has a first opening that reaches the first conductive layer. The first insulating layer and the third conductive layer have a second opening that reaches the second conductive layer. The first metal oxide layer has a first region in contact with the top surface of the first conductive layer at the first opening, a second region in contact with the side surface of the first insulating layer at the first opening, and a third region in contact with the top surface of the first insulating layer. The third region is in contact with the second region. The second metal oxide layer has a fourth region in contact with the top surface of the second conductive layer at the second opening, a fifth region in contact with the side surface of the first insulating layer at the second opening, and a sixth region in contact with the side surface of the third conductive layer at the second opening. The first region, the third region, and the fourth region each have a first element. The first element is boron or phosphorus. The gate insulating layer is located on the first metal oxide layer and the second metal oxide layer, and is in contact with the first metal oxide layer and the second metal oxide layer. The first gate electrode has a region that overlaps with the first metal oxide layer through the gate insulating layer in the first opening. The second gate electrode has a region that overlaps with the second metal oxide layer through the gate insulating layer in the second opening.

In the above-mentioned semiconductor device, the first region preferably has a portion having a higher concentration of the first element than the second region. The third region preferably has a portion having a higher concentration of the first element than the second region. The fourth region preferably has a portion having a higher concentration of the first element than the fifth region.

In the above-mentioned semiconductor device, the second metal oxide layer preferably has a seventh region in contact with the upper surface of the third conductive layer. The seventh region preferably has the first element. The seventh region preferably has a portion having a higher concentration of the first element than the fifth region.

In the above-mentioned semiconductor device, the gate insulating layer preferably contains the first element.

In the semiconductor device described above, it is preferable that the angle between the side surface of the first insulating layer at the first opening and the top surface of the first conductive layer is greater than or equal to 65 degrees and less than or equal to 90 degrees.

In the above-mentioned semiconductor device, the first insulating layer preferably includes a second insulating layer and a third insulating layer on the second insulating layer. The second insulating layer preferably includes silicon and oxygen. The third insulating layer preferably includes silicon and nitrogen.

In the above-mentioned semiconductor device, the first insulating layer preferably has a second insulating layer and a third insulating layer on the second insulating layer. The second insulating layer preferably has silicon and oxygen. The third insulating layer preferably has one or both of aluminum and hafnium and oxygen.

According to one embodiment of the present invention, a semiconductor device having a finely sized transistor can be provided. Or a semiconductor device having a transistor with a short channel length can be provided. Or a semiconductor device having a transistor with a large on-state current can be provided. Or a semiconductor device having a transistor with high field-effect mobility can be provided. Or a transistor with a small occupancy area can be provided. Or a semiconductor device having a highly saturation transistor can be provided. Or a semiconductor device having a transistor with good electrical characteristics can be provided. Or a semiconductor device that operates at high speed can be provided. Or a semiconductor device with a small occupancy area can be provided. Or a semiconductor device with low wiring resistance can be provided. Or a semiconductor device or display device with low power consumption can be provided. Or a highly reliable transistor, semiconductor device, or display device can be provided. Or a high-definition display device can be provided. Or a method for manufacturing a semiconductor device or display device with high productivity can be provided. Or a novel transistor, semiconductor device, display device, or a manufacturing method thereof can be provided.

Note that the description of these effects does not preclude the existence of other effects. One embodiment of the present invention does not necessarily have to have all of these effects. Effects other than these can be extracted from the description in the specification, drawings, and claims.

Fig. 1A is a top view illustrating an example of a semiconductor device, and Fig. 1B and Fig. 1C are cross-sectional views illustrating the example of the semiconductor device.
2A to 2D are perspective views showing an example of a semiconductor device.
3A and 3B are cross-sectional views showing an example of a semiconductor device.
Fig. 4A is a top view illustrating an example of a semiconductor device, and Fig. 4B and Fig. 4C are cross-sectional views illustrating the example of the semiconductor device.
5A and 5B are cross-sectional views showing an example of a semiconductor device.
6A and 6B are cross-sectional views showing an example of a semiconductor device.
FIG. 7 is a cross-sectional view showing an example of a semiconductor device.
8A to 8C are cross-sectional views showing an example of a semiconductor device.
9A to 9C are cross-sectional views showing an example of a semiconductor device.
10A to 10C are cross-sectional views showing an example of a semiconductor device.
11A and 11B are cross-sectional views showing an example of a semiconductor device.
12A and 12B are cross-sectional views showing an example of a semiconductor device.
Fig. 13A is a top view illustrating an example of a semiconductor device, and Fig. 13B and Fig. 13C are cross-sectional views illustrating the example of the semiconductor device.
14A and 14B are cross-sectional views showing an example of a semiconductor device.
15A to 15E are cross-sectional views showing an example of a semiconductor device.
16A to 16C are cross-sectional views showing an example of a semiconductor device.
17A and 17B are cross-sectional views showing an example of a semiconductor device.
18A to 18E are circuit diagrams showing an example of a semiconductor device.
19A is a top view illustrating an example of a semiconductor device, and FIG 19B is a cross-sectional view illustrating the example of the semiconductor device.
20A is a top view illustrating an example of a semiconductor device, and FIG 20B is a cross-sectional view illustrating the example of the semiconductor device.
21A is a top view illustrating an example of a semiconductor device, and FIG 21B is a cross-sectional view illustrating the example of the semiconductor device.
Fig. 22A is a top view illustrating an example of a semiconductor device, and Fig. 22B and Fig. 22C are cross-sectional views illustrating an example of the semiconductor device.
23A is a top view illustrating an example of a semiconductor device, and FIG 23B is a cross-sectional view illustrating the example of the semiconductor device.
24A to 24E are cross-sectional views showing an example of a method for manufacturing a semiconductor device.
25A to 25D are cross-sectional views showing an example of a method for manufacturing a semiconductor device.
26A to 26D are cross-sectional views showing an example of a method for manufacturing a semiconductor device.
27A and 27B are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device.
Fig. 28A is a perspective view showing an example of a display device, and Fig. 28B is a block diagram showing an example of the display device.
29A to 29D are circuit diagrams of pixel circuits.
30A to 30C are circuit diagrams of pixel circuits.
31A and 31B are cross-sectional views showing an example of a display device.
FIG. 32 is a cross-sectional view showing an example of a display device.
33A to 33C are cross-sectional views showing an example of a display device.
34A and 34B are cross-sectional views showing an example of a display device.
FIG. 35 is a cross-sectional view showing an example of a display device.
FIG. 36 is a cross-sectional view showing an example of a display device.
FIG. 37 is a cross-sectional view showing an example of a display device.
FIG. 38 is a cross-sectional view showing an example of a display device.
39A to 39F are cross-sectional views showing an example of a method for manufacturing a display device.
40A to 40D are diagrams showing an example of an electronic device.
41A to 41F are diagrams showing an example of an electronic device.
42A to 42G are diagrams showing an example of an electronic device.

The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and those skilled in the art will easily understand that the form and details can be modified in various ways without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments shown below.

In the configuration of the invention described below, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and repeated explanations will be omitted. In addition, when referring to similar functions, the same hatching pattern may be used and no particular reference numeral may be used.

The position, size, range, etc. of each component shown in the drawings may not represent the actual position, size, range, etc., for ease of understanding. Therefore, the disclosed invention is not necessarily limited to the position, size, range, etc., disclosed in the drawings.

In this specification, the ordinal numbers "first" and "second" are used for convenience and do not limit the number of components or the order of the components (e.g., process order or stacking order). In addition, an ordinal number attached to a component in one place in this specification may not match an ordinal number attached to the same component in another place in this specification or in the claims.

The words "film" and "layer" can be interchanged depending on the circumstances or situation. For example, the term "conductive layer" can be changed to the term "conductive film." Or, for example, the term "insulating film" can be changed to the term "insulating layer."

A transistor is a type of semiconductor element that can perform functions such as amplifying current or voltage, and switching operations that control conduction or non-conduction. In this specification, the term "transistor" includes IGFETs (Insulated Gate Field Effect Transistors) and thin film transistors (TFTs).

The functions of "source" and "drain" may be interchangeable when transistors of different polarity are used, or when the direction of current changes during circuit operation. For this reason, in this specification and elsewhere, the terms "source" and "drain" may be used interchangeably. The source and drain of a transistor may be referred to as the source terminal and drain terminal, or the source electrode and drain electrode, or other appropriate terms depending on the situation.

"Gate" and "backgate" can be used interchangeably. For this reason, in this specification and the like, the terms "gate" and "backgate" can be used interchangeably. Note that the names of the gate and backgate of a transistor can be appropriately changed depending on the situation, such as gate electrode and backgate electrode.

In this specification, "electrically connected" includes cases where the connection is made via "something that has some kind of electrical action." Here, "something that has some kind of electrical action" is not particularly limited as long as it allows the transmission and reception of electrical signals between the connected objects. For example, "something that has some kind of electrical action" includes electrodes or wiring, as well as switching elements such as transistors, resistive elements, coils, and other elements with various functions.

In this specification, unless otherwise specified, on-current refers to the drain current (also written as Id) when a transistor is in the on state (also called the conductive state). Unless otherwise specified, the on state refers to a state in which the voltage between the gate and source (also written as Vg or Vgs) is equal to or higher than the threshold voltage (also written as Vth) in an n-channel transistor, and a state in which it is equal to or lower than the threshold voltage in a p-channel transistor.

Unless otherwise specified in this specification, the off-state current refers to the leakage current between the source and drain when the transistor is in the off state (also called the non-conducting state or cut-off state).Unless otherwise specified, the off-state refers to a state in which the voltage between the gate and source is lower than the threshold voltage in an n-channel transistor, and a state in which the voltage is higher than the threshold voltage in a p-channel transistor.

In this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10 degrees or more and 10 degrees or less. This therefore includes cases in which the angle is -5 degrees or more and 5 degrees or less. "Approximately parallel" refers to a state in which two straight lines are arranged at an angle of -30 degrees or more and 30 degrees or less. "Perpendicular" refers to a state in which two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. This therefore includes cases in which the angle is 85 degrees or more and 95 degrees or less. "Approximately perpendicular" refers to a state in which two straight lines are arranged at an angle of 60 degrees or more and 120 degrees or less.

In this specification, "top surface shapes roughly match" means that at least a portion of the contours of the stacked layers overlap. For example, this includes cases where the upper and lower layers are processed using the same mask pattern, or where parts of the mask pattern are the same. However, strictly speaking, the contours may not overlap, and the upper layer may be located inside the lower layer, or outside the lower layer, in which case it may also be said that "top surface shapes roughly match." Furthermore, when the top surface shapes match or roughly match, it can also be said that the edges are aligned or roughly aligned.

In this specification, a tapered shape refers to a shape in which at least a portion of the side of the structure is inclined with respect to the substrate surface or the surface to be formed. For example, it is preferable to have a region in which the angle (also called the taper angle) between the inclined side and the substrate surface or the surface to be formed is less than 90 degrees. Note that the side of the structure, the substrate surface, and the surface to be formed do not necessarily need to be completely flat, and may be approximately planar with a slight curvature, or approximately planar with fine irregularities.

In this specification, etc., a device manufactured using a metal mask or an FMM (fine metal mask, high-definition metal mask) may be referred to as a device with an MM (metal mask) structure. Also, in this specification, etc., a device manufactured without using a metal mask or an FMM may be referred to as a device with an MML (metal maskless) structure. Note that since devices with an MML structure can be manufactured without using a metal mask, they can exceed the upper limit of fineness resulting from the alignment accuracy of the metal mask. Furthermore, devices with an MML structure can eliminate the need for equipment related to the manufacture of metal masks and the process of cleaning the metal masks. Furthermore, devices with an MML structure are suitable for mass production because they make it possible to keep manufacturing costs low.

In this specification, a structure in which separate light-emitting layers are created for light-emitting elements (also called light-emitting devices) with different emission wavelengths is sometimes referred to as an SBS (Side By Side) structure.

In this specification and the like, holes or electrons may be referred to as "carriers". For example, the hole injection layer or electron injection layer in a light-emitting element may be referred to as a "carrier injection layer", the hole transport layer or electron transport layer may be referred to as a "carrier transport layer", and the hole block layer or electron block layer may be referred to as a "carrier block layer". Note that the above-mentioned carrier injection layer, carrier transport layer, and carrier block layer may not be clearly distinguishable. Also, one layer may have two or three functions among the carrier injection layer, carrier transport layer, and carrier block layer.

In this specification, the light-emitting element has an EL layer between a pair of electrodes. The EL layer has at least a light-emitting layer. Here, examples of layers (also called functional layers) that the EL layer has include a light-emitting layer, a carrier injection layer (hole injection layer and electron injection layer), a carrier transport layer (hole transport layer and electron transport layer), and a carrier block layer (hole block layer and electron block layer). In this specification, the light-receiving element (also called a light-receiving device) has at least an active layer that functions as a photoelectric conversion layer between a pair of electrodes. In this specification, one of the pair of electrodes may be referred to as a pixel electrode, and the other as a common electrode.

In this specification, the sacrificial layer is a layer that is located at least above the light-emitting layer (more specifically, the layer that is processed into an island shape among the layers that make up the EL layer) and has the function of protecting the light-emitting layer during the manufacturing process.

In this specification, step discontinuity refers to the phenomenon in which a layer, film, or electrode is separated due to the shape of the surface on which it is formed (e.g., a step, etc.).

(Embodiment 1)
In this embodiment, a semiconductor device of one embodiment of the present invention will be described with reference to FIGS. 1A to 23B.

One aspect of the present invention is a semiconductor device having a first transistor, a second transistor, and a first insulating layer.

The first transistor has a first conductive layer, a first metal oxide layer, a gate insulating layer, and a first gate electrode. In the first transistor, the first conductive layer functions as one of a source electrode and a drain electrode. The first metal oxide layer has a region that functions as the other of the source electrode and drain electrode of the first transistor, and also has a channel formation region. In the first transistor, the region of the first metal oxide layer that is in contact with the first conductive layer functions as one of a source region and a drain region.

The second transistor has a second conductive layer, a third conductive layer, a second metal oxide layer, a gate insulating layer, and a second gate electrode. In the second transistor, the second conductive layer functions as one of the source electrode and the drain electrode, and the third conductive layer functions as the other of the source electrode and the drain electrode. The second metal oxide layer has a channel formation region of the second transistor. In addition, in the second transistor, a region of the second metal oxide layer in contact with the second conductive layer functions as one of the source region and the drain region, and a region of the second metal oxide layer in contact with the third conductive layer functions as the other of the source region and the drain region.

The first insulating layer is located on the first conductive layer and the second conductive layer. The third conductive layer has an area that overlaps with the second conductive layer via the first insulating layer. The first insulating layer has a first opening that reaches the first conductive layer. The first insulating layer and the third conductive layer have a second opening that reaches the second conductive layer.

The first metal oxide layer has a first region that contacts the top surface of the first conductive layer at the first opening, a second region that contacts the side surface of the first insulating layer at the first opening, and a third region that contacts the top surface of the first insulating layer. The third region contacts the second region.

The second metal oxide layer has a fourth region in contact with the top surface of the second conductive layer at the second opening, a fifth region in contact with the side surface of the first insulating layer at the second opening, and a sixth region in contact with the side surface of the third conductive layer at the second opening. Furthermore, it is preferable that the second metal oxide layer has a seventh region in contact with the top surface of the third conductive layer.

The gate insulating layer is located on the first metal oxide layer and the second metal oxide layer, and is in contact with the first metal oxide layer and the second metal oxide layer. The first gate electrode has a region that overlaps with the first metal oxide layer through the gate insulating layer at the first opening. The second gate electrode has a region that overlaps with the second metal oxide layer through the gate insulating layer at the second opening.

The first region, the third region, the fourth region, and the seventh region each have a first element as an impurity element. For example, boron or phosphorus can be suitably used as the first element. By having the first region, the third region, the fourth region, and the seventh region have the first element, the electrical resistance of these regions can be reduced. This allows the third region to function as the other of the source electrode and drain electrode of the first transistor. Furthermore, reducing the electrical resistance of one of the source region and drain region of the first transistor can increase the on-current. Similarly, the electrical resistance of the source region and drain region of the second transistor can be reduced, and the on-current can be increased.

The channel length of the first transistor and the second transistor can be controlled by the thickness of the insulating layer sandwiched between the source electrode and the drain electrode. In other words, the channel length of the first transistor and the second transistor is not affected by the exposure performance of the exposure device used in the fabrication. Therefore, the channel length of the first transistor and the second transistor can be made shorter than the minimum value of the dimension that the exposure device can expose (hereinafter also referred to as the minimum dimension). By shortening the channel length, it is possible to make the transistor have a large on-current. In addition, since the source electrode, the layer having the channel formation region, and the drain electrode can be provided in an overlapping manner, the occupation area of the semiconductor device can be significantly reduced.

In the first transistor, since the first metal oxide layer has a third region that functions as the other of the source electrode and drain electrode, there is no need to provide a conductive layer that functions as the other of the source electrode and drain electrode. Therefore, by using the first transistor, the occupation area of the semiconductor device can be further reduced. Depending on the material used for the first metal oxide layer, the electrical resistance of the third conductive layer that functions as the other of the source electrode and drain electrode of the second transistor may be lower than the electrical resistance of the third region that functions as the other of the source electrode and drain electrode of the first transistor. When the other of the source electrode and drain electrode functions as wiring and the wiring resistance required for the wiring is relatively low, the second transistor can be preferably used.

Below, more specific examples are explained using drawings.

<Configuration Example 1>
[Configuration Example 1-1]
A semiconductor device according to one embodiment of the present invention will be described. A top view (also referred to as a plan view) of a semiconductor device 10 is shown in FIG 1A. A cross-sectional view of a cut surface taken along dashed dotted line A1-A2 in FIG 1A is shown in FIG 1B, and cross-sectional views of cut surfaces taken along dashed dotted line B1-B2 and dashed dotted line B3-B4 are shown in FIG 1C. Note that some of the components of the semiconductor device 10 (such as a gate insulating layer) are omitted in FIG 1A. As in FIG 1A, some of the components are omitted in the top views of the semiconductor device in the following drawings.

The semiconductor device 10 includes a transistor 100, a transistor 200, and an insulating layer 110. The semiconductor device 10 is provided on an insulating surface. FIGS. 1B and 1C show a configuration in which the semiconductor device 10 is provided on a substrate 102 having an insulating surface. Note that an insulating film may be provided on the substrate 102, and the semiconductor device 10 may be provided on the insulating film. The transistors 100 and 200 have different structures, and can be formed on the same substrate by sharing some of the processes.

The perspective views of the transistor 100 are shown in Figs. 2A and 2B. Fig. 2B shows a cross section taken along dashed line C1-C2 in Fig. 2A. The perspective views of the transistor 200 are shown in Figs. 2C and 2D. Fig. 2D shows a cross section taken along dashed line C3-C4 in Fig. 2C. Note that in Figs. 2A to 2D, the insulating layer 110 and the insulating layer 106 are shown in a transparent manner with their contours indicated by dashed lines. An enlarged view of the transistor 100 shown in Fig. 1B is shown in Fig. 3A, and an enlarged view of the transistor 200 is shown in Fig. 3B.

The transistor 100 has a conductive layer 104, an insulating layer 106, a layer 108, and a conductive layer 112. In the transistor 100, the conductive layer 104 functions as a gate electrode, the insulating layer 106 functions as a gate insulating layer, and the conductive layer 112 functions as one of a source electrode and a drain electrode. The layer 108 includes a semiconductor material. The layer 108 has a channel formation region of the transistor 100 and a region that functions as the other of the source electrode and the drain electrode.

The transistor 200 has a conductive layer 204, an insulating layer 106, a layer 208, a conductive layer 212a, and a conductive layer 212b. In the transistor 200, the conductive layer 204 functions as a gate electrode, the insulating layer 106 functions as a gate insulating layer, the conductive layer 212a functions as one of a source electrode and a drain electrode, and the conductive layer 212b functions as the other of the source electrode and drain electrode. The layer 208 includes a semiconductor material. The layer 208 has a channel formation region of the transistor 200.

An insulating layer 195 is provided to cover the transistors 100 and 200. The insulating layer 195 functions as a protective layer for the transistors 100 and 200. Note that the insulating layer 195 is omitted in the perspective views shown in Figures 2A to 2D.

The conductive layer 112 and the conductive layer 212a are provided on the substrate 102, the insulating layer 110 is provided on the conductive layer 112 and the conductive layer 212a, and the conductive layer 212b is provided on the insulating layer 110. The insulating layer 110 has a region in contact with the upper surface and side surface of the conductive layer 112, the upper surface and side surface of the conductive layer 212a, and the upper surface of the substrate 102. The conductive layer 212b has a region in contact with the upper surface of the insulating layer 110. The conductive layer 212b has a region that overlaps with the conductive layer 212a via the insulating layer 110. It can also be said that the insulating layer 110 has a region sandwiched between the conductive layer 212a and the conductive layer 212b. The conductive layer 212a can be formed in the same process as the conductive layer 112. For example, the conductive layer 112 and the conductive layer 212a can be formed by forming a film that becomes the conductive layer 112 and the conductive layer 212a and processing the film. Alternatively, the conductive layer 212a can be formed in a process different from that of the conductive layer 112. By forming the conductive layer 212a and the conductive layer 112 in different processes, different materials can be used for the conductive layer 212a and the conductive layer 112, which allows a wider range of material selection.

The insulating layer 110 has an opening 141 that reaches the conductive layer 112, and an opening 241 that reaches the conductive layer 212a. It can also be said that the conductive layer 112 is exposed in the opening 141, and the conductive layer 212a is exposed in the opening 241. The opening 241 can be formed in the same process as the opening 141. For example, the insulating layer 110 having the openings 141 and 241 can be formed by forming a film that will become the insulating layer 110 on the conductive layer 112 and the conductive layer 212a, and processing the film. Alternatively, the opening 241 can be formed in a process different from that of the opening 141.

The conductive layer 212b has an opening 243 in a region overlapping with the conductive layer 212a. The opening 243 is provided in a region overlapping with the opening 241. Note that in FIG. 1B and other figures, the opening 241 in the insulating layer 110 and the opening 243 in the conductive layer 212b are given different reference numerals, but these openings can be collectively referred to as one opening. In other words, the insulating layer 110 and the conductive layer 212b can be said to have openings that reach the conductive layer 212a.

The layer 108 is provided so as to cover the opening 141. The layer 108 is provided along the opening 141. The layer 108 has a region in contact with the top surface of the conductive layer 112 in the opening 141, a region in contact with the side surface of the insulating layer 110 in the opening 141, and a region in contact with the top surface of the insulating layer 110. The layer 108 has a shape that matches the shapes of the top surface and side surface of the insulating layer 110 and the top surface of the conductive layer 112. The region of the layer 108 in contact with the conductive layer 112 functions as one of the source region and drain region of the transistor 100.

Layer 108 has a first region that contacts conductive layer 112 at opening 141, a second region that contacts the side of insulating layer 110 at opening 141, and a third region that contacts the top surface of insulating layer 110. The third region contacts the second region. The second region contacts the first region. It can also be said that the third region is continuous with the second region, and the second region is continuous with the first region. Or, it can also be said that the third region is continuous with the second region, and the second region is continuous with the first region.

The layer 208 is provided so as to cover the opening 241 and the opening 243. The layer 208 is provided along the opening 241 and the opening 243. The layer 208 has a region in contact with the upper surface of the conductive layer 212a in the opening 241, a region in contact with the side of the insulating layer 110 in the opening 241, and a region in contact with the side of the conductive layer 212b in the opening 243. Furthermore, the layer 208 preferably has a region in contact with the upper surface of the conductive layer 212b. The layer 208 has a shape that conforms to the shapes of the upper surface and side of the conductive layer 212b, the side of the insulating layer 110, and the upper surface of the conductive layer 212a. The region of the layer 208 in contact with the conductive layer 212a functions as one of the source region and the drain region of the transistor 200, and the region in contact with the conductive layer 212b functions as the other of the source region and the drain region.

It is preferable that the conductive layer 212b has a region in contact with the insulating layer 110 and the layer 208 and sandwiched therebetween. When the layer 208 is in contact with not only the side surface but also the top surface of the conductive layer 212b, the contact area between the layer 208 and the conductive layer 212b is increased, and the contact resistance between the layer 208 and the conductive layer 212b can be reduced. This can increase the on-current of the transistor 200. Note that although FIG. 1B and other figures show a structure in which the end of the layer 208 is in contact with the top surface of the conductive layer 212b, one embodiment of the present invention is not limited to this. The end of the layer 208 can be configured to coincide or approximately coincide with the end of the conductive layer 212b on the side that does not face the opening 243. Alternatively, the layer 208 can be configured to cover the end of the conductive layer 212b on the side that does not face the opening 243, and the end of the layer 208 can be in contact with the top surface of the insulating layer 110. It is also possible to configure the layer 208 so that it does not come into contact with the top surface of the conductive layer 212b, but only comes into contact with the side surface of the conductive layer 212b on the opening 243 side.

Layer 208 can be formed in the same process as layer 108. For example, layers 108 and 208 can be formed by forming a film that will become layers 108 and 208, and processing the film. Note that layers 108 and 208 can also be formed in different processes. By forming layers 108 and 208 in different processes, different materials can be used for layers 108 and 208, which allows for a wider range of material choices.

As shown in FIG. 1A, etc., the top shape of the opening 241 and the top shape of the opening 243 can be made to match or approximately match each other. In this case, as shown in FIG. 1B and FIG. 1C, etc., it is preferable that the bottom end of the conductive layer 212b on the opening 243 side matches or approximately matches the top end of the insulating layer 110 on the opening 241 side. The bottom surface of the conductive layer 212b refers to the surface on the insulating layer 110 side. The top surface of the insulating layer 110 refers to the surface on the conductive layer 212b side. Note that the top shapes of the opening 241 and the opening 243 may not match each other. When the top shape of the opening 243 does not match the top shape of the opening 241, it is preferable that the opening 243 includes the opening 241 in a top view (also referred to as a plan view). The coverage of the layer 208 can be improved by the top shape of the opening 243 matching the top shape of the opening 241 or by the opening 243 including the opening 241 in a top view.

In this specification, the top surface shape of opening 141 refers to the shape of the top surface end portion on the opening 141 side of insulating layer 110. The top surface shape of opening 241 refers to the shape of the top surface end portion on the opening 241 side of insulating layer 110. The top surface shape of opening 243 refers to the shape of the bottom surface end portion on the opening 243 side of conductive layer 212b.

The insulating layer 106 is provided on the layer 108, the layer 208, the conductive layer 212b, and the insulating layer 110. The insulating layer 106 has a region in contact with the top and side surfaces of the layer 108, the top and side surfaces of the layer 208, the top and side surfaces of the conductive layer 212b, and the top surface of the insulating layer 110. A part of the insulating layer 106 functions as a gate insulating layer for the transistor 100, and another part functions as a gate insulating layer for the transistor 200. The insulating layer 106 is provided so as to cover the openings 141, 241, and 243, and has a shape that conforms to the shapes of the top and side surfaces of the layer 108, the top and side surfaces of the layer 208, the top and side surfaces of the conductive layer 212b, and the top surface of the insulating layer 110.

The conductive layer 104 and the conductive layer 204 are provided on the insulating layer 106. The conductive layer 104 and the conductive layer 204 each have a region in contact with the insulating layer 106 and have a shape that conforms to the shape of the upper surface and side surface of the insulating layer 106. The conductive layer 104 has a region that overlaps with the layer 108 through the insulating layer 106 in the opening 141. The conductive layer 204 has a region that overlaps with the layer 208 through the insulating layer 106 in the opening 241. The conductive layer 104 is provided to cover the opening 141 and has a shape that conforms to the shape of the upper surface and side surface of the insulating layer 106 in the opening 141. The conductive layer 204 is provided to cover the opening 241 and the opening 243 and has a shape that conforms to the shape of the upper surface and side surface of the insulating layer 106 in the opening 241 and the opening 243. The conductive layer 204 can be formed in the same process as the conductive layer 104. For example, the conductive layer 104 and the conductive layer 204 can be formed by forming a film that will become the conductive layer 104 and the conductive layer 204 and processing the film. Note that the conductive layer 104 and the conductive layer 204 can also be formed in different steps. By forming the conductive layer 104 and the conductive layer 204 in different steps, different materials can be used for the conductive layer 104 and the conductive layer 204, which allows a wider range of material selection.

The layer 108 has regions 108Da and 108Db. The layer 208 has regions 208Da and 208Db. The regions 108Da, 108Db, 208Da, and 208Db each have an impurity element. The regions 108Da and 108Db each have a higher concentration of the impurity element and a lower electrical resistance than other regions (e.g., channel formation regions) of the layer 108. In the layer 108, the channel formation region of the transistor 100 is located between the regions 108Da and 108Db. The regions 208Da and 208Db each have a higher concentration of the impurity element and a lower electrical resistance than other regions (e.g., channel formation regions) of the layer 208. In the layer 208, the channel formation region of the transistor 200 is located between the regions 208Da and 208Db.

3A and the like show an example in which region 108Da is formed in a region located between the upper surface of conductive layer 112 and the lower surface of conductive layer 104 among the regions in contact with the upper surface of conductive layer 112 of layer 108, and region 108Db is formed in a region in contact with the upper surface of insulating layer 110 of layer 108. The region in which region 108Da is formed is not limited to this, and for example, a configuration in which region 108Da is formed in the entire region in contact with the upper surface of conductive layer 112 of layer 108 can be used. Region 108Db can also be provided in a part of the region in layer 108 that contacts the side surface of insulating layer 110. For example, when an impurity element is supplied to layer 108, or due to heat applied in a process after the impurity element is supplied, the impurity element may diffuse. Note that, although two regions 108Db are shown in the cross-sectional view of FIG. 3A and the like, the regions 108Db are connected together in a top view. Additionally, layer 108 may also be configured to have multiple regions 108Db that are separated from one another.

By having the region 108Da in the layer 108, the electrical resistance of one of the source region and the drain region of the transistor 100 can be reduced. This can reduce the contact resistance between the one of the source region and the drain region and the conductive layer 112. Therefore, the on-current of the transistor 100 can be increased.

Region 108Db functions as the other of the source electrode and drain electrode of transistor 100. Since a part of layer 108 (here, region 108Db) functions as the other of the source electrode and drain electrode, there is no need to provide a separate conductive layer that functions as the other of the source electrode and drain electrode. Therefore, the number of layers constituting transistor 100 can be reduced.

Here, when photolithography is used to manufacture a semiconductor device, each component of the semiconductor device is arranged according to a design rule. Examples of components formed using photolithography include the layers (here, layers 108, conductive layer 104, conductive layer 204, etc.) of transistor 100 and transistor 200. In addition, openings 141, 241, and 243 are also arranged according to a design rule. When a semiconductor device has wiring formed using photolithography, the wiring is also arranged according to a design rule. Examples of design rules include the width of a layer (hereinafter also referred to as a line), the width of a wiring, and the spacing between layers in the same layer (hereinafter also referred to as a space), the spacing between a layer and a wiring, and the spacing between wirings. The size of the opening is also included in the design rule. Between different layers, it is necessary to arrange layers, openings, and wiring taking into account the alignment accuracy of an exposure device (hereinafter also referred to as alignment accuracy or overlay accuracy). Since the transistor 100 does not have a separate conductive layer that functions as the other of the source electrode and drain electrode, there is no need to consider the space for the conductive layer and the accuracy of overlay. Therefore, the distance between the transistor 100 and adjacent elements (e.g., a transistor and a capacitor) or wiring can be shortened, and the area occupied by the semiconductor device can be reduced. Note that the layers, openings, and wiring formed by photolithography, or the top surface shape of the photoresist used to form them, may be called a pattern.

The layer 208 is provided so as to cover the opening 241 of the insulating layer 110 and the opening 243 of the conductive layer 212b. As described above, the top surface shape of the opening 243 matches the top surface shape of the opening 241, or the opening 243 encompasses the opening 241 in a top view, thereby improving the coverage of the layer 208. In forming the opening 241 and the opening 243, it is preferable to use processing conditions such that the top surface shapes of these openings match, or the opening 243 encompasses the opening 241. On the other hand, the layer 108 is provided so as to cover the opening 141 of the insulating layer 110. Since the transistor 100 does not have a conductive layer corresponding to the conductive layer 212b, the difficulty of forming the opening 141 is lower than the difficulty of forming the opening 241 and the opening 243. Therefore, even when the opening 141 and the opening 241 are formed in the same process, the size of the opening 141 can be made finer than the opening 241.

By reducing the number of layers constituting the transistor 100, it is possible to reduce the unevenness caused by the transistor 100. Here, if the unevenness of the surface on which a layer is formed is large, defects such as step discontinuities or voids due to reduced coverage of the layer, or etching residues occurring when processing the layer, may occur. By reducing the unevenness caused by the transistor 100, defects (e.g., step discontinuities, voids, and etching residues) occurring in the formation of layers provided on the transistor 100 are suppressed, and the manufacturing yield can be increased.

The transistor 200 has a conductive layer 212b on the insulating layer 110, which functions as the other of the source electrode and drain electrode. The layer 208 has a region on the insulating layer 110 that is in contact with the conductive layer 212b. On the other hand, the transistor 100 does not have a separate conductive layer that functions as the other of the source electrode and drain electrode, because a part of the layer 108 (here, the region 108Db) functions as the other of the source electrode and drain electrode. In other words, the layer 108 is provided on the insulating layer 110 without a conductive layer therebetween. The region of the layer 108 that contacts the side surface of the insulating layer 110 and the region that contacts the top surface of the insulating layer 110 are continuous.

Compared to the region 108Db functioning as the other of the source electrode and drain electrode of the transistor 100 and the layer 108 having a channel formation region, the conductive layer 212b functioning as the other of the source electrode and drain electrode of the transistor 200 has a wider range of materials to choose from. Therefore, depending on the material used for the layer 108, the electrical resistance of the conductive layer 212b may be lower than the electrical resistance of the region 108Db. When the other of the source electrode and drain electrode functions as a wiring, the length of the wiring is long, and the wiring resistance required for the wiring is relatively low, the transistor 200 having the conductive layer 212b can be preferably used. By using the transistor 200, a semiconductor device that operates at high speed can be obtained. On the other hand, when the length of the wiring is short and the wiring resistance required for the wiring is relatively high, the transistor 100 can be preferably used. By using the transistor 100, a semiconductor device with a small occupancy area can be obtained.

3B and other figures show an example in which region 208Da is formed in a region located between the upper surface of conductive layer 212a and the lower surface of conductive layer 204 among the regions in contact with the upper surface of conductive layer 212a of layer 208, and region 208Db is formed in a region in contact with the upper surface of conductive layer 212b of layer 208. The region in which region 208Da is formed is not limited to this, and for example, region 208Da can be formed in the entire region in contact with the upper surface of conductive layer 212a of layer 208. Region 208Db can also be provided in a region in layer 208 that contacts the side of conductive layer 212b. Region 208Db can also be provided in a part of a region in layer 208 that contacts the side of insulating layer 110. For example, the impurity element may diffuse due to heat applied when the impurity element is supplied to layer 208 or in a process after the impurity element is supplied. In addition, in the cross-sectional view of FIG. 3B and the like, two regions 208Db are shown, but in top view, the regions 208Db are connected into one. By making the regions 208Db connected into one, the contact area between the region 208Db and the conductive layer 212b is increased, and the contact resistance between the region 208Db and the conductive layer 212b can be reduced. In addition, the layer 208 can also be configured to have multiple regions 208Db that are separated from each other.

By having the layer 208 have the regions 208Da and 208Db, the electrical resistance of the source region and the drain region of the layer 208 can be reduced. This can reduce the contact resistance between one of the source region and the drain region and the conductive layer 212a, and the contact resistance between the other of the source region and the drain region and the conductive layer 212b. Therefore, the on-current of the transistor 200 can be increased.

As described above, the region of the layer 108 in contact with the conductive layer 112 functions as one of the source region and drain region of the transistor 100, and the region 108Db functions as the other of the source electrode and drain electrode of the transistor 100. The region of the layer 108 that overlaps with the conductive layer 104 via the insulating layer 106 between the region that functions as one of the source region and drain region and the region that functions as the other of the source electrode and drain electrode functions as the channel formation region of the transistor 100. The region of the layer 208 in contact with the conductive layer 212a functions as one of the source region and drain region of the transistor 200, and the region that contacts with the conductive layer 212b functions as the other of the source region and drain region of the transistor 200. The region of the layer 208 that overlaps with the conductive layer 204 via the insulating layer 106 between the source region and drain region functions as the channel formation region of the transistor 200.

In transistor 100 and transistor 200, the source electrode and drain electrode are located at different heights relative to the surface of substrate 102 on which they are formed, and the drain current flows perpendicular or approximately perpendicular to the surface of substrate 102. In other words, the channel length direction can be said to have a component in the height direction (vertical direction), so transistor 100 and transistor 200 can also be called VFET (Vertical Field Effect Transistor), vertical transistor, vertical channel transistor, vertical channel transistor, etc.

The channel length of the transistor 100 and the channel length of the transistor 200 can be controlled by the thickness of the insulating layer 110. Specifically, in the transistor 100, the channel length can be controlled by the thickness of the insulating layer 110 provided between the conductive layer 112 and the layer 108. In the transistor 200, the channel length can be controlled by the thickness of the insulating layer 110 provided between the conductive layer 212a and the conductive layer 212b. Therefore, the transistors 100 and 200 having a channel length shorter than the minimum exposure dimension of the exposure device used to manufacture the transistors can be manufactured with high precision. In addition, the variation in characteristics of multiple transistors is reduced, so that the operation of the semiconductor device 10 can be stabilized and the reliability can be improved. In addition, the reduction in the variation in characteristics of the transistors increases the degree of freedom in circuit design, and the operating voltage of the semiconductor device 10 can be reduced. Therefore, the power consumption of the semiconductor device 10 can be reduced.

Transistor 100 can be provided with one of the source electrode and drain electrode, the other of the source electrode and drain electrode, and a layer having a channel formation region, stacked together. Transistor 200 can be provided with a source electrode, a layer having a channel formation region, and a drain electrode, stacked together. Therefore, compared to a so-called planar type transistor in which these are arranged in a plane, the occupied area can be significantly reduced. This allows for a small semiconductor device.

Region 108Db, conductive layer 112, and conductive layer 104 can each function as wiring, and transistor 100 can be provided in the region where these wirings overlap. Similarly, conductive layer 212a, conductive layer 212b, and conductive layer 204 can each function as wiring, and transistor 200 can be provided in the region where these wirings overlap. In other words, in a circuit having transistor 100, transistor 200, and wiring, the area occupied by these can be reduced. Therefore, the area occupied by the circuit can be reduced, and a small-sized semiconductor device can be obtained.

For example, when a semiconductor device of one embodiment of the present invention is applied to a pixel circuit of a display device, the area occupied by the pixel circuit can be reduced, and a high-definition display device can be obtained. Furthermore, for example, when a semiconductor device of one embodiment of the present invention is applied to a driver circuit of a display device (e.g., one or both of a gate line driver circuit and a source line driver circuit), the area occupied by the driver circuit can be reduced, and a display device with a narrow frame can be obtained.

The semiconductor material used for layer 108 and layer 208 is not particularly limited. For example, a semiconductor made of a single element or a compound semiconductor can be used. Examples of semiconductors made of a single element include silicon and germanium. Examples of compound semiconductors include gallium arsenide and silicon germanium. Other examples of compound semiconductors include organic semiconductors, nitride semiconductors, and oxide semiconductors (OS: oxide semiconductor). Note that these semiconductor materials may contain impurities as dopants.

The crystallinity of the semiconductor material used for layers 108 and 208 is not particularly limited, and any of an amorphous semiconductor, a single crystal semiconductor, and a semiconductor having crystallinity other than single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor having a crystalline region in part) can be used. The use of a single crystal semiconductor or a semiconductor having crystallinity is preferable because it can suppress deterioration of the transistor characteristics.

The layers 108 and 208 may each be made of silicon, for example. Examples of silicon include single crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. Examples of polycrystalline silicon include low temperature polysilicon (LTPS). A transistor using amorphous silicon in the channel formation region can be formed on a large glass substrate and manufactured at low cost. A transistor using polycrystalline silicon in the channel formation region has high field effect mobility and can operate at high speed. A transistor using microcrystalline silicon in the channel formation region has higher field effect mobility and can operate at high speed than a transistor using amorphous silicon. Note that a transistor using silicon in the channel formation region may be referred to as a Si transistor, and a transistor using LTPS in the channel formation region may be referred to as a LTPS transistor.

The layers 108 and 208 each preferably contain a metal oxide (also referred to as an oxide semiconductor) that exhibits semiconductor characteristics. When a metal oxide is used for the layers 108 and 208, the layers 108 and 208 can each be referred to as a metal oxide layer. The band gap of the metal oxide used for the layers 108 and 208 is preferably 2.0 eV or more, and more preferably 2.5 eV or more.

Transistors using an oxide semiconductor (hereinafter referred to as OS transistors) have extremely high field-effect mobility compared to transistors using amorphous silicon. In addition, OS transistors have an extremely small off-state current and can retain charge accumulated in a capacitor connected in series with the transistor for a long period of time. Furthermore, the use of OS transistors can reduce the power consumption of a semiconductor device.

The insulating layer 110 will now be described.

As the insulating layer 110, one or both of an inorganic insulating layer and an organic insulating layer can be used. Examples of materials that can be used for the organic insulating layer include acrylic resin and polyimide resin. It is preferable that the insulating layer 110 has one or more inorganic insulating layers. Examples of materials that can be used for the inorganic insulating layer include oxides, nitrides, oxynitrides, and nitride oxides. Examples of oxides include silicon oxide, aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, cerium oxide, gallium zinc oxide, and hafnium aluminate. Examples of nitrides include silicon nitride and aluminum nitride. Examples of oxynitrides include silicon oxynitride, aluminum oxynitride, gallium oxynitride, yttrium oxynitride, and hafnium oxynitride. Examples of nitride oxides include silicon nitride oxide and aluminum nitride oxide.

In this specification and the like, an oxynitride refers to a material whose composition contains more oxygen than nitrogen. An oxynitride refers to a material whose composition contains more nitrogen than oxygen.

The insulating layer 110 has a region in contact with the layer 108 and a region in contact with the layer 208. When a metal oxide is used for the layers 108 and 208, in order to improve the interface characteristics between the layer 108 and the insulating layer 110 and between the layer 208 and the insulating layer 110, it is preferable that at least a part of the region of the insulating layer 110 in contact with the layer 108 and at least a part of the region of the insulating layer 110 in contact with the layer 208 each contain oxygen. In particular, it is preferable that the part of the insulating layer 110 in contact with the channel formation region of the layer 108 and the part in contact with the channel formation region of the layer 208 each contain oxygen. One or more of an oxide and an oxynitride can be suitably used for the part in contact with the channel formation region of the insulating layer 110.

When a metal oxide is used for the layer 108 and the layer 208, at least a part of a region of the insulating layer 110 in contact with the layer 108 and at least a part of a region of the insulating layer 110 in contact with the layer 208 preferably release oxygen when heat is applied. In particular, a portion of the insulating layer 110 in contact with the channel formation region of the layer 108 and a portion of the insulating layer 110 in contact with the channel formation region of the layer 208 preferably release oxygen when heat is applied. As a result, oxygen is supplied from the insulating layer 110 to the layer 108 and the layer 208, and oxygen vacancies ( _VO ) and defects in which hydrogen has entered an oxygen vacancy ( _VO ) (hereinafter also referred to as _VOH ) in the layer 108 and the layer 208 can be reduced.

Here, when _V0H is increased in the metal oxide, carriers may be generated by _V0H , and the carrier concentration may increase. In particular, when the carrier concentration in the channel formation region is high, the threshold voltage of the transistor may shift, and the drain current (hereinafter also referred to as cutoff current) that flows when the gate voltage is 0 V may increase. For example, in the case of an n-channel transistor, the threshold voltage may shift to the negative side, and the cutoff current may increase. In addition, the reliability of the transistor may decrease. By reducing oxygen vacancies ( _V0 ) and _V0H in the channel formation region, the carrier concentration in the channel formation region can be suppressed from increasing. As a result, the threshold voltage is suppressed from shifting, and a transistor with a small cutoff current can be obtained, and a semiconductor device with low power consumption can be obtained. In addition, a highly reliable transistor and semiconductor device can be obtained.

The insulating layer 110 preferably has a laminated structure. FIG. 1B and other figures show an example in which the insulating layer 110 has an insulating layer 110a, an insulating layer 110b on the insulating layer 110a, and an insulating layer 110c on the insulating layer 110b. The insulating layers 110a, 110b, and 110c can each be made of the materials listed for the insulating layer 110.

As shown in Figures 3A and 3B, layer 108 has region 108M in contact with insulating layer 110b, and layer 208 has region 208M in contact with insulating layer 110b. Region 108M functions as a channel formation region for transistor 100, and region 208M functions as a channel formation region for transistor 200. It can also be said that the channel formation regions for transistors 100 and 200 are provided along the side of insulating layer 110. Conductive layer 104 has a portion that overlaps with region 108M via insulating layer 106, and conductive layer 204 has a portion that overlaps with region 208M via insulating layer 106.

The insulating layer 110b preferably contains oxygen, and preferably uses one or more of the oxides and oxynitrides described above. As a result, in the layer 108, at least the region 108M can function as a channel formation region of the transistor 100. In addition, in the layer 208, at least the region 208M can function as a channel formation region of the transistor 200. The insulating layer 110b preferably contains silicon and oxygen. For example, one or both of silicon oxide and silicon oxynitride can be suitably used for the insulating layer 110b. Note that, although two regions of the layer 108 that contact the insulating layer 110b are shown in the cross-sectional views of FIG. 3A and the like, the regions 108M are connected together in a top view. Similarly, in the cross-sectional views of FIG. 3B and the like, two regions of the layer 208 that contact the insulating layer 110b are shown, but the regions 208M are connected together in a top view.

It is more preferable to use a material that releases oxygen when heat is applied for the insulating layer 110b. When heat is applied during the manufacturing process of the semiconductor device 10, the insulating layer 110b releases oxygen, so that oxygen can be supplied to the layers 108 and 208. When oxygen is supplied from the insulating layer 110b to the layers 108 and 208, particularly to the channel formation region, oxygen vacancies (V _O ) are repaired and oxygen vacancies (V _O ) can be reduced. Furthermore, V _O H can be reduced. Thus, the transistors 100 and 200 can have favorable electrical characteristics and high reliability.

For example, oxygen can be supplied to the insulating layer 110b by performing heat treatment in an atmosphere containing oxygen or plasma treatment in an atmosphere containing oxygen. Alternatively, oxygen can be supplied by forming a film on the upper surface of the insulating layer 110b in an atmosphere containing oxygen by a sputtering method. Then, the film can be removed. When a metal oxide is used for the layers 108 and 208, the metal oxide films to be the layers 108 and 208 are preferably formed in an atmosphere containing oxygen. In this manner, oxygen can be supplied to the insulating layer 110b. Then, oxygen is supplied from the insulating layer 110b to the layers 108 and 208 in a later step, and oxygen vacancies ( _VO ) and _VOH in the layers 108 and 208 can be reduced. Note that a method for supplying oxygen to the insulating layer 110b will be specifically described in Embodiment 2.

The insulating layer 110b is preferably formed by sputtering or plasma enhanced chemical vapor deposition (PECVD) method. In particular, by forming the insulating layer 110b by a method that does not use a gas containing hydrogen elements (e.g., hydrogen gas and ammonia gas) in the deposition gas, a film with an extremely low hydrogen content can be obtained. The sputtering method is particularly suitable for forming the insulating layer 110b. This can prevent hydrogen from being supplied to the channel formation region, and stabilize the electrical characteristics of the transistor 100 and the transistor 200.

Here, by using a material with high conductivity for the layer 108 and the layer 208, the transistor 100 and the transistor 200 can have a large on-state current. However, when a material with high conductivity is used, oxygen vacancies (V _O ) are easily formed, and V _O H in the channel formation region may increase. In addition, an increase in V _O H may cause a shift in the threshold voltage of the transistor and a large cutoff current. By providing the insulating layer 110b, oxygen is supplied to at least the region 108M and the region 208M, and the oxygen vacancies (V _O ) and V _O H in these regions can be reduced. As a result, a shift in the threshold voltage is suppressed, and the transistor 100 and the transistor 200 can have both a small cutoff current and a large on-state current. Therefore, a semiconductor device that has both low power consumption and high performance can be provided.

The insulating layer 110a is provided between the insulating layer 110b and the conductive layer 112 and the conductive layer 212a. The insulating layer 110c is provided between the insulating layer 110b and the layer 108 and the conductive layer 212b. It is preferable that the amount of impurities (e.g., hydrogen and water) released from the insulating layer 110a and the insulating layer 110c is small. Furthermore, it is preferable that the insulating layer 110a and the insulating layer 110c are each impermeable to substances (e.g., atoms, molecules, and ions). It can be said that the insulating layer 110a and the insulating layer 110c function as a barrier film. Specifically, it is preferable that the insulating layer 110a and the insulating layer 110c are each impermeable to impurities. This makes it possible to suppress the diffusion of impurities contained in the insulating layer 110a and the insulating layer 110c into the channel formation regions of the layer 108 and the layer 208. Therefore, the transistor 100 and the transistor 200 can be obtained, which exhibit good electrical characteristics and are highly reliable.

In this specification and the like, a barrier film refers to a film that has barrier properties. Barrier properties refer to one or both of the following functions: making it difficult for a target substance to diffuse, thereby suppressing the substance from permeating the film (also called low permeability), and the function of capturing or fixing the substance (also called gettering). For example, an insulating layer that has barrier properties can be called a barrier insulating layer.

The insulating layer 110b is in contact with the insulating layer 110a and the insulating layer 110c and has a region sandwiched therebetween. The insulating layer 110a and the insulating layer 110c are preferably made of a material that is difficult for oxygen to permeate. This suppresses the oxygen contained in the insulating layer 110b from diffusing to the insulating layer 110a side and to the insulating layer 110c side, so that the amount of oxygen supplied from the insulating layer 110b to the region 108M and the region 208M increases, and oxygen vacancies (V _O ) and V _O H in the channel formation region can be reduced. Therefore, the transistor 100 and the transistor 200 can have good electrical characteristics and high reliability. When oxygen is supplied to the conductive layer 112, the conductive layer 212a, and the conductive layer 212b, they may be oxidized, resulting in high electrical resistance. By providing the insulating layer 110a between the conductive layer 112 and the insulating layer 110b and between the conductive layer 212a and the insulating layer 110b and by providing the insulating layer 110c between the conductive layer 212b and the insulating layer 110b, oxygen can be prevented from diffusing into these conductive layers, and an increase in the electrical resistance of these conductive layers can be prevented. Therefore, the transistor 100 and the transistor 200 each having a large on-state current can be obtained.

The insulating layer 110a and the insulating layer 110c, which function as a barrier film, can each be made of one or more of the following: an oxide having one or both of aluminum and hafnium, an oxide having magnesium, an oxide having gallium, a nitride having silicon, and a nitride oxide having silicon. Specifically, the insulating layer 110a and the insulating layer 110c can each be made of one or more of aluminum oxide, hafnium oxide, hafnium aluminate, magnesium oxide, gallium oxide, gallium zinc oxide, silicon nitride, and silicon nitride oxide. The insulating layer 110a and the insulating layer 110c can be made of the same material. Alternatively, the insulating layer 110a and the insulating layer 110c can be made of different materials.

In this specification, different materials refer to materials in which some or all of the constituent elements are different, or materials in which the constituent elements are the same but the composition is different.

The insulating layer 110a, the insulating layer 110b, and the insulating layer 110c each preferably contains a small amount of impurities. The insulating layer 110a, the insulating layer 110b, and the insulating layer 110c each preferably releases a small amount of impurities. In particular, the amount of impurities containing a hydrogen element (e.g., hydrogen and water) released is preferably small. The insulating layer 110a, the insulating layer 110b, and the insulating layer 110c each preferably contains as little impurity containing a hydrogen element as possible. This can suppress an increase in oxygen vacancies ( _VO ) and _VOH in the layer 108 and the layer 208.

By using an oxide or an oxynitride for the insulating layer 110c, oxygen can be supplied to the insulating layer 110b or the insulating film that will become the insulating layer 110b when the insulating layer 110c or the insulating film that will become the insulating layer 110c is formed. This allows the amount of oxygen supplied from the insulating layer 110b to the layer 108 and the layer 208 to be increased, and oxygen vacancies ( _VO ) and _VOH can be efficiently reduced. For example, an aluminum oxide film can be formed by a sputtering method using an aluminum target in an atmosphere containing oxygen as the insulating layer 110c or the insulating film that will become the insulating layer 110c. This allows oxygen to be supplied to the insulating layer 110b or the insulating film that will become the insulating layer 110b while the aluminum oxide film is being formed.

The insulating layer 110b may also function as a barrier film. The above-mentioned materials may be used as the barrier film. For example, silicon nitride may be preferably used as the insulating layer 110b. The insulating layer 110 may have a single-layer structure of a silicon nitride film. The insulating layer 110b functions as a barrier film, which can suppress diffusion of impurities into the channel formation regions of the layers 108 and 208, and can provide the transistors 100 and 200 with good electrical characteristics and high reliability. Note that the amount of oxygen supplied from the insulating layer 110b to the layers 108 and 208 may be reduced depending on the material used for the insulating layer 110b. In that case, it is preferable that at least a portion of the insulating layer 106 in contact with the channel formation region of the layer 108 and a portion in contact with the channel formation region of the layer 208 contain oxygen. Furthermore, it is more preferable to use a material that releases oxygen when heat is applied to the portions. Heat applied during the manufacturing process of the semiconductor device 10 causes the insulating layer 106 to release oxygen, which can be supplied to the layer 108 and the layer 208. Supplying oxygen from the insulating layer 106 to the layer 108 and the layer 208, particularly to the channel formation region, can reduce oxygen vacancies ( _VO ) and _VOH . For example, one or more of silicon oxide, silicon oxynitride, and aluminum oxide can be suitably used for the portion of the insulating layer 106 in contact with the layer 108 and the portion in contact with the layer 208.

Note that although the insulating layer 110 is shown here as having a three-layer stacked structure, one embodiment of the present invention is not limited to this. It is preferable that the insulating layer 110 has at least the insulating layer 110b. For example, a structure without the insulating layer 110a is possible. The insulating layer 110 can have a two-layer or four or more layer stacked structure, or a single layer structure.

Areas 108M, 108Da, 108Db, 208M, 208Da, and 208Db will now be described in detail.

It is preferable that the electrical resistance of regions 108Da, 108Db, 208Da, and 208Db is low. It is preferable that the electrical resistance of regions 108Da and 108Db is lower than the electrical resistance of region 108M. It is preferable that the electrical resistance of regions 208Da and 208Db is lower than the electrical resistance of region 208M.

The region 108Db, which functions as the other of the source electrode and drain electrode of the transistor 100, preferably has a particularly low electrical resistance. The sheet resistance (also called surface resistivity or sheet resistivity) of the region 108Db is preferably 1000 Ω/□ (also written as Ω/sq) or less, more preferably 500 Ω/□ or less, even more preferably 300 Ω/□ or less, even more preferably 200 Ω/□ or less, and even more preferably 100 Ω/□ or less. Since it is preferable that the electrical resistance of the region 108Db is low, there is no lower limit to the sheet resistance.

Region 108Da, region 108Db, region 208Da, and region 208Db each have a first element as an impurity element. As the first element, it is preferable to use one or more of boron, aluminum, indium, carbon, silicon, germanium, tin, phosphorus, arsenic, antimony, magnesium, calcium, titanium, copper, zinc, tungsten, molybdenum, tantalum, hafnium, cerium, and noble gases (helium, neon, argon, krypton, xenon, etc.). In addition to the above elements, one or more of the elements included in the first transition elements (3d transition elements, 3d transition metals), second transition elements (4d transition elements, 4d transition metals), third transition elements (5d transition elements, 5d transition metals), alkaline earth metal elements, and rare earth elements can be used.

The regions 108Da, 108Db, 208Da, and 208Db can be formed by supplying (adding or injecting) the first element to the layers 108 and 208. When a metal oxide is used for the layers 108 and 208, oxygen vacancies (V O ) are generated in the regions 108Da, 108Db, 208Da, and 208Db by supplying the first element to these regions. Carriers are generated by V _O H in which hydrogen enters the oxygen vacancies _{(V O )} , and the electrical resistance of these regions can be reduced. These regions can function as conductors. In the semiconductor device according to one embodiment of the present invention, the region 108Db functions as the other of the source electrode and drain electrode of the transistor 100. Note that a metal oxide functioning as a conductor can be referred to as an oxide conductor (OC). Generally, metal oxides have a large band gap and therefore transmit visible light (or have translucency to visible light). An oxide conductor is a metal oxide having a donor level in the vicinity of the conduction band. Therefore, the oxide conductor is less affected by absorption due to the donor level and has translucency to visible light to the same extent as a metal oxide.

When an element that easily bonds with oxygen is used as the first element, the first element takes away oxygen in the layers 108 and 208 and exists in a state bonded with oxygen. In addition, oxygen vacancies (V 2 _O 3 ) are generated in the layers 108 and 208. When an element that bonds with oxygen to become stable is used as the first element, the first element in the layers 108 and 208 exists stably in an oxidized state, so that it is difficult to be desorbed by heat applied during the manufacturing process of the semiconductor device 10, and the electrical resistance can be kept low. For this reason, it is preferable to use an element whose oxide can exist in a solid state at least at the temperature during the manufacturing process as the first element. Specifically, examples of preferred first elements include typical nonmetallic elements other than hydrogen, typical metallic elements, and transition elements (transition metals). Specifically, it is more preferable to use boron, phosphorus, magnesium, aluminum, or silicon as one of the first elements. It is even more preferable to use boron or phosphorus as one of the first elements.

Here, when oxygen is supplied to the regions 108Da, 108Db, 208Da, and 208Db, the oxygen vacancies (V _O ) and V _O H in these regions may decrease, resulting in an increase in electrical resistance. As described above, it is preferable that the region 108Db functioning as the other of the source electrode and drain electrode of the transistor 100 has particularly low electrical resistance. By providing the insulating layer 110c functioning as a barrier film between the region 108Db and the insulating layer 110b, oxygen is prevented from diffusing from the insulating layer 110b to the region 108Db, and an increase in the electrical resistance of the region 108Db can be suppressed.

It is preferable that each of regions 108Da and 108Db has a portion having a higher concentration of the first element than region 108M. It is preferable that each of regions 208Da and 208Db has a portion having a higher concentration of the first element than region 208M.

Each of the regions 108Da, 108Db, 208Da, and 208Db preferably includes a portion in which the concentration of the first element is 1×10 ¹⁹ atoms/cm ³ or more and 1×10 ²³ atoms/cm ³ or less, preferably 5×10 ¹⁹ atoms/cm ³ or more and 5×10 ²² atoms/cm ³ or less ^, and more preferably 5×10 19 atoms/cm ³ or more and 5×10 ²¹ atoms/cm ³ or less. If the concentration of the first element is low, the electrical resistance of the regions 108Da, 108Db, 208Da, and 208Db may become high. On the other hand, if the concentration of the first element is high, that is, if a large amount of the first element is supplied, the layers 108 and 208 may be damaged during supply, which may increase the electrical resistance of the regions 108Da, 108Db, 208Da, and 208Db. Therefore, by setting the concentration of the first element in the regions 108Da, 108Db, 208Da, and 208Db within the above-mentioned range, the electrical resistance of the regions 108Da, 108Db, 208Da, and 208Db can be reduced, and the transistors 100 and 200 can have large on-currents.

If region 108Da contains two or more types of first elements, it is preferable that at least one of them is in the above range. It is also more preferable that the concentration of each of the first elements is in the above range. The same applies to regions 108Db, 208Da, and 208Db.

When the first element is supplied, the first element may also be supplied to the channel formation region of the layer 108 (here, region 108M) and the channel formation region of the layer 208 (here, region 208M). Alternatively, due to heat applied during the manufacturing process, a part of the first element contained in the regions 108Da, 108Db, 208Da, and 208Db may diffuse into the channel formation region. The concentration of the first element in the region 108M and the concentration of the first element in the region 208M are preferably low. The concentration of the first element in the region 108M is preferably lower than the concentrations of the first element in the regions 108Da and 108Db, respectively. The concentration of the first element in the region 208M is preferably lower than the concentrations of the first element in the regions 208Da and 208Db, respectively.

By lowering the concentration of the first element in region 108M, it is possible to prevent the carrier concentration in the channel formation region from increasing. By preventing the carrier concentration in the channel formation region from increasing, it is possible to prevent the threshold voltage from shifting, and to provide transistor 100 with a small cutoff current. The same is true for region 208M and transistor 200. Therefore, it is possible to provide a semiconductor device with low power consumption.

The concentration of the first element in the region 108M is preferably 1×10 −1 times or less, more preferably 1×10 ⁻² times or less, more preferably 1×10 ⁻³ times or less, and even more preferably 1×10 ⁻⁴ times or less than the concentration of the first element in the region 108Da. Similarly, the concentration of the first element in the region 108M is preferably 1×10 ⁻¹ times or less, more preferably 1×10 ⁻² times or less, more preferably 1×10 ⁻³ times or less, and even more preferably 1×10 ⁻⁴ times or less than the concentration of the first element in ^the region 108Db. This allows the transistor 100 to have both a small cutoff current and a large on-current.

The concentration of the first element in the region 208M is preferably 1×10 −1 times or less, more preferably 1×10 ⁻² times or less, more preferably 1×10 ⁻³ times or less, and even more preferably 1×10 ⁻⁴ times or less than the concentration of the first element in the region 208Da. Similarly, the concentration of the first element in the region 208M is preferably 1×10 ⁻¹ times or less, more preferably 1×10 ⁻² times or less, more preferably 1×10 ⁻³ times or less, and even more preferably 1×10 ⁻⁴ times or less than the concentration of the first element in ^the region 208Db. This allows the transistor 200 to have both a small cutoff current and a large on-current.

The first element is preferably supplied to the layers 108 and 208 through the insulating layer 106. For example, after the insulating layer 106 is formed and before the conductive layers 104 and 204 are formed, the first element can be supplied to the layers 108 and 208 through the insulating layer 106. By supplying the first element to the layers 108 and 208 through the insulating layer 106, the first element can be preferentially supplied to the regions 108Da and 108Db in the layer 108, and the first element can be preferentially supplied to the regions 208Da and 208Db in the layer 208. Furthermore, by supplying the first element through the insulating layer 106, damage to the layers 108 and 208 during supply can be reduced.

When the first element is supplied to the layer 108 and the layer 208 through the insulating layer 106, the insulating layer 106 may also have the first element. If the regions 108Da, 108Db, 208Da, and 208Db each have a portion with a higher concentration of the first element than the insulating layer 106, the electrical resistance of the regions 108Da, 108Db, 208Da, and 208Db can be lowered, which is preferable. The first element may also be supplied to the insulating layer 110 through the insulating layer 106 and the layer 108, or through the insulating layer 106. In this case, the concentration of the impurity element in the region that does not overlap with the layer 108 is higher than that in the region of the insulating layer 110 that overlaps with the layer 108. In addition, the concentration of the impurity element in the insulating layer 110 is higher in the closer to the insulating layer 106. For example, the concentration of the impurity element in the insulating layer 110c is higher than that in the insulating layer 110a.

The concentration of the first element in layers 108, 208, insulating layer 106, and insulating layer 110 can be analyzed by, for example, secondary ion mass spectrometry (SIMS), X-ray photoelectron spectrometry (XPS), or electron spectrometry for chemical analysis (ESCA). When using XPS analysis, the concentration distribution in the depth direction can be known by combining ion sputtering from the front or back side of the sample with XPS analysis. Note that in low concentration areas, quantification may be difficult or may be below the detection limit.

In the manufacturing of the semiconductor device according to one embodiment of the present invention, the first element is preferably more easily supplied to the regions 108Da and 108Db than to the region 108M. Similarly, the first element is preferably more easily supplied to the regions 208Da and 208Db than to the region 208M. The first element is preferably supplied to the layers 108 and 208 from a direction perpendicular or substantially perpendicular to the top surface of the substrate 102. In this case, the amount of the first element supplied to the regions 108 and 208 that are inclined with respect to the top surface of the substrate 102 is smaller than that to the regions that are parallel or substantially parallel to the top surface of the substrate 102. That is, the amount of the first element supplied to the regions 108Da and 108Db is larger than that to the region 108M. Therefore, the electrical resistance of the regions 108Da and 108Db in the layer 108 can be preferentially reduced. Similarly, the amount of the first element supplied to the regions 208Da and 208Db is greater than that to the region 208M. Therefore, in the layer 208, the electrical resistance of the regions 208Da and 208Db can be preferentially reduced. Note that, when the first element is supplied to the layer 108, oxygen vacancies (V _O ) may occur in the layer 108. Alternatively, when the first element is supplied to the layer 108, the first element may bond with oxygen vacancies (V _O ) in the layer 108. The same applies to the layer 208.

Ion implantation is preferably used to supply the first element. The ion implantation can control the concentration profile in the depth direction with high precision by the acceleration energy and dose of the ions. In addition, by using an ion implantation method in which a source gas is ionized and the ions are mass-separated before supply, ions of a specific mass can be supplied, and the purity of the supplied impurity element can be increased. Alternatively, by using an ion implantation method in which ions are supplied without mass separation, productivity can be increased. Unless otherwise specified in this specification, the presence or absence of mass separation is not limited. The method of supplying ions after mass separation is sometimes called the ion implantation method, and the method of supplying ions without mass separation is sometimes called the ion doping method.

When boron is used as the first element, for example, _BF3 gas can be used as the source gas. When phosphorus is used as the first element, for example, _PH3 gas can be used as the source gas. Moreover, by mass-separating and supplying ions generated from these gases, ions of a specific mass can be supplied to the regions 108Da, 108Db, 208Da, and 208Db, which is more preferable.

When a plurality of elements are used as the first element, it is preferable to use an element that easily bonds with oxygen and an element that has a larger mass number than the element. When the mass number of the supplied element is large, the number of metal-oxygen bonds cut in the metal oxide of the layer 108 and the layer 208 increases. That is, in the region to which the element is supplied, more oxygen vacancies (V ₀ ) occur due to the cutting of metal-oxygen bonds. By cutting many metal-oxygen bonds by supplying an element with a large mass number, the element that easily bonds with oxygen can be more efficiently bonded to oxygen. Therefore, the electrical resistance of the region 108Da, the region 108Db, the region 208Da, and the region 208Db can be efficiently reduced. When boron, phosphorus, magnesium, aluminum, or silicon is used as the element that easily bonds with oxygen, argon, krypton, or xenon can be used as the element with a large mass number. For example, boron and argon can be preferably used as the first element.

When multiple elements are supplied as the first element, a gas containing these elements can be used as the raw material gas. For example, when boron and argon are used as the first element, a gas containing boron and argon can be used as the raw material gas. Alternatively, multiple elements can be supplied separately. For example, when an element that easily bonds with oxygen and an element with a large mass number are used as the first element, it is preferable to supply the element that easily bonds with oxygen after supplying the element with a large mass number. By supplying the element with a large mass number to break the bonds between more metals and oxygen, and then supplying the element that easily bonds with oxygen, it is possible to efficiently bond with oxygen. Therefore, the electrical resistance of the regions 108Da, 108Db, 208Da, and 208Db can be efficiently reduced. For example, argon can be supplied to the layers 108 and 208 using a gas containing argon, and then boron can be supplied to the layers 108 and 208 using a gas containing boron. This allows the electrical resistance of regions 108Da, 108Db, 208Da, and 208Db to be efficiently reduced.

When the first element is supplied to the regions 108Da, 108Db, 208Da, and 208Db, hydrogen can also be supplied to these regions. Hydrogen is suitable as an impurity element because oxygen vacancies (V _O ) are generated by supplying hydrogen, and V _O H is generated by entering the oxygen vacancies (V _O ). Supplying hydrogen in addition to the first element makes it easier to lower the electrical resistance of the regions 108Da, 108Db, 208Da, and 208Db, and can maintain a low electrical resistance state.

When both the first element and hydrogen are supplied, a gas containing the first element and hydrogen (for example, PH ₃ gas and B ₂ H ₆ gas) can be used as the source gas. Alternatively, a mixed gas of a gas containing the first element and a gas containing hydrogen can be used as the source gas. By using a source gas containing the first element and hydrogen, ions generated from the source gas can be supplied without mass separation, which is preferable because it can increase productivity. For example, by using B ₂ H ₆ gas as the source gas, boron and hydrogen can be supplied as impurity elements. In addition, by using PH ₃ gas as the source gas, phosphorus and hydrogen can be supplied as impurity elements.

Since the insulating layer 106 is provided so as to cover the openings 141, 241, and 243, it is preferable to use a method with high coverage for its formation. The insulating layer 106 is preferably formed by sputtering, PECVD, or atomic layer deposition (ALD: Atomic Layer Deposition). As the ALD method, thermal ALD or PEALD (Plasma Enhanced ALD) can be used. The thermal ALD method is preferable because it exhibits extremely high coverage. The PEALD method is preferable because it exhibits high coverage and allows low-temperature film formation.

3A shows the thickness Ta of the portion of the insulating layer 106 that contacts the region 108Da, the thickness Tb of the portion that contacts the region 108Db, and the thickness Tc of the portion that contacts the region 108M. The thicknesses Ta, Tb, and Tc are thicknesses in a direction perpendicular or approximately perpendicular to the surface on which the insulating layer 106 is formed. More specifically, the thickness Ta is the shortest distance between the upper surface of the layer 108 provided along the upper surface of the conductive layer 112 and the upper surface of the insulating layer 106. The thickness Tb is the shortest distance between the upper surface of the layer 108 provided along the upper surface of the insulating layer 110 and the upper surface of the insulating layer 106. The thickness Tc is the shortest distance between the side surface of the layer 108 provided along the side surface of the insulating layer 110 on the insulating layer 106 side and the side surface of the insulating layer 106 on the conductive layer 104 side.

3B shows thickness Xa of the portion of insulating layer 106 that contacts region 208Da, thickness Xb of the portion that contacts region 208Db, and thickness Xc of the portion that contacts region 208M. Thickness Xa, thickness Xb, and thickness Xc are thicknesses in a direction perpendicular or approximately perpendicular to the surface on which insulating layer 106 is formed. More specifically, thickness Xa is the shortest distance between the upper surface of layer 208 provided along the upper surface of conductive layer 212a and the upper surface of insulating layer 106. Thickness Xb is the shortest distance between the upper surface of layer 208 provided along the upper surface of conductive layer 212b and the upper surface of insulating layer 106. Thickness Xc is the shortest distance between the side of layer 208 provided along the side of insulating layer 110 on the insulating layer 106 side and the side of insulating layer 106 on the conductive layer 204 side.

Note that although Figures 3A and 3B show a configuration in which thickness Ta, thickness Tb, thickness Tc, thickness Xa, thickness Xb, and thickness Xc are the same, one aspect of the present invention is not limited to this. A configuration in which some or all of these thicknesses are different may also be used.

The thicknesses Tc and Xc of the region provided along the side of the insulating layer 110 may be thinner than the thicknesses Ta, Tb, Xa, and Xb of the region provided along the upper surface of the conductive layer 112, the upper surface of the insulating layer 110, the upper surface of the conductive layer 212a, and the upper surface of the conductive layer 212b of the insulating layer 106. For example, when the insulating layer 106 is formed by PECVD or sputtering, the thickness Tc may be thinner than both the thicknesses Ta and Tb, and the thickness Xc may be thinner than both the thicknesses Xa and Xb. When the insulating layer 106 is formed by ALD, the thickness Tc may be closer to the thicknesses Ta and Tb, and the thickness Xc may be closer to the thicknesses Xa and Xb. Alternatively, the thickness Tc may be the same or approximately the same as the thicknesses Ta and Tb, and the thickness Xc may be the same or approximately the same as the thicknesses Xa and Xb.

As described above, the insulating layer 106 functions as a gate insulating layer for the transistor 100 and the transistor 200. The thickness Tc of the portion of the insulating layer 106 in contact with the region 108M and the thickness Xc of the portion in contact with the region 208M are each preferably 1 nm or more and 200 nm or less, more preferably 1 nm or more and 150 nm or less, and even more preferably 1 nm or more and 100 nm or less. For example, when the channel length of the transistor 100 is 100 nm or more and 500 nm or less, the thickness Tc is preferably 30 nm or more and 100 nm or less. Also, for example, when the channel length is 10 nm or more and 100 nm or less, the thickness Tc is preferably 1 nm or more and 50 nm or less. Also, for example, when the channel length is 1 nm or more and 10 nm or less, the thickness Tc is preferably 1 nm or more and 10 nm or less. The same applies to the transistor 200 and the thickness Xc.

The supply of the first element to layer 108 and layer 208 will be described. Here, an example will be described in which the first element is supplied from a direction perpendicular to the top surface of the substrate 102. Note that the cross-sectional views shown in Figures 3A and 3B show a configuration in which the surface of the insulating layer 106 (specifically, the top and side surfaces of the insulating layer 106) is parallel to the top and side surfaces of layer 108, which are the surfaces on which the insulating layer 106 is formed, and the top and side surfaces of layer 208.

As described above, it is preferable that the first element is supplied to layers 108 and 208 through insulating layer 106. When the first element is supplied to layer 108 through insulating layer 106, the first element penetrates from the surface of insulating layer 106, passes through insulating layer 106, and then reaches layer 108 through the interface between insulating layer 106 and layer 108. At this time, the thickness of insulating layer 106 in the direction in which the first element is supplied can also be said to be the depth from the surface of insulating layer 106 to layer 108 of the first element. Specifically, thickness Ta is the depth from the surface of insulating layer 106 to region 108Da of the first element, and thickness Tb is the depth from the surface of insulating layer 106 to region 108Db of the first element. Similarly, thickness Xa is the depth to which the first element reaches region 208Da from the surface of insulating layer 106, and thickness Xb is the depth to which the first element reaches region 208Db from the surface of insulating layer 106.

3A and 3B show thicknesses Td and Xd of the region of insulating layer 106 provided along the side of insulating layer 110 in a direction perpendicular to the top surface of substrate 102. Thickness Td can also be said to be the depth to which the first element reaches region 108M from the surface of insulating layer 106. Thickness Xd can also be said to be the depth to which the first element reaches region 208M from the surface of insulating layer 106. For example, thickness Td and thickness Xd can be the thickness of insulating layer 106 on a straight line extending from the midpoint between the top and bottom ends of insulating layer 110b in a direction perpendicular to the top surface of substrate 102.

Compared to thickness Td, thicknesses Ta and Tb are thin. As a result, in the region of layer 108 provided along the upper surface of conductive layer 112 or the upper surface of insulating layer 110 (e.g., region 108Da and region 108Db), the amount of the first element supplied is greater than that in the region provided along the side of insulating layer 110 (e.g., region 108M). In this way, the supply of the first element to the channel formation region of layer 108 is suppressed, and the electrical resistance of regions 108Da and 108Db can be preferentially reduced. Similarly, thicknesses Xa and Xb are thin compared to thickness Xd. As a result, in the region of layer 208 provided along the upper surface of conductive layer 212a or the upper surface of conductive layer 212b (e.g., region 208Da and region 208Db), the amount of the first element supplied is greater than that in the region provided along the side of insulating layer 110 (e.g., region 208M). In this way, the supply of the first element to the channel formation region of layer 208 is suppressed, and the electrical resistance of regions 208Da and 208Db can be preferentially reduced.

The thicker the insulating layer 106, the larger the difference between thickness Ta and thickness Td, the difference between thickness Tb and thickness Td, the difference between thickness Xa and thickness Xd, and the difference between thickness Xb and thickness Xd can be. This suppresses the supply of the first element to regions 108M and 208M, and preferentially reduces the electrical resistance of regions 108Da, 108Db, 208Da, and 208Db. On the other hand, in order to miniaturize transistors or to fabricate transistors with extremely short channel lengths, it is preferable that thicknesses Tc and Xc are thin from the standpoint of improving the on-current and suppressing the short channel effect.

The insulating layer 106 preferably has an insulating layer containing oxygen. When an element that easily bonds with oxygen is used as the first element, the first element exists in a state of being bonded with oxygen in the insulating layer 106 as in the layers 108 and 208. When oxygen and the first element are bonded and stabilized, oxygen is less likely to be desorbed even when heat is applied in the region containing the first element, so that oxygen can be prevented from diffusing to other layers. This makes it possible to efficiently supply oxygen to the channel formation region while preventing oxygen from being supplied from the insulating layer 106 to the regions 108Da, 108Db, 208Da, and 208Db. Therefore, oxygen deficiency in the channel formation region can be reduced while preventing the electrical resistance of the regions 108Da, 108Db, 208Da, and 208Db from increasing. As a result, a transistor with good electrical characteristics and high reliability can be realized.

For example, when boron is used as the first element, the boron contained in the regions 108Da, 108Db, 208Da, 208Db, and the insulating layer 106 may exist in a state of being bonded to oxygen. This can be confirmed, for example, by observing a peak due to a B ₂ O ₃ bond in an XPS analysis. Also, in an XPS analysis, a spectrum peak due to a state in which the boron element exists as a single element is not observed, or the peak intensity is extremely small to the background level. Similarly, when the insulating layer 110 contains boron, in the portion of the insulating layer 110 containing oxygen, boron may exist in a state of being bonded to oxygen.

Note that a layer to which an impurity element (here, a first element) is supplied may be referred to as an implanted layer. For example, when a first element is supplied to layers 108 and 208 through insulating layer 106, insulating layer 106, layer 108, and layer 208 may each be referred to as an implanted layer.

The acceleration energy used to supply the impurity element is preferably set according to the type of impurity element (specifically, the type of ion) to be supplied, as well as the composition, film density, and thickness of the implanted layer. If the acceleration energy in supplying the first element is too high, the first element may also be supplied to the regions 108M and 208M, and the concentration of the first element in these regions may become high. Therefore, it is preferable to set the acceleration energy so that the first element is supplied as little as possible to the regions 108M and 208M. For example, it is preferable to set the acceleration energy used to supply the first element so that the concentration of the first element is highest at the interface between the region 108Da and the insulating layer 106, the interface between the region 108Db and the insulating layer 106, the interface between the region 208Da and the insulating layer 106, and the interface between the region 208Db and the insulating layer 106, or in the vicinity of these.

The concentration of the impurity element in the depth direction can be simulated, for example, using software. Examples of simulation software include TRIM (Transport of Ion in Matter) and SRIM (Stopping and Range of Ions in Matter). These are software that simulate the ion implantation process using the Monte Carlo method. The type of impurity element to be supplied (specifically, the type of ion), the composition and film density of the implanted layer, and the acceleration energy can be used as simulation parameters. When the first element is supplied to the layer 108 and the layer 208 through the insulating layer 106, the depth to the region 108Da is "Ta", the depth to the region 108Db is "Tb", the depth to the region 108M is "Td", the depth to the region 208Da is "Xa", the depth to the region 208Db is "Xb", and the depth to the region 208M is "Xd". It is preferable to select an acceleration energy that causes the concentration of the first element to be high in regions 108Da, 108Db, 208Da, and 208Db, and to be low in regions 108M and 208M. Furthermore, it is preferable to select an acceleration energy that causes the concentration of the first element to be in the aforementioned range in regions 108Da, 108Db, 108M, 208Da, 208Db, and 208M, respectively.

1B and other figures show an example in which the layer 108, the insulating layer 106, and the conductive layer 104 cover the opening 141 in the transistor 100, and the layer 208, the insulating layer 106, and the conductive layer 204 cover the opening 241 and the opening 243 in the transistor 200, but one embodiment of the present invention is not limited to this. In the transistor 100, a step can be formed by the insulating layer 110 and the conductive layer 112, and the layer 108, the insulating layer 106, and the conductive layer 104 can be provided along the step. Similarly, in the transistor 200, a step can be formed by the insulating layer 110, the conductive layer 212b, and the conductive layer 212a, and the layer 208, the insulating layer 106, and the conductive layer 204 can be provided along the step.

[Layer 108, layer 208]
Metal oxides that can be used for the layer 108 and the layer 208 will be specifically described. Examples of metal oxides include indium oxide (also referred to as indium oxide), gallium oxide (also referred to as gallium oxide), and zinc oxide (also referred to as zinc oxide). The metal oxide preferably contains at least indium or zinc. The metal oxide preferably contains one or more elements selected from indium, element M, and zinc. The element M is a metal element or semi-metal element having a high bond energy with oxygen, for example, a metal element or semi-metal element having a bond energy with oxygen higher than that of indium. Specific examples of the element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony. The element M of the metal oxide is preferably one or more of the above elements, more preferably one or more selected from gallium, aluminum, tin, and yttrium, and even more preferably one or more of gallium, aluminum, and tin. These elements are more preferable because they have a high bond energy with oxygen and have an ionic radius similar to that of indium or zinc. In addition, tin is more preferable because it is tetravalent and can increase carrier mobility. In this specification, metal elements and metalloid elements may be collectively referred to as "metal elements", and the "metal elements" described in this specification may include metalloid elements.

Layer 108 and layer 208 may be, for example, indium zinc oxide (In-Zn oxide, also referred to as IZO (registered trademark)), indium tin oxide (In-Sn oxide, also referred to as ITO), indium titanium oxide (In-Ti oxide), indium gallium oxide (In-Ga oxide), indium tungsten oxide (In-W oxide, also referred to as IWO), indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (In-Ga-Sn oxide, also referred to as IGTO), gallium zinc oxide (Ga-Zn oxide, also referred to as GZO), aluminum zinc oxide (Al-Zn oxide), Indium aluminum zinc oxide (In-Al-Zn oxide, also written as AZO), indium tin zinc oxide (In-Sn-Zn oxide, also written as ITZO (registered trademark)), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also written as IGZO), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also written as IGZTO), indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also written as IGAZO, IGZAO, or IAGZO), etc. can be used. Alternatively, indium tin oxide containing silicon (also written as ITSO), gallium tin oxide (Ga-Sn oxide), aluminum tin oxide (Al-Sn oxide), etc. can be used.

Note that the metal oxide may have one or more metal elements with a higher period number in the periodic table instead of or in addition to indium. The greater the overlap of the orbits of the metal elements, the greater the carrier conduction in the metal oxide. Therefore, by having a metal element with a higher period number, the field effect mobility of the transistor may be increased. Examples of metal elements with a higher period number include metal elements belonging to the fifth period and metal elements belonging to the sixth period. Specific examples of the metal elements include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. Note that lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.

By increasing the ratio of the number of indium atoms to the total number of atoms of all metal elements contained in the metal oxide, the field effect mobility of the transistor can be increased. In addition, a transistor with a large on-current can be realized.

In this specification, the ratio of the number of indium atoms to the sum of the numbers of atoms of all contained metal elements may be referred to as the indium content. The same applies to other metal elements. When there are multiple elements as element M, the sum of the ratios of the number of atoms of element M to the sum of the numbers of atoms of all contained metal elements can be taken as the content of element M.

Increasing the zinc content in the metal oxide results in a highly crystalline metal oxide, which can suppress the diffusion of impurities in the metal oxide. This suppresses fluctuations in the electrical characteristics of the transistor, and increases reliability.

By increasing the content of element M in the metal oxide, the metal oxide can have a large band gap. Furthermore, by suppressing the formation of oxygen vacancies (V _{2 O 3} ) in the metal oxide, carrier generation due to oxygen vacancies (V 2 _{O 3} ) can be suppressed, and a shift in the threshold voltage of the transistor can be suppressed. As a result, the cutoff current can be reduced, and a normally-off transistor can be obtained. Furthermore, a transistor with a small off-current can be obtained. Furthermore, fluctuations in the electrical characteristics of the transistor can be suppressed, and reliability can be improved.

The electrical characteristics and reliability of the transistors 100 and 200 vary depending on the composition of the metal oxide applied to the layers 108 and 208. Therefore, by varying the composition of the metal oxide depending on the electrical characteristics and reliability required of the transistor, a semiconductor device that has both excellent electrical characteristics and high reliability can be obtained.

When the metal oxide is an In-M-Zn oxide, it is preferable that the atomic ratio of In in the In-M-Zn oxide is equal to or greater than the atomic ratio of element M. Examples of atomic ratios of metal elements in such In-M-Zn oxides include In:M:Zn = 1:1:1, In:M:Zn = 1:1:1.2, In:M:Zn = 2:1:3, In:M:Zn = 3:1:1, In:M:Zn = 3:1:2, In:M:Zn = 4:2:3, In:M:Zn = 4:2:4.1, In:M:Zn = 5:1:3, In:M:Zn = 5:1:6, In:M:Zn = 5:1:7, In:M:Zn = 5:1:8, In:M :Zn=5:1:9, In:M:Zn=6:1:6, In:M:Zn=10:1:1, In:M:Zn=10:1:3, In:M:Zn=10:1:4, In:M:Zn=10:1:6, In:M:Zn=10:1:7, In:M:Zn=10:1:8, In:M:Zn=5:2:5, In:M:Zn=10:1:10, In:M:Zn=20:1:10, In:M:Zn=40:1:10, and compositions in the vicinity of these. Note that the composition in the vicinity includes a range of ±30% of the desired atomic ratio. By increasing the atomic ratio of indium in the metal oxide, the on-current or field effect mobility of the transistor can be increased.

The atomic ratio of In in the In-M-Zn oxide can be less than the atomic ratio of element M. Examples of atomic ratios of metal elements in such In-M-Zn oxide include In:M:Zn=1:3:2, In:M:Zn=1:3:3, In:M:Zn=1:3:4, In:M:Zn=1:3:6, and compositions close to these. By increasing the proportion of M atoms in the metal oxide, the generation of oxygen vacancies ( _VO ) can be suppressed.

In addition, when there are multiple elements as element M, the sum of the atomic ratios of these elements can be regarded as the atomic ratio of element M.

By using a material having a high indium content for the layers 108 and 208, the on-state current or field effect mobility of the transistors 100 and 200 can be increased. Furthermore, by containing the element M, the generation of oxygen vacancies (V ₀ ) can be suppressed. The content of the element M in the metal oxide contained in the layers 108 and 208 is preferably 0.1% to 25%, more preferably 0.1% to 20%, more preferably 0.1% to 10%, more preferably 0.1% to 8%, more preferably 0.1% to 6%, and even more preferably 0.1% to 4%. This allows a transistor with good electrical characteristics to be obtained. For example, it is preferable to use a metal oxide of In:M:Zn=40:1:10 or a metal oxide in the vicinity thereof. The element M is preferably one or more of the above elements, and more preferably one or more selected from aluminum, gallium, tin, and yttrium. Specifically, In:Sn:Zn=40:1:10 and metal oxides in the vicinity thereof can be preferably used, or In:Al:Zn=40:1:10 and metal oxides in the vicinity thereof can be preferably used.

Here, if a polycrystalline metal oxide is used for the layers 108 and 208, the grain boundaries become recombination centers, and carriers are captured, which may reduce the on-current of the transistor. In addition, if a polycrystalline metal oxide is used for the layers 108 and 208, the surface of the layers 108 and 208 may become uneven. This increases the step of the surface on which the layer (e.g., the insulating layer 106) formed on the layers 108 and 208 is formed, and defects such as step breaks or pores may occur in the layers. When a metal oxide having a composition that is likely to form a polycrystalline structure is used for the layers 108 and 208, it is preferable to include an element that inhibits crystallization. This prevents the layers 108 and 208 from becoming polycrystalline, and allows the transistor to have a large on-current. In addition, the coverage of the layers (e.g., the insulating layer 106) formed on the layers 108 and 208 can be improved, and defects such as step breaks or pores in the layers can be suppressed.

For example, compared with indium tin oxide (ITO), indium tin oxide containing silicon (ITSO) is less likely to become a polycrystalline structure, and therefore can be suitably used for the layers 108 and 208. When ITSO is used, the silicon content is preferably 1% to 20%, more preferably 3% to 20%, even more preferably 3% to 15%, and even more preferably 5% to 15%. As the atomic ratio of metal elements, for example, In:Sn:Si=45:5:4, In:Sn:Si=95:5:8, and metal oxides in the vicinity thereof can be suitably used. When indium tin oxide containing silicon (ITSO) is used for the layers 108 and 208, it is preferable that it has crystallinity. Note that the layer 108 may have an amorphous region or may be amorphous.

A metal oxide that does not contain element M can be applied to layers 108 and 208. When the metal oxide is an In-Zn oxide, the atomic ratio of the metal elements can be, for example, In:Zn=1:1, In:Zn=2:1, In:Zn=1:2, In:Zn=3:1, In:Zn=3:2, In:Zn=2:3, In:Zn=4:1, In:Zn=4:3, In:Zn=5:1, In:Zn=5:2, In:Zn=5:3, In:Zn=5:4, In:Zn=5:6, In:Zn=5:7, In:Zn=5:8, In:Zn=5:9, In:Zn=7:1, In:Zn=10:1, In:Zn=10:3, In:Zn=10:7, and compositions close to these can be mentioned. Furthermore, it is more preferable that the atomic ratio of In is equal to or greater than the atomic ratio of Zn. By increasing the atomic ratio of indium in the metal oxide, the on-current or field effect mobility of the transistor can be increased.

The composition of layers 108 and 208 can be analyzed using, for example, energy dispersive X-ray spectrometry (EDX), X-ray photoelectron spectrometry (XPS), inductively coupled plasma mass spectrometry (ICP-MS), or inductively coupled plasma-atomic emission spectrometry (ICP-AES). Alternatively, a combination of these techniques can be used for analysis. It is preferable to separate the peaks of the spectrum obtained by the analysis and identify and quantify the elements. In addition, for elements with low content, the actual content may differ from the content obtained by analysis due to the influence of analytical accuracy. For example, if the content of element M is low, the content of element M obtained by analysis may be lower than the actual content, may be difficult to quantify, or may be below the detection limit.

The metal oxide can be formed by sputtering or ALD. Thermal ALD or PEALD can be used as the ALD. When forming a metal oxide by sputtering, the composition of the formed metal oxide may differ from the composition of the sputtering target. In particular, the zinc content in the formed metal oxide may decrease to about 50% compared to the sputtering target. The PECVD method can also be used to form the metal oxide.

The layers 108 and 208 are preferably made of a crystalline metal oxide. Examples of the structure of a crystalline metal oxide include a CAAC (c-axis aligned crystal) structure, a polycrystalline structure, and a nano-crystalline (nc: nano-crystal) structure. By using a crystalline metal oxide, the density of defect levels in the layers 108 and 208 can be reduced, and a highly reliable semiconductor device can be realized.

Layer 108 and layer 208 are preferably made of CAAC-OS or nc-OS.

CAAC-OS has multiple layered crystals. The c-axes of the crystals are oriented in the normal direction of the surface on which the transistor is formed. The layers 108 and 208 preferably have layered crystals parallel or approximately parallel to the surface on which the transistor is formed. For example, the layer 108 preferably has layered crystals parallel or approximately parallel to the upper surface of the conductive layer 112 in a region in contact with the upper surface of the conductive layer 112. In particular, the layer 108 preferably has layered crystals parallel or approximately parallel to the side surface of the insulating layer 110, which is the surface on which the transistor is formed, in the opening 141. With this configuration, the layered crystals of the layer 108 are formed parallel or approximately parallel to the channel length direction of the transistor 100, and therefore the transistor can have a large on-current. Similarly, the layered crystals of the layer 208 are formed parallel or approximately parallel to the channel length direction of the transistor 200, and therefore the transistor can have a large on-current.

By using a metal oxide with high crystallinity in the channel formation region, the density of defect states in the channel formation region can be reduced. On the other hand, by using a metal oxide with low crystallinity, a transistor capable of passing a large current can be realized.

The higher the substrate temperature during metal oxide formation, the more crystalline the metal oxide that can be formed. The substrate temperature during formation can be adjusted, for example, by the temperature of the stage on which the substrate is placed during formation. In addition, the higher the ratio of the flow rate of oxygen gas to the total flow rate of the deposition gas (hereinafter also referred to as the oxygen flow rate ratio) or the oxygen partial pressure in the processing chamber, the more crystalline the metal oxide that can be formed.

The crystallinity of layers 108 and 208 can be analyzed, for example, by X-ray diffraction (XRD), transmission electron microscope (TEM), or electron diffraction (ED). Alternatively, the analysis can be performed by combining a plurality of these techniques.

When a metal oxide is used for the layers 108 and 208, it is preferable to reduce the _VOH of the channel formation region as much as possible to make it highly pure or substantially highly pure. In order to obtain a metal oxide with sufficiently reduced _VOH , it is important to remove impurities such as water and hydrogen from the metal oxide (sometimes referred to as dehydration or dehydrogenation treatment) and to supply oxygen to the metal oxide to repair oxygen vacancies ( _VOH ). By using a metal oxide with sufficiently reduced impurities such as _VOH for the channel formation region of a transistor, stable electrical characteristics can be imparted. Note that supplying oxygen to a metal oxide to repair oxygen vacancies ( _VOH ) may be referred to as oxygen addition treatment.

When a metal oxide is used for the layers 108 and 208, the carrier concentration of each of the regions 108M and 208M functioning as a channel formation region is preferably 1×10 ¹⁸ cm ⁻³ or less, more preferably less than 1×10 ¹⁷ cm ⁻³ , even more preferably less than 1×10 ¹⁶ cm ⁻³ , even more preferably less than 1×10 ¹³ cm ⁻³ , and even more preferably less than 1×10 ¹² cm ⁻³ . Note that there is no limitation on the lower limit of the carrier concentration of the channel formation region, but it can be, for example, 1×10 ⁻⁹ cm ⁻³ .

As described above, the region of layer 108 in contact with conductive layer 112 functions as one of the source region and drain region of transistor 100, and region 108Db functions as the other of the source electrode and drain electrode. The region of layer 208 in contact with conductive layer 212a functions as one of the source region and drain region of transistor 200, and the region in contact with conductive layer 212b functions as the other of the source region and drain region. Region 108Db, the source region, and the drain region are regions with lower electrical resistance than the channel formation region. Region 108Db, the source region, and the drain region can also be said to be regions with a higher carrier concentration and a higher oxygen defect density than the channel formation region.

At least one of the regions of the layer 108 in contact with the insulating layer 110a and the region in contact with the insulating layer 110c can be a region having a lower electrical resistance than the channel formation region (hereinafter also referred to as a low-resistance region). The region can also be said to be a region having a higher carrier concentration and a higher oxygen defect density than the channel formation region. By using a material that releases impurities (e.g., water and hydrogen) in the insulating layer 110a, the region of the layer 108 in contact with the insulating layer 110a can be a low-resistance region. The layer 108 can be configured to have a low-resistance region between one of the source and drain regions and the region 108M that functions as the channel formation region. Similarly, by using a material that releases impurities in the insulating layer 110c, the region of the layer 108 in contact with the insulating layer 110c can be a low-resistance region. The layer 108 can be configured to have a low-resistance region between the region 108Db that functions as the other of the source and drain electrodes and the region 108M that functions as the channel formation region. The low resistance regions can function as buffer regions to reduce the drain electric field. These low resistance regions can also function as source or drain regions. The same applies to layer 208.

OS transistors have small variations in electrical characteristics due to radiation exposure, i.e., they have high resistance to radiation, and therefore can be suitably used in environments where radiation may be present. It can also be said that OS transistors have high reliability against radiation. For example, OS transistors can be suitably used in pixel circuits of X-ray flat panel detectors. OS transistors can also be suitably used in semiconductor devices used in outer space. Examples of radiation include electromagnetic radiation (e.g., X-rays and gamma rays) and particle radiation (e.g., alpha rays, beta rays, proton rays, and neutron rays).

Layer 108 and layer 208 may have a layered material that functions as a semiconductor. A layered material is a general term for a group of materials that have a layered crystal structure. A layered crystal structure is a structure in which layers formed by covalent or ionic bonds are stacked via bonds weaker than covalent or ionic bonds, such as van der Waals bonds. A layered material has high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity in the channel formation region, a transistor with a large on-current can be provided.

Examples of the layered material include graphene, silicene, and chalcogenides. Chalcogenides are compounds containing chalcogen (an element belonging to Group 16). Examples of the chalcogenides include transition metal chalcogenides and Group 13 chalcogenides. Specific examples of transition metal chalcogenides that can be used as the channel formation region of a transistor include molybdenum sulfide (representatively MoS ₂ ), molybdenum selenide (representatively MoSe ₂ ), molybdenum tellurium (representatively MoTe ₂ ), tungsten sulfide (representatively WS ₂ ), tungsten selenide (representatively WSe _{2 ), tungsten tellurium (representatively WTe 2 )} , hafnium sulfide (representatively HfS _{2 ), hafnium selenide (representatively HfSe 2 )} , zirconium sulfide (representatively ZrS ₂ ), zirconium selenide (representatively ZrSe ₂ ), and the like.

Layer 108 and layer 208 can each have a stacked structure having two or more metal oxide layers. The compositions of the two or more metal oxide layers in layer 108 and layer 208 can be the same or approximately the same. By using a stacked structure of metal oxide layers with the same composition, for example, they can be formed using the same sputtering target, reducing manufacturing costs. When the compositions of the two or more metal oxide layers in layer 108 and layer 208 are the same or approximately the same, the boundary (interface) between these metal oxide layers may not be clearly identified.

When layers 108 and 208 each have a two-layer structure of a first metal oxide layer and a second metal oxide layer on the first metal oxide layer, the surface on which the second metal oxide layer is formed becomes the surface of the first metal oxide layer, and the crystallinity of the second metal oxide layer may be high. Furthermore, by performing a heat treatment after forming the second metal oxide layer, the crystallinity of the first metal oxide layer can be increased. The heat treatment can also be called a crystallization treatment.

A first metal oxide layer is formed, and a second metal oxide layer having higher crystallinity than the first layer is formed. For example, the ALD method can be suitably used to form the first metal oxide layer, and the sputtering method can be suitably used to form the second metal oxide layer. By performing a heat treatment after the formation of the second metal oxide layer, the crystallinity of the first metal oxide layer and the second metal oxide layer can be further increased. At this time, the crystals contained in the second metal oxide layer grow continuously toward the first metal oxide layer, and the boundary between the first metal oxide layer and the second metal oxide layer may not be clearly identified. It is particularly preferable that the second metal oxide layer has a CAAC structure. This allows the crystals having the CAAC structure of the second metal oxide layer to be used as nuclei or seeds to increase the crystallinity of the first metal oxide layer.

A three-layer structure having a third metal oxide layer on the second metal oxide layer can be formed. For example, the ALD method can be suitably used to form the first metal oxide layer and the third metal oxide layer, and the sputtering method can be suitably used to form the second metal oxide layer. By performing a heat treatment after the formation of the third metal oxide layer, the crystallinity of the first metal oxide layer, the second metal oxide layer, and the third metal oxide layer can be increased. At this time, the crystals contained in the second metal oxide layer grow continuously toward the first metal oxide layer and the third metal oxide layer, and the boundary between the first metal oxide layer and the second metal oxide layer, and the boundary between the second metal oxide layer and the third metal oxide layer may not be clearly identified. By the second metal oxide layer having a CAAC structure, the crystals having the CAAC structure of the second metal oxide layer can be used as nuclei or seeds to increase the crystallinity of the first metal oxide layer and the third metal oxide layer.

By stacking a metal oxide layer with low crystallinity and a metal oxide layer with high crystallinity, crystal growth occurs continuously in the thickness direction between them, and the crystallinity can be increased throughout the entire metal oxide layer. Alternatively, by stacking a metal oxide layer with low crystallinity and a metal oxide layer with high crystallinity and then performing a heat treatment, crystal growth occurs continuously in the thickness direction between them, and the crystallinity can be increased throughout the entire metal oxide layer. This makes it possible to realize a highly reliable transistor. The thickness direction refers to a direction perpendicular or approximately perpendicular to the surface on which the metal oxide layer is formed. A metal oxide layer with increased crystallinity in this way can be called an Axial Growth CAAC (AG CAAC). In addition to crystal growth in the thickness direction, crystal growth may also occur in a direction parallel or approximately parallel to the surface on which the metal oxide layer is formed.

The temperature of the heat treatment can be 100°C or higher and lower than the distortion point of the substrate. The temperature of the heat treatment is preferably 100°C or higher and 800°C or lower, more preferably 250°C or higher and 650°C or lower, and even more preferably 350°C or higher and 550°C or lower. The time of the heat treatment is, for example, preferably 1 minute or higher and 1 hour or lower, more preferably 10 minutes or higher and 30 minutes or lower, at a temperature of 350°C or higher and 550°C or lower. The heating device used for the heat treatment is not particularly limited, and a device that heats the workpiece by thermal conduction or thermal radiation from a heating element (e.g., a resistance heating element) can be used. For the heat treatment, for example, an electric furnace or an RTA (Rapid Thermal Anneal) device such as an LRTA (Lamp Rapid Thermal Anneal) device or a GRTA (Gas Rapid Thermal Anneal) device can be used. The LRTA device is a device that heats the workpiece by radiating light (electromagnetic waves) emitted from a lamp (e.g., a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high-pressure sodium lamp, and a high-pressure mercury lamp). The GRTA device is a device that heats the workpiece using a high-temperature gas.

[Insulating layer 110]
As described above, the insulating layer 110 preferably has a stacked structure. The insulating layer 110b has a function of supplying oxygen to channel formation regions (here, the regions 108M and 208M) of the layer 108 and the layer 208. The insulating layers 110a and 110c function as barrier films.

If the thickness T110a of the insulating layer 110a and the thickness T110c of the insulating layer 110c are thin, the oxygen contained in the insulating layer 110b may diffuse to the conductive layer 112 and the conductive layer 212a side through the insulating layer 110a, and to the region 108Db and the conductive layer 212b side through the insulating layer 110c. This may reduce the amount of oxygen supplied to the channel formation region of the layer 108 and the layer 208, and may increase the electrical resistance of the region 108Db, the conductive layer 112, the conductive layer 212a, and the conductive layer 212b. On the other hand, if the thickness T110a and the thickness T110c are thick, the amount of impurities released from the insulating layer 110a and the insulating layer 110c may increase, and the amount of impurities diffusing into the channel formation region may increase. 3A and 3B, the thickness T110a can be the shortest distance between the surface of the insulating layer 110a to be formed (here, the upper surface of the conductive layer 112 or the upper surface of the conductive layer 212a) and the upper surface of the insulating layer 110a in a cross-sectional view. The thickness T110c can be the shortest distance between the surface of the insulating layer 110c to be formed (here, the upper surface of the insulating layer 110b) and the upper surface of the insulating layer 110c in a cross-sectional view.

The thickness T110c is preferably 3 nm or more and 200 nm or less, more preferably 3 nm or more and 100 nm or less, even more preferably 3 nm or more and 50 nm or less, even more preferably 3 nm or more and 30 nm or less, even more preferably 3 nm or more and 20 nm or less, even more preferably 3 nm or more and 10 nm or less, even more preferably 5 nm or more and 10 nm or less.

Thickness T110a can be thicker than thickness T110c. If the region of layer 108 in contact with insulating layer 110a functions as the source or drain region of transistor 100, the distance from the source or drain region to the gate electrode can be made more uniform by increasing thickness T110a. Similarly, if the region of layer 208 in contact with insulating layer 110a functions as the source or drain region of transistor 200, the distance from the source or drain region to the gate electrode can be made more uniform by increasing thickness T110a. This can make the electric field of the gate electrode applied to the channel formation region more uniform. The thickness T110a of the insulating layer 110a is preferably 3 nm or more and 500 nm or less, more preferably 5 nm or more and 400 nm or less, more preferably 10 nm or more and 300 nm or less, more preferably 20 nm or more and 300 nm or less, more preferably 50 nm or more and 300 nm or less, more preferably 100 nm or more and 300 nm or less, more preferably 100 nm or more and 250 nm or less, and more preferably 150 nm or more and 250 nm or less.

By setting the thickness T110a and the thickness T110c within the above-mentioned ranges, the amount of oxygen supplied to the channel formation regions of the layer 108 and the layer 208 can be increased, and oxygen vacancies ( _VO ) and _VOH in the channel formation regions can be reduced. In addition, it is possible to prevent the electrical resistance of the region 108Db, the conductive layer 112, the conductive layer 212a, and the conductive layer 212b from increasing due to oxygen contained in the insulating layer 110b. Note that the thickness T110a and the thickness T110c are not limited to the above-mentioned ranges.

Note that impurities released from the insulating layer 110a may diffuse into the channel formation region of the layer 108 through the insulating layer 110b or through a region of the layer 108 in contact with the insulating layer 110a. Similarly, impurities released from the insulating layer 110c may diffuse into the channel formation region of the layer 108 through the insulating layer 110b or through a region of the layer 108 in contact with the insulating layer 110c. When the impurity is hydrogen, hydrogen released from the insulating layer 110a or the insulating layer 110c may diffuse into the channel formation region of the layer 108. However, oxygen is supplied from the insulating layer 110b to at least a region of the layer 108 in contact with the insulating layer 110b, so that oxygen vacancies (V _O ) and V _O H in the channel formation region can be reduced. This suppresses a shift in the threshold voltage, and a transistor having both a small cutoff current and a large on-current can be obtained. The same applies to the layer 208. Therefore, a semiconductor device that achieves both low power consumption and high performance can be obtained.

However, if the amount of impurities released from the insulating layers 110a and 110c becomes too large, the amount of oxygen vacancies ( _VO ) and _VOH generated by the impurities may be greater than the amount of oxygen vacancies ( _VO ) and _VOH repaired by oxygen supplied from the insulating layer 110b. Even when a material that releases impurities is used for the insulating layers 110a and 110c, it is more preferable that the amount of impurities released from these layers is small.

One or more of the insulating layers 110a, 110b, and 110c may have a laminated structure.

When the insulating layer 110c has a laminated structure, the materials listed for the insulating layer 110c can be used for each layer constituting the insulating layer 110c. An oxide or an oxynitride can be preferably used for the layer provided on the insulating layer 110b side. More specifically, one or more of aluminum oxide, hafnium oxide, hafnium aluminate, magnesium oxide, gallium oxide, and gallium zinc oxide can be particularly preferably used for the layer provided on the insulating layer 110b side. By using an oxide or an oxynitride for the layer provided on the insulating layer 110b side, oxygen can be supplied to the insulating layer 110b (or the insulating film that becomes the insulating layer 110b) when forming the layer (or the film that becomes the layer), which is preferable. The insulating layer 110c can have a laminated structure of, for example, a first film having an oxide or an oxynitride and a second film having a nitride or a nitride oxide on the first film. More specifically, the insulating layer 110c can have a laminated structure of, for example, an aluminum oxide film and a silicon nitride film on the aluminum oxide film.

[Opening 141, Opening 241, Opening 243]
The upper surface shapes of the openings 141, 241, and 243 are not limited, and each of them may be, for example, a circle, an ellipse, a triangle, a quadrangle (including a rectangle, a rhombus, and a square), a polygon such as a pentagon, or a shape with rounded corners of these polygons. The polygon may be either a concave polygon (a polygon with at least one interior angle exceeding 180 degrees) or a convex polygon (a polygon with all interior angles less than 180 degrees). As shown in FIG. 1A, etc., the upper surface shapes of the openings 141, 241, and 243 are preferably circular. By making the upper surface shape of the openings circular, the processing accuracy when forming the openings can be improved, and openings of fine size can be formed. When the upper surface shapes of the openings 241 and 243 are circular, the openings 241 and 243 may be concentric or not concentric. In this specification, etc., a circle is not limited to a perfect circle.

The channel length and channel width of the transistor 100 and the transistor 200 will be described with reference to Figures 4A to 4C. Figure 4A is a top view of the transistor 100 and the transistor 200, Figure 4B is a cross-sectional view of the transistor 100, and Figure 4C is a cross-sectional view of the transistor 200.

In FIG. 4B, the channel length L100 of the transistor 100 is indicated by a double-headed dashed arrow. The channel length L100 of the transistor 100 corresponds to the length of the side of the insulating layer 110b on the opening 141 side in a cross-sectional view. In other words, the channel length L100 is determined by the thickness T110b of the insulating layer 110b and the angle θ100 between the side of the insulating layer 110b on the opening 141 side and the surface on which the insulating layer 110b is formed (here, the top surface of the insulating layer 110a). In FIG. 4C, the channel length L200 of the transistor 200 is indicated by a double-headed dashed arrow. The channel length L200 of the transistor 200 corresponds to the length of the side of the insulating layer 110b on the opening 241 side in a cross-sectional view. That is, the channel length L200 is determined by the thickness T110b of the insulating layer 110b and the angle θ200 between the side of the insulating layer 110b on the opening 241 side and the surface on which the insulating layer 110b is to be formed (here, the upper surface of the insulating layer 110a). Therefore, the channel length L100 and the channel length L200 can be set to values smaller than the minimum exposure dimension of the exposure device, and a transistor of a fine size can be realized. Specifically, a transistor with an extremely short channel length that could not be realized with a conventional exposure device for mass production of flat panel displays (for example, a minimum dimension of about 2 μm or 1.5 μm) can be realized. In addition, a transistor with a channel length of less than 10 nm can be realized without using an extremely expensive exposure device used in cutting-edge LSI technology.

The channel length L100 and the channel length L200 can each be, for example, 5 nm or more, 7 nm or more, or 10 nm or more, and can be less than 3 μm, 2.5 μm or less, 2 μm or less, 1.5 μm or less, 1.2 μm or less, 1 μm or less, 500 nm or less, 300 nm or less, 200 nm or less, 100 nm or less, 50 nm or less, 30 nm or less, or 20 nm or less. For example, the channel length L100 can be 100 nm or more and 1 μm or less.

By shortening the channel length L100 and the channel length L200, the on-state current of the transistor 100 and the transistor 200 can be increased. By using the transistor 100 and the transistor 200, a circuit capable of high-speed operation can be manufactured. Furthermore, the area occupied by the circuit can be reduced. Therefore, a small-sized semiconductor device can be obtained. For example, when the semiconductor device of one embodiment of the present invention is applied to a large display device or a high-definition display device, even if the number of wirings is increased, the signal delay in each wiring can be reduced and display unevenness can be suppressed. Furthermore, since the area occupied by the circuit can be reduced, the frame of the display device can be narrowed.

The channel length L100 can be controlled by adjusting the thickness T110b and the angle θ100. Similarly, the channel length L200 can be controlled by adjusting the thickness T110b and the angle θ200.

The thickness T110b can be, for example, 5 nm or more, 7 nm or more, or 10 nm or more, and can be less than 3 μm, 2.5 μm or less, 2 μm or less, 1.5 μm or less, 1.2 μm or less, 1 μm or less, 500 nm or less, 300 nm or less, 200 nm or less, 100 nm or less, 50 nm or less, 30 nm or less, or 20 nm or less. The thickness T110b can be appropriately set to obtain the desired channel length L100. As shown in FIG. 4B, the thickness T110b can be the shortest distance between the surface on which the insulating layer 110b is formed (here, the upper surface of the insulating layer 110a) and the upper surface of the insulating layer 110b in a cross-sectional view.

It is preferable that the angles θ100 and θ200 are each 90 degrees or less. By reducing the angles θ100 and θ200, the coverage of the layers (e.g., layers 108 and 208) formed on the insulating layer 110 can be improved. Furthermore, when the angle θ100 is 90 degrees or less, the smaller the angle θ100, the longer the channel length L100 can be, and the larger the angle θ100, the shorter the channel length L100 can be. The same applies to the angle θ200 and the channel length L200.

When the angle θ100 is less than 90 degrees, the larger the angle θ100, the larger the difference between the thickness Ta and the thickness Td, and the difference between the thickness Tb and the thickness Td. Therefore, the supply of the first element to the region 108M is suppressed, and the first element is preferentially supplied to the regions 108Da and 108Db. This makes it possible to efficiently lower the electrical resistance of the regions 108Da and 108Db. Similarly, when the angle θ200 is less than 90 degrees, the larger the angle θ200, the larger the difference between the thickness Xa and the thickness Xd, and the difference between the thickness Xb and the thickness Xd. Therefore, the supply of the first element to the region 208M is suppressed, and the first element is preferentially supplied to the regions 208Da and 208Db. This makes it possible to efficiently lower the electrical resistance of the regions 208Da and 208Db.

In FIG. 4B and other figures, the angles θ100 and θ200 are each shown as less than 90 degrees, but this is not a limitation of one aspect of the present invention. The angles θ100 and θ200 can each be 90 degrees or approximately 90 degrees. This allows the channel lengths L100 and L200 to be shortened.

In a configuration in which the angle θ100 is 90 degrees, when the first element is supplied to layer 108 through insulating layer 106, the first element passes through the region in contact with insulating layer 106 and the side of insulating layer 110c of layer 108 to reach region 108M. Therefore, the depth in region 108M is deeper than the depth in regions 108Da and 108Db. Therefore, the concentration of the first element in region 108M is lower than the concentration of the first element in regions 108Da and 108Db. In a configuration in which the angle θ200 is 90 degrees, when the first element is supplied to layer 208 through insulating layer 106, the first element passes through the region in contact with insulating layer 106 and the side of conductive layer 212b of layer 208, and the region in contact with the side of insulating layer 110c to reach region 208M. Therefore, the depth in region 208M is greater than the depth in regions 208Da and 208Db. Therefore, the concentration of the first element in region 208M is less than the concentration of the first element in regions 208Da and 208Db.

The higher the film density of the material used for layers 108 and 208, the higher the stopping power in ion implantation, and the smaller the amount of the first element that reaches regions 108M and 208M. For example, if layer 108 has a higher film density than insulating layer 106, the amount of the first element supplied to layer 108 will be smaller even at the same depth. In addition, since the stopping power in ion implantation differs depending on the type of element, the amount of the first element supplied also differs depending on the composition of the implanted layer.

The angles θ100 and θ200 can each be, for example, 30 degrees or more, 35 degrees or more, 40 degrees or more, 45 degrees or more, 50 degrees or more, 55 degrees or more, 60 degrees or more, 65 degrees or more, or 70 degrees or more, and 90 degrees or less, 85 degrees or less, or 80 degrees or less. The angles θ100 and θ200 can also each be 75 degrees or less, 70 degrees or less, 65 degrees or less, or 60 degrees or less. The angles θ100 and θ200 can be appropriately set to the desired channel length L100 and channel length L200, respectively.

As described above, the larger the angles θ100 and θ200, the more the first element can be preferentially supplied to regions 108Da, 108Db, 208Da, and 208Db. However, if the angle θ100 is large, the coverage of the layers (e.g., layer 108 and insulating layer 106) provided in the opening 141 may decrease, and if the angle θ200 is large, the coverage of the layers (e.g., layer 208 and insulating layer 106) provided in the opening 241 and opening 243 may decrease. Therefore, the angles θ100 and θ200 are preferably 65 degrees or more and 90 degrees or less, more preferably 70 degrees or more and 90 degrees or less, and even more preferably 75 degrees or more and 90 degrees or less.

By making the angle θ200 the same or approximately the same as the angle θ100, the channel length L200 becomes the same or approximately the same as the channel length L100. For example, by forming the opening 141 and the opening 241 in the same process, the angles θ100 and θ200 can be made the same or approximately the same. Or, the angles θ100 and θ200 can be made different from each other. For example, by forming the opening 141 and the opening 241 in different processes and making the angles θ100 and θ200 different from each other, the channel length L100 and the channel length L200 can be made different from each other. For example, when the angle θ200 is 90 degrees or less, by making the angle θ200 smaller, the channel length L200 becomes longer, and the saturation of the transistor 200 can be improved.

In this specification, the term "high saturation" may be used to refer to a small change in current in the saturation region in the Id-Vd characteristics of a transistor.

When angles θ100 and θ200 are large, it is preferable to use a film formation method with higher coverage for forming the layers provided in openings 141, 241, and 243. For example, when angles θ100 and θ200 are 85 degrees or more and 90 degrees or less, the ALD method can be suitably used for forming insulating layer 106, layer 108, and layer 208. On the other hand, when angles θ100 and θ200 are small, a film formation method with higher productivity can be suitably used. For example, when angles θ100 and θ200 are less than 85 degrees, the PECVD method can be suitably used for forming insulating layer 106, and sputtering can be suitably used for forming layers 108 and 208.

The thickness of region 108Db provided along the top surface of insulating layer 110 of layer 108 may be thicker than the thickness of region 108M provided along the side surface of insulating layer 110. By increasing the thickness of region 108Db, the electrical resistance of the other of the source electrode and drain electrode of transistor 100 can be reduced.

In FIG. 1B and other figures, the shape of the side of the insulating layer 110 on the opening 141 side and the shape of the side of the opening 241 side are straight in cross section, but this is not a limitation of one embodiment of the present invention. In cross section, the shape of the side of the insulating layer 110 on the opening 141 side and the shape of the side of the opening 241 side can be curved. Alternatively, the side can have both straight and curved regions.

Here, it is preferable that the conductive layer 212b is not provided inside the opening 241. Specifically, it is preferable that the conductive layer 212b does not have a region that contacts the side of the insulating layer 110 on the opening 241 side. If the conductive layer 212b is provided also inside the opening 241, the channel length L200 of the transistor 200 becomes shorter than the length of the side of the insulating layer 110b, which may make it difficult to control the channel length L200. Therefore, it is preferable that the top shape of the opening 243 matches the top shape of the opening 241, or that the opening 243 encompasses the opening 241 when viewed from above.

In Figures 4A and 4B, the width D141 of the opening 141 is indicated by a double-headed arrow with two dashed lines, and in Figures 4A and 4C, the width D241 of the opening 241 is indicated by a double-headed arrow with two dashed lines. Figure 4A shows an example in which the top surface shape of the openings 141 and 241 is circular. In this case, the width D141 corresponds to the diameter of the circle, and the channel width W100 of the transistor 100 is the circumference of the circle. In other words, the channel width W100 is π x D141. Similarly, when the top surface shape of the opening 241 is circular, the channel width W200 of the transistor 200 is π x D241. When the top surface shape of the openings 141 and 241 is circular, it is possible to realize transistors 100 and 200 with smaller channel widths compared to other shapes.

The width D141 and the width D241 may vary in the depth direction. For example, the average value of the diameter at the highest point of the insulating layer 110b (or the insulating layer 110) in a cross-sectional view, the diameter at the lowest point, and the diameter at the midpoint between these three diameters may be used as the width D141 and the width D241. Alternatively, for example, any of the diameters at the highest point of the insulating layer 110b (or the insulating layer 110) in a cross-sectional view, the diameter at the lowest point, and the diameter at the midpoint between these two diameters may be used as the width D141 and the width D241.

When the openings 141 and 241 are formed using photolithography, the widths D141 and D241 are each equal to or greater than the minimum exposure dimension of the exposure device. The widths D141 and D241 can each be, for example, 20 nm or more, 50 nm or more, 100 nm or more, 200 nm or more, 300 nm or more, 400 nm or more, or 500 nm or more, and less than 5 μm, 4.5 μm or less, 4 μm or less, 3.5 μm or less, 3 μm or less, 2.5 μm or less, 2 μm or less, 1.5 μm or less, or 1 μm or less.

In FIG. 4A etc., the width D141 and the width D241 are shown to be the same, but one aspect of the present invention is not limited to this. The width D141 and the width D241 may also be different. By making the width D141 and the width D241 different, the channel width W100 and the channel width W200 can be made different.

Note that, although the example described here is a configuration in which region 108M functions as the channel formation region of transistor 100 and region 208M functions as the channel formation region of transistor 200, one embodiment of the present invention is not limited to this. The region of layer 108 in contact with insulating layer 110a may also function as a channel formation region. The region of layer 108 in contact with insulating layer 110c may also function as a channel formation region. The same applies to layer 208.

[Conductive layer 112, conductive layer 104, conductive layer 212a, conductive layer 212b, conductive layer 204]
The conductive layer 112, the conductive layer 104, the conductive layer 212a, the conductive layer 212b, and the conductive layer 204 can each have a single layer structure or a stacked structure of two or more layers. Examples of materials that can be used for these include one or more of chromium, copper, aluminum, gold, silver, zinc, tantalum, titanium, tungsten, manganese, nickel, iron, cobalt, molybdenum, and niobium, and alloys containing one or more of the above-mentioned metals. The conductive layer 112, the conductive layer 104, the conductive layer 212a, the conductive layer 212b, and the conductive layer 204 can each be preferably made of a conductive material with low electrical resistivity, including one or more of copper, silver, gold, and aluminum. In particular, copper or aluminum is preferable because of its excellent mass productivity.

Oxide conductors can be used for the conductive layer 112, the conductive layer 104, the conductive layer 212a, the conductive layer 212b, and the conductive layer 204. Examples of oxide conductors include indium oxide, zinc oxide, In-Sn oxide (ITO), In-Zn oxide, In-W oxide, In-W-Zn oxide, In-Ti oxide, In-Ti-Sn oxide, In-Sn-Si oxide (also called ITO containing silicon, ITSO), zinc oxide with added gallium, and In-Ga-Zn oxide. In particular, oxide conductors containing indium are preferred because of their high conductivity.

The conductive layer 112, the conductive layer 104, the conductive layer 212a, the conductive layer 212b, and the conductive layer 204 can each have a stacked structure of a conductive film containing the oxide conductor described above and a conductive film containing a metal or an alloy. By using a conductive film containing a metal or an alloy, the wiring resistance can be reduced.

The conductive layers 112, 104, 212a, 212b, and 204 can each be a Cu-X alloy film (X is Mn, Ni, Cr, Fe, Co, Mo, Ta, or Ti). By using a Cu-X alloy film, they can be processed by wet etching, reducing manufacturing costs.

Note that the conductive layer 112, the conductive layer 104, the conductive layer 212a, the conductive layer 212b, and the conductive layer 204 can be made of the same material. Alternatively, at least one of these layers can be made of a different material.

The layer 108 is formed after the conductive layer 112 is formed, and the layer 208 is formed after the conductive layer 212a and the conductive layer 212b are formed. When the layer 108 and the layer 208 contain oxygen or are formed in an atmosphere containing oxygen, if a metal (e.g., aluminum) that is easily oxidized is used for the conductive layer 112, the conductive layer 212a, and the conductive layer 212b, an insulating oxide (e.g., aluminum oxide) may be formed between the conductive layer 112 and the layer 108, between the conductive layer 212a and the layer 208, and between the conductive layer 212b and the layer 208, which may prevent the conduction between them. Therefore, it is preferable to use a conductive material that is not easily oxidized, a conductive material that maintains low electrical resistance even when oxidized, or an oxide conductor for the conductive layer 112, the conductive layer 212a, and the conductive layer 212b.

The conductive layer 112, the conductive layer 212a, and the conductive layer 212b are preferably made of, for example, titanium, tantalum nitride, titanium nitride, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel. These are preferable because they are conductive materials that are difficult to oxidize, or materials that maintain low electrical resistance even when oxidized. Note that when the conductive layer 112, the conductive layer 212a, or the conductive layer 212b has a stacked structure, it is preferable to use a conductive material that is difficult to oxidize at least for the layer in contact with the layer 108 and the layer in contact with the layer 208.

The conductive layer 112, the conductive layer 212a, and the conductive layer 212b can each use the oxide conductors described above. Specifically, oxide conductors such as indium oxide, zinc oxide, ITO, In-Zn oxide, In-W oxide, In-W-Zn oxide, In-Ti oxide, In-Ti-Sn oxide, In-Sn oxide containing silicon, and zinc oxide doped with gallium can be used.

The conductive layer 112, the conductive layer 212a, and the conductive layer 212b may each be made of a nitride conductor. Examples of nitride conductors include tantalum nitride and titanium nitride. The aforementioned nitride conductors may also be used for the conductive layer 104 and the conductive layer 204.

Cross-sectional views of a semiconductor device 10A according to one embodiment of the present invention are shown in FIGS. 5A to 6B. For a top view of the semiconductor device 10A, refer to FIG. 1A. Each of FIGS. 5A to 6B is a cross-sectional view of a cut surface taken along dashed line A1-A2 shown in FIG. 1A.

The semiconductor device 10A includes a transistor 100A, a transistor 200A, and an insulating layer 110. The transistor 100A differs mainly from the transistor 100 shown in FIG. 1B etc. in that the conductive layer 112 has a stacked structure, and the transistor 200A differs mainly from the transistor 200 in that the conductive layer 212a has a stacked structure.

FIGS. 5A and 5B show a configuration in which the conductive layer 112 has a two-layer structure of a conductive layer 112_1 and a conductive layer 112_2 on the conductive layer 112_1, and the conductive layer 212a has a two-layer structure of a conductive layer 212a_1 and a conductive layer 212a_2 on the conductive layer 212a_1.

For the conductive layer 112_2 having a region in contact with the layer 108, a conductive material that is not easily oxidized, a conductive material that maintains low electrical resistance even when oxidized, or an oxide conductor is preferably used. For materials that can be used for the conductive layer 112_2, see the description of the conductive layer 112.

Since the conductive layer 112_1 does not have an area in contact with the layer 108, the material used is not particularly limited. For example, it is preferable to use a material having a lower electrical resistivity than the conductive layer 112_2 for the conductive layer 112_1. This can reduce the electrical resistance of the conductive layer 112. For example, it is preferable to use In-Sn-Si oxide (ITSO) for the conductive layer 112_2, and copper or tungsten for the conductive layer 112_1.

As shown in FIG. 5A, the end of conductive layer 112_2 can be configured to be aligned or approximately aligned with the end of conductive layer 112_1. For example, conductive layer 112 can be formed by forming a first film that will become conductive layer 112_1 and a second film that will become conductive layer 112_2, and processing the first film and second film. By processing the first film and the second film in the same process, manufacturing costs can be reduced.

The conductive layer 112_2 may have an end that is not aligned with the end of the conductive layer 112_1. As shown in FIG. 5B, the conductive layer 112_2 may be provided so as to cover the conductive layer 112_1. The conductive layer 112_2 has an area that is in contact with the upper surface and side surface of the conductive layer 112_1. It can also be said that the conductive layer 112_2 has a portion that protrudes from the end of the conductive layer 112_1. For example, the conductive layer 112_1 may be formed, a film that becomes the conductive layer 112_2 may be formed on the conductive layer 112_1, and the conductive layer 112_2 may be formed by processing the film. By making the conductive layer 112_2 protrude from the end of the conductive layer 112_1, the step of the surface on which the layer (e.g., the insulating layer 110) is formed on the conductive layer 112 is reduced, and the coverage of the layer can be improved. This can suppress the occurrence of defects such as step discontinuities or porosity in the layer.

As shown in Figures 5A and 5B, some or all of the layers constituting the conductive layer 112 may have different thicknesses. By making the layer using a material with low electrical resistivity thicker than the other layers, the electrical resistance of the conductive layer 112 can be reduced. For example, a material with a lower electrical resistivity than the conductive layer 112_2 may be used for the conductive layer 112_1, and the thickness of the conductive layer 112_1 may be made thicker than the thickness of the conductive layer 112_2. This reduces the electrical resistance of the conductive layer 112. Note that the thicknesses of the layers constituting the conductive layer 112 may be the same or approximately the same.

The conductive layer 212a_1 can be formed in the same process as the conductive layer 112_1, and the conductive layer 212a_2 can be formed in the same process as the conductive layer 112_2. For the conductive layer 212a_1 and the conductive layer 212a_2, the description of the conductive layer 112_1 and the conductive layer 112_2 can be referred to.

FIGS. 6A and 6B show a configuration in which the conductive layer 112 has a three-layer structure of a conductive layer 112_3, a conductive layer 112_1 on the conductive layer 112_3, and a conductive layer 112_2 on the conductive layer 112_1, and the conductive layer 212a has a three-layer structure of a conductive layer 212a_3, a conductive layer 212a_1 on the conductive layer 212a_3, and a conductive layer 212a_2 on the conductive layer 212a_1.

As shown in FIG. 6A, the end of the conductive layer 112_1 can be configured to be in contact with the upper surface of the conductive layer 112_3. The conductive layer 112_2 has an area in contact with the upper surface and side surface of the conductive layer 112_1 and the upper surface of the conductive layer 112_3. In other words, it can be said that the conductive layer 112_2 and the conductive layer 112_3 each have a portion protruding from the end of the conductive layer 112_1. It can also be said that the upper surface, side surface, and lower surface of the conductive layer 112_1 are surrounded by the conductive layer 112_2 and the conductive layer 112_3. It is preferable to use a material for the conductive layer 112_3 that has high adhesion to the surface on which the conductive layer 112_3 is formed (here, the surface of the substrate 102). In addition, the end of the conductive layer 112_3 can be configured to be aligned or approximately aligned with the end of the conductive layer 112_2. For example, a first film that will become conductive layer 112_3 is formed, a conductive layer 112_1 is formed on the first film, and a second film that will become conductive layer 112_2 is formed on the first film and conductive layer 112_1. Then, by processing the first film and the second film, a conductive layer 112 having conductive layer 112_3, conductive layer 112_1, and conductive layer 112_2 can be formed. By processing the first film and the second film in the same process, the manufacturing cost can be reduced.

As described above, it is preferable to use a material with low electrical resistivity for the conductive layer 112_1. However, depending on the material, the adhesiveness between the conductive layer 112_1 and the surface on which the conductive layer 112_1 is formed (for example, the surface of the substrate 102) may be low, which may result in a low manufacturing yield of the semiconductor device. By using a material for the conductive layer 112_3 that has higher adhesiveness to the surface on which the conductive layer 112 is formed than the conductive layer 112_1, it is possible to increase the manufacturing yield of the semiconductor device. Note that the thickness of the conductive layer 112_3 is preferably a thickness that has the effect of increasing the adhesiveness of the conductive layer 112 to the surface on which the conductive layer 112 is formed, and can be thinner than the thicknesses of the conductive layer 112_1 and the conductive layer 112_2. By reducing the thickness of the conductive layer 112_3, it is possible to reduce the manufacturing cost.

For example, In-Sn-Si oxide (ITSO) can be suitably used for the conductive layer 112_3, copper for the conductive layer 112_1, and In-Sn-Si oxide (ITSO) for the conductive layer 112_2. When a glass substrate is used for the substrate 102, the adhesion between the glass substrate and the ITSO film is higher than that between the glass substrate and the copper film. In addition, by using the same material for the conductive layers 112_2 and 112_3, the processing when forming the conductive layers 112_2 and 112_3 in the same process becomes easier, and the manufacturing yield of the semiconductor device can be increased.

As shown in FIG. 6B, the end of conductive layer 112_3 can be aligned or approximately aligned with the end of conductive layer 112_1. For example, a first film that will become conductive layer 112_3 is formed, a second film that will become conductive layer 112_1 is formed on the first film, and the first film and second film are processed to form conductive layer 112_3 and conductive layer 112_1. Then, conductive layer 112 can be formed by forming conductive layer 112_2 on conductive layer 112_3 and conductive layer 112_1. By processing the first film and the second film in the same process, manufacturing costs can be reduced.

The conductive layer 212a_3 can be formed in the same process as the conductive layer 112_3. For the conductive layer 212a_3, the description of the conductive layer 112_3 can be referred to.

Here, an example is shown in which the conductive layer 112 and the conductive layer 212a each have a stacked structure of two or three layers, but one embodiment of the present invention is not limited to this. The conductive layer 112 and the conductive layer 212a can also have a stacked structure of four or more layers.

The configurations of the conductive layer 112 and the conductive layer 212a shown in Figures 5A to 6B can also be applied to other configuration examples.

[Insulating layer 106]
The insulating layer 106 preferably includes one or more inorganic insulating layers. The insulating layer 106 can be made of any of the materials that can be used for the insulating layer 110.

The insulating layer 106 is provided over the layer 108, the layer 208, the conductive layer 212b, and the insulating layer 110. When a metal oxide is used for the layer 108 and the layer 208, it is preferable to use any of the above-mentioned oxides and oxynitrides for at least the films constituting the insulating layer 106 that are in contact with the layer 108 and the layer 208. When the insulating layer 106 has a single-layer structure, silicon oxide, silicon oxynitride, or aluminum oxide can be preferably used for the insulating layer 106.

In a miniaturized transistor, if the thickness of the gate insulating layer becomes thin, the leakage current may become large. By using a material with a high relative dielectric constant (also called a high-k material) for the gate insulating layer, it is possible to reduce the voltage during transistor operation while maintaining the physical film thickness. Examples of high-k materials that can be used for the insulating layer 106 include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

In FIG. 1B and other figures, the insulating layer 106 is shown as having a single-layer structure, but one embodiment of the present invention is not limited to this. The insulating layer 106 can have a stacked structure of two or more layers.

A cross-sectional view of a semiconductor device 10B according to one embodiment of the present invention is shown in FIG. 7. For a top view of the semiconductor device 10B, refer to FIG. 1A. FIG. 7 is a cross-sectional view of a cut surface taken along dashed line A1-A2 shown in FIG. 1A.

The semiconductor device 10B has a transistor 100B, a transistor 200B, and an insulating layer 110. The transistors 100B and 200B differ mainly from the transistors 100 and 200 shown in FIG. 1B and the like in that the insulating layer 106 has a stacked structure. FIG. 7 shows a configuration in which the insulating layer 106 has a two-layer structure of an insulating layer 106a and an insulating layer 106b on the insulating layer 106a.

When the insulating layer 106 has a stacked structure, the insulating layer on the side of the layers 108 and 208 (here, the insulating layer 106a) preferably has an oxide or an oxynitride. For example, the insulating layer 106a can be preferably made of one or more of silicon oxide, silicon oxynitride, and aluminum oxide.

It is preferable to provide a layer functioning as a barrier film in one or more of the layers constituting the insulating layer 106. This can suppress the diffusion of metal components contained in the conductive layer 104 and the conductive layer 204 and impurities (e.g., water and hydrogen) contained in the layers formed on the transistor 100B and the transistor 200B to the layer 108 and the layer 208 through the insulating layer 106. Furthermore, it can suppress the diffusion of oxygen contained in the layer 108 and the layer 208 to the conductive layer 104 and the conductive layer 204 through the insulating layer 106. This can suppress the increase in oxygen vacancy (V _O ) and V _O H in the layer 108 and the layer 208. In addition, it can suppress the conductive layer 104 and the conductive layer 204 from being oxidized by the oxygen contained in the layer 108 and the layer 208, and the increase in the electrical resistance of the conductive layer 104 and the conductive layer 204. As a result, a transistor having good electrical characteristics and high reliability can be obtained. It is preferable to use one or more of the above-mentioned nitrides and nitride oxides for the layer functioning as a barrier film. Alternatively, one or more of an oxide and an oxynitride can be used for the layer. For example, aluminum oxide can be preferably used.

For example, silicon oxynitride can be used for the insulating layer 106a, and silicon nitride can be used for the insulating layer 106b. Alternatively, silicon oxynitride can be used for the insulating layer 106a, and aluminum oxide can be used for the insulating layer 106b. Alternatively, aluminum oxide can be used for the insulating layer 106a, and silicon oxynitride can be used for the insulating layer 106b. Alternatively, aluminum oxide can be used for the insulating layer 106a, and silicon nitride can be used for the insulating layer 106b.

Here, an example is shown in which the insulating layer 106 has a two-layer stacked structure, but one embodiment of the present invention is not limited to this. The insulating layer 106 can also have a three or more layer stacked structure.

The configuration of the insulating layer 106 shown in FIG. 7 can also be applied to other configuration examples.

[Insulating layer 195]
The insulating layer 195, which functions as a protective layer for the transistors 100 and 200, is preferably made of a material through which impurities do not easily diffuse. By providing the insulating layer 195, diffusion of impurities from the outside into the transistors can be effectively suppressed, thereby improving the reliability of the semiconductor device. Examples of impurities include water and hydrogen.

The insulating layer 195 can be an insulating layer having an inorganic material or an insulating layer having an organic material. For example, an inorganic material such as oxide, oxynitride, nitride oxide, or nitride can be suitably used for the insulating layer 195. More specifically, one or more of silicon nitride, silicon nitride oxide, silicon oxynitride, aluminum oxide, aluminum oxynitride, aluminum nitride, hafnium oxide, and hafnium aluminate can be used. For example, one or more of acrylic resin and polyimide resin can be used as the organic material. A photosensitive material can be used as the organic material. Two or more of the above insulating films can also be stacked. The insulating layer 195 can have a stacked structure of an insulating layer having an inorganic material and an insulating layer having an organic material.

[Substrate 102]
There is no significant limitation on the material of the substrate 102, but it is necessary that the substrate 102 has at least a heat resistance sufficient to withstand subsequent heat treatment. For example, a single crystal semiconductor substrate made of silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate such as silicon germanium, an SOI substrate, a glass substrate, a quartz substrate, a sapphire substrate, a ceramic substrate, or a resin substrate can be used as the substrate 102. A substrate provided with a semiconductor element can be used as the substrate 102. A substrate having an insulating film formed on its surface can be used as the substrate 102. The shapes of the semiconductor substrate and the insulating substrate are not particularly limited, and may be circular or rectangular.

A flexible substrate can be used as the substrate 102, and the transistor 100 and the like can be formed directly on the flexible substrate. Alternatively, a peeling layer can be provided between the substrate 102 and the transistor 100 and the like. By providing a peeling layer, after a semiconductor device is partially or entirely completed on the substrate, it can be separated from the substrate 102 and transferred to another substrate. In this case, the transistor 100 and the like can also be transferred to a substrate with low heat resistance or a flexible substrate.

Below, we will explain a configuration example of a semiconductor device that has some configurations that differ from the above-mentioned configuration example. Note that below, explanations of parts that overlap with the above-mentioned configuration example may be omitted. Also, in the drawings shown below, parts that have the same functions as the above-mentioned configuration example may be marked with the same hatching pattern and may not be assigned reference numerals.

[Configuration Example 1-2]
8A is a cross-sectional view of a semiconductor device 10C according to one embodiment of the present invention. For a top view of the semiconductor device 10C, refer to FIG 1A. FIG 8A is a cross-sectional view of a cut surface taken along dashed line A1-A2 in FIG 1A.

The semiconductor device 10C has a transistor 100C, a transistor 200C, and an insulating layer 110. The semiconductor device 10C differs from the semiconductor device 10 shown in FIG. 1B etc. mainly in that the insulating layer 110 has insulating layers 110d and 110e.

FIG. 8B shows an enlarged view of the transistor 100C shown in FIG. 8A, and FIG. 8C shows an enlarged view of the transistor 200C. The insulating layer 110 has an insulating layer 110d, an insulating layer 110a on the insulating layer 110d, an insulating layer 110b on the insulating layer 110a, an insulating layer 110c on the insulating layer 110b, and an insulating layer 110e on the insulating layer 110c. The insulating layer 110d and the insulating layer 110e can be made of the same material as the insulating layer 110a and the insulating layer 110c, respectively. The insulating layer 110d and the insulating layer 110e can be made of, for example, silicon nitride or silicon oxynitride, respectively. The insulating layer 110d and the insulating layer 110e can be made of the same material. Alternatively, different materials can be used for these.

The insulating layer 110d is provided between the conductive layer 112 and the conductive layer 212a and the insulating layer 110a. The insulating layer 110d is provided so as to cover the conductive layer 112 and the conductive layer 212a. The insulating layer 110d has an area in contact with the upper surface and side surface of the conductive layer 112, the upper surface and side surface of the conductive layer 212a, the upper surface of the substrate 102, the side surface of the layer 108, and the side surface of the layer 208.

Insulating layer 110e is provided between layer 108 and conductive layer 212b and insulating layer 110c. Insulating layer 110e has an area in contact with the upper surface of insulating layer 110c, the lower surface of conductive layer 212b, the lower surface of insulating layer 106, the side and lower surface of layer 108, and the side of layer 208.

The insulating layer 110d and the insulating layer 110e are preferably made of a material that emits impurities that increase the conductivity (or decrease the electrical resistance) of the layer 108 and the layer 208, respectively. When a metal oxide is used for the layer 108 and the layer 208, the element contained in the impurity (hereinafter also referred to as the second element) can be one or more of hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, arsenic, aluminum, magnesium, silicon, and noble gas. Representative examples of noble gases include helium, neon, argon, krypton, and xenon. The second element is more preferably one or more of hydrogen, boron, phosphorus, aluminum, magnesium, and silicon, and hydrogen is particularly preferable. The second element can be different from the first element. Alternatively, the second element can be the same as the first element.

When a metal oxide is used for the layer 108 and the layer 208, it is more preferable that the impurities released by the insulating layer 110d and the insulating layer 110e include hydrogen. Hydrogen reacts with oxygen that is bonded to the metal atom of the metal oxide to become water, and oxygen vacancies (V _O ) are formed. Furthermore, defects (V _O H) in which hydrogen has entered the oxygen vacancies (V _O ) function as donors, and electrons, which are carriers, are generated. As a result, the carrier concentration in the region of the layer 108 in contact with the insulating layer 110d, the region of the layer 108 in contact with the insulating layer 110e, the region of the layer 208 in contact with the insulating layer 110d, and the region of the layer 208 in contact with the insulating layer 110e, is increased, and the electrical resistance of these regions can be reduced. Note that in this specification and the like, hydrogen may be used as an example to explain the second element.

The insulating layer 110d and the insulating layer 110e each have a second element. In addition, the insulating layer 110d and the insulating layer 110e each preferably contain nitrogen, and it is preferable to use one or more of the above-mentioned nitrides and nitride oxides. In other words, the insulating layer 110d and the insulating layer 110e each preferably have nitrogen and a second element. When hydrogen is used as the second element, the insulating layer 110d and the insulating layer 110e each preferably have silicon, nitrogen, and hydrogen. For example, the insulating layer 110d and the insulating layer 110e can each preferably use silicon nitride containing hydrogen or silicon nitride oxide containing hydrogen.

The impurities emitted from the insulating layer 110e can further reduce the electrical resistance of the region 108Db in contact with the top surface of the insulating layer 110e, and can also make the region of the layer 108 in contact with the side of the insulating layer 110e and the region of the layer 208 in contact with the insulating layer 110e into low-resistance regions. Similarly, the impurities emitted from the insulating layer 110d can also make the region of the layer 108 in contact with the insulating layer 110d and the region of the layer 208 in contact with the insulating layer 110d into low-resistance regions. The layer 108 can be configured to have low-resistance regions between the region in contact with the conductive layer 112 (one of the source region and drain region of the transistor 100C) and the channel formation region, and between the region 108Db (the other of the source electrode and drain electrode) and the channel formation region. Similarly, the layer 208 can have low resistance regions between the region in contact with the conductive layer 212a (one of the source region and drain region of the transistor 200C) and the channel formation region, and between the region in contact with the conductive layer 212b (the other of the source region and drain region) and the channel formation region. These low resistance regions can function as buffer regions for relaxing the drain electric field. Note that these low resistance regions may function as source or drain regions.

By providing a low resistance region between the drain and the channel formation region, a high electric field is unlikely to occur near the drain, the generation of hot carriers is suppressed, and the deterioration of the transistor can be suppressed. For example, in the transistor 100C, when the conductive layer 112 functions as a drain electrode and the region 108Db functions as a source electrode, by making the region of the layer 108 in contact with the insulating layer 110d into a low resistance region, a high electric field is unlikely to occur near the drain, the generation of hot carriers is suppressed, and the deterioration of the transistor can be suppressed. Similarly, in the transistor 200C, when the conductive layer 212b functions as a drain electrode and the conductive layer 212a functions as a source electrode, by making the region of the layer 208 in contact with the insulating layer 110e into a low resistance region, a high electric field is unlikely to occur near the drain, the generation of hot carriers is suppressed, and the deterioration of the transistor can be suppressed.

When the region of layer 108 in contact with insulating layer 110d functions as the source region or drain region of transistor 100C, the distance from the source region of layer 108 to the gate electrode, or the distance from the drain region to the gate electrode, can be made more uniform. This makes it possible to make the electric field of the gate electrode applied to the channel formation region in transistor 100C more uniform. The same applies to transistor 200C and layer 208.

It is more preferable to use a material that releases impurities that lower the electrical resistance of the conductive layers 112 and 212a for the insulating layer 110d. Similarly, it is more preferable to use a material that releases impurities that lower the electrical resistance of the conductive layer 212b for the insulating layer 110e. For example, when a metal oxide is used for the conductive layers 112, 212a, and 212b, the electrical resistance of the conductive layers 112, 212a, and 212b can be lowered by using a material that releases impurities containing a second element (e.g., hydrogen) for the insulating layers 110d and 110e. In addition, the conductive layers 112 and 212a can function as wirings, and a semiconductor device with low wiring resistance can be obtained. Note that the impurities that lower the electrical resistance of the conductive layers 112 and 212a may be the same as or different from the impurities that lower the electrical resistance of the layers 108 and 208.

The insulating layer 110d and the insulating layer 110e can be formed using a gas containing an impurity. When hydrogen is used as the impurity, the insulating layer 110d and the insulating layer 110e can be formed using a gas containing a hydrogen element. Examples of the gas containing a hydrogen element include silane (SiH ₄ ), disilane (Si ₂ H ₆ ), trisilane (Si ₃ H ₈ ), tetraethoxysilane (TEOS, Si(OC ₂ H ₅ ) ₄ ), hydrogen (H ₂ ), and ammonia (NH ₃ ). When a silicon nitride film is formed as the insulating layer 110d and the insulating layer 110e by using a PECVD method, silane (SiH ₄ ), nitrogen (N ₂ ), and ammonia (NH ₃ ) can be used as a deposition gas. At this time, the amount of hydrogen released from the insulating layers 110d and 110e can be adjusted by changing the ratio of the flow rate of the ammonia gas to the entire film formation gas (hereinafter also referred to as the ammonia flow rate ratio). For example, by increasing the ammonia flow rate ratio, the amount of hydrogen contained in the insulating layers 110d and 110e can be increased, and the amount of hydrogen released by heat applied to the insulating layers 110d and 110e can be increased.

Here, impurities released from the insulating layer 110d and the insulating layer 110e may diffuse into the region 108M and the region 208M through the region of the layer 108 and the layer 208 that contacts the insulating layer 110d and the insulating layer 110e. When the impurity is hydrogen, hydrogen released from the insulating layer 110d and the insulating layer 110e may diffuse into the region 108M and the region 208M. However, since oxygen vacancies (V _O ) are reduced in the region 108M and the region 208M by supplying oxygen from the insulating layer 110b, an increase in V _O H in the region 108M is suppressed even if hydrogen diffuses into the region 108M. In addition, even if oxygen vacancies (V _O ) and V _O H are generated in the region 108M and the region 208M by the hydrogen diffused into these regions, the oxygen vacancies (V _O ) and V _O H are reduced by the oxygen supplied from the insulating layer 110b. Therefore, at least the regions 108M and 208M in the layers 108 and 208 function as channel formation regions, and can provide the transistors 100 and 200 with good electrical characteristics and high reliability. Note that the diffusion coefficient of oxygen in the layers 108 and 208 is smaller than the diffusion coefficient of hydrogen, and therefore the electrical resistance of the regions 108Da, 108Db, 208Da, and 208Db is unlikely to increase due to oxygen released from the insulating layer 110b. Therefore, the electrical resistance of these regions can be kept low.

The insulating layer 110d preferably includes a portion in which the concentration of the second element is 1×10 ²¹ atoms/cm ³ or more and 1×10 ²³ atoms/cm ³ or less, preferably 1×10 ²¹ atoms/cm ³ or more and 5×10 ²² atoms/cm ³ or less, and more preferably 5×10 ²¹ atoms/cm ³ or more and 5×10 ²² atoms/cm ³ or less. The same applies to the insulating layer 110e.

Note that the concentration of the impurity element may vary in the thickness direction of the layer (also referred to as having a concentration gradient). When analyzing the concentration of the impurity element in the thickness direction of the layer, it is preferable that the maximum concentration in the layer is in the above-mentioned range.

If the concentrations of impurity elements in the insulating layers 110d and 110e are high, the amount of impurities diffusing from the insulating layers 110d and 110e to the regions 108M and 208M may be too large. By setting the concentrations of impurity elements in the insulating layers 110d and 110e within the above-mentioned ranges, an increase in oxygen vacancies ( _VO ) and _VOH in the regions 108M and 208M can be suppressed.

The regions of layer 108 and layer 208 in contact with insulating layer 110d contain elements (impurity elements) contained in the impurities released from insulating layer 110d. Similarly, the regions of layer 108 and layer 208 in contact with insulating layer 110e contain elements (impurity elements) contained in the impurities released from insulating layer 110e. Furthermore, the region of layer 108 in contact with insulating layer 110d and the region of layer 110e each preferably have a portion with a higher concentration of impurity elements than the region 108M that functions as a channel formation region. The region of layer 208 in contact with insulating layer 110d and the region of layer 208 in contact with insulating layer 110e each preferably have a portion with a higher concentration of impurity elements than the region 208M that functions as a channel formation region.

When insulating layers 110d and 110e release impurities containing hydrogen elements (e.g., hydrogen and water), the regions of layers 108 and 208 in contact with insulating layer 110d and in contact with insulating layer 110e contain hydrogen. Furthermore, it is preferable that the regions of layer 108 in contact with insulating layer 110d and in contact with insulating layer 110e each have a portion with a higher hydrogen concentration than region 108M. It is preferable that the regions of layer 208 in contact with insulating layer 110d and in contact with insulating layer 110e each have a portion with a higher hydrogen concentration than region 208M.

For an analysis of the concentration of the second element in layers 108, 208, and insulating layer 110, the description of the analysis of the first element described above can be referred to.

It is preferable to provide insulating layer 110a between insulating layer 110d and insulating layer 110b, and insulating layer 110c between insulating layer 110e and insulating layer 110b. By providing insulating layer 110a and insulating layer 110c that function as barrier films, it is possible to suppress the diffusion of impurities released from insulating layer 110d through insulating layer 110a and insulating layer 110b, or the diffusion of impurities released from insulating layer 110e through insulating layer 110c and insulating layer 110b into the channel formation regions of layers 108 and 208. This allows the transistors 100 and 200 to have good electrical characteristics and high reliability.

It is preferable that insulating layer 110d has a region having a higher concentration of the second element than insulating layer 110a. For example, it is preferable that insulating layer 110d has a region having a higher concentration of hydrogen than insulating layer 110a.

The amount of hydrogen released can be adjusted by making the film formation conditions different between insulating layer 110d and insulating layer 110a. Specifically, one or more of the film formation power (film formation power density), film formation pressure, film formation gas type, film formation gas flow rate ratio, film formation temperature, and distance between the substrate and the electrode can be made different between insulating layer 110d and insulating layer 110a. For example, by making the film formation power density of insulating layer 110d smaller than the film formation power density of insulating layer 110a, the hydrogen content in insulating layer 110d can be made larger than the hydrogen content in insulating layer 110a. This makes it possible to increase the amount of hydrogen released from insulating layer 110d itself due to heat applied to it.

The hydrogen content in the deposition gas used to form the insulating layer 110d is preferably higher than the hydrogen content in the deposition gas used to form the insulating layer 110a. Specifically, when a silicon nitride film or a silicon nitride oxide film is formed by using a PECVD method as the insulating layer 110d and the insulating layer 110a, respectively, the ratio of the flow rate of ammonia gas to the total deposition gas used to form the insulating layer 110d (hereinafter also referred to as the ammonia flow rate ratio) is preferably higher than the ammonia flow rate ratio of the deposition gas used to form the insulating layer 110a. By forming the insulating layer 110d under conditions where the ammonia flow rate ratio is high, the hydrogen content in the insulating layer 110d can be increased. In addition, the amount of hydrogen released from the insulating layer 110d due to heat applied to the insulating layer 110d can be increased. For example, the insulating layer 110d can be formed using ammonia gas, and the insulating layer 110a can be formed without using ammonia gas (the flow rate of ammonia gas can be said to be zero). In this case, the ammonia flow ratio of the deposition gas used to form the insulating layer 110a can be said to be zero, and the ammonia flow ratio of the deposition gas used to form the insulating layer 110d can be said to be higher than the ammonia flow ratio of the deposition gas used to form the insulating layer 110a.

It is more preferable that the film density of the insulating layer 110a is higher than that of the insulating layer 110d. This can prevent hydrogen contained in the insulating layer 110d from diffusing into the channel formation region of the layer 108 through the insulating layers 110a and 110b. The film density can be evaluated, for example, by Rutherford Backscattering Spectrometry (RBS) or X-ray Reflectivity (XRR). The difference in film density can sometimes be evaluated by a transmission electron microscope (TEM) image of the cross section. In TEM observation, if the film density is high, the transmission electron (TE) image is dense (dark), and if the film density is low, the transmission electron (TE) image is faint (bright). Therefore, in a transmission electron (TE) image, insulating layer 110a may appear darker than insulating layer 110d. Even if the same material is used for insulating layers 110d and 110a, the film densities are different, so the boundary between them may be observed as a difference in contrast in a cross-sectional TEM image.

It is preferable that insulating layer 110e has an area with a higher hydrogen content than insulating layer 110c. It is more preferable that insulating layer 110c has a higher film density than insulating layer 110e. For insulating layer 110c and insulating layer 110e, the description of insulating layer 110a and insulating layer 110d can be referred to.

Although the insulating layer 110 is shown here as having a five-layer stacked structure, one embodiment of the present invention is not limited to this. The insulating layer 110 can have a two-layer, three-layer, four-layer, or six or more-layer stacked structure. Alternatively, the insulating layer 110 can have a single-layer structure.

The configuration of the insulating layer 110 shown in configuration example 1-2 can also be applied to other configuration examples.

[Configuration Example 1-3]
9A is a cross-sectional view of a semiconductor device 10D according to one embodiment of the present invention. For a top view of the semiconductor device 10D, refer to FIG. 1A. FIG. 9A is a cross-sectional view of a cut surface taken along dashed line A1-A2 in FIG. 1A.

The semiconductor device 10D has a transistor 100D, a transistor 200D, an insulating layer 110, and an insulating layer 109. The semiconductor device 10D differs from the semiconductor device 10 shown in FIG. 1B etc. mainly in that the semiconductor device 10D has an insulating layer 109 and that the insulating layer 110 has an insulating layer 110e.

9B shows an enlarged view of the transistor 100D shown in FIG. 9A, and FIG. 9C shows an enlarged view of the transistor 200D. The insulating layer 109 is provided between the conductive layer 112 and the conductive layer 212a and the substrate 102. The insulating layer 109 is provided on the substrate 102, the conductive layer 112 and the conductive layer 212a are provided on the insulating layer 109, and the insulating layer 110 is provided on the conductive layer 112, the conductive layer 212a, and the insulating layer 109. The insulating layer 109 has a region in contact with the lower surface of the conductive layer 112, the lower surface of the conductive layer 212a, the lower surface of the insulating layer 110, and the upper surface of the substrate 102. The conductive layer 112 has a region in contact with the insulating layer 109 and the insulating layer 110 and sandwiched therebetween. The conductive layer 212a has a region in contact with the insulating layer 109 and the insulating layer 110 and sandwiched therebetween. For information about insulating layer 110e, please refer to the above description.

The insulating layer 109 is preferably made of a material that emits impurities that reduce the electrical resistance of the layers 108 and 208. The impurity preferably contains a second element. The insulating layer 109 can be made of a material that can be used for the insulating layers 110d and 110e. For example, the insulating layer 109 can be made of silicon nitride or silicon nitride oxide. For the insulating layer 109, the description of the insulating layers 110d and 110e can be referred to.

The impurities released from the insulating layer 109 diffuse into the region of the conductive layer 112 in contact with the insulating layer 109 and into the region of the conductive layer 212a in contact with the insulating layer 109. The impurities diffused into the conductive layer 112 diffuse into the region of the layer 108 in contact with the conductive layer 112, and the impurities diffused into the conductive layer 212a diffuse into the region of the layer 208 in contact with the conductive layer 212a. This makes it possible to lower the electrical resistance of the region of the layer 108 in contact with the conductive layer 112, that is, one of the source region and drain region of the transistor 100. Similarly, it is possible to lower the electrical resistance of the region of the layer 208 in contact with the conductive layer 212a, that is, one of the source region and drain region of the transistor 200. Therefore, the transistors 100D and 200D can have a large on-current, and can be semiconductor devices that operate at high speed.

When a metal oxide is used for the layers 108 and 208, it is more preferable that the impurities released by the insulating layer 109 include hydrogen elements. Examples of such impurities include hydrogen and water. Hydrogen diffused from the insulating layer 109 to the layer 108 through the conductive layer 112 increases the carrier concentration in the region of the layer 108 that contacts the conductive layer 112, and the electrical resistance of one of the source and drain regions of the transistor 100 can be reduced. Similarly, hydrogen diffused from the insulating layer 109 to the layer 208 through the conductive layer 212a increases the carrier concentration in the region of the layer 208 that contacts the conductive layer 212a, and the electrical resistance of one of the source and drain regions of the transistor 200 can be reduced.

The insulating layer 109 is preferably made of a material that releases impurities that reduce the electrical resistance of the conductive layer 112 and the conductive layer 212a. This can reduce the electrical resistance of the conductive layer 112 and the conductive layer 212a. For example, when a metal oxide is used for the conductive layer 112 and the conductive layer 212a, the impurity preferably contains hydrogen. This can increase the carrier concentration of the conductive layer 112 and the conductive layer 212a and reduce the electrical resistance. The conductive layer 112 and the conductive layer 212a can function as wirings, and a semiconductor device with low wiring resistance can be obtained. Note that the impurities that reduce the electrical resistance of the conductive layer 112 and the conductive layer 212a may be the same as or different from the impurities that reduce the electrical resistance of the layer 108 and the layer 208.

The materials that can be used for the conductive layer 112 and the conductive layer 212a are as described above. Note that it is more preferable that the conductive layer 112 and the conductive layer 212a are easily permeable to impurities. It is more preferable that the conductive layer 112 and the conductive layer 212a are less likely to adsorb impurities.

Insulating layer 110a has regions that contact the top surface of insulating layer 109, the top and side surfaces of conductive layer 112, and the top and side surfaces of conductive layer 212a. This makes it possible to prevent impurities contained in insulating layer 109, conductive layer 112, and conductive layer 212a from diffusing into the channel formation regions of layers 108 and 208 via insulating layer 110a and insulating layer 110b.

The insulating layer 109 preferably has a region having a higher concentration of impurity elements than the insulating layer 110a. For example, the insulating layer 109 preferably has a region having a higher concentration of hydrogen than the insulating layer 110a. The film density of the insulating layer 110a is preferably higher than the film density of the insulating layer 109. For the insulating layer 109 and the insulating layer 110a, the description of the insulating layer 110d and the insulating layer 110c can be referred to.

Note that impurities released from the insulating layer 109 may diffuse into the channel formation region of the layer 108 through the conductive layer 112 and one of the source region and drain region of the layer 108. Similarly, impurities released from the insulating layer 109 may diffuse into the channel formation region of the layer 208 through the conductive layer 212a and one of the source region and drain region of the layer 208. For example, when the impurity is hydrogen, hydrogen released from the insulating layer 109 may diffuse into the channel formation regions of the layer 108 and the layer 208. However, oxygen is supplied from the insulating layer 110b to at least the regions of the layer 108 and the layer 208 in contact with the insulating layer 110b, so that oxygen vacancies (V _O ) and V _O H in these channel formation regions can be reduced. As a result, a shift in the threshold voltage is suppressed, and the transistor 100 and the transistor 200 can have both a small cutoff current and a large on-current. Therefore, a semiconductor device that has both low power consumption and high performance can be obtained.

9A and other figures show a four-layer structure of insulating layer 110 consisting of insulating layer 110a, insulating layer 110b, insulating layer 110c, and insulating layer 110e, but one embodiment of the present invention is not limited to this. For example, insulating layer 110 can have a three-layer structure consisting of insulating layer 110a, insulating layer 110b, and insulating layer 110c. Alternatively, insulating layer 110 can have a five-layer structure consisting of insulating layer 110a, insulating layer 110b, insulating layer 110c, insulating layer 110d, and insulating layer 110e.

The configuration of the insulating layer 109 shown in configuration example 1-3 can also be applied to other configuration examples.

[Configuration Example 1-4]
10A is a cross-sectional view of a semiconductor device 10E according to one embodiment of the present invention. For a top view of the semiconductor device 10E, refer to FIG 1A. FIG 10A is a cross-sectional view of a cut surface taken along dashed line A1-A2 in FIG 1A.

The semiconductor device 10E includes a transistor 100E, a transistor 200E, and an insulating layer 110. The semiconductor device 10E differs from the semiconductor device 10 shown in FIG. 1B etc. mainly in that the layer 108 and the layer 208 each have a stacked structure.

An enlarged view of transistor 100E shown in FIG. 10A is shown in FIG. 10B, and an enlarged view of transistor 200E is shown in FIG. 10C. FIGS. 10A to 10C show a configuration in which layer 108 has a three-layer structure of layer 108a, layer 108b on layer 108a, and layer 108c on layer 108b, and layer 208 has a three-layer structure of layer 208a, layer 208b on layer 208a, and layer 208c on layer 208b.

Layer 108a, layer 108b, layer 108c, layer 208a, layer 208b, and layer 208c can be made of the materials listed for layer 108 and layer 208, respectively. Layer 108a, layer 108b, layer 108c, layer 208a, layer 208b, and layer 208c each preferably contain a metal oxide that exhibits semiconductor properties. In addition, layer 108a can be made of the same material as layer 208a, layer 108b can be made of the same material as layer 208b, and layer 108c can be made of the same material as layer 208c.

For example, layers 108a and 208a can be formed in the same process. Layers 108b and 208b can be formed in the same process. Layers 108c and 208c can be formed in the same process. Layers 108 and 208 can be formed by forming a first film that will become layers 108a and 208a, forming a second film that will become layers 108b and 208b, forming a third film that will become layers 108c and 208c, and processing the first film, second film, and third film to form layers 108 and 208. Alternatively, the layers included in layer 108 can be formed in a process different from the layers included in layer 208.

The band gap of the first metal oxide in layers 108a and 208a, the second metal oxide in layers 108b and 208b, and the third metal oxide in layers 108c and 208c is preferably 2.0 eV or more, and more preferably 2.5 eV or more.

The band gap of the first metal oxide is preferably larger than the band gap of the second metal oxide. The band gap of the third metal oxide is preferably larger than the band gap of the second metal oxide. Layer 108b can be sandwiched between layers 108a and 108c, which have larger band gaps than layer 108b, to form a buried channel. This makes layer 108b the main current path in layer 108. Similarly, layer 208b is sandwiched between layers 208a and 208c to form a buried channel. This makes layer 208b the main current path in layer 208.

In the following, layer 108 having layers 108a, 108b, and 108c will be described as an example, and a description of layer 208 may be omitted. With regard to layer 208, the description of layers 108a, 108b, and 108c may be read as layers 208a, 208b, and 208c.

The difference between the band gap of the first metal oxide and the band gap of the second metal oxide is preferably 0.1 eV or more, more preferably 0.2 eV or more, more preferably 0.3 eV or more, and even more preferably 0.5 eV or more. The difference between the band gap of the third metal oxide and the band gap of the second metal oxide is preferably 0.1 eV or more, more preferably 0.2 eV or more, more preferably 0.3 eV or more, and even more preferably 0.5 eV or more.

The conduction band lower edge of the first metal oxide is preferably closer to the vacuum level than the conduction band lower edge of the second metal oxide. The conduction band lower edge of the third metal oxide is preferably closer to the vacuum level than the conduction band lower edge of the second metal oxide. In other words, the electron affinity of the first metal oxide is preferably smaller than the electron affinity of the second metal oxide. The electron affinity of the third metal oxide is preferably smaller than the electron affinity of the second metal oxide.

The band gaps of the first metal oxide, the second metal oxide, and the third metal oxide can be evaluated by optical evaluation using a spectrophotometer, spectroscopic ellipsometry, photoluminescence, X-ray photoelectron spectroscopy (XPS or ESCA), or X-ray absorption fine structure (XAFS). Alternatively, the analysis can be performed by combining a plurality of these techniques. The electron affinity or the bottom of the conduction band can be determined from the ionization potential, which is the energy difference between the vacuum level and the top of the valence band, and the band gap. The ionization potential can be evaluated by, for example, ultraviolet photoelectron spectroscopy (UPS).

Trap levels due to impurities or defects may be formed at the interface between insulating layer 110 and layer 108 and in the vicinity thereof. Such impurities include residual components of the etchant or etching gas used when forming opening 141, and components of conductive layer 112 that adhere to the side surface of insulating layer 110 when forming opening 141. By providing layer 108a between layer 108b and insulating layer 110, it is possible to distance layer 108b from the trap levels.

The interface between insulating layer 106 and layer 108 and its vicinity may be damaged during the formation of insulating layer 106. This may result in the formation of trap levels at the interface between insulating layer 106 and layer 108 and its vicinity. By providing layer 108c between layer 108b and insulating layer 106, it is possible to distance layer 108b from the trap levels.

By sandwiching layer 108b, which is the main current path of layer 108, between layers 108a and 108c, it is possible to reduce the trap levels at the interface and in the vicinity of the interface of layer 108b. This makes it possible to obtain a transistor with a large on-current and high reliability. Therefore, it is possible to obtain a semiconductor device that achieves both high speed operation and high reliability.

The composition of the first metal oxide is preferably different from that of the second metal oxide. The composition of the third metal oxide is preferably different from that of the second metal oxide. By varying the composition of the metal oxides, the band gap can be adjusted. Specifically, the content of element M in the first metal oxide and the content of element M in the third metal oxide are preferably higher than the content of element M in the second metal oxide. This allows the band gap of the first metal oxide and the band gap of the third metal oxide to be larger than the band gap of the second metal oxide.

The indium content in the second metal oxide is preferably higher than the indium content in the first metal oxide and the indium content in the third metal oxide. This allows a transistor with a large on-state current to be obtained.

For example, when the first metal oxide and the second metal oxide are In-M-Zn oxides, the first metal oxide can have a composition of In:M:Zn = 1:1:1 [atomic ratio] or a composition thereabout, and the second metal oxide can have a composition of In:M:Zn = 40:1:10 [atomic ratio] or a composition thereabout. Alternatively, the first metal oxide can have a composition of In:M:Zn = 1:1:1 [atomic ratio] or a composition thereabout, and the second metal oxide can have a composition of In:M:Zn = 10:1:10 [atomic ratio] or a composition thereabout. Alternatively, the first metal oxide can have a composition of In:M:Zn = 1:1:1 [atomic ratio] or a composition thereabout, and the second metal oxide can have a composition of In:M:Zn = 10:1:40 [atomic ratio] or a composition thereabout. It is particularly preferable to use one or more of gallium, aluminum, and tin as the element M. The element M in the first metal oxide, the element M in the second metal oxide, and the element M in the third metal oxide can have the same structure. Alternatively, some or all of these elements can be different. In addition, when one or more of the first metal oxide, the second metal oxide, and the third metal oxide have multiple elements M, each element of the element M may be the same as the element M in the other metal oxide, or some or all of them may be different.

More specifically, the first metal oxide may preferably have a composition of In:Ga:Zn=1:1:1 [atomic ratio] or a composition close thereto, the second metal oxide may preferably have a composition of In:Sn:Zn=40:1:10 [atomic ratio] or a composition close thereto, and the third metal oxide may preferably have a composition of In:Ga:Zn=1:1:1 [atomic ratio] or a composition close thereto. Alternatively, the first metal oxide may preferably have a composition of In:Ga:Zn=1:1:1 [atomic ratio] or a composition close thereto, the second metal oxide may preferably have a composition of In:Sn:Zn=10:1:10 [atomic ratio] or a composition close thereto, and the third metal oxide may preferably have a composition of In:Ga:Zn=1:1:1 [atomic ratio] or a composition close thereto. Alternatively, the first metal oxide can preferably have a composition of In:Ga:Zn = 1:1:1 [atomic ratio] or a composition close thereto, the second metal oxide can preferably have a composition of In:Sn:Zn = 10:1:40 [atomic ratio] or a composition close thereto, and the third metal oxide can preferably have a composition of In:Ga:Zn = 1:1:1 [atomic ratio] or a composition close thereto.

The second metal oxide may be configured not to include element M. For example, the second metal oxide may be In-Zn oxide, and the first metal oxide and the third metal oxide may be In-M-Zn oxide. Specifically, the second metal oxide may be In-Zn oxide, and the first metal oxide and the third metal oxide may be In-M-Zn oxide. More specifically, the first metal oxide may preferably have a composition of In:Ga:Zn=1:1:1 [atomic ratio] or thereabout, the second metal oxide may preferably have a composition of In:Zn=4:1 [atomic ratio] or thereabout, and the third metal oxide may preferably have a composition of In:Ga:Zn=1:1:1 [atomic ratio] or thereabout. Alternatively, the first metal oxide may preferably have a composition of In:Ga:Zn = 1:1:1 [atomic ratio] or a composition in the vicinity thereof, the second metal oxide may preferably have a composition of In:Zn = 1:1 [atomic ratio] or a composition in the vicinity thereof, and the third metal oxide may preferably have a composition of In:Ga:Zn = 1:1:1 [atomic ratio] or a composition in the vicinity thereof. Alternatively, the first metal oxide may preferably have a composition of In:Ga:Zn = 1:1:1 [atomic ratio] or a composition in the vicinity thereof, the second metal oxide may preferably have a composition of In:Zn = 1:4 [atomic ratio] or a composition in the vicinity thereof, and the third metal oxide may preferably have a composition of In:Ga:Zn = 1:1:1 [atomic ratio] or a composition in the vicinity thereof.

11A shows an enlarged view of the side of layer 108 and insulating layer 110 and their vicinity, and FIG. 11B shows an enlarged view of the side of layer 208 and insulating layer 110 and their vicinity. In FIG. 11A, the thickness T108a of layer 108a, the thickness T108b of layer 108b, and the thickness T108c of layer 108c are each indicated by solid arrows. In FIG. 11B, the thickness T208a of layer 208a, the thickness T208b of layer 208b, and the thickness T208c of layer 208c are each indicated by solid arrows. Here, the thickness of layer 108 is the shortest distance between insulating layer 110b and insulating layer 106 in the region in contact with layer 108 in a cross-sectional view. For example, the thickness of each layer of layer 108 at the midpoint between the height of the upper surface and the height of the lower surface of insulating layer 110 can be used as the thickness of each layer of layer 108. The same applies to layer 208.

As described above, layers 208a, 208b, and 208c can be formed in the same process as layers 108a, 108b, and 108c. In addition, when the angles θ100 and θ200 (see FIG. 4B and FIG. 4C) of insulating layer 110, which is the surface on which layers 108 and 208 are formed, are the same or approximately the same, thicknesses T108a and T208a may be the same or approximately the same, thicknesses T108b and T208b may be the same or approximately the same, and thicknesses T108c and T208c may be the same or approximately the same. Note that thicknesses T108a and T208a may be different from each other. The same applies to thicknesses T108b and T208b, and thicknesses T108c and T208c.

The following describes the thickness of each layer of layer 108 as an example. Note that for layer 208, the descriptions of thickness T108a, thickness T108b, and thickness T108c can be read as thickness T208a, thickness T208b, and thickness T208c.

By increasing the thickness T108b of the layer 108b, which is the main current path of the layer 108, the transistor 100 can have a large on-state current. The thickness T108b is preferably thicker than the thickness T108a and the thickness T108c. However, if the thickness T108b is too thick, the amount of oxygen vacancies (V _O ) and V _O H in the layer 108b may be greater than the amount of oxygen vacancies (V O ) and V O H repaired by oxygen supplied from the insulating layer 110. The thickness T108b is preferably 1 _nm or more and 50 nm or less, more preferably 3 nm or more and 30 nm or less, even more preferably 3 nm or more and 20 nm or less, even more preferably 5 nm or more and ₂₀ nm or less, and even more preferably 5 nm or more and 15 nm or less.

Thickness T108c is preferably thicker than thickness T108a. By making thickness T108c thicker, trap levels that may be formed at the interface between insulating layer 106 and layer 108 and in the vicinity thereof can be distanced from layer 108b. Also, damage to layer 108b during the formation of insulating layer 106 can be suppressed. If thickness T108c is too thick, the distance between conductive layer 104 functioning as a gate electrode and layer 108b becomes longer, and the on-current may become smaller. Thickness T108c is preferably 1 nm or more and 30 nm or less, more preferably 1 nm or more and 20 nm or less, even more preferably 1 nm or more and 10 nm or less, and even more preferably 2 nm or more and 10 nm or less.

Oxygen contained in the insulating layer 110 is supplied to the layer 108b through the layer 108a. Therefore, it is preferable that the layer 108a is easily permeable to oxygen. By making the thickness T108a thinner than the thickness T108c, the oxygen contained in the insulating layer 110 can be efficiently supplied to the layer 108b. This can reduce oxygen vacancies (V _O ) and V _O H in the layer 108b, which are the main current paths of the layer 108. If the thickness T108a is too thin, the distance between the layer 108b and the interface between the insulating layer 110 and the layer 108 and the trap level near the interface is shortened, and the on-current may become small. In addition, the reliability may be deteriorated. The thickness T108a is preferably 0.1 nm or more and 10 nm or less, more preferably 0.3 nm or more and 5 nm or less, more preferably 0.5 nm or more and 5 nm or less, and even more preferably 0.5 nm or more and 3 nm or less.

It is more preferable that each of layers 108a, 108b, and 108c has crystallinity. When layer 108a has crystallinity, the crystallinity of layer 108b formed thereon can be increased. Similarly, when layer 108b has crystallinity, the crystallinity of layer 108c formed thereon can be increased.

The band gap of the first metal oxide and the band gap of the third metal oxide can be different. The band gap of the third metal oxide is preferably larger than the band gap of the first metal oxide. By using a material with a large band gap for the layer 108c located on the conductive layer 104 side functioning as a gate electrode, carriers are prevented from being generated and induced in the layer 108c and at the interface between the layer 108c and the gate insulating layer (the insulating layer 106 in this case), so that a highly reliable transistor can be obtained. For example, carriers are prevented from being generated and induced in the layer 108c and at the interface by light incident on the transistor, so that fluctuations in the electrical characteristics of the transistor due to light can be suppressed.

Note that by making the band gap of the first metal oxide in layer 208a smaller than the band gap of the third metal oxide in layer 208c, the contact resistance between layer 208a and conductive layer 212a and the contact resistance between layer 208a and conductive layer 212b can be reduced. Therefore, the transistor 200 can have a large on-current.

The difference between the band gap of the first metal oxide and the band gap of the third metal oxide is preferably 0.1 eV or more, more preferably 0.2 eV or more, and even more preferably 0.3 eV or more. The conduction band lower edge of the third metal oxide is preferably closer to the vacuum level than the conduction band lower edge of the first metal oxide. In other words, the electron affinity of the third metal oxide is preferably smaller than the electron affinity of the first metal oxide.

The content of element M in the third metal oxide is preferably higher than the content of element M in the first metal oxide. This allows the band gap of the third metal oxide to be larger than the band gap of the first metal oxide.

When the first metal oxide, the second metal oxide, and the third metal oxide are In-M-Zn oxides, for example, the first metal oxide can have a composition of In:M:Zn=1:1:1 [atomic ratio] or a composition thereabout, the second metal oxide can have a composition of In:M:Zn=40:1:10 [atomic ratio] or a composition thereabout, and the third metal oxide can have a composition of In:M:Zn=1:3:4 [atomic ratio] or a composition thereabout. Alternatively, the first metal oxide can have a composition of In:M:Zn=1:1:1 [atomic ratio] or a composition thereabout, the second metal oxide can have a composition of In:M:Zn=10:1:10 [atomic ratio] or a composition thereabout, and the third metal oxide can have a composition of In:M:Zn=1:3:4 [atomic ratio] or a composition thereabout.

More specifically, the first metal oxide can be suitably composed of In:Ga:Zn = 1:1:1 [atomic ratio] or a composition close thereto, the second metal oxide can be suitably composed of In:Sn:Zn = 40:1:10 [atomic ratio] or a composition close thereto, and the third metal oxide can be suitably composed of In:Ga:Zn = 1:3:4 [atomic ratio] or a composition close thereto. Alternatively, the first metal oxide can be suitably composed of In:Ga:Zn = 1:1:1 [atomic ratio] or a composition close thereto, the second metal oxide can be suitably composed of In:Sn:Zn = 10:1:10 [atomic ratio] or a composition close thereto, and the third metal oxide can be suitably composed of In:Ga:Zn = 1:3:4 [atomic ratio] or a composition close thereto.

The second metal oxide may be configured not to include element M. For example, the second metal oxide may be an In-Zn oxide, and the first metal oxide and the third metal oxide may be an In-M-Zn oxide. Specifically, the first metal oxide may preferably have a composition of In:Ga:Zn=1:1:1 [atomic ratio] or a composition in the vicinity thereof, the second metal oxide may preferably have a composition of In:Zn=4:1 [atomic ratio] or a composition in the vicinity thereof, and the third metal oxide may preferably have a composition of In:Ga:Zn=1:3:4 [atomic ratio] or a composition in the vicinity thereof. Alternatively, the first metal oxide may preferably have a composition of In:Ga:Zn=1:1:1 [atomic ratio] or a composition in the vicinity thereof, the second metal oxide may preferably have a composition of In:Zn=1:1 [atomic ratio] or a composition in the vicinity thereof, and the third metal oxide may preferably have a composition of In:Ga:Zn=1:3:4 [atomic ratio] or a composition in the vicinity thereof.

10A and the like show an example in which the layers 108 and 208 each have a three-layer structure, but one embodiment of the present invention is not limited to this. For example, the layer 108 may have a structure in which the layer 108 does not have one or both of the layers 108a and 108c, and the layer 208 does not have one or both of the layers 208a and 208c. For example, as shown in FIG. 12A, the layer 108 may have a two-layer structure of the layers 108b and 108c, and the layer 208 may have a two-layer structure of the layers 208b and 208c. Alternatively, as shown in FIG. 12B, the layer 108 may have a two-layer structure of the layers 108a and 108b, and the layer 208 may have a two-layer structure of the layers 208a and 208b. Alternatively, the layer 108 and the layer 208 may each have a stacked structure of four or more layers.

The configurations of layers 108 and 208 shown in configuration example 1-4 can also be applied to other configuration examples.

[Configuration Example 1-5]
13A is a top view of a semiconductor device 10F according to one embodiment of the present invention, FIG 13B is a cross-sectional view taken along dashed dotted line A1-A2 in FIG 13A, and FIG 13C is a cross-sectional view taken along dashed dotted line B1-B2 and dashed dotted line B3-B4 in FIG 13A.

The semiconductor device 10F has a transistor 100F, a transistor 200F, and an insulating layer 110. The semiconductor device 10F differs from the semiconductor device 10 shown in FIG. 1B etc. mainly in that the transistor 100F has a conductive layer 103, a layer 105, and an insulating layer 116, and the transistor 200F has a conductive layer 203, a layer 205, and an insulating layer 216.

An enlarged view of transistor 100F shown in FIG. 13B is shown in FIG. 14A, and an enlarged view of transistor 200F is shown in FIG. 14B.

The transistor 100F has a conductive layer 103 and a layer 105 between the insulating layer 110a and the insulating layer 110b. The conductive layer 103 is provided on the insulating layer 110a, and the layer 105 is provided on the upper surface and side surface of the conductive layer 103. The insulating layer 110, the layer 105, and the conductive layer 103 have an opening 141 that reaches the conductive layer 112. The insulating layer 116 has a region that contacts the side surface of the insulating layer 110 and the side surface of the layer 105 in the opening 141. Since the insulating layer 116 is provided along the side surface of the insulating layer 110 and the side surface of the layer 105 in the opening 141, it can be called a sidewall or sidewall insulating layer. In addition, the insulating layer 116 has a region that contacts a part of the upper surface of the conductive layer 112 in the opening 141. The layer 108 has a region that contacts a part of the upper surface of the conductive layer 112 and the side surface of the insulating layer 116 in the opening 141. The insulating layer 116 is located between the conductive layer 103 and the layer 105 and the layer 108, and the conductive layer 103 and the layer 108 are electrically insulated from each other by the insulating layer 116.

In transistor 100F, layer 108 has a region that overlaps with conductive layer 104 via insulating layer 106, and also overlaps with conductive layer 103 via insulating layer 116. In other words, layer 108 has a region that is sandwiched between conductive layer 104 via insulating layer 106 and conductive layer 103 via insulating layer 116.

In the transistor 100F, the conductive layer 104 functions as a gate electrode (also referred to as a first gate electrode). A part of the insulating layer 106 functions as a gate insulating layer (also referred to as a first gate insulating layer). The conductive layer 103 functions as a backgate electrode (also referred to as a second gate electrode). The insulating layer 116 functions as a backgate insulating layer (also referred to as a second gate insulating layer).

By providing a backgate electrode in the transistor 100F, the potential on the backgate electrode side (backchannel side) of the layer 108 is fixed, and the saturation of the Id-Vd characteristics can be improved. In addition, by fixing the potential on the backchannel side of the layer 108, a shift in the threshold voltage can be suppressed. Therefore, a transistor with a small cutoff current can be obtained, and a semiconductor device with low power consumption can be obtained.

The insulating layer 116 can be made of a material that can be used for the insulating layer 106. When a metal oxide is used for the layer 108, it is preferable to use any one of the above-mentioned oxides and oxynitrides for at least a film that is in contact with the layer 108 among the films that constitute the insulating layer 116. The insulating layer 116 has a region in contact with the insulating layer 110. It is preferable that the insulating layer 116 has a region in contact with the insulating layer 110b in particular. Oxygen released from the insulating layer 110b by heat applied during a manufacturing process of the semiconductor device is supplied to the insulating layer 116. Furthermore, oxygen can be supplied to the layer 108 by releasing oxygen from the insulating layer 116. Oxygen vacancies (V _O ) and V _O H can be reduced by supplying oxygen from the insulating layer 110b to the layer 108, particularly to the channel formation region, through the insulating layer 116. Therefore, the transistor 100F exhibits favorable electrical characteristics and is highly reliable.

In the case where a metal oxide is used for the layer 108, the metal oxide film to be the layer 108 is preferably formed in an atmosphere containing oxygen. In this manner, oxygen can be supplied to the insulating layer 116. Then, oxygen is supplied from the insulating layer 116 to the layer 108 in a later step, and oxygen vacancies ( _VO ) and _VOH in the layer 108 can be reduced.

The layer 105 is located between the conductive layer 103 and the insulating layer 110 and between the conductive layer 103 and the insulating layer 116. The layer 105 has a region in contact with the top surface and side surface of the conductive layer 103. The conductivity of the layer 105 is not particularly limited. The layer 105 preferably functions as a barrier film. When the layer 105 functions as a barrier film, the conductive layer 103 can be prevented from being oxidized by oxygen contained in the insulating layer 110b, and the electrical resistance can be prevented from increasing. In addition, the amount of oxygen supplied from the insulating layer 110b to the insulating layer 116 can be increased, so that the amount of oxygen supplied to the channel formation region of the layer 108 can be increased. Therefore, oxygen vacancies (V _O ) and V _O H in the channel formation region can be reduced.

The materials that can be used as the barrier film are as described above. It is more preferable that the layer 105 contains a component contained in the conductive layer 103. When an oxide is used for the layer 105, the layer 105 preferably contains an element contained in the conductive layer 103 and oxygen. When a nitride is used for the layer 105, the layer 105 preferably contains an element contained in the conductive layer 103 and nitrogen. When aluminum is used for the conductive layer 103, the layer 105 preferably contains aluminum and oxygen. For example, aluminum can be used for the conductive layer 103, and aluminum oxide can be used for the layer 105.

When an oxide is used for layer 105, layer 105 can be formed by oxidizing conductive layer 103 or a film that will become conductive layer 103. When a nitride is used for layer 105, layer 105 can be formed by nitriding conductive layer 103 or a film that will become conductive layer 103. Note that the boundary between conductive layer 103 and layer 105 may be unclear, so in Figure 14A etc., these boundaries are shown by dashed lines.

The treatment for oxidizing the conductive layer 103 (hereinafter also referred to as an oxidation treatment) or the treatment for nitriding the conductive layer 103 (hereinafter also referred to as a nitridation treatment) can be, for example, a plasma treatment. The atmosphere used for the oxidation treatment preferably contains oxygen. For example, an atmosphere containing one or more of oxygen (O ₂ ), nitrous oxide (N ₂ O), nitrogen dioxide (NO ₂ ), carbon monoxide, and carbon dioxide can be preferably used as the atmosphere. The atmosphere used for the nitridation treatment preferably contains nitrogen. For example, an atmosphere containing nitrogen (N ₂ ) can be preferably used as the atmosphere.

For example, after forming the layer that will become the conductive layer 103 and before forming the film that will become the insulating layer 110b, the conductive layer 103 is subjected to an oxidation treatment or a nitridation treatment to form an oxide or a nitride on the surface of the layer that will become the conductive layer 103. Furthermore, after forming the opening 141 and before forming the insulating layer 116, the conductive layer 103 is subjected to an oxidation treatment or a nitridation treatment to form an oxide or a nitride on the surface of the conductive layer 103 on the opening 141 side. This allows the layer 105 to be formed on the top and side surfaces of the conductive layer 103.

14A, the channel length L100 of the transistor 100F is indicated by a double-headed dashed arrow. The channel length L100 corresponds to the length of the region where the insulating layer 116 and the layer 108 are in contact in a cross-sectional view. When the insulating layer 116 is provided on the side surfaces of the conductive layer 103, the layer 105, and the insulating layer 110, the channel length L100 is determined by the sum of the thicknesses of the conductive layer 103, the layer 105, and the insulating layer 110, and the angle θ100 between the side surface of the insulating layer 110 on the opening 141 side and the surface on which the insulating layer 110 is to be formed (here, the top surface of the conductive layer 112). Therefore, the transistor 100F can have a channel length shorter than the minimum exposure dimension of the exposure device used to fabricate the transistor.

The conductive layer 103 can be electrically connected to the conductive layer 112. For example, an opening is provided in a region of the insulating layer 110a that overlaps with the conductive layer 112, and the conductive layer 103 is provided to cover the opening, so that the conductive layer 103 and the conductive layer 112 are in contact with each other. By electrically connecting the conductive layer 112 and the conductive layer 103, one of the source electrode and the drain electrode and the back gate electrode can be made to have the same potential. For example, when the conductive layer 112 functions as a source electrode, a shift in the threshold voltage of the transistor 100F can be suppressed. In addition, the reliability of the transistor 100F can be improved. Note that the conductive layer 103 can also be formed in contact with the upper surface of the conductive layer 112 without providing the insulating layer 110a.

The conductive layer 103 can be electrically connected to the conductive layer 104. For example, openings can be provided in the regions of the insulating layers 110b, 110c, and 106 that overlap with the conductive layer 103, and the conductive layer 104 can be provided to cover the openings, so that the conductive layers 103 and 104 are in contact with each other. The conductive layer 104, which functions as a gate electrode, and the conductive layer 103, which functions as a backgate electrode, are electrically connected to each other, so that the backgate electrode and the gate electrode can be at the same potential, and the on-current of the transistor 100F can be increased.

Note that the transistor 100F may have a conductive layer 103, which may increase the unevenness of the upper surface of the insulating layer 110. If the unevenness of the upper surface of the insulating layer 110 is large, the unevenness of the layer 108 provided in contact with the upper surface of the insulating layer 110 may also increase, which may reduce the uniformity of the amount of impurity elements supplied to the region 108Db and reduce the uniformity of the electrical resistance of the region 108Db. Therefore, it is preferable that the upper surface of the insulating layer 110 is flatter. For example, it is preferable to perform a planarization process after forming the insulating layer 110 or the insulating film that will become the insulating layer 110 and before forming the layer 108 or the film that will become the layer 108, to flatten the upper surface of the insulating layer 110 or the insulating film that will become the insulating layer 110. Examples of the planarization process include a process using a chemical mechanical polishing (CMP) method (also referred to as a CMP process) and a process using etching (also referred to as an etch-back process). Alternatively, by using an organic insulating layer for the insulating layer 110, the upper surface of the insulating layer 110 can be made more flat. For materials that can be used for the organic insulating layer, please refer to the above description.

Transistor 200F has conductive layer 203 and layer 205 between insulating layer 110a and insulating layer 110b. Conductive layer 203 is provided on insulating layer 110a, and layer 205 is provided on the top and side surfaces of conductive layer 203. Insulating layer 110, layer 205, and conductive layer 203 have opening 141 that reaches conductive layer 212a. Insulating layer 216 has a region in contact with the side surface of insulating layer 110 and the side surface of layer 205 in opening 241, and has a region in contact with the side surface of conductive layer 212b in opening 243. Conductive layer 203 can be formed in the same process as conductive layer 103. Layer 205 can be formed in the same process as layer 105. Insulating layer 216 can be formed in the same process as insulating layer 116. The conductive layer 203, layer 205, and insulating layer 216 can be described in detail in the description of the conductive layer 103, layer 105, and insulating layer 116, and therefore will not be described in detail here.

In the transistor 200F, the conductive layer 204 functions as a gate electrode (also referred to as a first gate electrode). A part of the insulating layer 106 functions as a gate insulating layer (also referred to as a first gate insulating layer). The conductive layer 203 functions as a backgate electrode (also referred to as a second gate electrode). The insulating layer 216 functions as a backgate insulating layer (also referred to as a second gate insulating layer). By providing a backgate electrode in the transistor 200F, the saturation in the Id-Vd characteristics can be increased. In addition, a shift in the threshold voltage can be suppressed. Therefore, a transistor with a small cutoff current can be obtained, and a semiconductor device with low power consumption can be obtained.

13B and the like show a structure in which the transistor 100F and the transistor 200F each have a backgate electrode, but one embodiment of the present invention is not limited to this. The semiconductor device can have a structure including a transistor having a backgate electrode and a transistor not having a backgate electrode. For example, the transistor 100F can have a conductive layer 103 and a layer 105, and the transistor 200F can have a conductive layer 203 and a layer 205. In this case, the transistor 200F can have an insulating layer 216. Alternatively, the insulating layer 216 can be omitted, and the layer 208 can have a region in contact with a side surface of the insulating layer 110.

As shown in FIG. 14A, the height of the upper surface of the insulating layer 116 can be configured to match or approximately match the height of the upper surface of the insulating layer 110. As shown in FIG. 14B, the height of the upper surface of the insulating layer 216 can be configured to match or approximately match the height of the upper surface of the conductive layer 212b. For example, the insulating layer 116 and the insulating layer 216 can be formed by providing a film to cover the openings 141, 241, and 243, and removing a part of the film to expose the upper surface of the insulating layer 110, the upper surface of the conductive layer 112, the upper surface of the conductive layer 212a, and the upper surface of the conductive layer 212b. For example, anisotropic etching can be suitably used to form the insulating layer 116 and the insulating layer 216.

15A and 15B show a configuration in which the height of the upper surface of insulating layer 116 is different from the height of the upper surface of insulating layer 110. FIG. 15A shows a configuration in which the height of the upper surface of insulating layer 116 is lower than the height of the upper surface of insulating layer 110c and higher than the height of the upper surface of insulating layer 110b. Also, as shown in FIG. 15B, the height of the upper surface of insulating layer 116 can be lower than the height of the upper surface of insulating layer 110b and higher than the height of the upper surface of layer 105. By contacting insulating layer 110b with layer 108, oxygen can be supplied from insulating layer 110b to layer 108. It is preferable that insulating layer 116 contacts at least the entire side surface of layer 105 on the opening 141 side.

15C to 15E show configurations in which the height of the upper surface of the insulating layer 216 is different from the height of the upper surface of the conductive layer 212b. FIG. 15C shows a configuration in which the height of the upper surface of the insulating layer 216 is lower than the height of the upper surface of the conductive layer 212b and higher than the height of the upper surface of the insulating layer 110c. By configuring the layer 208 to be in contact with the side surface of the conductive layer 212b as well, the contact area between the layer 208 and the conductive layer 212b is increased, so that the electrical resistance of the other of the source region and drain region of the transistor 200F can be reduced. FIG. 15D also shows a configuration in which the height of the upper surface of the insulating layer 216 is lower than the height of the upper surface of the insulating layer 110c and higher than the height of the upper surface of the insulating layer 110b. As shown in FIG. 15E, the height of the upper surface of the insulating layer 216 can also be lower than the height of the upper surface of the insulating layer 110b and higher than the height of the upper surface of the layer 205. By contacting the insulating layer 110b with the layer 208, oxygen can be supplied from the insulating layer 110b to the layer 208. It is preferable that the insulating layer 216 contacts at least the entire side surface of the layer 205 on the opening 241 side.

Insulating layer 110b is shown as a single-layer structure in FIG. 13B and other figures, but this is not a limitation of one embodiment of the present invention. Insulating layer 110b can have a stacked structure of two or more layers.

FIG. 16A shows a cross-sectional view of a semiconductor device 10G according to one embodiment of the present invention. For a top view of the semiconductor device 10G, refer to FIG. 13A. FIG. 16A is a cross-sectional view of a cut surface taken along dashed line A1-A2 shown in FIG. 13A.

The semiconductor device 10G has a transistor 100G, a transistor 200G, and an insulating layer 110. The semiconductor device 10G differs from the semiconductor device 10F shown in FIG. 13B etc. mainly in that the insulating layer 110b has an insulating layer 110b_1, an insulating layer 110b_2 on the insulating layer 110b_1, and an insulating layer 110b_3 on the insulating layer 110b_2. The detailed description of the transistors 100G and 200G can be referred to in the description of the transistors 100 and 200, so that it will not be described here.

The insulating layer 110b_1, the insulating layer 110b_2, and the insulating layer 110b_3 can each be made of the materials listed for the insulating layer 110.

The insulating layer 110b_1 is provided on the insulating layer 110a so as to fill the recess between the layer 105 and the layer 205. The insulating layer 110b_1 has an area in contact with the side of the layer 105, the side of the layer 205, and the top surface of the insulating layer 110a. It is preferable that the insulating layer 110b_1 covers at least the side of the layer 105 that does not face the opening 141 and the side of the layer 205 that does not face the opening 241. The insulating layer 110b_1 has a function of reducing unevenness caused by the conductive layer 103 and the layer 105 and making the top surface of the insulating layer 110 flatter. In addition, by providing the insulating layer 110b_1, the unevenness caused by the conductive layer 112 and the conductive layer 212a can also be reduced. Note that in this specification and the like, the insulating layer 110b_1 may be referred to as a planarization layer. An organic insulating layer can be suitably used as the insulating layer 110b_1. For example, acrylic resin or polyimide resin can be suitably used for the insulating layer 110b_1.

By making the top surface of the insulating layer 110 flatter, the regions 108Db and 208Db located on the insulating layer 110 become flatter, and the uniformity of the amount of the first element supplied to the regions 108Db and 208Db can be improved. This can improve the uniformity of the electrical resistance of the regions 108Db and 208Db.

Insulating layer 110b_2 is provided on insulating layer 110b_1. Insulating layer 110b_2 has an area in contact with the upper surface of insulating layer 110b_1, the upper surface of layer 105, the upper surface of layer 205, the side of insulating layer 116, and the side of insulating layer 216.

The insulating layer 110b_2 functions as a barrier film that prevents impurities contained in the insulating layer 110b_1 from diffusing toward the insulating layer 110b_3. The insulating layer 110b_2 can be made of any of the materials listed for the insulating layer 110a and the insulating layer 110c. For example, the insulating layer 110b_2 can be made of silicon nitride or aluminum oxide.

Insulating layer 110b_3 is provided on insulating layer 110b_2. Insulating layer 110b_3 has an area in contact with the upper surface of insulating layer 110b_2, the side surface of insulating layer 116, and the side surface of insulating layer 216.

The insulating layer 110b_3 can be preferably an inorganic insulating layer. The insulating layer 110b_3 can be preferably made of any of the materials listed for the insulating layer 110b. The insulating layer 110b_3 preferably contains oxygen, and preferably uses one or more of the oxides and oxynitrides described above. The insulating layer 110b_3 preferably contains silicon and oxygen. For example, the insulating layer 110b_3 can be preferably made of one or both of silicon oxide and silicon oxynitride.

The insulating layer 110b_3 preferably has a region in contact with the insulating layer 116 and a region in contact with the insulating layer 216. This allows oxygen to be supplied from the insulating layer 110b_3 to the layer 108 via the insulating layer 116 and to the layer 208 via the insulating layer 216.

In FIG. 16A, the height of the top surface of the insulating layer 110b_3 is the same as the height of the top surface of the layer 105 and the height of the top surface of the layer 205, but one embodiment of the present invention is not limited to this. The height of the top surface of the insulating layer 110b_3 may be different from the height of the top surface of the layer 105 and the height of the top surface of the layer 205.

As shown in FIG. 16B, the height of the upper surface of insulating layer 110b_2 can be higher than the height of the upper surface of layer 105 and the height of the upper surface of layer 205. Alternatively, as shown in FIG. 16C, the height of the upper surface of insulating layer 110b_2 can be lower than the height of the upper surface of layer 105 and the height of the upper surface of layer 205.

The configuration of the insulating layer 110b shown in Figures 16A to 16C can also be applied to other configuration examples.

FIGS. 17A and 17B show examples of configurations different from those of transistors 100F and 200F shown in FIGS. 14A and 14B. Transistor 100H shown in FIG. 17A differs from transistor 100F mainly in that insulating layer 110a is also provided between conductive layer 112 and insulating layer 116. Transistor 200H shown in FIG. 17B differs from transistor 100F mainly in that insulating layer 110a is also provided between conductive layer 212a and insulating layer 216.

By providing the insulating layer 110a between the insulating layer 116 and the conductive layer 112, the insulating layer 116 and the conductive layer 112 are not in contact with each other, and therefore it is possible to prevent the conductive layer 112 from being oxidized by oxygen being supplied from the insulating layer 116 to the conductive layer 112, and therefore it is possible to prevent the electrical resistance of the conductive layer 112 from increasing. Similarly, by providing the insulating layer 110a between the insulating layer 216 and the conductive layer 212a, the insulating layer 216 and the conductive layer 212a are not in contact with each other, and therefore it is possible to prevent the conductive layer 212a from being oxidized by oxygen being supplied from the insulating layer 216 to the conductive layer 212a, and therefore it is possible to prevent the electrical resistance of the conductive layer 212a from increasing.

For example, a first insulating film that will become insulating layer 110a and a conductive layer that will become conductive layer 103 are formed on conductive layer 112. A layer that will become layer 105 is formed on the surface of the conductive layer that will become conductive layer 103, and a second insulating film that will become insulating layer 110b and a third insulating film that will become insulating layer 110c are formed. By removing parts of the conductive layer that will become conductive layer 103, the layer that will become layer 105, the second insulating film, and the third insulating film, and forming an opening that will become opening 141, conductive layer 103, insulating layer 110b, and insulating layer 110c are formed. Layer 105 is also formed on the surface of conductive layer 103 that faces the opening. A fourth insulating layer that will become insulating layer 116 is formed so as to cover the opening that will become opening 141. By removing parts of the fourth insulating layer and exposing the upper surface of insulating layer 110c and the upper surface of conductive layer 112, opening 141 and insulating layer 116 can be formed. Conductive layer 203, layer 205, and opening 241 can also be formed in the same manner. Here, when forming the opening that becomes opening 141, the thickness of the first insulating film at the opening may be thin. As a result, as shown in FIG. 17A, the thickness of the region of insulating layer 110a that contacts insulating layer 116 may be thinner than the thickness of the region of insulating layer 110a that contacts conductive layer 103. Similarly, as shown in FIG. 17B, the thickness of the region of insulating layer 110a that contacts insulating layer 216 may be thinner than the thickness of the region of insulating layer 110a that contacts conductive layer 203.

The configurations of the conductive layer 103, insulating layer 116, conductive layer 203, and insulating layer 216 shown in configuration example 1-5 can also be applied to other configuration examples. In addition, the configurations of the conductive layer 103, layer 105, insulating layer 116, conductive layer 203, layer 205, and insulating layer 216 can also be applied to other configuration examples.

<Configuration Example 2>
18A to 18E are circuit diagrams of a semiconductor device of one embodiment of the present invention. FIGS. 19A to 21B are top views and cross-sectional views of the semiconductor device of one embodiment of the present invention. In the following, transistors 100 and 200 will be mainly used as examples of transistors included in the semiconductor device of one embodiment of the present invention. The semiconductor device of one embodiment of the present invention is not limited thereto, and can have a structure including one or more of the above-described transistors 100 to 100H and transistors 200 to 200H.

A semiconductor device according to one embodiment of the present invention has at least two transistors, and one of the gate, source, or drain of the transistor is electrically connected to the gate, source, or drain of the other transistor. Alternatively, a semiconductor device according to one embodiment of the present invention has a transistor and a capacitor, and one of the gate, source, or drain of the transistor is electrically connected to one terminal of the capacitor.

The semiconductor device according to one embodiment of the present invention can be applied to a display device. The display device includes a transistor and a display element. The source or drain of the transistor is electrically connected to a pixel electrode of the display element.

[Configuration Example 2-1]
FIG. 18A illustrates a circuit diagram of a semiconductor device 20 according to one embodiment of the present invention. FIG. 19A illustrates a top view of the semiconductor device 20 according to one embodiment of the present invention. FIG. 19B illustrates a cross-sectional view of the cut surface taken along dashed dotted line A1-A2 in FIG. 19A. FIG. 1C can be referred to for cross-sectional views of the cut surfaces taken along dashed dotted line B1-B2 and dashed dotted line B3-B4 in FIG. 19A. FIG. 1C can be referred to for cross-sectional views of the cut surfaces taken along dashed dotted line B5-B6 in FIG. 19A, and the cross-sectional view of the cut surface taken along dashed dotted line B1-B2 in FIG. 1C can be referred to for cross-sectional views of the cut surface taken along dashed dotted line B7-B8.

The semiconductor device 20 includes a transistor 100, a transistor 100s, a transistor 200, a transistor 200s, and an insulating layer 110. The semiconductor device 20 is provided on a substrate 102. For the transistors 100 and 200, the above description can be referred to.

Transistor 100s has conductive layer 104A, insulating layer 106, layer 108, and conductive layer 112A. Transistor 100s has a similar configuration to transistor 100. Conductive layer 104A corresponds to conductive layer 104, and conductive layer 112A corresponds to conductive layer 112. Layer 108 is shared between transistor 100 and transistor 100s.

In the transistor 100s, the conductive layer 104A functions as a gate electrode, and the insulating layer 106 functions as a gate insulating layer. In the transistor 100s, the conductive layer 112A functions as one of the source electrode and the drain electrode, and the region 108Db functions as the other of the source electrode and the drain electrode. In the transistor 100s, the region of the layer 108 in contact with the conductive layer 112A functions as one of the source region and the drain region, and the region in contact with the insulating layer 110b functions as a channel formation region. The layer 108 has a region 108Dc in a region located between the upper surface of the conductive layer 112A and the lower surface of the conductive layer 104A, among the regions in contact with the upper surface of the conductive layer 112A. The region 108Dc has a first element as an impurity element. The region 108Dc functions as one of the source region and the drain region of the transistor 100s. For the region 108Dc, refer to the description of the region 108Da.

The layer 108 has regions 108Da, 108Db, and 108Dc, a channel formation region of the transistor 100, and a channel formation region of the transistor 100s. Region 108Db functions as the other of the source electrode and drain electrode of the transistor 100 and also functions as the other of the source electrode and drain electrode of the transistor 100s. By sharing region 108Db between the transistors 100 and 100s, the other of the source electrode and drain electrode of the transistor 100 and the other of the source electrode and drain electrode of the transistor 100s are electrically connected. In the semiconductor device 20, region 108Db electrically connects the transistors 100 and 100s. Furthermore, by sharing layer 108 between the transistors 100 and 100s, the occupation area of the semiconductor device 20 can be reduced.

Transistor 200s has conductive layer 204A, insulating layer 106, layer 208A, conductive layer 212aA, and conductive layer 212b. Transistor 200s has a similar configuration to transistor 200. Conductive layer 204A corresponds to conductive layer 204, layer 208A corresponds to layer 208, and conductive layer 212aA corresponds to conductive layer 212a. Conductive layer 212b is shared by transistor 200 and transistor 200s.

In the transistor 200s, the conductive layer 204A functions as a gate electrode, and the insulating layer 106 functions as a gate insulating layer. In the transistor 200s, the conductive layer 212aA functions as one of the source electrode and the drain electrode, and the conductive layer 212b functions as the other of the source electrode and the drain electrode. In the transistor 200s, the region of the layer 208A in contact with the conductive layer 212aA functions as one of the source region and the drain region, the region in contact with the conductive layer 212b functions as the other of the source region and the drain region, and the region in contact with the insulating layer 110b functions as a channel formation region. The layer 208 has a region 208Dc in a region located between the upper surface of the conductive layer 212aA and the lower surface of the conductive layer 204A, among the regions in contact with the upper surface of the conductive layer 212aA, and has a region 208Dd in a region in contact with the upper surface of the conductive layer 212b. Region 208Dc and region 208Dd each have a first element as an impurity element. Region 208Dc functions as one of the source region and drain region of transistor 200s, and region 208Dd functions as the other of the source region and drain region of transistor 200s. For region 208Dc and region 208Dd, the description of region 208Da and region 208Db can be referred to.

The conductive layer 212b functions as the other of the source and drain electrodes of the transistor 200 and also functions as the other of the source and drain electrodes of the transistor 200s. By sharing the conductive layer 212b between the transistors 200 and 200s, the other of the source and drain electrodes of the transistor 200 is electrically connected to the other of the source and drain electrodes of the transistor 200s. In the semiconductor device 20, the conductive layer 212b electrically connects the transistors 200 and 200s. Furthermore, by sharing the conductive layer 212b between the transistors 200 and 200s, the occupation area of the semiconductor device 20 can be reduced.

As described above, depending on the material used for layer 108, the electrical resistance of conductive layer 212b may be lower than the electrical resistance of region 108Db. When the other of the source electrode and drain electrode functions as a wiring, if the length of the wiring is long and the wiring resistance required for the wiring is relatively low, the transistor 200 having the conductive layer 212b can be preferably used. By using the transistor 200, a semiconductor device that operates at high speed can be obtained. On the other hand, if the length of the wiring is short and the wiring resistance required for the wiring is relatively high, the transistor 100 can be preferably used. By using the transistor 100, a semiconductor device that occupies a small area can be obtained.

19A and 19B, the distance between transistor 200 and transistor 200s can be longer than the distance between transistor 100 and transistor 100s. Note that one embodiment of the present invention is not limited to this, and the distance between transistor 100 and transistor 100s can be the same as the distance between transistor 200 and transistor 200s or longer than the distance between transistor 200 and transistor 200s.

The conductive layer 112, conductive layer 112A, conductive layer 212a, and conductive layer 212aA are provided on the substrate 102. The conductive layer 112, conductive layer 112A, conductive layer 212a, and conductive layer 212aA can be formed in the same process. For example, the conductive layer 112, conductive layer 112A, conductive layer 212a, and conductive layer 212aA can be formed by forming a film that will become the conductive layer 112, conductive layer 112A, conductive layer 212a, and conductive layer 212aA, and processing the film. Alternatively, some of these can be formed in different processes.

An insulating layer 110 is provided on conductive layer 112, conductive layer 112A, conductive layer 212a, and conductive layer 212aA. Insulating layer 110 has an opening 141 that reaches conductive layer 112, an opening 141A that reaches conductive layer 112A, an opening 241 that reaches conductive layer 212a, and an opening 241A that reaches conductive layer 212aA. Opening 141, opening 141A, opening 241, and opening 241A can be formed in the same process. Alternatively, some of these can be formed in different processes.

The conductive layer 212b is provided on the insulating layer 110. The conductive layer 212b has an area that overlaps with the conductive layer 212a and an area that overlaps with the conductive layer 212aA via the insulating layer 110. It can also be said that the insulating layer 110 has an area sandwiched between the conductive layer 212a and the conductive layer 212b, and an area sandwiched between the conductive layer 212aA and the conductive layer 212b.

The conductive layer 212b has an opening 243 that reaches the conductive layer 212a, and an opening 243A that reaches the conductive layer 212aA. The opening 243 is provided in a region that overlaps with the opening 241, and the opening 243A is provided in a region that overlaps with the opening 241A. The openings 243 and the openings 243A can be formed in the same process. Alternatively, some of them can be formed in different processes.

Layer 108 is provided to cover openings 141 and 141A, layer 208 is provided to cover openings 241 and 243, and layer 208A is provided to cover openings 241A and 243A. Layers 108, 208, and 208A can be formed in the same process. Alternatively, some of these layers can be formed in different processes.

The layer 108 has a region in contact with the top surface of the conductive layer 112 and a region in contact with the side surface of the insulating layer 110 at the opening 141. The layer 108 also has a region in contact with the top surface of the conductive layer 112A and a region in contact with the side surface of the insulating layer 110 at the opening 141A. The layer 208 has a region in contact with the top surface of the conductive layer 212a and a region in contact with the side surface of the insulating layer 110 at the opening 241, and a region in contact with the side surface of the conductive layer 212b at the opening 243. The layer 208A has a region in contact with the top surface of the conductive layer 212aA and a region in contact with the side surface of the insulating layer 110 at the opening 241A, and a region in contact with the side surface of the conductive layer 212b at the opening 243A.

It is preferable that each of layer 208 and layer 208A has an area in contact with the upper surface of conductive layer 212b. By having layer 208b in contact with not only the side surface but also the upper surface of conductive layer 212b, the contact area between layer 208b and conductive layer 212b is increased, and the contact resistance between layer 208b and conductive layer 212b can be reduced. The same applies to layer 208 and conductive layer 212b.

An insulating layer 106 is provided on layer 108, layer 208, layer 208A, conductive layer 212b and insulating layer 110.

The first element is preferably supplied to layers 108, 208, and 208A through the insulating layer 106. For example, after the insulating layer 106 is formed and before the conductive layers 104, 104A, 204, and 204A are formed, the first element can be supplied to layers 108, 208, and 208A through the insulating layer 106. This allows the first element to be preferentially supplied to regions 108Da, 108Db, and 108Dc in layer 108, the first element to be preferentially supplied to regions 208Da and 208Db in layer 208, and the first element to be preferentially supplied to regions 208Dc and 208Dd in layer 208A.

　Conductive layer 104, conductive layer 104A, conductive layer 204, and conductive layer 204A are provided on insulating layer 106.

The conductive layer 104 has an area in the opening 141 where it overlaps with the layer 108 via the insulating layer 106. The conductive layer 104A has an area in the opening 141A where it overlaps with the layer 108 via the insulating layer 106. The conductive layer 204 has an area in the opening 241 where it overlaps with the layer 208 via the insulating layer 106. The conductive layer 204A has an area in the opening 241A where it overlaps with the layer 208A via the insulating layer 106. The conductive layers 104, 104A, 204, and 204A can be formed in the same process. Alternatively, some of these layers can be formed in different processes.

Although Figures 18A, 19A, and 19B do not show electrical connections between transistors 100 and 100s and transistors 200 and 200s, they may also be configured to be electrically connected.

Note that the configurations of transistors 100 and 100s and the configurations of transistors 200 and 200s shown in configuration example 2-1 can also be applied to other configuration examples.

Below, a configuration example having some different configuration from the above-mentioned configuration example 2-1 will be described. Note that below, explanations of parts that overlap with the above-mentioned configuration example 2-1 may be omitted. Also, in the drawings shown below, parts that have the same function as the above-mentioned configuration example 2-1 may be marked with the same hatching pattern and may not be assigned reference numerals.

[Configuration Example 2-2]
A circuit diagram of a semiconductor device 20A according to one embodiment of the present invention is shown in FIG 18B. A top view of the semiconductor device 20A according to one embodiment of the present invention is shown in FIG 20A. A cross-sectional view of the cut surface taken along dashed dotted line A1-A2 in FIG 20A is shown in FIG 20B. For cross-sectional views of the cut surfaces taken along dashed dotted line B1-B2 and dashed dotted line B3-B4 in FIG 20A, refer to FIG 1C.

The semiconductor device 20A includes a transistor 100, a transistor 200, and an insulating layer 110. The semiconductor device 20A is provided on a substrate 102. The other of the source and drain of the transistor 100 is electrically connected to the other of the source and drain of the transistor 200.

The layer 108 of the transistor 100 has a portion on the insulating layer 110 that contacts the conductive layer 212b of the transistor 200. That is, the region 108Db has a portion that contacts the conductive layer 212b. It is preferable that the region 108Db contacts not only the side surface of the conductive layer 212b but also the top surface of the conductive layer 212b. This increases the contact area between the region 108Db and the conductive layer 212b, and reduces the contact resistance between the region 108Db and the conductive layer 212b. A portion of the end of the layer 108 is located on the conductive layer 212b.

By contacting region 108Db with conductive layer 212b, the other of the source and drain of transistor 100 is electrically connected to the other of the source and drain of transistor 200. By contacting region 108Db with conductive layer 212b, there is no need to provide a separate conductive layer that electrically connects region 108Db with conductive layer 212b, so the area occupied by semiconductor device 20A can be reduced.

The configuration of layer 108 and conductive layer 212b shown in configuration example 2-2 can also be applied to other configuration examples.

[Configuration Example 2-3]
FIG 21A shows a top view of a semiconductor device 20B according to one embodiment of the present invention. FIG 21B shows a cross-sectional view taken along dashed dotted line A1-A2 in FIG 21A. FIG 1C can be referred to for cross-sectional views taken along dashed dotted line B1-B2 and dashed dotted line B3-B4 in FIG 21A. FIG 18B can be referred to for a circuit diagram of the semiconductor device 20B.

The semiconductor device 20B has a transistor 100, a transistor 200, an insulating layer 110, and a conductive layer 193. The semiconductor device 20B is provided on a substrate 102.

The other of the source and drain of transistor 100 is electrically connected to the other of the source and drain of transistor 200 through conductive layer 193. The conductive layer 193 functions as a wiring that electrically connects the transistor and transistor 200.

The insulating layer 106 has an opening 145 that reaches the region 108Db, and an opening 145A that reaches the conductive layer 212b. The conductive layer 104, the conductive layer 204, and the conductive layer 193 are provided on the insulating layer 106. The conductive layer 193 is provided so as to cover the opening 145 and the opening 145A. The conductive layer 193 has a region that contacts the region 108Db in the opening 145, and a region that contacts the conductive layer 212b in the opening 145A. The conductive layer 193 is electrically connected to the region 108Db in the opening 145, and is electrically connected to the conductive layer 212b in the opening 145A. In other words, the region 108Db is electrically connected to the conductive layer 212b via the conductive layer 193.

The conductive layer 193 can be formed, for example, in the same process as the conductive layer 104 and the conductive layer 204. Note that the conductive layer 193 can also be formed in a process different from that for the conductive layer 104 and the conductive layer 204. For example, after forming the insulating layer 195 on the conductive layer 104 and the conductive layer 204, the openings 145 and the openings 145A can be formed in the insulating layer 106 and the insulating layer 195, and the conductive layer 193 can be formed so as to cover the openings 145 and the openings 145A.

Here, when a metal or an alloy is used for the wiring, the electrical resistance of the wiring can be made lower than when an oxide conductor is used. When the distance between the transistor 100 and the transistor 200 is long and the wiring resistance required for the wiring electrically connecting the transistor 100 and the transistor 200 is relatively low, a metal or an alloy can be suitably used for the conductive layer 193 that functions as the wiring.

When the distance between transistor 100 and transistor 200 is short and the wiring resistance required for electrically connecting transistor 100 and transistor 200 is relatively high, a configuration can be used in which conductive layer 193 is not provided, as shown in FIG. 20B, etc. By contacting region 108Db of transistor 100 and conductive layer 212b of transistor 200, the other of the source and drain of transistor 100 can be electrically connected to the other of the source and drain of transistor 200.

The method of electrical connection between transistor 100 and transistor 200 can be determined according to the material used for layer 108 and the wiring resistance required for the wiring that electrically connects transistor 100 and transistor 200.

The top surface shapes of the openings 145 and 145A are not particularly limited. The top surface shapes of the openings 145 and 145A can be shapes that can be applied to the openings 141, 241, and 243. For example, as shown in FIG. 21A, the top surface shapes of the openings 145 and 145A can each be a rectangle with rounded corners. Note that FIG. 21A shows a configuration in which the top surface shapes of the openings 145 and 145A are different from the top surface shapes of the openings 141, 241, and 243, but one aspect of the present invention is not limited to this. The top surface shapes of the openings 145 and 145A can be the same as the top surface shapes of the openings 141, 241, and 243.

Note that the configurations of layer 108, conductive layer 212b, and conductive layer 193 shown in configuration example 2-3 can also be applied to other configuration examples.

[Configuration Example 2-4]
A circuit diagram of a semiconductor device 20C according to one embodiment of the present invention is shown in Fig. 18C. A top view of the semiconductor device 20C is shown in Fig. 22A. A cross-sectional view of the cut surface taken along dashed dotted line A1-A2 in Fig. 22A is shown in Fig. 22B, and cross-sectional views of the cut surfaces taken along dashed dotted line B1-B2 and dashed dotted line B3-B4 are shown in Fig. 22C.

The semiconductor device 20C includes a transistor 100, a transistor 200, and an insulating layer 110. The semiconductor device 20C is provided on a substrate 102. One of the source and drain of the transistor 100 is electrically connected to one of the source and drain of the transistor 200.

The transistor 200 shown in Figures 22A to 22C has a conductive layer 112 instead of the conductive layer 212a shown in Figure 1B and the like. The conductive layer 112 is shared by the transistor 100 and the transistor 200.

The conductive layer 112 functions as one of the source and drain electrodes of the transistor 100 and one of the source and drain electrodes of the transistor 200. By sharing the conductive layer 112 between the transistors 100 and 200, one of the source and drain electrodes of the transistor 100 is electrically connected to one of the source and drain electrodes of the transistor 200. In the semiconductor device 20C, the conductive layer 112 electrically connects the transistors 100 and 200. Furthermore, by sharing the conductive layer 112 between the transistors 100 and 200, the occupation area of the semiconductor device 20C can be reduced.

The configuration of the conductive layer 112 shown in configuration example 2-4 can also be applied to other configuration examples.

[Configuration Example 2-5]
A circuit diagram of a semiconductor device 20D according to one embodiment of the present invention is shown in FIG 18D. A top view of the semiconductor device 20D is shown in FIG 23A. A cross-sectional view of the cut surface taken along dashed dotted line A1-A2 in FIG 23A is shown in FIG 23B. For cross-sectional views of the cut surfaces taken along dashed dotted line B1-B2 and dashed dotted line B3-B4 in FIG 23A, refer to FIG 1C.

The semiconductor device 20D has a transistor 100, a transistor 200, and an insulating layer 110. The semiconductor device 20D is provided on a substrate 102.

The insulating layer 106 has an opening 145B that reaches the region 108Db. The conductive layer 204 is provided to cover the opening 145B. The conductive layer 204 has a region that contacts the region 108Db at the opening 145B. The conductive layer 204 is electrically connected to the region 108Db at the opening 145B.

By contacting region 108Db with conductive layer 204, there is no need to provide a separate conductive layer that electrically connects region 108Db with conductive layer 204, so the area occupied by semiconductor device 20D can be reduced.

Here, a structure in which the other of the source electrode and drain electrode of the transistor 100 is electrically connected to the gate electrode of the transistor 200 is shown, but one embodiment of the present invention is not limited to this. As shown in FIG. 18E, a structure in which the other of the source electrode and drain electrode of the transistor 200 is electrically connected to the gate electrode of the transistor 100 can be used. For example, an opening that reaches the conductive layer 212b can be provided in the insulating layer 106, and the conductive layer 104 can be formed to cover the opening. The conductive layer 212b and the conductive layer 104 can be electrically connected to each other by being in contact with each other in the opening.

The configuration of layer 108 and conductive layer 204 shown in configuration example 2-5 can also be applied to other configuration examples.

Note that although the structure of a semiconductor device having a plurality of transistors has been described here, one embodiment of the present invention is not limited thereto. The semiconductor device which is one embodiment of the present invention can be suitably used for a display device. In the display device which is one embodiment of the present invention, the region 108Db of the transistor can be in contact with a pixel electrode of a display element. The structure of the display device will be described in detail in embodiment 3.

This embodiment can be combined with other embodiments as appropriate. In addition, in this specification, when multiple configuration examples are shown in one embodiment, the configuration examples can be combined as appropriate.

(Embodiment 2)
In this embodiment, a manufacturing method of a semiconductor device according to one embodiment of the present invention will be described with reference to Fig. 24A to Fig. 27B. Note that with regard to materials and formation methods of elements, description of the same parts as those described in Embodiment 1 may be omitted.

Thin films (e.g., insulating films and conductive films) that make up semiconductor devices can be formed using methods such as sputtering, chemical vapor deposition (CVD), vacuum deposition, pulsed laser deposition (PLD), and ALD. CVD methods include PECVD and thermal CVD. One type of thermal CVD method is metal organic chemical vapor deposition (MOCVD).

The thin films (e.g., insulating films and conductive films) that make up semiconductor devices can be formed by wet film formation methods such as spin coating, dipping, spray coating, inkjet, dispensing, screen printing, offset printing, doctor knife method, slit coating, roll coating, curtain coating, or knife coating.

When processing the thin film that constitutes the semiconductor device, a photolithography method or the like can be used. Alternatively, the thin film can be processed using a nanoimprint method, a sandblasting method, a lift-off method, or the like. Also, island-shaped thin films can be directly formed using a film formation method that uses a shielding mask such as a metal mask.

There are two typical photolithography methods. One is to form a resist mask on the thin film to be processed, process the thin film by etching or other methods, and then remove the resist mask. The other is to form a photosensitive thin film, and then expose and develop it to process the thin film into the desired shape.

In photolithography, the light used for exposure can be, for example, i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), or a mixture of these. In addition, ultraviolet light, KrF laser light, ArF laser light, etc. can also be used. Exposure can also be performed by immersion exposure technology. Extreme ultraviolet (EUV) light or X-rays can also be used as the light used for exposure. Electron beams can also be used instead of the light used for exposure. Extreme ultraviolet light, X-rays, or electron beams are preferable because they enable extremely fine processing. When exposure is performed by scanning a beam such as an electron beam, a photomask is not required.

To etch the thin film, one or more of the following methods can be used: dry etching, wet etching, and sandblasting.

Here, an example of a method for manufacturing the semiconductor device 10D shown in Figures 9A to 9C will be described with reference to Figures 24A to 27B. Figures 24A to 27B show cross-sectional views taken along dashed line A1-A2 in Figure 9A.

First, an insulating layer 109 is formed on the substrate 102. The insulating layer 109 can be formed preferably by a sputtering method or a PECVD method.

Next, a conductive film is formed on the insulating layer 109, and the conductive film is processed to form the conductive layer 112 and the conductive layer 212a (Figure 24A). The conductive film can be preferably formed by a sputtering method.

Next, an insulating film 110af that will become the insulating layer 110a, and an insulating film 110bf that will become the insulating layer 110b are formed on the conductive layer 112 and the conductive layer 212a (Figure 24B).

The insulating films 110af and 110bf can be preferably formed by sputtering or PECVD. After forming the insulating film 110af, it is preferable to form the insulating film 110bf without exposing the surface of the insulating film 110af to the atmosphere. This makes it possible to prevent impurities from the atmosphere from adhering to the surface of the insulating film 110af. Examples of such impurities include water and organic matter. For example, it is preferable to form the insulating film 110bf continuously in the same device after forming the insulating film 110af.

The substrate temperature during the formation of the insulating film 110af and the insulating film 110bf is preferably 180°C or higher and 450°C or lower, more preferably 200°C or higher and 450°C or lower, even more preferably 250°C or higher and 450°C or lower, even more preferably 300°C or higher and 450°C or lower, even more preferably 300°C or higher and 400°C or lower, even more preferably 350°C or higher and 400°C or lower. By setting the substrate temperature during the formation of the insulating film 110af and the insulating film 110bf within the above-mentioned range, the amount of impurities (e.g., water and hydrogen) released from the insulating film 110af and the insulating film 110bf can be reduced, and the diffusion of impurities into the layer 108 and the layer 208 can be suppressed. Therefore, a transistor exhibiting good electrical characteristics and high reliability can be obtained.

In addition, since the insulating films 110af and 110bf are formed before the layers 108 and 208, there is no need to worry about oxygen being desorbed from the layers 108 and 208 due to the heat applied during the formation of the insulating films 110af and 110bf.

After the insulating films 110af and 110bf are formed, a heat treatment can be performed. By performing the heat treatment, impurities (e.g., water and hydrogen) can be removed from the insulating film 110af and from the insulating film 110bf and its surface.

After the insulating film 110bf is formed, oxygen can be supplied to the insulating film 110bf. For example, ion implantation or plasma treatment can be used as a method for supplying oxygen. Oxygen radicals, oxygen atoms, oxygen atomic ions, or oxygen molecular ions can be supplied by ion implantation or plasma treatment of the insulating film 110bf. For the plasma treatment, an apparatus that converts oxygen gas into plasma by high-frequency power can be preferably used. For example, a PECVD apparatus, a plasma etching apparatus, and a plasma ashing apparatus can be used as an apparatus that converts gas into plasma by high-frequency power. The ion implantation or plasma treatment is preferably performed in an atmosphere containing oxygen. For example, an atmosphere containing one or more of oxygen (O ₂ ), nitrous oxide (N ₂ O), nitrogen dioxide (NO ₂ ), carbon monoxide, and carbon dioxide can be preferably used as the atmosphere. In addition, oxygen can be supplied by irradiating high-frequency electromagnetic waves in an atmosphere containing oxygen to generate oxygen plasma. For example, oxygen can be supplied by performing microwave treatment in an atmosphere containing oxygen. Alternatively, a film that suppresses oxygen desorption can be formed over the insulating film 110bf, and then oxygen can be supplied to the insulating film 110bf through the film. The film is preferably removed after oxygen is supplied. As the film that suppresses oxygen desorption, a conductive film or a semiconductor film containing one or more of indium, zinc, gallium, tin, aluminum, chromium, tantalum, titanium, molybdenum, nickel, iron, cobalt, and tungsten can be used.

In this specification, microwaves refer to electromagnetic waves with a frequency of 300 MHz or more and 300 GHz or less. A representative example of microwaves is electromagnetic waves with a frequency of 2.45 GHz. Microwave processing refers to processing using a device with a power source that generates high-density plasma using microwaves, for example. Microwave processing can also be called microwave-excited high-density plasma processing.

Note that oxygen can be supplied by performing a plasma treatment without exposing the surface of the insulating film 110bf to the air after the insulating film 110bf is formed. For example, when a PECVD apparatus is used to form the insulating film 110bf, it is preferable to perform the plasma treatment in the PECVD apparatus. This can increase productivity. Specifically, after the insulating film 110bf is formed in the PECVD apparatus, an N ₂ O plasma treatment can be performed continuously.

It is preferable to form a film 137 on the insulating film 110bf (FIG. 24C). It is preferable that the film 137 contains oxygen. By forming the film 137, oxygen can be supplied to the insulating film 110bf.

The conductivity of the film 137 does not matter. At least one of an insulating film, a semiconductor film, and a conductive film can be used as the film 137. For example, aluminum oxide, hafnium oxide, hafnium aluminate, indium oxide, indium tin oxide (ITO), or indium tin oxide containing silicon (ITSO) can be used as the film 137.

As film 137, it is preferable to use an oxide material containing one or more of the same elements as layers 108 and 208. In particular, it is preferable to use a metal oxide applicable to layers 108 and 208. In addition, by using the same material as layers 108 and 208 for film 137, the equipment used to form film 137 can be the same as the equipment used to form the films that become layers 108 and 208, so that productivity can be increased and manufacturing costs can be reduced.

When forming film 137, the higher the oxygen flow ratio of the film formation gas introduced into the processing chamber of the film formation apparatus or the oxygen partial pressure in the processing chamber, the more oxygen can be supplied to insulating film 110bf. The oxygen flow ratio or oxygen partial pressure is, for example, 50% or more and 100% or less, preferably 65% or more and 100% or less, more preferably 80% or more and 100% or less, and even more preferably 90% or more and 100% or less. In particular, it is preferable to set the oxygen flow ratio to 100% and the oxygen partial pressure as close to 100% as possible.

By forming the film 137 in an atmosphere containing oxygen, oxygen can be supplied to the insulating film 110bf during the formation of the film 137, and oxygen can be prevented from being released from the insulating film 110bf. As a result, a large amount of oxygen can be trapped in the insulating film 110bf. Then, a large amount of oxygen can be supplied to the layers 108 and 208 by subsequent heat treatment. As a result, oxygen vacancies ( _VO ) and _VOH in the layers 108 and 208 can be reduced, and a transistor with good electrical characteristics and high reliability can be obtained.

After the film 137 is formed, a heat treatment can be performed. By performing a heat treatment after the film 137 is formed, oxygen can be effectively supplied from the film 137 to the insulating film 110bf.

The temperature of the heat treatment is preferably 150°C or more, 200°C or more, 230°C or more, or 250°C or more, and is less than the distortion point of the substrate, 450°C or less, 400°C or less, 350°C or less, or 300°C or less. The heat treatment can be performed in an atmosphere containing one or more of a noble gas, nitrogen, or oxygen. As the atmosphere containing nitrogen or the atmosphere containing oxygen, dry air (CDA: Clean Dry Air) can be used. Note that it is preferable that the content of hydrogen, water, and the like in the atmosphere is as small as possible. As the atmosphere, it is preferable to use a high-purity gas with a dew point of -60°C or less, preferably -100°C or less. By using an atmosphere containing as little hydrogen, water, and the like as possible, it is possible to prevent hydrogen, water, and the like from being taken into the insulating film 110af and the insulating film 110bf as much as possible. For the heat treatment, an oven, a rapid heating (RTA: Rapid Thermal Annealing) device, and the like can be used. Using an RTA device can shorten the heating process time.

After forming film 137 or after the above-mentioned heat treatment, oxygen can be further supplied to insulating film 110bf via film 137. The above description can be referred to for the method of supplying oxygen, so a detailed description is omitted.

Next, film 137 is removed. There is no particular limitation on the method for removing film 137, but wet etching can be suitably used. By using wet etching, etching of insulating film 110bf can be suppressed when film 137 is removed. This can suppress the thickness of insulating film 110bf from becoming thin, and the thickness of insulating layer 110b can be made uniform.

After removing film 137, oxygen can be further supplied to insulating film 110bf. The above description can be referred to for the method of supplying oxygen. For example, as shown in FIG. 24D, film 139 can be formed on insulating film 110bf, and oxygen can be supplied to insulating film 110bf through film 139. As the treatment, plasma treatment in an atmosphere containing oxygen can be used. FIG. 24D shows a schematic diagram with arrows showing how oxygen is supplied to insulating film 110bf.

The film 139 is preferably a conductive film or a semiconductor film. The film 139 can be a metal oxide film, a metal film, or an alloy film. It is preferable to use a metal oxide as the film 139 and form it by a sputtering method or the like in an atmosphere containing oxygen, because oxygen can be supplied to the insulating film 110bf even during the formation of the film 139.

Since oxygen is supplied to the insulating film 110bf through the film 139, it is preferable that the thickness of the film 139 is thin. Specifically, the thickness of the film 139 is preferably 1 nm or more and 20 nm or less, more preferably 2 nm or more and 15 nm or less, and even more preferably 3 nm or more and 10 nm or less. Typically, it can be about 5 nm.

The substrate temperature during the formation of film 139 is preferably 350°C or less, more preferably 340°C or less, even more preferably 330°C or less, and even more preferably 300°C or less. This allows a large amount of oxygen to be supplied to insulating film 110bf.

By providing film 139, when a bias voltage is applied between the pair of electrodes when oxygen is supplied, ionized oxygen is more likely to be attracted. Therefore, the amount of oxygen supplied to insulating film 110bf can be increased.

As the processing apparatus for supplying oxygen, a dry etching apparatus, an ashing apparatus, or a PECVD apparatus can be suitably used. In particular, it is preferable to use an ashing apparatus. When a bias voltage is applied between a pair of electrodes of the processing apparatus, the bias voltage can be, for example, 10 V or more and 1 kV or less. Alternatively, the power density of the bias can be, for example, 1 W/cm ² or more and 5 W/cm ² or less.

Next, film 139 is removed (Figure 24E). A wet etching method can be suitably used to remove film 139.

By supplying oxygen to the insulating film 110bf, which becomes the insulating layer 110b, the amount of oxygen contained in the insulating layer 110b increases, and the amount of oxygen supplied from the insulating layer 110b to the layers 108 and 208 can be increased, so that even the transistors 100 and 200 with short channel lengths can exhibit good electrical characteristics.

Next, insulating film 110cf, which will become insulating layer 110c, and insulating film 110ef, which will become insulating layer 110e, are formed on insulating film 110bf (FIG. 25A). The description of the formation of insulating film 110cf and insulating film 110ef can be referred to in relation to the formation of insulating film 110af and insulating layer 109, so a detailed description will be omitted.

Next, a conductive film 212f that will become the conductive layer 212b is formed on the insulating film 110ef (FIG. 25B). The conductive film 212f can be preferably formed by a sputtering method.

Then, the conductive film 212f is processed to form the conductive layer 212B (FIG. 25C). The conductive layer 212B has an area that overlaps with the conductive layer 212a, and will later become the conductive layer 212b. The conductive layer 212B can be formed, for example, by a wet etching method.

Subsequently, a resist mask 185 is formed on the insulating film 110ef and the conductive layer 212B (FIG. 25D). The resist mask 185 has an opening 181 and an opening 183. The opening 181 is provided in the region where the opening 141 is to be formed. The opening 183 is provided in the region where the opening 241 and the opening 243 are to be formed.

Then, a part of the conductive layer 212B is removed using the resist mask 185 as a mask, forming a conductive layer 212b having an opening 243. A wet etching method can be suitably used to form the conductive layer 212b.

Then, using the resist mask 185 as a mask, the insulating films 110af, 110bf, 110cf, and 110ef are partially removed to form the insulating layer 110 having the openings 141 and 241 (FIG. 26A). The insulating layer 110 can be preferably formed by dry etching. The formation of the openings 141 exposes a portion of the conductive layer 112, and the formation of the openings 241 exposes a portion of the conductive layer 212a.

By using the same resist mask (here, resist mask 185) to form openings 141, 241, and 243, productivity can be improved. Note that different resist masks can also be used to form openings 141 and openings 241 and 243. It is preferable to use the same resist mask at least to form openings 241 and 243. This allows the top surface shapes of openings 241 and 243 to match or roughly match.

Then, the resist mask 185 is removed (FIG. 26A). The resist mask 185 can be removed by using either or both of a wet etching method and a dry etching method.

Note that although an example of using a resist mask to form the openings 141, 241, and 243 has been shown here, one embodiment of the present invention is not limited to this. A hard mask can also be used to form the openings 141, 241, and 243.

Next, film 108f, which will become layers 108 and 208, is formed so as to cover openings 141, 241, and 243 (FIG. 26B). Film 108f is provided in contact with the upper and side surfaces of insulating layer 110, the upper surface of conductive layer 112, the upper surface of conductive layer 212a, and the upper and side surfaces of conductive layer 212b.

The film 108f is preferably formed by a sputtering method using a metal oxide target. Alternatively, the film 108f is preferably formed by an ALD method. Since the ALD method has high coverage, it can be suitably used to form the film 108f that covers the openings 141, 241, and 243. By using the ALD method, the film 108f can be formed with high coverage on the side surface of the insulating layer 110. In addition, since the ALD method makes it easy to control the film formation rate, a thin film can be formed with good yield. Therefore, when the film 108f is thin, the ALD method can be suitably used. As the ALD method, a thermal ALD method or a PEALD method can be used. In addition, the PECVD method can also be used to form the film 108f. Note that when a metal oxide is used for the film 108f, the film 108f can be called a metal oxide film.

It is preferable that film 108f is a dense film with as few defects as possible. It is also preferable that film 108f is a high-purity film with as few impurities, including hydrogen, as possible reduced. In particular, it is preferable to use a crystalline metal oxide film as film 108f.

When forming the metal oxide film, it is preferable to use oxygen gas. By using oxygen gas, oxygen can be suitably supplied to the insulating layer 110. For example, when an oxide or an oxynitride is used for the insulating layer 110b, oxygen can be suitably supplied to the insulating layer 110b.

By supplying oxygen to the insulating layer 110b, oxygen can be supplied to the layers 108 and 208 in a later step, and oxygen vacancies (V _O ) and V _OH in the layers 108 and 208 can be reduced.

To form a metal oxide film, a mixture of oxygen gas and an inert gas (e.g., helium gas, argon gas, xenon gas, etc.) can be used. Note that the higher the oxygen flow ratio or oxygen partial pressure when forming the metal oxide film, the higher the crystallinity of the metal oxide film can be, and a highly reliable transistor can be realized. On the other hand, the lower the oxygen flow ratio or oxygen partial pressure, the lower the crystallinity and the higher the electrical conductivity of the metal oxide film can be, and the larger the on-current of the transistor can be.

Here, if the oxygen flow ratio or oxygen partial pressure is high, the metal oxide film may become polycrystalline. In the case of a polycrystalline metal oxide film, the grain boundaries become the recombination center, and carriers may be captured, resulting in a small on-current of the transistor. Therefore, it is preferable to adjust the oxygen flow ratio or oxygen partial pressure so that the metal oxide film does not become polycrystalline. Since the ease with which the metal oxide film becomes polycrystalline differs depending on the composition of the metal oxide film, it is preferable to adjust the oxygen flow ratio or oxygen partial pressure according to the composition of the metal oxide film.

The higher the substrate temperature when forming the metal oxide film, the higher the crystallinity and the denser the metal oxide film can be. This allows for a highly reliable transistor. On the other hand, the lower the substrate temperature, the lower the crystallinity and the higher the electrical conductivity of the metal oxide film can be. This allows for a transistor with a large on-state current.

The substrate temperature during the formation of the metal oxide film is preferably from room temperature to 250°C, more preferably from room temperature to 200°C, and even more preferably from room temperature to 140°C. For example, a substrate temperature of from room temperature to 140°C is preferable because it increases productivity. In addition, by forming the metal oxide film at room temperature or without heating the substrate, the crystallinity can be reduced.

Note that if the substrate temperature is too high, the metal oxide film may have a polycrystalline structure. It is preferable to vary the substrate temperature depending on the composition of the material used for the metal oxide film.

The metal oxide film can be formed, for example, by the ALD method using a precursor containing the constituent metal elements and an oxidizing agent.

For example, when forming an In-Ga-Zn oxide, three precursors can be used: a precursor containing indium, a precursor containing gallium, and a precursor containing zinc. Or, two precursors can be used: a precursor containing indium, and a precursor containing gallium and zinc.

Examples of precursors containing indium include triethylindium, trimethylindium, tris(2,2,6,6-tetramethyl-3,5-heptanedionate)indium, cyclopentadienylindium, indium(III) chloride, (3-(dimethylamino)propyl)dimethylindium, and [1,1,1-trimethyl-N-(trimethylsilyl)amide]-indium.

Examples of precursors containing gallium include trimethylgallium, triethylgallium, gallium trichloride, tris(dimethylamido)gallium(III), gallium(III) acetylacetonate, tris(2,2,6,6-tetramethyl-3,5-heptanedionate)gallium, dimethylchlorogallium, and diethylchlorogallium.

Examples of aluminum-containing precursors include aluminum chloride and trimethylaluminum.

Examples of precursors containing tin include tin(IV) chloride and tetrakis(dimethylamido)tin.

Examples of zinc-containing precursors include dimethylzinc, diethylzinc, zinc bis(2,2,6,6-tetramethyl-3,5-heptanedionate), and zinc chloride.

Oxidizing agents include, for example, ozone, oxygen, and water.

Methods for controlling the composition of the resulting film include adjusting one or more of the type of raw material gas, the flow ratio of the raw material gas, the time for which the raw material gas is flowed, and the order in which the raw material gas is flowed. By adjusting these, it is possible to control the composition of the metal oxide film. Furthermore, by adjusting these, it is also possible to form a metal oxide film whose composition changes continuously.

Before forming the metal oxide film, it is preferable to perform at least one of a treatment for removing impurities (e.g., water, hydrogen, and organic substances) adsorbed on the surface of the insulating layer 110 and a treatment for supplying oxygen into the insulating layer 110. For example, a heat treatment can be performed at a temperature of 70° C. or higher and _{200° C. or lower in a reduced pressure atmosphere. Alternatively, a plasma treatment can be performed in an atmosphere containing oxygen. Alternatively, oxygen can be supplied to the insulating layer 110 by a plasma treatment in an atmosphere containing an oxidizing gas such as nitrous oxide (N 2} O). When a plasma treatment containing nitrous oxide gas is performed, oxygen can be supplied while the organic substances on the surface of the insulating layer 110 are suitably removed. After such a treatment, it is preferable to continuously form a metal oxide film without exposing the surface of the insulating layer 110 to the air.

When layers 108 and 208 have a laminated structure, it is preferable to deposit the next metal oxide film in succession after depositing the first metal oxide film without exposing the surface to the atmosphere.

When layers 108 and 208 each have a laminated structure, all layers constituting layers 108 and 208 can be formed by the same deposition method (e.g., sputtering or ALD). Alternatively, different deposition methods can be used for different layers. For example, when layers 108 and 208 each have a two-layer structure of a first metal oxide layer and a second metal oxide layer on the first metal oxide layer, the first metal oxide layer can be deposited by sputtering, and the second metal oxide layer can be deposited by ALD.

Next, film 108f is processed into islands to form layers 108 and 208 (Figure 26C).

The layers 108 and 208 can be preferably formed by wet etching. At this time, a part of the conductive layer 212b in the region that does not overlap with the layer 208 may be etched and thinned. Similarly, a part of the insulating layer 110 in the region that does not overlap with the layers 108, 208, and the conductive layer 212b may be etched and thinned. For example, in the region of the insulating layer 110 that does not overlap with the layers 108, 208, and the conductive layer 212b, a part of the insulating layer 110e may be removed by etching, and a recess may be formed in the insulating layer 110e. In addition, in the etching of the film 108f, by using a material with a high selectivity for the insulating layer 110e, the thickness of the insulating layer 110e can be prevented from becoming thin.

After the film 108f is formed or after the film 108f is processed into the layers 108 and 208, it is preferable to perform heat treatment. The heat treatment can remove impurities (e.g., hydrogen and water) contained in the film 108f or the layers 108 and 208 or adsorbed on the surfaces. The heat treatment can also improve the film quality of the film 108f or the layers 108 and 208 (e.g., reduce defects or improve crystallinity).

By the heat treatment, oxygen can be supplied from the insulating layer 110b to the film 108f, or to the layer 108 and the layer 208. In this case, it is more preferable to perform the heat treatment before processing into the layer 108 and the layer 208. Since the above description can be referred to for the heat treatment, a detailed description is omitted.

Note that this heat treatment does not have to be performed if it is not necessary. Also, instead of performing the heat treatment here, it is possible to combine this with a heat treatment performed in a later process. Also, a later process in which heat is applied (e.g., a film formation process) may also serve as this heat treatment.

After the film 108f is formed or after the film 108f is processed into the layer 108 and the layer 208, oxygen can be supplied to the film 108f, or the layer 108 and the layer 208. This can reduce oxygen vacancies (V _O ) and V _O H in the film 108f, or the layer 108 and the layer 208. The above description can be referred to for the method of supplying oxygen. For example, microwave processing can be performed in an atmosphere containing oxygen. In addition, by supplying oxygen while heating the substrate, the crystallinity of the film 108f, or the layer 108 and the layer 208 can be improved, and impurities (e.g., hydrogen and water) contained in the film 108f, or the layer 108 and the layer 208 or adsorbed on the surface can also be removed. The substrate temperature during heating is preferably higher than room temperature (e.g., 25° C.) and not higher than 600° C., more preferably 100° C. or higher and not higher than 600° C., and even more preferably 300° C. or higher and not higher than 450° C. The substrate temperature is preferably 100° C. to 700° C., more preferably 300° C. to 450° C. This can further increase the crystallinity of the film 108f, or the layer 108 and the layer 208. When the substrate temperature increases with the treatment of supplying oxygen, the treatment can increase the crystallinity and remove impurities.

Then, insulating layer 106 is formed covering layer 108, layer 208, conductive layer 212b, and insulating layer 110 (FIG. 26D). For example, PECVD, sputtering, or ALD can be suitably used to form insulating layer 106.

In the case where an oxide semiconductor is used for the layers 108 and 208, the insulating layer 106 preferably functions as a barrier film that suppresses diffusion of oxygen. The insulating layer 106 suppresses diffusion of oxygen, thereby suppressing desorption of oxygen from the layers 108 and 208, and thus an increase in oxygen vacancy ( _VO ) in the layers 108 and 208 can be suppressed. Furthermore, oxygen contained in the layers 108 and 208 is suppressed from diffusing into the conductive layers 104 and 204 through the insulating layer 106, and thus oxidation of the conductive layers 104 and 204 can be suppressed. As a result, a transistor having favorable electrical characteristics and high reliability can be obtained.

By increasing the temperature during the formation of the insulating layer 106 functioning as a gate insulating layer, an insulating layer with fewer defects can be obtained. However, if the temperature during the formation of the insulating layer 106 is high, oxygen is released from the layers 108 and 208, and oxygen vacancies (V _O ) and V _O H in the layers 108 and 208 may increase. The substrate temperature during the formation of the insulating layer 106 is preferably 180° C. to 450° C., more preferably 200° C. to 450° C., more preferably 250° C. to 450° C., even more preferably 300° C. to 450° C., and even more preferably 300° C. to 400° C. By setting the substrate temperature during the formation of the insulating layer 106 within the above range, defects in the insulating layer 106 can be reduced and oxygen can be prevented from being released from the layers 108 and 208. Therefore, a transistor exhibiting good electrical characteristics and high reliability can be obtained.

Before the insulating layer 106 is formed, a plasma treatment can be performed on the surfaces of the layers 108 and 208. The plasma treatment can reduce impurities such as water adsorbed on the surfaces of the layers 108 and 208. Therefore, impurities at the interfaces between the layers 108 and 208 and the insulating layer 106 can be reduced, and a highly reliable transistor can be realized. This is particularly suitable for the case where the surfaces of the layers 108 and 208 are exposed to the air between the formation of the layers 108 and 208 and the formation of the insulating layer 106. The plasma treatment can be performed in an atmosphere of oxygen, ozone, nitrogen, nitrous oxide, argon, or the like. It is also preferable that the plasma treatment and the formation of the insulating layer 106 are performed successively without exposure to the air.

After the insulating layer 106 is formed, oxygen can be supplied to the insulating layer 106. The above description can be referred to for a method of supplying oxygen. For example, microwave treatment can be performed in an atmosphere containing oxygen. The oxygen supplied to the insulating layer 106 is further supplied to the layer 108 and the layer 208, and oxygen vacancies (V _O ) and V _O H in the layer 108 and the layer 208 can be reduced. Therefore, a transistor having good electrical characteristics and high reliability can be obtained. In addition, by supplying oxygen while heating the substrate, impurities (e.g., hydrogen and water) contained in the insulating layer 106 or adsorbed on the surface can be removed and defects in the insulating layer 106 can be reduced. By reducing defects in the insulating layer 106 that functions as a gate insulating layer of the transistors 100 and 200, the transistors 100 and 200 can have good electrical characteristics. The above description of the heat treatment can be referred to for the substrate temperature during heating. Note that when the substrate temperature is increased by the treatment of supplying oxygen, the treatment may remove impurities and reduce defects.

Next, impurity element 187 is supplied to layer 108 and layer 208 (FIG. 27A). The above-mentioned first element can be suitably used as impurity element 187. By supplying impurity element 187, regions 108Da, 108Db, 208Da, and 208Db are formed.

The impurity element 187 is preferably supplied from a direction perpendicular or approximately perpendicular to the top surface of the substrate 102. Furthermore, the impurity element 187 is preferably supplied to the layer 108 and the layer 208 through the insulating layer 106. At this time, the impurity element 187 is also supplied to the insulating layer 106. The impurity element 187 may also be supplied to the insulating layer 110. In particular, the impurity element 187 may also be supplied to a region of the insulating layer 110 that does not overlap with any of the layer 108, the layer 208, and the conductive layer 212b. In the region of the insulating layer 110, the concentration of the impurity element 187 becomes higher at a position closer to the insulating layer 106. For example, the concentration of the impurity element 187 in the insulating layer 110e is higher than the concentration of the impurity element 187 in the insulating layer 110a.

The elements that can be used for the impurity element 187 are as described above. It is more preferable to use boron or phosphorus as the impurity element 187. By using an element that becomes stable when bonded with oxygen as the impurity element 187, it is possible to realize regions 108Da, 108Db, 208Da, and 208Db that are stable and have low electrical resistance.

Ion implantation is preferably used to supply the impurity element (specifically, the first element). By using ion implantation, which ionizes the raw material gas and supplies the ions after mass separation, the purity of the supplied impurity element can be increased. In addition, since ion implantation equipment is also used in the manufacture of Si transistors such as LTPS transistors, it is preferable because equipment from existing LTPS manufacturing lines can be reused and no new capital investment is required. This makes it possible to reduce the initial capital investment costs associated with the manufacture of semiconductor devices.

When hydrogen is also supplied as the impurity element 187, it can be supplied without mass separation. This can increase productivity. It is preferable to use both the first element and hydrogen as the impurity element 187, and it is even more preferable to use both boron or phosphorus and hydrogen. By using both an element that becomes stable when bonded with oxygen and hydrogen as the impurity element 187, it is easier to lower the electrical resistance of regions 108Da, 108Db, 208Da, and 208Db, and the low electrical resistance state can be stably maintained.

The supply of the impurity element 187 can be controlled by setting conditions such as acceleration energy and dose amount, taking into consideration the type of impurity element 187, the composition, film density, and thickness of each of the insulating layer 106, layer 108, and layer 208. It is preferable to set conditions so that the concentration of the impurity element 187 is higher in regions 108Da and 108Db than in region 108M, and the concentration of the impurity element 187 is higher in regions 208Da and 208Db than in region 208M. This allows an optimal amount of impurity element 187 to be supplied to regions 108Da, 108Db, 208Da, and 208Db.

A gas containing the above-mentioned impurity element 187 can be used as a source gas _for the impurity element 187. When boron is supplied, typically, _B2H6 gas, _BF3 gas, or the like can be used. When phosphorus is supplied, typically, _PH3 gas can be used. Also, a mixed gas in which these source gases are diluted with hydrogen or a noble gas can be used.

Other examples of the source gas that can be _used include _CH4 , _N2 , _NH3 , _AlH3 , _AlCl3 , _SiH4 , _Si2H6 , _F2 , HF, _H2 , _{( C5H5} ) _2Mg , and noble gases. The source material used to supply the impurity element 187 is not limited to gas, and a solid or liquid may be heated and vaporized for use.

For example, it is preferable to use a gas containing boron and hydrogen to supply boron and hydrogen as the impurity element 187. In this case, the impurity element 187 can be supplied without mass separation, and it is easy to reduce the electrical resistance of the regions 108Da, 108Db, 208Da, and 208Db, which is preferable because it is possible to improve the productivity and characteristics of the semiconductor device.

The method of supplying the impurity element 187 is not limited, and for example, plasma processing or processing utilizing thermal diffusion by heating can be used. In the case of the plasma processing method, the impurity element 187 can be supplied by generating plasma in a gas atmosphere containing the impurity element 187 to be supplied and performing plasma processing. As an apparatus for generating the above plasma, a dry etching apparatus, an ashing apparatus, a plasma CVD apparatus, a high density plasma CVD apparatus, etc. can be used.

In one embodiment of the present invention, the impurity element 187 is supplied to the layers 108 and 208 through the insulating layer 106. This can prevent the crystallinity of the layers 108 and 208 from decreasing when the impurity element 187 is supplied. Therefore, an increase in electrical resistance due to a decrease in crystallinity can be prevented.

If the insulating layer 106 is formed after the impurity element 187 is supplied, the inside of the deposition chamber for the insulating layer 106 may be contaminated. For this reason, it is preferable to supply the impurity element 187 after the insulating layer 106 is formed.

On the other hand, the impurity element 187 can be directly supplied to the layers 108 and 208, and then the insulating layer 106 can be formed on the layers 108 and 208. This can prevent the insulating layer 106 from being damaged by the supply of the impurity element 187.

The supplying step of the impurity element 187 is preferably performed while heating the substrate 102. This makes it possible to repair damage to the layers 108 and 208 that occurs when the impurity element 187 is supplied. That is, the supply of the impurity element 187 to the layers 108 and 208 and the repair of damage caused by the supplying can be performed in parallel. In addition, damage to the insulating layer 106 that occurs when the impurity element 187 is supplied can also be repaired. Note that one embodiment of the present invention is not limited thereto, and the supplying step of the impurity element 187 can be performed without heating the substrate 102.

The substrate temperature during the supply process of the impurity element 187 is preferably 150°C or higher and lower than the distortion point of the substrate, more preferably 200°C or higher and 500°C or lower, even more preferably 200°C or higher and 450°C or lower, even more preferably 250°C or higher and 400°C or lower, even more preferably 250°C or higher and 350°C or lower, or 300°C or higher and 400°C or lower, even more preferably 300°C or higher and 350°C or lower.

After supplying the impurity element 187, a heat treatment can be performed. By performing this heat treatment, it is possible to repair damage that has been caused to the layer 108, the layer 208, and the insulating layer 106 during the supplying process of the impurity element 187. If the temperature of the heat treatment is too high, there is a risk that the electrical resistance of each of the regions 108Da, 108Db, 208Da, and 208Db, the contact resistance between the region 108Da and the conductive layer 112, the contact resistance between the region 208Da and the conductive layer 212a, and the contact resistance between the region 208Db and the conductive layer 212b will increase. Therefore, the temperature of the heat treatment after supplying the impurity element 187 is preferably 150°C or higher and lower than the distortion point of the substrate, more preferably 200°C or higher and 500°C or lower, even more preferably 200°C or higher and 450°C or lower, even more preferably 250°C or higher and 400°C or lower, even more preferably 250°C or higher and 350°C or lower, or even more preferably 300°C or higher and 400°C or lower, even more preferably 300°C or higher and 350°C or lower.

By using an element that becomes stable when bonded with oxygen as the impurity element 187, it is possible to prevent the impurity element 187 from being detached during the process of applying heat. Therefore, after the impurity element 187 is supplied, the electrical resistance of the regions 108Da, 108Db, 208Da, and 208Db can be kept low even after the process of applying heat.

Next, a conductive film is formed on the insulating layer 106, and the conductive film is processed to form the conductive layer 104 and the conductive layer 204 (Figure 27B). The conductive film can be formed by, for example, a sputtering method, a thermal CVD method (including a MOCVD method), or an ALD method.

Next, insulating layer 195 is formed (Figure 9A). The insulating layer 195 can be preferably formed using the PECVD method.

By the above steps, a semiconductor device 10D according to one embodiment of the present invention can be manufactured.

(Embodiment 3)
In this embodiment, a display device of one embodiment of the present invention will be described with reference to FIGS.

The display device of this embodiment can be a high-resolution display device or a large display device. Therefore, the display device of this embodiment can be used in electronic devices with relatively large screens, such as television devices, desktop or notebook computers, computer monitors, digital signage, and large game machines such as pachinko machines, as well as in the display units of digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, personal digital assistants, and audio playback devices.

The display device of this embodiment can be a high-definition display device. Therefore, the display device of this embodiment can be used, for example, in the display section of wristwatch-type and bracelet-type information terminals (wearable devices), as well as in the display section of wearable devices that can be worn on the head, such as VR devices such as head-mounted displays (HMDs) and glasses-type AR devices.

The semiconductor device of one embodiment of the present invention can be used in a display device or a module having the display device. Examples of the module having the display device include a module in which a connector such as a flexible printed circuit (hereinafter, referred to as FPC) or a TCP (Tape Carrier Package) is attached to the display device, and a module in which an integrated circuit (IC) is mounted by a COG (chip on glass) method, a COF (chip on film) method, or the like.

The display device of this embodiment may have a function as a touch panel. For example, various detection elements (also called sensor elements) that can detect the proximity or contact of a detectable object such as a finger can be applied to the display device.

Sensor types include, for example, capacitive type, resistive film type, surface acoustic wave type, infrared type, optical type, and pressure sensitive type.

Examples of the capacitance type include the surface capacitance type and the projected capacitance type. Examples of the projected capacitance type include the self-capacitance type and the mutual capacitance type. The mutual capacitance type is preferable because it allows simultaneous multi-point detection.

Examples of touch panels include out-cell, on-cell, and in-cell types. Note that an in-cell touch panel is one in which electrodes constituting a sensing element are provided on one or both of the substrate supporting the display element (also called a display device) and the opposing substrate.

<Configuration Example 1 of Display Device>
FIG. 28A shows a perspective view of a display device 50A.

Display device 50A has a configuration in which substrate 152 and substrate 151 are bonded together. In FIG. 28A, substrate 152 is indicated by a dashed line.

The display device 50A has a display section 162, a connection section 140, a circuit section 164, a conductive layer 165, etc. FIG. 28A shows an example in which an IC 173 and an FPC 172 are mounted on the display device 50A. Therefore, the configuration shown in FIG. 28A can also be said to be a display module having the display device 50A, an IC, and an FPC.

The connection portion 140 is provided on the outside of the display portion 162. The connection portion 140 can be provided along one side or multiple sides of the display portion 162. There may be one or multiple connection portions 140. FIG. 28A shows an example in which the connection portion 140 is provided so as to surround the four sides of the display portion 162. The connection portion 140 electrically connects the common electrode of the display element and the conductive layer, and can supply a potential to the common electrode.

The circuit portion 164 has, for example, a scanning line driver circuit (also called a gate driver). The circuit portion 164 may also have both a scanning line driver circuit and a signal line driver circuit (also called a source driver).

The conductive layer 165 has a function of supplying signals and power to the display portion 162 and the circuit portion 164. The signals and power are input to the conductive layer 165 from the outside via the FPC 172, or are input to the conductive layer 165 from the IC 173.

FIG. 28A shows an example in which an IC 173 is provided on a substrate 151 by a COG method or a COF method. For example, an IC having one or both of a scanning line driver circuit and a signal line driver circuit can be used as the IC 173. Note that the display device 50A and the display module may be configured without an IC. Also, the IC may be mounted on an FPC by a COF method or the like.

The semiconductor device of one embodiment of the present invention can be used, for example, as one or both of the display portion 162 and the circuit portion 164 of the display device 50A.

For example, when the semiconductor device of one embodiment of the present invention is applied to a pixel circuit of a display device, the area occupied by the pixel circuit can be reduced, and a high-definition display device can be obtained. Furthermore, when the semiconductor device of one embodiment of the present invention is applied to a driver circuit of a display device (e.g., one or both of a gate line driver circuit and a source line driver circuit), the area occupied by the driver circuit can be reduced, and a display device with a narrow frame can be obtained. Furthermore, since the semiconductor device of one embodiment of the present invention has good electrical characteristics, the reliability of the display device can be improved by using it in a display device.

The display unit 162 is an area in the display device 50A that displays an image, and has a number of periodically arranged pixels 210. Figure 28A shows an enlarged view of one pixel 210.

There are no particular limitations on the pixel arrangement in the display device of this embodiment, and various methods can be applied. Examples of pixel arrangements include a stripe arrangement, an S-stripe arrangement, a matrix arrangement, a delta arrangement, a Bayer arrangement, and a Pentile arrangement.

The pixel 210 shown in FIG. 28A has a pixel 230R that emits red light, a pixel 230G that emits green light, and a pixel 230B that emits blue light. A full-color display can be realized by configuring one pixel 210 with pixels 230R, 230G, and 230B. Each of pixels 230R, 230G, and 230B functions as a subpixel. In addition, the display device 50A shown in FIG. 28A shows an example in which pixels 230 that function as subpixels are arranged in a stripe array. The number of subpixels that configure one pixel 210 is not limited to three, and may be four or more. For example, the pixel 210 may have four subpixels that emit R, G, B, and white (W) light. Or, the pixel 210 may have four subpixels that emit R, G, B, and Y light.

Pixel 230R, pixel 230G, and pixel 230B each have a display element and a circuit that controls the driving of the display element.

Various elements can be used as display elements, including liquid crystal elements (also called liquid crystal devices) and light-emitting elements. Other elements that can be used include shutter-type or optical interference-type MEMS (Micro Electro Mechanical Systems) elements, display elements that use microcapsules, electrophoresis, electrowetting, or electronic liquid powder (registered trademark) methods, etc. Also usable are QLEDs (Quantum-dot LEDs) that use a light source and color conversion technology using quantum dot materials.

Display devices using liquid crystal elements include, for example, transmissive liquid crystal display devices, reflective liquid crystal display devices, and semi-transmissive liquid crystal display devices.

Modes that can be used in displays using liquid crystal elements include, for example, vertical alignment (VA) mode, FFS (Fringe Field Switching) mode, IPS (In-Plane Switching) mode, TN (Twisted Nematic) mode, and ASM (Axially Symmetrically aligned Micro-cell) mode. Examples of the VA mode include the MVA (Multi-Domain Vertical Alignment) mode, the PVA (Patterned Vertical Alignment) mode, and the ASV (Advanced Super View) mode.

Liquid crystal materials that can be used in liquid crystal elements include, for example, thermotropic liquid crystal, low molecular weight liquid crystal, polymer liquid crystal, polymer dispersed liquid crystal (PDLC: Polymer Dispersed Liquid Crystal), polymer network liquid crystal (PNLC: Polymer Network Liquid Crystal), ferroelectric liquid crystal, and antiferroelectric liquid crystal. Depending on the conditions, these liquid crystal materials can exhibit cholesteric phase, smectic phase, cubic phase, chiral nematic phase, isotropic phase, blue phase, etc. In addition, either positive type liquid crystal or negative type liquid crystal can be used as the liquid crystal material, and can be selected according to the mode or design to be applied.

Light-emitting elements include, for example, self-emitting light-emitting elements such as LEDs (Light Emitting Diodes), OLEDs (Organic LEDs), and semiconductor lasers. LEDs can also include, for example, mini LEDs and micro LEDs.

Light-emitting materials that light-emitting elements have include, for example, materials that emit fluorescence (fluorescent materials), materials that emit phosphorescence (phosphorescent materials), materials that exhibit thermally activated delayed fluorescence (thermally activated delayed fluorescence (TADF) materials), and inorganic compounds (quantum dot materials, etc.).

The light-emitting element can emit light of infrared, red, green, blue, cyan, magenta, yellow, or white. The color purity can be increased by providing the light-emitting element with a microcavity structure.

Of the pair of electrodes that the light-emitting element has, one electrode functions as an anode and the other electrode functions as a cathode.

Note that the display device of one embodiment of the present invention may be a top-emission type that emits light in a direction opposite to the substrate on which the light-emitting elements are formed, a bottom-emission type that emits light toward the substrate on which the light-emitting elements are formed, or a dual-emission type that emits light on both sides.

FIG. 28B is a block diagram illustrating the display device 50A. The display device 50A has a display unit 162 and a circuit unit 164. The display unit 162 has a plurality of periodically arranged pixels 230 (pixels 230[1,1] to 230[m,n], where m and n are each independently an integer of 2 or more). The circuit unit 164 has a first drive circuit unit 231 and a second drive circuit unit 232.

The circuit included in the first drive circuit unit 231 functions, for example, as a scanning line drive circuit. The circuit included in the second drive circuit unit 232 functions, for example, as a signal line drive circuit. Note that some kind of circuit may be provided at a position facing the first drive circuit unit 231 across the display unit 162. Some kind of circuit may be provided at a position facing the second drive circuit unit 232 across the display unit 162.

The circuit portion 164 may include various circuits such as a shift register circuit, a level shifter circuit, an inverter circuit, a latch circuit, an analog switch circuit, a demultiplexer circuit, and a logic circuit. The circuit portion 164 may include transistors and capacitors. The transistors in the circuit portion 164 may be formed in the same process as the transistors in the pixel 230.

Display device 50A has wirings 236 that are arranged in parallel or approximately parallel and whose potential is controlled by a circuit included in first drive circuit section 231, and wirings 238 that are arranged in parallel or approximately parallel and whose potential is controlled by a circuit included in second drive circuit section 232. Note that FIG. 28B shows an example in which wirings 236 and 238 are connected to pixel 230. However, wirings 236 and 238 are just an example, and wirings connected to pixel 230 are not limited to wirings 236 and 238.

The semiconductor device of one embodiment of the present invention has a vertical transistor (VFET) that has a channel length of submicron size and a large on-state current. An oxide semiconductor (OS) can be preferably used for a channel formation region of the transistor, and the transistor can have a small off-state current. The semiconductor device of one embodiment of the present invention can be preferably used for one or both of the display portion 162 and the circuit portion 164. In addition, the semiconductor device of one embodiment of the present invention can be used for both the display portion 162 and the circuit portion 164, that is, all the transistors included in the display device can be OS transistors. By using OS transistors for all the transistors included in the display device in this manner, it is possible to achieve an effect of keeping the manufacturing cost low.

<Example of pixel circuit configuration>
29A shows an example of the configuration of the pixel 230. The pixel 230 includes a pixel circuit 51 and a light-emitting device 61.

The pixel circuit 51 has a transistor 52A, a transistor 52B, and a capacitor 53. The pixel circuit 51 is a 2Tr1C type pixel circuit having two transistors and one capacitor. Note that there is no particular limitation on the pixel circuit that can be applied to the display device of one embodiment of the present invention.

The anode of the light-emitting device 61 is electrically connected to one of the source and drain of the transistor 52B and one electrode of the capacitance element 53. The other of the source and drain of the transistor 52B is electrically connected to the wiring ANO. The gate of the transistor 52B is electrically connected to one of the source and drain of the transistor 52A and the other electrode of the capacitance element 53. The other of the source and drain of the transistor 52A is electrically connected to the wiring SL. The gate of the transistor 52A is electrically connected to the wiring GL. The cathode of the light-emitting device 61 is electrically connected to the wiring VCOM.

The wiring GL corresponds to the wiring 236, and the wiring SL corresponds to the wiring 238. The wiring VCOM is a wiring that provides a potential for supplying a current to the light-emitting device 61. The transistor 52A has a function of controlling the conductive state or non-conductive state between the wiring SL and the gate of the transistor 52B based on the potential of the wiring GL. For example, VDD is supplied to the wiring ANO, and VSS is supplied to the wiring VCOM.

Transistor 52A functions as a selection transistor for controlling the selection state of pixel 230. Transistor 52B functions as a drive transistor for controlling the amount of current flowing through light-emitting device 61. Capacitive element 53 has the function of holding the gate potential of transistor 52B. The intensity of light emitted by light-emitting device 61 is controlled according to an image signal supplied to the gate of transistor 52B.

The above-mentioned semiconductor device can be used for the pixel circuit 51. This allows the area occupied by the pixel circuit 51 to be reduced, resulting in a high-definition display device. Furthermore, when the distance between a transistor and an element (e.g., a transistor and a capacitor) or a wiring electrically connected to the transistor is short, one of the transistors 100 to 100H can be preferably used as the transistor. This allows for higher definition. On the other hand, when the distance between a transistor and an element or wiring electrically connected to the transistor is long, one of the transistors 200 to 200H can be preferably used as the transistor. This allows for a display device that operates at high speed.

A display device that operates at high speed can be obtained by using any one of the transistors 100 to 100H and the transistors 200 to 200H, which have a short channel length and a large on-state current, as the transistor 52A functioning as a selection transistor. It is more preferable that the transistor 52B functioning as a driving transistor has high saturation. For example, any one of the transistors 100F, 100H, 200F, and 200H, which have a backgate electrode, can be preferably used as the transistor 52B. Note that a transistor without a backgate electrode can also be used as the transistor 52B.

By using a plurality of transistors and capacitors in a pixel circuit, a high-performance display device can be obtained. By applying a semiconductor device that is one embodiment of the present invention, the area occupied can be reduced even if the number of transistors and capacitors is increased, and a high-performance and high-resolution display device can be obtained. For example, a display device with a resolution of 300 ppi or more, 500 ppi or more, 1000 ppi or more, 2000 ppi or more, or 3000 ppi or more can be realized.

The semiconductor device according to one embodiment of the present invention can reduce the area occupied by the device, and therefore can increase the aperture ratio of pixels in a display device having a bottom emission structure. For example, a display device having an aperture ratio of 50% or more, 55% or more, or 60% or more can be realized.

In this specification, the aperture ratio refers to the ratio of the area of the region through which light is emitted to the area of the pixel.

FIG. 29B shows an example of a configuration different from that of pixel 230 shown in FIG. 29A. Pixel 230 has a pixel circuit 51A and a light-emitting device 61.

Pixel circuit 51A differs from pixel circuit 51 shown in FIG. 29A mainly in that it has transistor 52C. Pixel circuit 51A has transistors 52A, 52B, and 52C, and a capacitance element 53. Pixel circuit 51A is a 3Tr1C type pixel circuit having three transistors and one capacitance element.

One of the source and drain of transistor 52C is electrically connected to one of the source and drain of transistor 52B. The other of the source and drain of transistor 52C is electrically connected to wiring V0. For example, a reference potential is supplied to wiring V0. The gate of transistor 52C is electrically connected to wiring GL.

Transistor 52C has a function of controlling the conductive state or non-conductive state between one of the source electrode and drain electrode of transistor 52B and wiring V0 based on the potential of wiring GL. The reference potential of wiring V0 provided via transistor 52C can suppress variations in the gate-source potential of transistor 52B.

The wiring V0 can be used to obtain a current value that can be used to set pixel parameters. Specifically, the wiring V0 can function as a monitor line for outputting the current flowing through the transistor 52B or the current flowing through the light-emitting device 61 to the outside. The current output to the wiring V0 can be converted to a voltage by a source follower circuit and output to the outside. Alternatively, it can be converted to a digital signal by an AD converter and output to the outside.

A backgate can be provided for some or all of the transistors included in the pixel circuit 51. The pixel circuit 51B shown in FIG. 29C shows a configuration in which the transistor 52B of the pixel circuit 51 shown in FIG. 29A has a backgate, and the backgate is electrically connected to one of the source and drain of the transistor 52B. The pixel circuit 51C shown in FIG. 29D shows a configuration in which the transistor 52B of the pixel circuit 51A shown in FIG. 29B has a backgate, and the backgate is electrically connected to one of the source and drain of the transistor 52B. This can improve reliability. Note that the backgate of the transistor 52B can also be electrically connected to the gate of the transistor 52B. This can increase the on-current of the transistor 52B.

FIG. 30A shows an example of a configuration different from the pixel 230 described above. The pixel 230 has a pixel circuit 51D and a light-emitting device 61.

Pixel circuit 51D has transistor M11, transistor M12, transistor M13, transistor M14, transistor M15, transistor M16, capacitance element C11, and capacitance element C12. Pixel circuit 51D is a 6Tr2C type pixel circuit having six transistors and two capacitance elements.

The anode of the light-emitting device 61 is electrically connected to one of the source and drain of the transistor M15. The cathode of the light-emitting device 61 is electrically connected to the wiring VCOM. The other of the source and drain of the transistor M15 is electrically connected to one of the source and drain of the transistor M12, one of the source and drain of the transistor M13, one of the source and drain of the transistor M16, one electrode of the capacitance element C11, and one electrode of the capacitance element C12. The gate of the transistor M12 is electrically connected to one of the source and drain of the transistor M11, the other of the source and drain of the transistor M13, and the other electrode of the capacitance element C11. The backgate of the transistor M12 is electrically connected to one of the source and drain of the transistor M14, and the other electrode of the capacitance element C12.

The other of the source and drain of transistor M11 is electrically connected to wiring SL. The other of the source and drain of transistor M12 is electrically connected to wiring ANO. The other of the source and drain of transistor M14 is electrically connected to wiring V0. The other of the source and drain of transistor M16 is electrically connected to wiring V1. For example, a constant potential is supplied to wiring V1. The gate of transistor M11 and the gate of transistor M16 are electrically connected to wiring GL1. The gate of transistor M13 and the gate of transistor M14 are electrically connected to wiring GL2. The gate of transistor M15 is electrically connected to wiring GL3.

The transistor M11 functions as a selection transistor that controls the conductive state or non-conductive state between the gate of the transistor M12 and the wiring SL. The transistor M12 functions as a drive transistor that controls the current flowing through the light-emitting device 61. The transistor M14 has a function of supplying the potential of the wiring V0 to the back gate of the transistor M12. The threshold voltage can be controlled by supplying a constant potential to the back gate of the transistor M12. The capacitance element C11 has a function of holding the gate potential of the transistor M12. The capacitance element C12 has a function of holding the back gate potential of the transistor M12. The pixel circuit 51D has a so-called internal threshold voltage correction function that corrects the threshold voltage of the transistor M12 by the back gate. Specifically, the capacitance element C12 is made to hold a back gate potential such that the threshold voltage of the transistor M12 becomes 0V. This makes it possible to correct the threshold voltage of the transistor M12 to a constant value of 0V or close to 0V, regardless of the variation in the threshold voltage of the transistor and deterioration over time.

FIG. 30B shows an example of a configuration different from that of the pixel 230 described above. The pixel 230 has a pixel circuit 51E and a liquid crystal device 62.

The pixel circuit 51E has a transistor 52A and a capacitor 53. One of the source and drain of the transistor 52A is electrically connected to a wiring SL, and the gate of the transistor 52A is electrically connected to a wiring GL. The other of the source and drain of the transistor 52A is electrically connected to one terminal of the capacitor 53 and the liquid crystal device 62. The other terminal of the capacitor 53 is electrically connected to a wiring VCOM.

As in pixel circuit 51F shown in FIG. 30C, transistor 52A can also have a backgate. FIG. 30C shows a configuration in which the backgate of transistor 52A is electrically connected to the gate.

FIG. 31A shows an example of a cross section of the display device 50A when a portion of the area including the FPC 172, a portion of the circuit section 164, a portion of the display section 162, a portion of the connection section 140, and a portion of the area including the end portion are cut away.

The display device 50A shown in FIG. 31A has transistor 207D, transistor 205R, transistor 205G, transistor 207G, transistor 207B, light-emitting element 130R, light-emitting element 130G, light-emitting element 130B, etc. between substrate 151 and substrate 152. Light-emitting element 130R is a display element included in pixel 230R that emits red light, light-emitting element 130G is a display element included in pixel 230G that emits green light, and light-emitting element 130B is a display element included in pixel 230B that emits blue light.

The display device 50A uses an SBS structure. The SBS structure allows the material and configuration to be optimized for each light-emitting element, expanding the range of material and configuration options, making it easier to improve brightness and reliability.

The display device 50A is a top emission type. In a top emission type, transistors and the like can be arranged so as to overlap the light emitting region of the light emitting element, so the aperture ratio of the pixel can be increased compared to a bottom emission type.

Transistor 207D, transistor 205R, transistor 205G, transistor 207G, and transistor 207B are all formed on substrate 151. These transistors can be manufactured using some of the same processes.

One or more of the transistors 100 to 100H and the transistors 200 to 200H described above can be applied to any one or more of the transistors 207D, 205R, 205G, 207G, and 207B. FIG. 31A shows a configuration example in which the transistor 100 described above is applied to the transistors 205R and 205G, and the transistor 200 described above is applied to the transistors 207D, 207G, and 207B.

A high-definition display device can be obtained by using one or more of the above-mentioned transistors 100 to 100H and transistors 200 to 200H in the display portion 162. Since the area per pixel is smaller as the resolution of the display device is higher, one or more of the transistors 100 to 100H can be preferably used. In addition, when the other of the source electrode and drain electrode of the transistor functions as a wiring and the wiring resistance required for the wiring is relatively low, any of the transistors 200 to 200H can be preferably used as the transistor. This allows the display device to operate at high speed.

By using one or more of the above-mentioned transistors 100 to 100H and transistors 200 to 200H in the circuit portion 164, the occupied area can be reduced, and a display device with a narrow frame can be obtained. In addition, by using a transistor with a short channel length, a display device that operates at high speed can be obtained. Compared to the display portion 162, the distance between the transistor and an element (e.g., a transistor and a capacitor) or a wiring electrically connected to the transistor may be longer in the circuit portion 164. Therefore, one or more of the transistors 200 to 200H having the conductive layer 212b can be preferably used. This allows a display device that operates at high speed.

Note that the transistors included in the display device of this embodiment are not limited to only the transistors included in the semiconductor device of one embodiment of the present invention. For example, the display device of this embodiment may have a combination of a transistor included in the semiconductor device of one embodiment of the present invention and a transistor having another structure. The display device of this embodiment may have, for example, one or more of a planar transistor, a staggered transistor, and an inverted staggered transistor. The transistors included in the display device of this embodiment may be either a top-gate type or a bottom-gate type. Alternatively, gates may be provided above and below a layer having a channel formation region.

Transistor 207D, transistor 205R, transistor 205G, transistor 207G, and transistor 207B can preferably be OS transistors.

The display device of this embodiment can also be configured to include Si transistors.

To increase the emission luminance of a light-emitting element included in a pixel circuit, it is necessary to increase the amount of current flowing through the light-emitting element. To achieve this, it is necessary to increase the source-drain voltage of a drive transistor included in the pixel circuit. Compared to Si transistors, OS transistors have a higher source-drain withstand voltage, so a high voltage can be applied between the source and drain of an OS transistor. Therefore, by using an OS transistor as the drive transistor included in a pixel circuit, it is possible to increase the amount of current flowing through the light-emitting element and increase the emission luminance of the light-emitting element.

When a transistor operates in the saturation region, an OS transistor can reduce the change in source-drain current in response to a change in gate-source voltage compared to a Si transistor. Therefore, by using an OS transistor as a driving transistor included in a pixel circuit, the current flowing between the source and drain can be precisely determined by changing the gate-source voltage, and the amount of current flowing to the light-emitting element can be controlled. This makes it possible to increase the number of gray levels in the pixel circuit.

In terms of the saturation of the current that flows when a transistor operates in the saturation region, an OS transistor can pass a more stable current (saturation current) than a Si transistor, even when the source-drain voltage gradually increases. Therefore, by using an OS transistor as a driving transistor, a stable current can be passed to the light-emitting element, for example, even when there is variation in the current-voltage characteristics of the light-emitting element. In other words, when an OS transistor operates in the saturation region, the source-drain current hardly changes even when the source-drain voltage is changed, so the light emission luminance of the light-emitting element can be stabilized.

The transistors in the circuit unit 164 and the transistors in the display unit 162 may have the same structure or different structures. The transistors in the circuit unit 164 may all have the same structure or may be of two or more types. Similarly, the transistors in the display unit 162 may all have the same structure or may be of two or more types.

All of the transistors in the display portion 162 may be OS transistors, all of the transistors in the display portion 162 may be Si transistors, or some of the transistors in the display portion 162 may be OS transistors and the rest may be Si transistors.

For example, by using both LTPS transistors and OS transistors in the display unit 162, a display device with low power consumption and high driving capability can be realized. A configuration in which LTPS transistors and OS transistors are combined is sometimes called LTPO. A more suitable example is a configuration in which an OS transistor is used as a transistor that functions as a switch for controlling conduction/non-conduction between wirings, and an LTPS transistor is used as a transistor for controlling current.

For example, one of the transistors in the display unit 162 functions as a transistor for controlling the current flowing to the light-emitting element, and can also be called a driving transistor. One of the source and drain of the driving transistor is electrically connected to the pixel electrode of the light-emitting element. It is preferable to use an LTPS transistor as the driving transistor. This makes it possible to increase the current flowing to the light-emitting element in the pixel circuit.

On the other hand, the other one of the transistors in the display unit 162 functions as a switch for controlling pixel selection/non-selection and can also be called a selection transistor. The gate of the selection transistor is electrically connected to a gate line, and one of the source and drain is electrically connected to a source line (signal line). It is preferable to use an OS transistor as the selection transistor. This makes it possible to maintain the gradation of the pixel even if the frame frequency is significantly lowered (for example, 1 fps or less), and therefore power consumption can be reduced by stopping the driver when displaying a still image.

An insulating layer 195 is provided to cover transistors 207D, 205R, 205G, 207G, and 207B, and an insulating layer 235 is provided on insulating layer 195. For the insulating layer 195, refer to the above description.

Light emitting elements 130R, 130G, and 130B are provided on insulating layer 235.

The light-emitting element 130R has a pixel electrode 111R on the insulating layer 235, an EL layer 113R on the pixel electrode 111R, and a common electrode 115 on the EL layer 113R. The light-emitting element 130R shown in FIG. 31A emits red light (R). The EL layer 113R has a light-emitting layer that emits red light.

The light-emitting element 130G has a pixel electrode 111G on the insulating layer 235, an EL layer 113G on the pixel electrode 111G, and a common electrode 115 on the EL layer 113G. The light-emitting element 130G shown in FIG. 31A emits green light (G). The EL layer 113G has a light-emitting layer that emits green light.

The light-emitting element 130B has a pixel electrode 111B on the insulating layer 235, an EL layer 113B on the pixel electrode 111B, and a common electrode 115 on the EL layer 113B. The light-emitting element 130B shown in FIG. 31A emits blue light (B). The EL layer 113B has a light-emitting layer that emits blue light.

The insulating layer 235 has a function of reducing unevenness caused by the transistors 207D, 205R, 205G, 207G, and 207B, and making the formation surfaces of the light-emitting elements 130R, 130G, and 130B more flat. Note that in this specification and the like, the insulating layer 235 may be referred to as a planarization layer.

The insulating layer 235 is preferably an organic insulating film. Materials that can be used for the organic insulating film include acrylic resin, polyimide resin, epoxy resin, polyamide resin, polyimideamide resin, siloxane resin, benzocyclobutene resin, phenol resin, and precursors of these resins. The insulating layer 235 can be a laminated structure of an organic insulating film and an inorganic insulating film. It is preferable that the insulating layer 235 is a laminated structure of an organic insulating film and an inorganic insulating film on the organic insulating film. This allows the inorganic insulating film to function as an etching protection layer when forming the light-emitting elements 130R, 130G, and 130B. Specifically, it is possible to prevent a part of the insulating layer 235 from being etched when the pixel electrode 111 is formed, and a recess from being formed in the insulating layer 235. Alternatively, the insulating layer 235 can be configured to have a recess when the pixel electrode 111 is formed.

Note that pixel electrode 111R, pixel electrode 111G, and pixel electrode 111B may be collectively referred to as pixel electrode 111.

In FIG. 31A, EL layers 113R, 113G, and EL layers 113B are all shown to have the same thickness, but this is not limited to the above. EL layers 113R, 113G, and EL layers 113B may each have a different thickness. For example, it is preferable to set the thickness of EL layers 113R, 113G, and EL layers 113B so that the optical path length is such that the light emitted by each layer is intensified. This makes it possible to realize a microcavity structure and increase the color purity of the light emitted from each light-emitting element.

Pixel electrode 111R has a region that contacts region 108Db of layer 108 of transistor 205R in an opening provided in insulating layer 106, insulating layer 195, and insulating layer 235, and is electrically connected to region 108Db. Similarly, pixel electrode 111G is electrically connected to region 108Db of transistor 205G, and pixel electrode 111B is electrically connected to region 108Db of transistor 205B (not shown).

The ends of the pixel electrodes 111R, 111G, and 111B are covered with an insulating layer 237. The insulating layer 237 functions as a partition wall. The insulating layer 237 can be formed in a single layer structure or a multilayer structure using one or both of an inorganic insulating material and an organic insulating material. For example, the material that can be used for the insulating layer 195 and the material that can be used for the insulating layer 235 can be used for the insulating layer 237. The insulating layer 237 can electrically insulate the pixel electrode and the common electrode. Furthermore, the insulating layer 237 can electrically insulate adjacent light-emitting elements from each other.

The insulating layer 237 is provided at least in the display section 162. The insulating layer 237 may be provided not only in the display section 162, but also in the connection section 140 and the circuit section 164. The insulating layer 237 may also be provided up to the edge of the display device 50A.

The common electrode 115 is a continuous film that is provided in common to the light-emitting elements 130R, 130G, and 130B. The common electrode 115 that is shared by the multiple light-emitting elements is electrically connected to a conductive layer 123 provided in the connection portion 140. For the conductive layer 123, it is preferable to use a conductive layer formed from the same material and in the same process as the pixel electrodes 111R, 111G, and 111B.

In a display device according to one embodiment of the present invention, a conductive film that transmits visible light is used for the pixel electrode and the common electrode, which is the electrode from which light is extracted. It is preferable to use a conductive film that reflects visible light for the electrode from which light is not extracted.

A conductive film that transmits visible light may also be used for the electrode on the side from which light is not extracted. In this case, it is preferable to place the electrode between the reflective layer and the EL layer. In other words, the light emitted from the EL layer may be reflected by the reflective layer and extracted from the display device.

As a material for forming a pair of electrodes of a light-emitting element, metals, alloys, electrically conductive compounds, and mixtures thereof can be appropriately used. Specific examples of the material include metals such as aluminum, magnesium, titanium, chromium, manganese, iron, cobalt, nickel, copper, gallium, zinc, indium, tin, molybdenum, tantalum, tungsten, palladium, gold, platinum, silver, yttrium, and neodymium, and alloys containing these in appropriate combinations. In addition, examples of the material include indium tin oxide (In-Sn oxide, also called ITO), In-Si-Sn oxide (also called ITSO), indium zinc oxide (In-Zn oxide), and In-W-Zn oxide. In addition, examples of the material include alloys containing aluminum (aluminum alloys), such as an alloy of aluminum, nickel, and lanthanum (Al-Ni-La), and alloys containing silver, such as an alloy of silver and magnesium, and an alloy of silver, palladium, and copper (Ag-Pd-Cu, also called APC). Other examples of such materials include elements belonging to Group 1 or 2 of the periodic table (e.g., lithium, cesium, calcium, and strontium) that are not listed above, rare earth metals such as europium and ytterbium, and alloys containing appropriate combinations of these, graphene, etc.

The light-emitting element preferably has a micro-optical resonator (microcavity) structure. Therefore, one of the pair of electrodes of the light-emitting element is preferably an electrode that is transparent and reflective to visible light (semi-transparent and semi-reflective electrode), and the other is preferably an electrode that is reflective to visible light (reflective electrode). By having the light-emitting element have a microcavity structure, the light emitted from the light-emitting layer can be resonated between both electrodes, thereby intensifying the light emitted from the light-emitting element.

The light transmittance of the transparent electrode is 40% or more. For example, it is preferable to use an electrode having a visible light (light having a wavelength of 400 nm or more and less than 750 nm) transmittance of 40% or more for the transparent electrode of the light emitting element. The visible light reflectance of the semi-transmissive/semi-reflective electrode is 10% or more and 95% or less, preferably 30% or more and 80% or less. The visible light reflectance of the reflective electrode is 40% or more and 100% or less, preferably 70% or more and 100% or less. In addition, the electrical resistivity of these electrodes is preferably 1×10 ⁻² Ω cm or less.

EL layer 113R, EL layer 113G, and EL layer 113B are each provided in an island shape. In FIG. 31A, the ends of adjacent EL layers 113R and 113G overlap, the ends of adjacent EL layers 113G and 113B overlap, and the ends of adjacent EL layers 113R and 113B overlap. When forming island-shaped EL layers using a fine metal mask, the ends of adjacent EL layers may overlap as shown in FIG. 31A, but this is not limited to this. In other words, adjacent EL layers may not overlap and may be separated from each other. In addition, in the display device, there may be both a portion where adjacent EL layers overlap and a portion where adjacent EL layers do not overlap and are separated from each other.

EL layer 113R, EL layer 113G, and EL layer 113B each have at least a light-emitting layer. The light-emitting layer has one or more types of light-emitting material. As the light-emitting material, a material that emits light of a color such as blue, purple, blue-purple, green, yellow-green, yellow, orange, or red is appropriately used. In addition, a material that emits near-infrared light can also be used as the light-emitting material.

Light-emitting materials include fluorescent materials, phosphorescent materials, TADF materials, and quantum dot materials.

The light-emitting layer may have one or more organic compounds (host material, assist material, etc.) in addition to the light-emitting substance (guest material). As the one or more organic compounds, one or both of a substance with high hole transport properties (hole transport material) and a substance with high electron transport properties (electron transport material) can be used. Furthermore, as the one or more organic compounds, a bipolar substance (a substance with high electron transport properties and hole transport properties) or a TADF material may be used.

The light-emitting layer preferably contains, for example, a phosphorescent material and a hole-transporting material and an electron-transporting material, which are a combination that easily forms an exciplex. With this configuration, light emission can be efficiently obtained using ExTET (Exciplex-Triple Energy Transfer), which is the energy transfer from the exciplex to the light-emitting material (phosphorescent material). By selecting a combination that forms an exciplex that emits light that overlaps with the wavelength of the lowest energy absorption band of the light-emitting material, the energy transfer becomes smooth and light emission can be efficiently obtained. With this configuration, it is possible to simultaneously achieve high efficiency, low voltage operation, and long life for the light-emitting element.

In addition to the light-emitting layer, the EL layer may have one or more of a layer containing a substance with high hole injection properties (hole injection layer), a layer containing a hole transport material (hole transport layer), a layer containing a substance with high electron blocking properties (electron blocking layer), a layer containing a substance with high electron injection properties (electron injection layer), a layer containing an electron transport material (electron transport layer), and a layer containing a substance with high hole blocking properties (hole blocking layer). In addition, the EL layer may contain one or both of a bipolar substance and a TADF material.

Either low molecular weight compounds or high molecular weight compounds can be used for the light emitting element, and it may contain inorganic compounds. The layers constituting the light emitting element can be formed by a deposition method (including vacuum deposition), a transfer method, a printing method, an inkjet method, a coating method, etc.

The light-emitting element may have a single structure (a structure having only one light-emitting unit) or a tandem structure (a structure having multiple light-emitting units). The light-emitting unit has at least one light-emitting layer. The tandem structure is a structure in which multiple light-emitting units are connected in series via a charge-generating layer. When a voltage is applied between a pair of electrodes, the charge-generating layer has the function of injecting electrons into one of the two light-emitting units and injecting holes into the other. The tandem structure makes it possible to obtain a light-emitting element capable of emitting light with high brightness. Furthermore, the tandem structure can reduce the current required to obtain the same brightness compared to a single structure, thereby improving reliability. The tandem structure can also be called a stack structure.

In FIG. 31A, when a light-emitting element with a tandem structure is used, it is preferable that EL layer 113R has a structure having multiple light-emitting units that emit red light, EL layer 113G has a structure having multiple light-emitting units that emit green light, and EL layer 113B has a structure having multiple light-emitting units that emit blue light.

A protective layer 131 is provided on the light-emitting elements 130R, 130G, and 130B. The protective layer 131 and the substrate 152 are bonded via an adhesive layer 142. The substrate 152 is provided with a light-shielding layer 117. For example, a solid sealing structure or a hollow sealing structure can be applied to seal the light-emitting elements. In FIG. 31A, the space between the substrates 152 and 151 is filled with an adhesive layer 142, and a solid sealing structure is applied. Alternatively, the space may be filled with an inert gas (such as nitrogen or argon), and a hollow sealing structure may be applied. In this case, the adhesive layer 142 may be provided so as not to overlap with the light-emitting elements. The space may also be filled with a resin different from the adhesive layer 142 provided in a frame shape.

The protective layer 131 is provided at least on the display unit 162, and is preferably provided so as to cover the entire display unit 162. The protective layer 131 is preferably provided so as to cover not only the display unit 162, but also the connection unit 140 and the circuit unit 164. The protective layer 131 is also preferably provided up to the end of the display device 50A. On the other hand, the connection unit 197 has a portion where the protective layer 131 is not provided in order to electrically connect the FPC 172 and the conductive layer 166.

By providing a protective layer 131 on the light-emitting elements 130R, 130G, and 130B, the reliability of the light-emitting elements can be improved.

The protective layer 131 can be a single layer structure or a laminated structure of two or more layers. The conductivity of the protective layer 131 does not matter. At least one of an insulating film, a semiconductor film, and a conductive film can be used as the protective layer 131.

The protective layer 131 has an inorganic film, which prevents oxidation of the common electrode 115 and prevents impurities (such as moisture and oxygen) from entering the light-emitting element, thereby suppressing deterioration of the light-emitting element and improving the reliability of the display device.

An inorganic insulating film can be used for the protective layer 131. Examples of materials that can be used for the inorganic insulating film include oxides, nitrides, oxynitrides, and nitride oxides. Specific examples of these inorganic insulating films are as described above. In particular, the protective layer 131 preferably contains a nitride or a nitride oxide, and more preferably contains a nitride.

The protective layer 131 may be an inorganic film containing ITO, In-Zn oxide, Ga-Zn oxide, Al-Zn oxide, IGZO, or the like. The inorganic film preferably has a high resistance, and more specifically, preferably has a higher resistance than the common electrode 115. The inorganic film may further contain nitrogen.

When the light emitted from the light-emitting element is extracted through the protective layer 131, it is preferable that the protective layer 131 has high transparency to visible light. For example, ITO, IGZO, and aluminum oxide are preferable because they are inorganic materials that have high transparency to visible light.

The protective layer 131 may be, for example, a laminated structure of an aluminum oxide film and a silicon nitride film on the aluminum oxide film, or a laminated structure of an aluminum oxide film and an IGZO film on the aluminum oxide film. By using this laminated structure, it is possible to prevent impurities (water, oxygen, etc.) from entering the EL layer side.

Furthermore, the protective layer 131 may have an organic film. For example, the protective layer 131 may have both an organic film and an inorganic film. An example of an organic film that can be used for the protective layer 131 is an organic insulating film that can be used for the insulating layer 235.

A connection portion 197 is provided in an area of the substrate 151 where the substrate 152 does not overlap. In the connection portion 197, the conductive layer 165 is electrically connected to the FPC 172 via the conductive layer 166 and the connection layer 242. The conductive layer 165 is an example of a conductive layer obtained by processing the same conductive film as the conductive layer 212b. The conductive layer 166 is an example of a conductive layer obtained by processing the same conductive film as the pixel electrodes 111R, 111G, and 111B. The conductive layer 166 is exposed on the upper surface of the connection portion 197. This allows the connection portion 197 and the FPC 172 to be electrically connected via the connection layer 242.

The display device 50A is a top emission type. Light emitted by the light emitting elements is emitted towards the substrate 152. It is preferable to use a material that is highly transparent to visible light for the substrate 152. The pixel electrodes 111R, 111G, and 111B contain a material that reflects visible light, and the counter electrode (common electrode 115) contains a material that transmits visible light.

It is preferable to provide a light-shielding layer 117 on the surface of the substrate 152 facing the substrate 151. The light-shielding layer 117 can be provided between adjacent light-emitting elements, in the connection section 140, in the circuit section 164, etc.

A colored layer such as a color filter may be provided on the surface of substrate 152 facing substrate 151 or on protective layer 131. By providing a color filter over the light-emitting element, the color purity of the light emitted from the pixel can be increased.

The colored layers are colored layers that selectively transmit light in a specific wavelength range and absorb light in other wavelength ranges. For example, a red (R) color filter that transmits light in the red wavelength range, a green (G) color filter that transmits light in the green wavelength range, and a blue (B) color filter that transmits light in the blue wavelength range can be used. For each colored layer, one or more of metal materials, resin materials, pigments, and dyes can be used. The colored layers are formed at the desired positions by printing, inkjet, etching using photolithography, or the like.

Various optical members can be arranged on the outside of the substrate 152 (the surface opposite to the substrate 151). Examples of optical members include a polarizing plate, a retardation plate, a light diffusion layer (such as a diffusion film), an anti-reflection layer, and a light collecting film. In addition, a surface protection layer such as an antistatic film that suppresses the adhesion of dust, a water-repellent film that makes it difficult for dirt to adhere, a hard coat film that suppresses the occurrence of scratches due to use, and an impact absorbing layer may be arranged on the outside of the substrate 152. For example, by providing a glass layer or a silica layer (SiO _x layer) as the surface protection layer, it is possible to suppress the occurrence of surface contamination and scratches, which is preferable. In addition, DLC (diamond-like carbon), aluminum oxide (AlO _x ), a polyester-based material, a polycarbonate-based material, or the like may be used as the surface protection layer. In addition, it is preferable to use a material with high transmittance for visible light for the surface protection layer. In addition, it is preferable to use a material with high hardness for the surface protection layer.

The substrates 151 and 152 may each be made of glass, quartz, ceramics, sapphire, resin, metal, alloy, semiconductor, or the like. A material that transmits light is used for the substrate on the side from which light from the light-emitting element is extracted. If a flexible material is used for the substrates 151 and 152, the flexibility of the display device can be increased, and a flexible display can be realized. A polarizing plate may also be used for at least one of the substrates 151 and 152.

The substrates 151 and 152 may each be made of polyester resins such as polyethylene terephthalate (PET) and polyethylene naphthalate (PEN), polyacrylonitrile resin, acrylic resin, polyimide resin, polymethyl methacrylate resin, polycarbonate (PC) resin, polyethersulfone (PES) resin, polyamide resin (nylon, aramid, etc.), polysiloxane resin, cycloolefin resin, polystyrene resin, polyamideimide resin, polyurethane resin, polyvinyl chloride resin, polyvinylidene chloride resin, polypropylene resin, polytetrafluoroethylene (PTFE) resin, ABS resin, cellulose nanofiber, etc. At least one of the substrates 151 and 152 may be made of glass having a thickness sufficient to provide flexibility.

When a circular polarizing plate is laminated on a display device, it is preferable to use a substrate with high optical isotropy as the substrate of the display device. A substrate with high optical isotropy has low birefringence (it can also be said that the amount of birefringence is small). Examples of films with high optical isotropy include triacetyl cellulose (TAC, also known as cellulose triacetate) film, cycloolefin polymer (COP) film, cycloolefin copolymer (COC) film, and acrylic film.

As the adhesive layer 142, various types of curing adhesives can be used, such as photo-curing adhesives such as ultraviolet curing adhesives, reactive curing adhesives, heat curing adhesives, and anaerobic adhesives. These adhesives include epoxy resin, acrylic resin, silicone resin, phenolic resin, polyimide resin, imide resin, PVC (polyvinyl chloride) resin, PVB (polyvinyl butyral) resin, and EVA (ethylene vinyl acetate) resin. In particular, materials with low moisture permeability such as epoxy resin are preferable. Two-part mixed resins may also be used. Adhesive sheets, etc. may also be used.

As the connection layer 242, an anisotropic conductive film (ACF), an anisotropic conductive paste (ACP), etc. can be used.

<Configuration Example 2 of Display Device>
FIG. 31B shows an example of a cross section of the display unit 162 of the display device 50B. The display device 50B is mainly different from the display device 50A in that a light-emitting element having a common EL layer 113 and a colored layer (such as a color filter) are used in each subpixel of each color. The configuration shown in FIG. 31B can be combined with the region including the FPC 172, the circuit portion 164, the laminated structure from the substrate 151 to the insulating layer 235 of the display unit 162, the connection portion 140, and the configuration of the end portion shown in FIG. 31A. Note that in the following description of the display device, the description of the same parts as those of the display device described above may be omitted.

The display device 50B shown in FIG. 31B has light emitting elements 130R, 130G, and 130B, a colored layer 132R that transmits red light, a colored layer 132G that transmits green light, and a colored layer 132B that transmits blue light.

The light-emitting element 130R has a pixel electrode 111R, an EL layer 113 on the pixel electrode 111R, and a common electrode 115 on the EL layer 113. The light emitted by the light-emitting element 130R is extracted as red light to the outside of the display device 50B via the colored layer 132R.

The light-emitting element 130G has a pixel electrode 111G, an EL layer 113 on the pixel electrode 111G, and a common electrode 115 on the EL layer 113. The light emitted by the light-emitting element 130G is extracted as green light to the outside of the display device 50B via the colored layer 132G.

The light-emitting element 130B has a pixel electrode 111B, an EL layer 113 on the pixel electrode 111B, and a common electrode 115 on the EL layer 113. The light emitted by the light-emitting element 130B is extracted as blue light to the outside of the display device 50B via the colored layer 132B.

Each of the light-emitting elements 130R, 130G, and 130B shares an EL layer 113 and a common electrode 115. A configuration in which a common EL layer 113 is provided for the subpixels of each color can reduce the number of manufacturing steps compared to a configuration in which a different EL layer is provided for each subpixel of each color.

For example, the light-emitting elements 130R, 130G, and 130B shown in FIG. 31B emit white light. The white light emitted by the light-emitting elements 130R, 130G, and 130B passes through the colored layers 132R, 132G, and 132B to obtain light of the desired color.

A light-emitting element that emits white light preferably includes two or more light-emitting layers. When two light-emitting layers are used to obtain white light emission, light-emitting layers can be selected such that the emission colors of the two light-emitting layers are complementary to each other. For example, by making the emission color of the first light-emitting layer and the emission color of the second light-emitting layer complementary to each other, a configuration can be obtained in which the light-emitting element as a whole emits white light. In addition, when three or more light-emitting layers are used to obtain white light emission, the emission colors of the three or more light-emitting layers can be combined to obtain a configuration in which the light-emitting element as a whole emits white light.

The EL layer 113 preferably has, for example, a light-emitting layer having a light-emitting material that emits blue light, and a light-emitting layer having a light-emitting material that emits visible light with a longer wavelength than blue. The EL layer 113 preferably has, for example, a light-emitting layer that emits yellow light, and a light-emitting layer that emits blue light. Alternatively, the EL layer 113 preferably has, for example, a light-emitting layer that emits red light, a light-emitting layer that emits green light, and a light-emitting layer that emits blue light.

For light-emitting elements that emit white light, it is preferable to use a tandem structure. Specifically, a two-stage tandem structure having a light-emitting unit that emits yellow light and a light-emitting unit that emits blue light, a two-stage tandem structure having a light-emitting unit that emits red and green light and a light-emitting unit that emits blue light, a three-stage tandem structure having, in this order, a light-emitting unit that emits blue light, a light-emitting unit that emits yellow, yellow-green or green light, and a light-emitting unit that emits blue light, or a three-stage tandem structure having, in this order, a light-emitting unit that emits blue light, a light-emitting unit that emits yellow, yellow-green or green light, and red light, and a light-emitting unit that emits blue light, etc. can be applied. For example, the number of layers and the order of colors of the light-emitting units can be, from the anode side, a two-layer structure of B and light-emitting unit X, a three-layer structure of B, Y, and B, or a three-layer structure of B, X, and B. The number of layers and the order of colors of the light-emitting layers in light-emitting unit X can be, from the anode side, a two-layer structure of R and Y, a two-layer structure of R and G, a two-layer structure of G and R, a three-layer structure of G, R, and G, or a three-layer structure of R, G, and R. In addition, another layer may be provided between the two light-emitting layers.

In addition, by applying a microcavity structure, a light-emitting element configured to emit white light may emit light of a specific wavelength, such as red, green, or blue, with the light being enhanced.

Or, for example, the light-emitting elements 130R, 130G, and 130B shown in FIG. 31B emit blue light. In this case, the EL layer 113 has one or more light-emitting layers that emit blue light. In the pixel 230B that emits blue light, the blue light emitted by the light-emitting element 130B can be extracted. In the pixel 230R that emits red light and the pixel 230G that emits green light, a color conversion layer is provided between the light-emitting element 130R or the light-emitting element 130G and the substrate 152, so that the blue light emitted by the light-emitting element 130R or the light-emitting element 130G can be converted into light with a longer wavelength, and red or green light can be extracted. Furthermore, it is preferable to provide a colored layer 132R between the color conversion layer and the substrate 152 on the light-emitting element 130R, and a colored layer 132G between the color conversion layer and the substrate 152 on the light-emitting element 130G. A part of the light emitted by the light-emitting element may be transmitted as it is without being converted by the color conversion layer. By extracting the light that has passed through the color conversion layer via the colored layer, light other than the desired color can be absorbed by the colored layer, thereby increasing the color purity of the light emitted by the subpixel.

<Configuration Example 3 of Display Device>
A display device 50C shown in FIG. 32 differs from the display device 50B mainly in that it is a bottom-emission type display device.

Light emitted by the light-emitting element is emitted toward the substrate 151. It is preferable to use a material that is highly transparent to visible light for the substrate 151. On the other hand, the translucency of the material used for the substrate 152 does not matter.

It is preferable to form a light-shielding layer 117 between the substrate 151 and the transistor. FIG. 32 shows an example in which the light-shielding layer 117 is provided on the substrate 151, the insulating layer 153 is provided on the light-shielding layer 117, and the transistors 207D, 205R (not shown), 205G, 207G, and 207B are provided on the insulating layer 153. In addition, the colored layer 132R and the colored layer 132G are provided on the insulating layer 195, and the insulating layer 195 is provided on the colored layer 132R and the colored layer 132G.

The light-emitting element 130R, which overlaps with the colored layer 132R, has a pixel electrode 111R, an EL layer 113, and a common electrode 115.

The light-emitting element 130G, which overlaps with the colored layer 132G, has a pixel electrode 111G, an EL layer 113, and a common electrode 115.

The light-emitting element 130B, which overlaps with the colored layer 132B, has a pixel electrode 111B, an EL layer 113, and a common electrode 115.

The pixel electrodes 111R, 111G, and 111B are each made of a material that is highly transparent to visible light. It is preferable to use a material that reflects visible light for the common electrode 115. In a bottom-emission display device, a metal with low electrical resistivity can be used for the common electrode 115, so that voltage drops caused by the electrical resistance of the common electrode 115 can be suppressed, and high display quality can be achieved.

The transistor of one embodiment of the present invention can be miniaturized and its occupation area can be reduced, so that in a display device with a bottom emission structure, the pixel aperture ratio can be increased or the pixel size can be reduced.

<Configuration Example 4 of Display Device>
A display device 50D shown in FIG. 33A differs from the display device 50A mainly in that a light receiving element 130S is included.

Display device 50D has a light-emitting element and a light-receiving element in each pixel. In display device 50D, it is preferable to use an organic EL element as the light-emitting element and an organic photodiode as the light-receiving element. The organic EL element and the organic photodiode can be formed on the same substrate. Therefore, an organic photodiode can be built into a display device that uses an organic EL element.

In display device 50D, where pixels have a light-emitting element and a light-receiving element, the pixels have a light-receiving function, so that it is possible to detect the contact or proximity of an object while displaying an image. Therefore, in addition to the image display function, display unit 162 has one or both of an imaging function and a sensing function. For example, in addition to displaying an image using all of the sub-pixels of display device 50D, some of the sub-pixels can provide light as a light source, some other sub-pixels can perform light detection, and the remaining sub-pixels can display an image.

Therefore, there is no need to provide a light receiving unit and a light source separate from the display device 50D, and the number of parts in the electronic device can be reduced. For example, there is no need to provide a separate biometric authentication device in the electronic device, or a capacitive touch panel for scrolling, etc. Therefore, by using the display device 50D, it is possible to provide an electronic device with reduced manufacturing costs.

When the light receiving element is used as an image sensor, the display device 50D can capture an image using the light receiving element. For example, the image sensor can be used to capture images for personal authentication using a fingerprint, palm print, iris, pulse shape (including vein shape and artery shape), face, etc.

The light receiving element can be used as a touch sensor (also called a direct touch sensor) or a non-contact sensor (also called a hover sensor, hover touch sensor, or touchless sensor). A touch sensor can detect an object (such as a finger, hand, or pen) when the display device and the object are in direct contact with each other. A non-contact sensor can detect an object even if the object does not come into contact with the display device.

The light receiving element 130S has a pixel electrode 111S on an insulating layer 235, a functional layer 113S on the pixel electrode 111S, and a common electrode 115 on the functional layer 113S. Light Lin is incident on the functional layer 113S from outside the display device 50D.

The pixel electrode 111S contacts the region 108Db of the layer 108 of the transistor 205S through openings provided in the insulating layer 106, the insulating layer 195, and the insulating layer 235, and is electrically connected to the region 108Db.

The ends of the pixel electrode 111S are covered by an insulating layer 237.

The common electrode 115 is a continuous film provided in common to the light receiving element 130S, the light emitting element 130R (not shown), the light emitting element 130G, and the light emitting element 130B. The common electrode 115 shared by the light emitting element and the light receiving element is electrically connected to the conductive layer 123 provided in the connection portion 140.

The functional layer 113S has at least an active layer (also called a photoelectric conversion layer). The active layer includes a semiconductor. Examples of the semiconductor include inorganic semiconductors such as silicon, and organic semiconductors including organic compounds. In this embodiment, an example is shown in which an organic semiconductor is used as the semiconductor of the active layer. By using an organic semiconductor, the light-emitting layer and the active layer can be formed by the same method (for example, vacuum deposition), which is preferable because the manufacturing equipment can be shared.

The functional layer 113S may further include a layer containing a material with high hole transport properties, a material with high electron transport properties, or a bipolar material, as a layer other than the active layer. In addition, without being limited to the above, the functional layer 113S may further include a layer containing a material with high hole injection properties, a hole blocking material, a material with high electron injection properties, or an electron blocking material. For example, the materials that can be used in the light-emitting element described above can be used for the functional layer 113S.

The light receiving element can be made of either a low molecular weight compound or a high molecular weight compound, and may contain an inorganic compound. The layers that make up the light receiving element can be formed by a deposition method (including vacuum deposition), a transfer method, a printing method, an inkjet method, a coating method, etc.

The display device 50D shown in Figures 33B and 33C has a layer 353 having light receiving elements, a circuit layer 355, and a layer 357 having light emitting elements between the substrate 151 and the substrate 152.

Layer 353 has, for example, light receiving element 130S. Layer 357 has, for example, light emitting elements 130R, 130G, and 130B.

Circuit layer 355 has a circuit that drives the light receiving element and a circuit that drives the light emitting element. Circuit layer 355 has, for example, transistor 205R, transistor 205G, and transistor 205B. In addition, circuit layer 355 can be provided with one or more of a switch, a capacitance, a resistance, a wiring, a terminal, and the like.

Figure 33B shows an example in which light receiving element 130S is used as a touch sensor. As shown in Figure 33B, light emitted by a light emitting element in layer 357 is reflected by a finger 352 that touches display device 50D, and the light receiving element in layer 353 detects the reflected light. This makes it possible to detect that finger 352 has touched display device 50D.

Figure 33C shows an example in which the light receiving element 130S is used as a non-contact sensor. As shown in Figure 33C, light emitted by a light emitting element in layer 357 is reflected by a finger 352 that is close to (i.e., not in contact with) the display device 50D, and the light receiving element in layer 353 detects the reflected light.

<Configuration Example 5 of Display Device>
The display device 50E shown in FIG. 34A is an example of a display device to which the MML (metal maskless) structure is applied. In other words, the display device 50E has a light-emitting element manufactured without using a fine metal mask. Note that the laminated structure from the substrate 151 to the insulating layer 235 and the laminated structure from the protective layer 131 to the substrate 152 are the same as those of the display device 50A, and therefore the description thereof will be omitted.

In FIG. 34A, light-emitting elements 130R, 130G, and 130B are provided on insulating layer 235.

The light-emitting element 130R has a conductive layer 124R on the insulating layer 235, a conductive layer 126R on the conductive layer 124R, a layer 133R on the conductive layer 126R, a common layer 114 on the layer 133R, and a common electrode 115 on the common layer 114. The light-emitting element 130R shown in FIG. 34A emits red light (R). The layer 133R has a light-emitting layer that emits red light. In the light-emitting element 130R, the layer 133R and the common layer 114 can be collectively referred to as an EL layer. In addition, one or both of the conductive layer 124R and the conductive layer 126R can be referred to as a pixel electrode.

The light-emitting element 130G has a conductive layer 124G on the insulating layer 235, a conductive layer 126G on the conductive layer 124G, a layer 133G on the conductive layer 126G, a common layer 114 on the layer 133G, and a common electrode 115 on the common layer 114. The light-emitting element 130G shown in FIG. 34A emits green light (G). The layer 133G has a light-emitting layer that emits green light. In the light-emitting element 130G, the layer 133G and the common layer 114 can be collectively referred to as an EL layer. In addition, one or both of the conductive layer 124G and the conductive layer 126G can be referred to as a pixel electrode.

The light-emitting element 130B has a conductive layer 124B on the insulating layer 235, a conductive layer 126B on the conductive layer 124B, a layer 133B on the conductive layer 126B, a common layer 114 on the layer 133B, and a common electrode 115 on the common layer 114. The light-emitting element 130B shown in FIG. 34A emits blue light (B). The layer 133B has a light-emitting layer that emits blue light. In the light-emitting element 130B, the layer 133B and the common layer 114 can be collectively referred to as an EL layer. In addition, one or both of the conductive layer 124B and the conductive layer 126B can be referred to as a pixel electrode.

In this specification, among the EL layers of the light-emitting elements, layers provided in an island shape for each light-emitting element are indicated as layer 133B, layer 133G, or layer 133R, and a layer shared by a plurality of light-emitting elements is indicated as common layer 114. Note that in this specification, layers 133R, 133G, and 133B may be referred to as island-shaped EL layers or EL layers formed in an island shape, without including common layer 114.

Layer 133R, layer 133G, and layer 133B are separated from each other. By providing an island-like EL layer for each light-emitting element, it is possible to suppress leakage current between adjacent light-emitting elements. This makes it possible to prevent unintended light emission caused by crosstalk, and to realize a display device with extremely high contrast.

Note that in FIG. 34A, layers 133R, 133G, and 133B are all shown to have the same thickness, but this is not limited to this. Layers 133R, 133G, and 133B may each have a different thickness.

The conductive layer 124R contacts and is electrically connected to the region 108Db of the layer 108 of the transistor 205R at the openings provided in the insulating layers 106, 195, and 235. Similarly, the conductive layer 124G is electrically connected to the region 108Db of the transistor 205G, and the conductive layer 124B is electrically connected to the region 108Db of the transistor 205B.

The conductive layers 124R, 124G, and 124B are formed to cover the openings provided in the insulating layer 235. Layer 128 is embedded in the recesses of the conductive layers 124R, 124G, and 124B, respectively.

Layer 128 has the function of planarizing the recesses of conductive layers 124R, 124G, and 124B. Conductive layers 126R, 126G, and 126B that are electrically connected to conductive layers 124R, 124G, and 124B are provided on conductive layers 124R, 124G, and 124B and layer 128. Therefore, the regions that overlap with the recesses of conductive layers 124R, 124G, and 124B can also be used as light-emitting regions, and the aperture ratio of the pixel can be increased. It is preferable to use a conductive layer that functions as a reflective electrode for conductive layer 124R and conductive layer 126R.

Layer 128 may be an insulating layer or a conductive layer. Various inorganic insulating materials, organic insulating materials, and conductive materials can be used as appropriate for layer 128. In particular, layer 128 is preferably formed using an insulating material, and is particularly preferably formed using an organic insulating material. For example, the organic insulating material that can be used for insulating layer 237 described above can be used for layer 128.

FIG. 34A shows an example in which the top surface of layer 128 has a flat portion, but the shape of layer 128 is not particularly limited. The top surface of layer 128 can have at least one of a convex curved surface, a concave curved surface, and a flat surface.

The height of the top surface of layer 128 and the height of the top surface of conductive layer 124R may be the same or approximately the same, or may be different from each other. For example, the height of the top surface of layer 128 may be lower or higher than the height of the top surface of conductive layer 124R.

The end of the conductive layer 126R may be aligned with the end of the conductive layer 124R, or may cover the side of the end of the conductive layer 124R. The ends of the conductive layer 124R and the conductive layer 126R preferably have a tapered shape. Specifically, the ends of the conductive layer 124R and the conductive layer 126R preferably have a tapered shape with a taper angle greater than 0 degrees and less than 90 degrees. When the end of the pixel electrode has a tapered shape, the layer 133R provided along the side of the pixel electrode has an inclined portion. By making the side of the pixel electrode tapered, the coverage of the EL layer provided along the side of the pixel electrode can be improved.

The conductive layers 124G, 126G and the conductive layers 124B, 126B are similar to the conductive layers 124R, 126R, so detailed description will be omitted.

The upper and side surfaces of conductive layer 126R are covered by layer 133R. Similarly, the upper and side surfaces of conductive layer 126G are covered by layer 133G, and the upper and side surfaces of conductive layer 126B are covered by layer 133B. Therefore, the entire area in which conductive layers 126R, 126G, and 126B are provided can be used as the light-emitting area of light-emitting elements 130R, 130G, and 130B, thereby increasing the aperture ratio of the pixel.

A portion of the top surface and the side surfaces of layers 133R, 133G, and 133B are covered with insulating layers 125 and 127. A common layer 114 is provided on layers 133R, 133G, 133B, and insulating layers 125 and 127, and a common electrode 115 is provided on common layer 114. Common layer 114 and common electrode 115 are each a continuous film provided in common to multiple light-emitting elements.

In FIG. 34A, the insulating layer 237 shown in FIG. 31A and the like is not provided between the conductive layer 126R and the layer 133R. In other words, the display device 50E does not have an insulating layer (also called a partition, bank, spacer, etc.) that contacts the pixel electrode and covers the upper end of the pixel electrode. This allows the distance between adjacent light-emitting elements to be extremely narrow. This allows a high-definition or high-resolution display device to be obtained. In addition, a mask (e.g., a photomask) for forming the insulating layer is not required, which reduces the manufacturing cost of the display device.

As described above, each of the layers 133R, 133G, and 133B has a light-emitting layer. Each of the layers 133R, 133G, and 133B preferably has a light-emitting layer and a carrier transport layer (electron transport layer or hole transport layer) on the light-emitting layer. Alternatively, each of the layers 133R, 133G, and 133B preferably has a light-emitting layer and a carrier block layer (hole block layer or electron block layer) on the light-emitting layer. Alternatively, each of the layers 133R, 133G, and 133B preferably has a light-emitting layer, a carrier block layer on the light-emitting layer, and a carrier transport layer on the carrier block layer. Since the surfaces of the layers 133R, 133G, and 133B are exposed during the manufacturing process of the display device, by providing one or both of the carrier transport layer and the carrier block layer on the light-emitting layer, it is possible to suppress exposure of the light-emitting layer to the outermost surface and reduce damage to the light-emitting layer. This can improve the reliability of the light-emitting element.

The common layer 114 has, for example, an electron injection layer or a hole injection layer. Alternatively, the common layer 114 may have an electron transport layer and an electron injection layer stacked together, or a hole transport layer and a hole injection layer stacked together. The common layer 114 is shared by the light-emitting elements 130R, 130G, and 130B.

The sides of layers 133R, 133G, and 133B are covered by insulating layer 125. Insulating layer 127 covers the sides of layers 133R, 133G, and 133B via insulating layer 125.

The side surfaces (and even parts of the top surfaces) of layers 133R, 133G, and 133B are covered with at least one of insulating layers 125 and 127, which prevents the common layer 114 (or common electrode 115) from coming into contact with the pixel electrodes and the side surfaces of layers 133R, 133G, and 133B, thereby preventing short circuits in the light-emitting elements. This improves the reliability of the light-emitting elements.

It is preferable that the insulating layer 125 contacts the side surfaces of the layers 133R, 133G, and 133B. By configuring the insulating layer 125 to contact the layers 133R, 133G, and 133B, peeling of the layers 133R, 133G, and 133B can be prevented, and the reliability of the light-emitting element can be improved.

The insulating layer 127 is provided on the insulating layer 125 so as to fill the recesses in the insulating layer 125. It is preferable that the insulating layer 127 covers at least a portion of the side surface of the insulating layer 125.

By providing insulating layers 125 and 127, the gap between adjacent island-shaped layers can be filled, reducing the large unevenness of the surface on which layers (such as the carrier injection layer and the common electrode) are formed on the island-shaped layers, making it possible to make the surface flatter. This improves the coverage of the carrier injection layer, the common electrode, etc.

The common layer 114 and the common electrode 115 are provided on the layers 133R, 133G, and 133B, the insulating layer 125, and the insulating layer 127. Before the insulating layer 125 and the insulating layer 127 are provided, there is a step between the region where the pixel electrode and the island-shaped EL layer are provided and the region (region between the light-emitting elements) where the pixel electrode and the island-shaped EL layer are not provided. In the display device of one embodiment of the present invention, the step can be flattened by having the insulating layer 125 and the insulating layer 127, and the coverage of the common layer 114 and the common electrode 115 can be improved. Therefore, poor connection due to step disconnection can be suppressed. In addition, the step can be suppressed from locally thinning the common electrode 115 and increasing the electrical resistance.

It is preferable that the upper surface of the insulating layer 127 has a shape with high flatness. The upper surface of the insulating layer 127 may have at least one of a flat surface, a convex curved surface, and a concave curved surface. For example, it is preferable that the upper surface of the insulating layer 127 has a convex curved shape with a large radius of curvature.

An inorganic insulating film can be used for the insulating layer 125. Examples of materials that can be used for the inorganic insulating film include oxides, nitrides, oxynitrides, and oxynitrides. Specific examples of these inorganic insulating films are as described above. The insulating layer 125 may have a single-layer structure or a multilayer structure. For example, the insulating layer 125 can be preferably made of one or more of silicon nitride, aluminum oxide, hafnium oxide, and silicon oxide. In particular, by applying an aluminum oxide film, hafnium oxide film, or silicon oxide film formed by the ALD method to the insulating layer 125, an insulating layer 125 with fewer pinholes and excellent function of protecting the EL layer can be formed.

The insulating layer 125 can be formed by sputtering, CVD (e.g., PECVD), PLD, or ALD. By using the ALD method, the coverage of the insulating layer 125 can be improved. Furthermore, by using the PECVD method, productivity can be improved.

The insulating layer 125 preferably has a function as a barrier insulating layer against at least one of water and oxygen. The insulating layer 125 preferably has a function of suppressing the diffusion of at least one of water and oxygen. In addition, the insulating layer 125 preferably has a function of capturing or fixing (also called gettering) at least one of water and oxygen.

The insulating layer 125 functions as a barrier insulating layer, making it possible to suppress the intrusion of impurities (typically at least one of water and oxygen) that may diffuse from the outside into each light-emitting element. This configuration makes it possible to provide a highly reliable light-emitting element and further a highly reliable display device.

The insulating layer 125 preferably has a low impurity concentration. This can prevent impurities from entering the EL layer from the insulating layer 125 and causing deterioration of the EL layer. In addition, by lowering the impurity concentration in the insulating layer 125, the barrier properties against at least one of water and oxygen can be improved. For example, it is desirable that the insulating layer 125 has a sufficiently low hydrogen concentration or carbon concentration, or preferably both.

The insulating layer 127 provided on the insulating layer 125 has the function of flattening the unevenness of the insulating layer 125 formed between adjacent light-emitting elements. In other words, the presence of the insulating layer 127 has the effect of improving the flatness of the surface on which the common electrode 115 is formed.

As the insulating layer 127, an insulating layer containing an organic material can be suitably used. As the organic material, it is preferable to use a photosensitive resin, for example, a photosensitive resin composition containing an acrylic resin. Note that in this specification and the like, acrylic resin does not only refer to polymethacrylic acid ester or methacrylic resin, but may refer to acrylic polymers in a broad sense.

The insulating layer 127 may be made of acrylic resin, polyimide resin, epoxy resin, imide resin, polyamide resin, polyimideamide resin, silicone resin, siloxane resin, benzocyclobutene resin, phenol resin, or precursors of these resins. The insulating layer 127 may be made of organic materials such as polyvinyl alcohol (PVA), polyvinyl butyral, polyvinylpyrrolidone, polyethylene glycol, polyglycerin, pullulan, water-soluble cellulose, or alcohol-soluble polyamide resin. A photoresist may be used as the photosensitive resin. Either a positive-type material or a negative-type material may be used as the photosensitive resin.

The insulating layer 127 may be made of a material that absorbs visible light. By having the insulating layer 127 absorb the light emitted from the light-emitting element, it is possible to suppress leakage of light from the light-emitting element to an adjacent light-emitting element through the insulating layer 127 (stray light). This can improve the display quality of the display device. In addition, since the display quality can be improved without using a polarizing plate in the display device, it is possible to reduce the weight and thickness of the display device.

Materials that absorb visible light include materials containing pigments such as black, materials containing dyes, resin materials with light absorbing properties (such as polyimide), and resin materials that can be used in color filters (color filter materials). In particular, it is preferable to use a resin material in which two or more colors of color filter materials are laminated or mixed, as this can enhance the visible light blocking effect. In particular, by mixing three or more colors of color filter materials, it is possible to create a resin layer that is black or close to black.

<Configuration Example 6 of Display Device>
Fig. 34B shows an example of a cross section of the display unit 162 of the display device 50F. The display device 50F is mainly different from the display device 50E in that a colored layer (such as a color filter) is provided in each subpixel of each color. The configuration shown in Fig. 34B can be combined with the region including the FPC 172, the circuit unit 164, the laminated structure from the substrate 151 to the insulating layer 235 of the display unit 162, the connection unit 140, and the configuration of the end portion shown in Fig. 34A.

The display device 50F shown in FIG. 34B has light emitting elements 130R, 130G, and 130B, a colored layer 132R that transmits red light, a colored layer 132G that transmits green light, and a colored layer 132B that transmits blue light.

The light emitted by the light-emitting element 130R is extracted as red light to the outside of the display device 50F via the colored layer 132R. Similarly, the light emitted by the light-emitting element 130G is extracted as green light to the outside of the display device 50F via the colored layer 132G. The light emitted by the light-emitting element 130B is extracted as blue light to the outside of the display device 50F via the colored layer 132B.

Each of the light-emitting elements 130R, 130G, and 130B has a layer 133. These three layers 133 are formed using the same material and in the same process. In addition, these three layers 133 are separated from one another. By providing an island-like EL layer for each light-emitting element, it is possible to suppress leakage current between adjacent light-emitting elements. This makes it possible to prevent unintended light emission due to crosstalk, and to realize a display device with extremely high contrast.

For example, the light emitting elements 130R, 130G, and 130B shown in FIG. 34B emit white light. The white light emitted by the light emitting elements 130R, 130G, and 130B passes through the colored layers 132R, 132G, and 132B to obtain light of the desired color.

Or, for example, the light-emitting elements 130R, 130G, and 130B shown in FIG. 34B emit blue light. In this case, the layer 133 has one or more light-emitting layers that emit blue light. In the pixel 230B that emits blue light, the blue light emitted by the light-emitting element 130B can be extracted. In addition, in the pixel 230R that emits red light and the pixel 230G that emits green light, a color conversion layer is provided between the light-emitting element 130R or the light-emitting element 130G and the substrate 152, so that the blue light emitted by the light-emitting element 130R or the light-emitting element 130G can be converted into light with a longer wavelength, and red or green light can be extracted. Furthermore, it is preferable to provide a colored layer 132R between the color conversion layer and the substrate 152 on the light-emitting element 130R, and a colored layer 132G between the color conversion layer and the substrate 152 on the light-emitting element 130G. By extracting the light that has passed through the color conversion layer via the colored layer, light other than the desired color can be absorbed by the colored layer, thereby increasing the color purity of the light emitted by the subpixel.

<Display Device Configuration Example 7>
A display device 50G shown in FIG. 35 differs from the display device 50F mainly in that it is a bottom emission type display device.

Light emitted by the light-emitting element is emitted toward the substrate 151. It is preferable to use a material that is highly transparent to visible light for the substrate 151. On the other hand, the translucency of the material used for the substrate 152 does not matter.

It is preferable to form a light-shielding layer 117 between the substrate 151 and the transistor. FIG. 35 shows an example in which the light-shielding layer 117 is provided on the substrate 151, the insulating layer 153 is provided on the light-shielding layer 117, and the transistors 207D, 205R (not shown), 205G, and 205B are provided on the insulating layer 153. In addition, the colored layers 132R, 132G, and 132B are provided on the insulating layer 195, and the insulating layer 235 is provided on the colored layers 132R, 132G, and 132B.

The light-emitting element 130R, which overlaps with the colored layer 132R, has a conductive layer 124R, a conductive layer 126R, a layer 133, a common layer 114, and a common electrode 115.

The light-emitting element 130G, which overlaps with the colored layer 132G, has a conductive layer 124G, a conductive layer 126G, a layer 133, a common layer 114, and a common electrode 115.

The light-emitting element 130B, which overlaps with the colored layer 132B, has a conductive layer 124B, a conductive layer 126B, a layer 133, a common layer 114, and a common electrode 115.

The conductive layers 124R, 124G, 124B, 126R, 126G, and 126B are each made of a material that is highly transparent to visible light. It is preferable to use a material that reflects visible light for the common electrode 115. In a bottom emission display device, a metal with low electrical resistivity can be used for the common electrode 115, so that voltage drops caused by the electrical resistance of the common electrode 115 can be suppressed, and high display quality can be achieved.

The transistor of one embodiment of the present invention can be miniaturized and its occupation area can be reduced, so that in a display device with a bottom emission structure, the pixel aperture ratio can be increased or the pixel size can be reduced.

<Configuration Example 8 of Display Device>
A display device 50H shown in FIG. 36 is a VA mode liquid crystal display device.

Substrate 151 and substrate 152 are bonded together by adhesive layer 144. Liquid crystal 262 is sealed in the area surrounded by substrate 151, substrate 152, and adhesive layer 144. Polarizing plate 260a is located on the outer surface of substrate 152, and polarizing plate 260b is located on the outer surface of substrate 151. Although not shown, a backlight can be provided outside polarizing plate 260a or polarizing plate 260b.

Transistors 207D, 205R, and 205G, a connection portion 197, a spacer 224, and the like are provided on the substrate 151. The transistor 207D is provided in the circuit portion 164, and the transistors 205R and 205G are provided in the display portion 162. As the transistors included in the circuit portion 164 and the display portion 162, one or more of the transistors 100 to 100H and the transistors 200 to 200H can be used.

The substrate 152 is provided with colored layers 132R and 132G, a light-shielding layer 117, an insulating layer 225, a conductive layer 263, etc. The conductive layer 263 functions as a common electrode for the liquid crystal element 60.

As described above, in this embodiment, an example in which OS transistors are used as the transistors 207D, 205R, and 205G will be described. The transistors of one embodiment of the present invention can be used as the transistors 207D, 205R, and 205G. That is, the display device 50H includes transistors of one embodiment of the present invention in both the display portion 162 and the circuit portion 164. By using the transistor of one embodiment of the present invention in the display portion 162, the pixel size can be reduced, leading to higher resolution. Furthermore, by using the transistor of one embodiment of the present invention in the circuit portion 164, the area occupied by the circuit portion 164 can be reduced, leading to a narrower frame. For the transistor of one embodiment of the present invention, refer to the description of the previous embodiment.

The display portion 162 can preferably use one or more of the transistors 100 to 100H described above. The circuit portion 164 can preferably use one or more of the transistors 200 to 200H described above. FIG. 36 shows a configuration example in which the transistor 100 is applied to the transistors 205R and 205G, and the transistor 200 is applied to the transistor 207D. The region 108Db of the transistors 205R and 205G functions as a pixel electrode of the liquid crystal element 60. By using the transistor 100 in the display portion 162, unevenness caused by the transistor is reduced, and the alignment state of the liquid crystal 262 can be made uniform. In addition, the distance between the transistor and the element (e.g., a transistor and a capacitor) or wiring electrically connected to the transistor may be longer in the circuit portion 164 than in the display portion 162. Therefore, by using the transistor 200 in the circuit portion 164, a display device that operates at high speed can be obtained. Note that one or more types of transistors 200 to 200H can be used in the display portion 162, and one or more types of transistors 100 to 100H can be used in the circuit portion 164.

The subpixels of the display unit 162 each have a transistor, a liquid crystal element 60, and a colored layer. For example, a subpixel that emits red light has a transistor 205R, a liquid crystal element 60, and a colored layer 132R that transmits red light. A subpixel that emits green light has a transistor 205G, a liquid crystal element 60, and a colored layer 132G that transmits green light. Although not shown, a subpixel that emits blue light similarly has a transistor, a liquid crystal element 60, and a colored layer that transmits blue light.

The liquid crystal element 60 has a region 108Db, a conductive layer 263, and liquid crystal 262 sandwiched between them.

A conductive layer 264 is provided on the substrate 151, and is located on the same plane as the conductive layer 112. The conductive layer 264 has a portion that overlaps with the region 108Db via the insulating layer 110. A storage capacitance is formed by the region 108Db, the conductive layer 264, and the insulating layer 110 therebetween. It is preferable that there be one or more insulating layers between the region 108Db and the conductive layer 264, and one or two of the insulating layers 110 may be removed by etching.

On the substrate 152 side, an insulating layer 225 is provided to cover the colored layers 132R and 132G and the light-shielding layer 117. The insulating layer 225 may also function as a planarizing layer. The insulating layer 225 can make the surface of the conductive layer 263 roughly flat, thereby making the orientation state of the liquid crystal 262 uniform.

In addition, an orientation film for controlling the orientation of the liquid crystal 262 may be provided on the surfaces of the conductive layer 263 and the insulating layer 195, etc. that come into contact with the liquid crystal 262 (see the orientation film 265 in Figure 38).

The region 108Db and the conductive layer 263 transmit visible light. In other words, it can be a transmissive liquid crystal device. For example, if a backlight is placed on the substrate 152 side, the light from the backlight polarized by the polarizing plate 260a passes through the substrate 152, the conductive layer 263, the liquid crystal 262, the region 108Db, and the substrate 151 to reach the polarizing plate 260b. At this time, the orientation of the liquid crystal 262 can be controlled by the voltage applied between the region 108Db and the conductive layer 263, and the optical modulation of the light can be controlled. In other words, the intensity of the light emitted through the polarizing plate 260b can be controlled. In addition, the colored layer absorbs light other than that in a specific wavelength range, so that the extracted light is, for example, red light.

Here, a linear polarizing plate may be used as polarizing plate 260b, but a circular polarizing plate may also be used. For example, a linear polarizing plate and a quarter-wave retardation plate stacked together may be used as the circular polarizing plate. By using a circular polarizing plate for polarizing plate 260b, it is possible to suppress reflection of external light.

When a circular polarizer is used as polarizer 260b, a circular polarizer may also be used as polarizer 260a, or a normal linear polarizer may be used. The desired contrast can be achieved by adjusting the cell gap, orientation, drive voltage, etc. of the liquid crystal element used in liquid crystal element 60 according to the type of polarizer used for polarizers 260a and 260b.

The conductive layer 263 is electrically connected to the conductive layer 166b provided on the substrate 151 side at the connection portion 140 by the connector 223. The conductive layer 166b is connected to the conductive layer 165b at an opening provided in the insulating layer 110. This allows a potential or signal to be supplied to the conductive layer 263 from an FPC or IC arranged on the substrate 151 side. The configuration shown in FIG. 36 shows an example in which the conductive layer 165b is formed in the same process using the same material as the conductive layer 112 and the conductive layer 212a, and an example in which the conductive layer 166b is formed in the same process using the same material as the conductive layer 212b.

As the connector 223, for example, conductive particles can be used. As the conductive particles, particles such as resin or silica whose surfaces are coated with a metal material can be used. Nickel or gold is preferably used as the metal material because it can reduce the contact resistance. It is also preferable to use particles coated with two or more metal materials in layers, such as nickel further coated with gold. It is also preferable to use a material that undergoes elastic or plastic deformation as the connector 223. In this case, the conductive particles may be crushed in the vertical direction as shown in FIG. 36. This increases the contact area between the connector 223 and the conductive layer electrically connected thereto, thereby reducing the contact resistance and suppressing the occurrence of problems such as poor connection. It is preferable to arrange the connector 223 so that it is covered by the adhesive layer 144. For example, it is preferable to disperse the connector 223 in the adhesive layer 144 before hardening.

A connection portion 197 is provided in a region near the end of the substrate 151. In the connection portion 197, the conductive layer 166a is electrically connected to the FPC 172 via the connection layer 242. The conductive layer 166a is connected to the conductive layer 165a via an opening provided in the insulating layer 110. The configuration shown in FIG. 36 shows an example in which the conductive layer 165a is formed in the same process using the same material as the conductive layer 212a, and an example in which the conductive layer 166a is formed in the same process using the same material as the conductive layer 212b.

<Configuration Example 9 of Display Device>
37 is a liquid crystal display device in the FFS mode. The display device 50I differs from the display device 50H mainly in the configuration of the liquid crystal element 60.

A region 108Db of the layer 108 of the transistor 205R functions as the other of the source electrode and drain electrode of the transistor and also functions as a pixel electrode of the liquid crystal element 60. An insulating layer 195 is provided on the transistor, and a conductive layer 263 that functions as a common electrode of the liquid crystal element 60 is provided on the insulating layer 195. In addition, an insulating layer 261 is provided on the conductive layer 263.

The conductive layer 263 has a comb-like shape or a shape with slits in a plan view. The conductive layer 263 is disposed so as to overlap the region 108Db. In the region overlapping the colored layer, there is a portion on the region 108Db where the conductive layer 263 is not disposed.

A capacitance is formed by stacking region 108Db and conductive layer 263 via insulating layer 106 and insulating layer 195. This eliminates the need to form a separate capacitive element, and allows the aperture ratio of the pixel to be increased.

In the liquid crystal element 60, both the region 108Db and the conductive layer 263 may have a comb-like upper surface shape. On the other hand, as shown in the display device 50I, in the liquid crystal element 60, by making only one of the region 108Db and the conductive layer 263 have a comb-like upper surface shape, the region 108Db and the conductive layer 263 partially overlap. This allows the capacitance between the region 108Db and the conductive layer 263 to be used as a storage capacitance, eliminating the need to provide a separate capacitive element and increasing the aperture ratio of the display device.

As shown in FIG. 38, an alignment film 265 can be provided on the surfaces of the conductive layer 263 and the insulating layer 225 facing the liquid crystal 262.

<Example of a method for manufacturing a display device>
A method for manufacturing a display device to which the MML (metal maskless) structure is applied will be described below with reference to Fig. 39. Here, a process for manufacturing a light-emitting element without using a fine metal mask will be described in detail. Fig. 39 shows cross-sectional views of three light-emitting elements and a connection part 140 of a display part 162 in each process.

Light-emitting elements can be fabricated using vacuum processes such as deposition, and solution processes such as spin coating and inkjet printing. Examples of deposition methods include physical deposition (PVD) methods such as sputtering, ion plating, ion beam deposition, molecular beam deposition, and vacuum deposition, and chemical deposition (CVD). In particular, the functional layers included in the EL layer (hole injection layer, hole transport layer, hole blocking layer, light-emitting layer, electron blocking layer, electron transport layer, electron injection layer, charge generation layer, etc.) can be formed by deposition (vacuum deposition, etc.), coating methods (dip coating, die coating, bar coating, spin coating, spray coating, etc.), printing methods (inkjet, screen (screen printing), offset (lithographic printing), flexo (letterpress), gravure, microcontact, etc.), etc.

The island-like layer (layer including the light-emitting layer) produced by the method for producing a display device described below is not formed using a fine metal mask, but is formed by depositing the light-emitting layer over one surface and then processing it using photolithography. This makes it possible to realize a high-definition display device or a display device with a high aperture ratio, which has been difficult to achieve until now. Furthermore, since the light-emitting layers can be produced separately for each color, it is possible to realize a display device that is extremely vivid, has high contrast, and has high display quality. Furthermore, by providing a sacrificial layer on the light-emitting layer, damage to the light-emitting layer during the production process of the display device can be reduced, and the reliability of the light-emitting element can be increased.

For example, if a display device is composed of three types of light-emitting elements, one that emits blue light, one that emits green light, and one that emits red light, three types of island-shaped light-emitting layers can be formed by repeating the deposition of the light-emitting layer and processing by photolithography three times.

First, pixel electrodes 111R, 111G, and 111B and a conductive layer 123 are formed on a substrate 151 on which transistors 205R, 205G, and 205B (not shown) are provided (Figure 39A).

The conductive film that becomes the pixel electrodes can be formed by, for example, sputtering or vacuum deposition. After forming a resist mask on the conductive film by a photolithography process, the conductive film can be processed to form pixel electrodes 111R, 111G, and 111B and conductive layer 123. The conductive film can be processed by one or both of wet etching and dry etching.

Next, a film 133Bf, which will later become layer 133B, is formed on pixel electrodes 111R, 111G, and 111B (Figure 39A). Film 133Bf (later layer 133B) includes a light-emitting layer that emits blue light.

In this embodiment, an example is shown in which an island-shaped EL layer of a light-emitting element that emits blue light is first formed, and then an island-shaped EL layer of a light-emitting element that emits light of another color is formed.

In the process of forming the island-shaped EL layer, the pixel electrodes of the light-emitting elements of the colors formed second or later may be damaged by the previous process. This may result in the driving voltage of the light-emitting elements of the colors formed second or later being higher.

Therefore, when manufacturing a display device according to one embodiment of the present invention, it is preferable to start with an island-shaped EL layer of a light-emitting element that emits light with the shortest wavelength (e.g., a blue light-emitting element). For example, it is preferable to manufacture the island-shaped EL layers in the order of blue, green, and red, or blue, red, and green.

As a result, the state of the interface between the pixel electrode and the EL layer in the blue light-emitting element can be kept good, and the drive voltage of the blue light-emitting element can be prevented from increasing. It also extends the life of the blue light-emitting element and improves its reliability. Furthermore, since the red and green light-emitting elements are less affected by increases in drive voltage compared to the blue light-emitting element, the drive voltage can be reduced and the reliability can be improved for the entire display device.

The order in which the island-shaped EL layers are fabricated is not limited to the above, and may be, for example, red, green, and blue.

As shown in FIG. 39A, film 133Bf is not formed on conductive layer 123. For example, by using an area mask, film 133Bf can be formed only in desired areas. By employing a film formation process using an area mask and a processing process using a resist mask, a light-emitting element can be manufactured through a relatively simple process.

The heat resistance temperature of the compounds contained in film 133Bf is preferably 100°C or higher and 180°C or lower, more preferably 120°C or higher and 180°C or lower, and more preferably 140°C or higher and 180°C or lower. This can improve the reliability of the light-emitting element. In addition, the upper limit of the temperature that can be applied in the manufacturing process of the display device can be increased. This can therefore broaden the range of choices for materials and formation methods used in the display device, improving yield and reliability.

The heat resistance temperature can be, for example, any one of the glass transition point, softening point, melting point, thermal decomposition temperature, and 5% weight loss temperature, preferably the lowest temperature among these.

The film 133Bf can be formed, for example, by a deposition method, specifically a vacuum deposition method. The film 133Bf may also be formed by a transfer method, a printing method, an inkjet method, a coating method, or other methods.

Subsequently, a sacrificial layer 118B is formed on the film 133Bf and on the conductive layer 123 (FIG. 39A). After a resist mask is formed by a photolithography process on the film that will become the sacrificial layer 118B, the film can be processed to form the sacrificial layer 118B.

By providing a sacrificial layer 118B on the film 133Bf, damage to the film 133Bf during the manufacturing process of the display device can be reduced, and the reliability of the light-emitting element can be improved.

The sacrificial layer 118B is preferably provided so as to cover the ends of each of the pixel electrodes 111R, 111G, and 111B. This means that the ends of the layer 133B formed in a later process will be located outside the ends of the pixel electrode 111B. This makes it possible to use the entire upper surface of the pixel electrode 111B as a light-emitting region, thereby increasing the aperture ratio of the pixel. In addition, since the ends of the layer 133B may be damaged in a process after the formation of the layer 133B, it is preferable that they are located outside the ends of the pixel electrode 111B, that is, are not used as a light-emitting region. This makes it possible to suppress variation in the characteristics of the light-emitting element and increase reliability.

By covering the top and side surfaces of pixel electrode 111B with layer 133B, each process after the formation of layer 133B can be performed without pixel electrode 111B being exposed. If the ends of pixel electrode 111B are exposed, corrosion may occur during an etching process or the like. By suppressing corrosion of pixel electrode 111B, the yield and characteristics of the light-emitting element can be improved.

It is preferable to provide the sacrificial layer 118B in a position that overlaps the conductive layer 123. This makes it possible to prevent the conductive layer 123 from being damaged during the manufacturing process of the display device.

For the sacrificial layer 118B, a film that is highly resistant to the processing conditions of the film 133Bf, specifically, a film that has a large etching selectivity with respect to the film 133Bf, is used.

The sacrificial layer 118B is formed at a temperature lower than the heat resistance temperature of each compound contained in the film 133Bf. The substrate temperature when forming the sacrificial layer 118B is typically 200°C or less, preferably 150°C or less, more preferably 120°C or less, more preferably 100°C or less, and even more preferably 80°C or less.

If the heat resistance temperature of the compound contained in film 133Bf is high, the deposition temperature of sacrificial layer 118B can be made high, which is preferable. For example, the substrate temperature when forming sacrificial layer 118B can be set to 100°C or higher, 120°C or higher, or 140°C or higher. The higher the deposition temperature, the denser the inorganic insulating film can be and the higher its barrier properties can be. Therefore, by depositing the sacrificial layer at such a temperature, damage to film 133Bf can be further reduced, and the reliability of the light-emitting element can be improved.

The same can be said about the deposition temperature of each of the other layers (e.g., insulating film 125f) formed on film 133Bf.

The sacrificial layer 118B can be formed, for example, by sputtering, ALD (including thermal ALD and PEALD), CVD, or vacuum deposition. It may also be formed by using the wet film formation method described above.

The sacrificial layer 118B (the layer provided in contact with the film 133Bf when the sacrificial layer 118B has a laminated structure) is preferably formed using a formation method that causes less damage to the film 133Bf. For example, it is preferable to use the ALD method or the vacuum deposition method rather than the sputtering method.

The sacrificial layer 118B can be processed by wet etching or dry etching. It is preferable to process the sacrificial layer 118B by anisotropic etching.

By using the wet etching method, damage to the film 133Bf during processing of the sacrificial layer 118B can be reduced compared to when using the dry etching method. When using the wet etching method, it is preferable to use, for example, a developer, a tetramethylammonium hydroxide (TMAH) aqueous solution, dilute hydrofluoric acid, oxalic acid, phosphoric acid, acetic acid, nitric acid, or a mixed solution containing two or more of these. Also, when using the wet etching method, a mixed acid-based chemical solution containing water, phosphoric acid, dilute hydrofluoric acid, and nitric acid may be used. The chemical solution used in the wet etching process may be alkaline or acidic.

The sacrificial layer 118B may be, for example, one or more of a metal film, an alloy film, a metal oxide film, a semiconductor film, an inorganic insulating film, and an organic insulating film.

The sacrificial layer 118B can be made of metal materials such as gold, silver, platinum, magnesium, nickel, tungsten, chromium, molybdenum, iron, cobalt, copper, palladium, titanium, aluminum, yttrium, zirconium, and tantalum, or alloy materials containing such metal materials.

The sacrificial layer 118B can be made of metal oxides such as In-Ga-Zn oxide, indium oxide, In-Zn oxide, In-Sn oxide, indium titanium oxide (In-Ti oxide), indium tin zinc oxide (In-Sn-Zn oxide), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide), and indium tin oxide containing silicon.

In addition, element M (wherein M is one or more elements selected from aluminum, silicon, boron, yttrium, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium) may be used in place of the above gallium.

For example, semiconductor materials such as silicon or germanium can be used as materials that have high compatibility with semiconductor manufacturing processes. Alternatively, oxides or nitrides of the above semiconductor materials can be used. Alternatively, non-metallic materials such as carbon, or compounds thereof can be used. Alternatively, metals such as titanium, tantalum, tungsten, chromium, and aluminum, or alloys containing one or more of these, can be used. Alternatively, oxides containing the above metals, such as titanium oxide or chromium oxide, or nitrides such as titanium nitride, chromium nitride, or tantalum nitride can be used.

As the sacrificial layer 118B, an inorganic insulating film that can be used for the protective layer 131 can be used. In particular, oxides are preferable because they have higher adhesion to the film 133Bf than nitrides. For example, one or more of aluminum oxide, hafnium oxide, and silicon oxide can be suitably used for the sacrificial layer 118B. As the sacrificial layer 118B, an aluminum oxide film can be formed, for example, using the ALD method. Using the ALD method is preferable because it can reduce damage to the base (particularly the film 133Bf).

For example, the sacrificial layer 118B can be a laminated structure of an inorganic insulating film (e.g., an aluminum oxide film) formed using the ALD method and an inorganic film (e.g., an In-Ga-Zn oxide film, a silicon film, or a tungsten film) formed using the sputtering method.

The same inorganic insulating film can be used for both the sacrificial layer 118B and the insulating layer 125 to be formed later. For example, an aluminum oxide film formed by ALD can be used for both the sacrificial layer 118B and the insulating layer 125. The same film-forming conditions can be applied to the sacrificial layer 118B and the insulating layer 125, or different film-forming conditions can be applied to each of them. For example, by forming the sacrificial layer 118B under the same conditions as the insulating layer 125, the sacrificial layer 118B can be an insulating layer with high barrier properties against at least one of water and oxygen. On the other hand, since the sacrificial layer 118B is a layer that is removed in most or all in a later process, it is preferable that it is easy to process. Therefore, it is preferable that the sacrificial layer 118B is formed under conditions where the substrate temperature during film formation is lower than that of the insulating layer 125.

An organic material may be used for the sacrificial layer 118B. For example, the organic material may be a material that is soluble in a solvent that is chemically stable with respect to at least the film located at the top of the film 133Bf. In particular, a material that dissolves in water or alcohol is preferably used. When forming a film of such a material, it is preferable to apply the material by a wet film formation method while dissolving it in a solvent such as water or alcohol, and then perform a heat treatment to evaporate the solvent. At this time, by performing the heat treatment under a reduced pressure atmosphere, the solvent can be removed at a low temperature in a short time, which is preferable as it reduces thermal damage to the film 133Bf.

The sacrificial layer 118B may be made of a resin such as polyvinyl alcohol (PVA), polyvinyl butyral, polyvinylpyrrolidone, polyethylene glycol, polyglycerin, pullulan, water-soluble cellulose, alcohol-soluble polyamide resin, or a fluororesin such as a perfluoropolymer.

For example, the sacrificial layer 118B can be a laminated structure of an organic film (e.g., a PVA film) formed using either a vapor deposition method or the above-mentioned wet film formation method, and an inorganic film (e.g., a silicon nitride film) formed using a sputtering method.

In addition, in a display device according to one embodiment of the present invention, a portion of the sacrificial film may remain as a sacrificial layer.

Then, the film 133Bf is processed using the sacrificial layer 118B as a hard mask to form layer 133B (Figure 39B).

As a result, as shown in FIG. 39B, a laminated structure of layer 133B and sacrificial layer 118B remains on pixel electrode 111B. Pixel electrodes 111R and 111G are exposed. In addition, in the region corresponding to connection portion 140, sacrificial layer 118B remains on conductive layer 123.

The film 133Bf is preferably processed by anisotropic etching. In particular, anisotropic dry etching is preferable. Alternatively, wet etching may be used.

Then, the process of forming film 133Bf, the process of forming sacrificial layer 118B, and the process of forming layer 133B are repeated at least twice, changing the light-emitting material, to form a layered structure of layer 133R and sacrificial layer 118R on pixel electrode 111R, and a layered structure of layer 133G and sacrificial layer 118G on pixel electrode 111G (FIG. 39C). Specifically, layer 133R is formed to include a light-emitting layer that emits red light, and layer 133G is formed to include a light-emitting layer that emits green light. The materials that can be used for sacrificial layer 118B can be applied to sacrificial layers 118R and 118G, and both may be the same material or different materials may be used.

It is preferable that the side surfaces of layers 133B, 133G, and 133R are perpendicular or approximately perpendicular to the surface on which they are to be formed. For example, it is preferable that the angle between the surface on which they are to be formed and these side surfaces is between 60 degrees or more and 90 degrees or less.

As described above, the distance between two adjacent layers of layers 133B, 133G, and 133R formed using photolithography can be narrowed to 8 μm or less, 5 μm or less, 3 μm or less, 2 μm or less, or 1 μm or less. Here, the distance can be defined as, for example, the distance between two adjacent opposing ends of layers 133B, 133G, and 133R. In this way, by narrowing the distance between the island-shaped EL layers, a display device with high definition and a large aperture ratio can be provided.

Then, insulating film 125f, which will later become insulating layer 125, is formed to cover the pixel electrode, layer 133B, layer 133G, layer 133R, sacrificial layer 118B, sacrificial layer 118G, and sacrificial layer 118R, and insulating layer 127 is formed on insulating film 125f (Figure 39D).

It is preferable to form the insulating film 125f with a thickness of 3 nm or more, 5 nm or more, or 10 nm or more, and 200 nm or less, 150 nm or less, 100 nm or less, or 50 nm or less.

The insulating film 125f is preferably formed by, for example, the ALD method. The ALD method is preferable because it can reduce film formation damage and can form a film with high coating properties. It is preferable to form an aluminum oxide film as the insulating film 125f by, for example, the ALD method.

In addition, the insulating film 125f may be formed using a sputtering method, a CVD method, or a PECVD method, which have a faster film formation speed than the ALD method. This allows a highly reliable display device to be manufactured with high productivity.

The insulating film that becomes the insulating layer 127 is preferably formed by the above-mentioned wet film formation method (e.g., spin coating) using, for example, a photosensitive resin composition containing an acrylic resin. After the film formation, it is preferable to remove the solvent contained in the insulating film by performing a heat treatment (also called pre-baking). Next, visible light or ultraviolet light is irradiated to a part of the insulating film to expose the part. Next, development is performed to remove the exposed area of the insulating film. Next, a heat treatment (also called post-baking) is performed. This allows the insulating layer 127 shown in FIG. 39D to be formed. Note that the shape of the insulating layer 127 is not limited to the shape shown in FIG. 39D. For example, the upper surface of the insulating layer 127 can have one or more of a convex curved surface, a concave curved surface, and a flat surface. In addition, the insulating layer 127 may cover the side surface of at least one end of the insulating layer 125, the sacrificial layer 118B, the sacrificial layer 118G, and the sacrificial layer 118R.

Next, as shown in FIG. 39E, an etching process is performed using the insulating layer 127 as a mask to remove the insulating film 125f and parts of the sacrificial layers 118B, 118G, and 118R. As a result, openings are formed in the sacrificial layers 118B, 118G, and 118R, respectively, and the top surfaces of the layers 133B, 133G, and 133R, and the conductive layer 123 are exposed. Note that parts of the sacrificial layers 118B, 118G, and 118R may remain at positions overlapping the insulating layer 127 and the insulating layer 125 (see sacrificial layers 119B, 119G, and 119R).

The etching process can be performed by dry etching or wet etching. If the insulating film 125f is formed using the same material as the sacrificial layers 118B, 118G, and 118R, this is preferable because the etching process can be performed in one step.

As described above, by providing insulating layer 127, insulating layer 125, sacrificial layer 118B, sacrificial layer 118G, and sacrificial layer 118R, it is possible to prevent connection failures caused by disconnected portions of common layer 114 and common electrode 115 between each light-emitting element, and increases in electrical resistance caused by locally thin portions. This allows the display device of one embodiment of the present invention to have improved display quality.

Next, the common layer 114 and the common electrode 115 are formed in this order on the insulating layer 127, the layer 133B, the layer 133G, and the layer 133R (Figure 39F).

The common layer 114 can be formed by a method such as a deposition method (including a vacuum deposition method), a transfer method, a printing method, an inkjet method, or a coating method.

The common electrode 115 can be formed by, for example, sputtering or vacuum deposition. Alternatively, a film formed by deposition and a film formed by sputtering can be laminated together.

As described above, in the manufacturing method of the display device according to one embodiment of the present invention, the island-shaped layers 133B, 133G, and 133R are not formed using a fine metal mask, but are formed by forming a film over the entire surface and processing the film, so that the island-shaped layers can be formed with a uniform thickness. This makes it possible to realize a high-definition display device or a display device with a high aperture ratio. Even if the definition or aperture ratio is high and the distance between the subpixels is extremely short, the layers 133B, 133G, and 133R can be prevented from contacting each other in adjacent subpixels. Therefore, it is possible to prevent leakage current from occurring between the subpixels. This makes it possible to prevent unintended light emission due to crosstalk, and to realize a display device with extremely high contrast.

By providing an insulating layer 127 having a tapered end between adjacent island-shaped EL layers, it is possible to suppress the occurrence of a step when forming the common electrode 115, and also to prevent the formation of locally thin areas in the common electrode 115. This makes it possible to suppress the occurrence of poor connection due to the disconnected areas in the common layer 114 and the common electrode 115, and an increase in electrical resistance due to locally thin areas. Therefore, the display device of one embodiment of the present invention can achieve both high definition and high display quality.

This embodiment can be combined with other embodiments as appropriate.

(Embodiment 4)
In this embodiment, electronic devices of one embodiment of the present invention will be described with reference to FIGS.

The electronic device of this embodiment has a display device of one embodiment of the present invention in a display portion. The display device of one embodiment of the present invention can easily achieve high definition and high resolution. Therefore, it can be used in the display portion of various electronic devices.

The semiconductor device of one embodiment of the present invention can be applied to parts other than the display part of an electronic device. For example, by using the semiconductor device of one embodiment of the present invention in a control part of an electronic device, it is possible to reduce power consumption, which is preferable.

Electronic devices include, for example, electronic devices with relatively large screens such as television sets, desktop or notebook computers, computer monitors, digital signage, large game machines such as pachinko machines, as well as digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, personal digital assistants, and audio playback devices.

In particular, the display device of one embodiment of the present invention can be used favorably in electronic devices having a relatively small display area because it is possible to increase the resolution. Examples of such electronic devices include wristwatch-type and bracelet-type information terminals (wearable devices), as well as wearable devices that can be worn on the head, such as VR devices such as head-mounted displays, glasses-type AR devices, and MR devices.

The display device of one embodiment of the present invention preferably has an extremely high resolution such as HD (1280 x 720 pixels), FHD (1920 x 1080 pixels), WQHD (2560 x 1440 pixels), WQXGA (2560 x 1600 pixels), 4K (3840 x 2160 pixels), or 8K (7680 x 4320 pixels). In particular, a resolution of 4K, 8K, or higher is preferable. Furthermore, the pixel density (resolution) of the display device of one embodiment of the present invention is preferably 100 ppi or more, preferably 300 ppi or more, more preferably 500 ppi or more, more preferably 1000 ppi or more, more preferably 2000 ppi or more, more preferably 3000 ppi or more, more preferably 5000 ppi or more, and even more preferably 7000 ppi or more. By using a display device having either or both of high resolution and high definition, it is possible to further enhance the sense of realism and depth. In addition, there is no particular limitation on the screen ratio (aspect ratio) of the display device of one embodiment of the present invention. For example, the display device can support various screen ratios such as 1:1 (square), 4:3, 16:9, and 16:10.

The electronic device of this embodiment can be configured to have a sensor (including the function of sensing, detecting, or measuring force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared light).

The electronic device of this embodiment can have various functions. For example, it can have a function to display various information (still images, videos, text images, etc.) on the display unit, a touch panel function, a function to display a calendar, date or time, etc., a function to execute various software (programs), a wireless communication function, a function to read out programs or data recorded on a recording medium, etc.

An example of a wearable device that can be worn on the head is described below using Figures 40A to 40D. These wearable devices have at least one of the following functions: a function to display AR content, a function to display VR content, a function to display SR content, and a function to display MR content. By having an electronic device have the function to display at least one of AR, VR, SR, and MR content, it is possible to enhance the user's sense of immersion.

Electronic device 700A shown in FIG. 40A and electronic device 700B shown in FIG. 40B each have a pair of display panels 751, a pair of housings 721, a communication unit (not shown), a pair of mounting units 723, a control unit (not shown), an imaging unit (not shown), a pair of optical members 753, a frame 757, and a pair of nose pads 758.

A display device according to one embodiment of the present invention can be applied to the display panel 751. Therefore, the electronic device can display images with extremely high resolution.

Electronic device 700A and electronic device 700B can each project an image displayed on display panel 751 onto display area 756 of optical member 753. Because optical member 753 is translucent, the user can see the image displayed in the display area superimposed on the transmitted image visible through optical member 753. Therefore, electronic device 700A and electronic device 700B are each electronic devices capable of AR display.

Electronic device 700A and electronic device 700B can be provided with a camera that captures an image in front of them as an imaging unit. In addition, electronic device 700A and electronic device 700B can each be provided with an acceleration sensor such as a gyro sensor, thereby detecting the orientation of the user's head and displaying an image corresponding to that orientation in display area 756.

The communication unit has a wireless communication device, and can supply video signals and the like via the wireless communication device. Note that instead of or in addition to the wireless communication device, a connector can be provided to which a cable through which a video signal and power supply potential can be connected.

Electronic device 700A and electronic device 700B are provided with a battery (not shown) and can be charged wirelessly, wired, or both.

The housing 721 may be provided with a touch sensor module. The touch sensor module has a function of detecting when the outer surface of the housing 721 is touched. The touch sensor module can detect a tap operation or a slide operation by the user and execute various processes. For example, a tap operation can execute processes such as pausing or resuming a video, and a slide operation can execute processes such as fast-forwarding or rewinding. Furthermore, by providing a touch sensor module on each of the two housings 721, the range of operations can be expanded.

Various types of touch sensors can be used as the touch sensor module. For example, various types can be adopted, such as the capacitance type, resistive film type, infrared type, electromagnetic induction type, surface acoustic wave type, and optical type. In particular, it is preferable to use a capacitance type or optical type sensor in the touch sensor module.

When using an optical touch sensor, a photoelectric conversion element can be used as the light receiving element. The active layer of the photoelectric conversion element can be made of either or both of an inorganic semiconductor and an organic semiconductor.

Electronic device 800A shown in FIG. 40C and electronic device 800B shown in FIG. 40D each have a pair of display units 820, a housing 821, a communication unit 822, a pair of mounting units 823, a control unit 824, a pair of imaging units 825, and a pair of lenses 832. Note that display unit 820, communication unit 822, and imaging unit 825 are omitted in FIG. 40D.

A display device according to one embodiment of the present invention can be applied to the display portion 820. Therefore, the electronic device can display images with extremely high resolution. This allows the user to feel a high sense of immersion.

The display unit 820 is provided inside the housing 821 at a position that can be seen through the lens 832. In addition, by displaying different images on the pair of display units 820, it is also possible to perform three-dimensional display using parallax.

The electronic device 800A and the electronic device 800B can each be considered electronic devices for VR. A user wearing the electronic device 800A or the electronic device 800B can view the image displayed on the display unit 820 through the lens 832.

Electric device 800A and electronic device 800B each preferably have a mechanism that can adjust the left-right positions of lens 832 and display unit 820 so that they are optimally positioned according to the position of the user's eyes. Also, it is preferable that they have a mechanism that can adjust the focus by changing the distance between lens 832 and display unit 820.

The attachment unit 823 allows the user to attach the electronic device 800A or electronic device 800B to the head. Note that in FIG. 40C and other figures, the attachment unit 823 is shaped like the temples of glasses, but is not limited to this. The attachment unit 823 has a shape that allows the user to wear it, and can be shaped like a helmet or band, for example.

The imaging unit 825 has a function of acquiring external information. The data acquired by the imaging unit 825 can be output to the display unit 820. An image sensor can be used for the imaging unit 825. In addition, multiple cameras may be provided to support multiple angles of view, such as telephoto and wide angle.

Note that although an example having an imaging unit 825 is shown here, a distance measuring sensor (hereinafter also referred to as a detection unit) capable of measuring the distance to an object can be provided. In other words, the imaging unit 825 is one aspect of the detection unit. As the detection unit, for example, an image sensor or a distance image sensor such as a LIDAR (Light Detection and Ranging) can be used. By using the image obtained by the camera and the image obtained by the distance image sensor, more information can be obtained, enabling more precise gesture operation.

The electronic device 800A may have a vibration mechanism that functions as a bone conduction earphone. For example, a configuration having such a vibration mechanism can be applied to one or more of the display unit 820, the housing 821, and the wearing unit 823. This makes it possible to enjoy video and audio by simply wearing the electronic device 800A without the need for separate audio equipment such as headphones, earphones, or speakers.

Each of electronic devices 800A and 800B may have an input terminal. The input terminal can be connected to a cable that supplies a video signal from a video output device or the like, and power for charging a battery provided within the electronic device.

The electronic device of one embodiment of the present invention may have a function of wireless communication with the earphone 750. The earphone 750 has a communication unit (not shown) and has a wireless communication function. The earphone 750 can receive information (e.g., audio data) from the electronic device through the wireless communication function. For example, the electronic device 700A shown in FIG. 40A has a function of transmitting information to the earphone 750 through the wireless communication function. Also, for example, the electronic device 800A shown in FIG. 40C has a function of transmitting information to the earphone 750 through the wireless communication function.

The electronic device may have an earphone unit. The electronic device 700B shown in FIG. 40B has an earphone unit 727. For example, the earphone unit 727 and the control unit may be configured to be connected to each other by wire. A portion of the wiring connecting the earphone unit 727 and the control unit may be disposed inside the housing 721 or the attachment unit 723.

Similarly, electronic device 800B shown in FIG. 40D has earphone unit 827. For example, earphone unit 827 and control unit 824 can be configured to be connected to each other by wire. Part of the wiring connecting earphone unit 827 and control unit 824 may be disposed inside housing 821 or mounting unit 823. Also, earphone unit 827 and mounting unit 823 may have magnets. This allows earphone unit 827 to be fixed to mounting unit 823 by magnetic force, which is preferable as it makes storage easier.

The electronic device may have an audio output terminal to which earphones or headphones can be connected. The electronic device may also have one or both of an audio input terminal and an audio input mechanism. For example, a sound collection device such as a microphone can be used as the audio input mechanism. By having the audio input mechanism, the electronic device may be endowed with the functionality of a so-called headset.

As such, electronic devices according to one embodiment of the present invention are suitable for both glasses-type devices (such as electronic device 700A and electronic device 700B) and goggle-type devices (such as electronic device 800A and electronic device 800B).

The electronic device of one embodiment of the present invention can transmit information to the earphones via wire or wirelessly.

The electronic device 6500 shown in FIG. 41A is a portable information terminal that can be used as a smartphone.

The electronic device 6500 has a housing 6501, a display portion 6502, a power button 6503, a button 6504, a speaker 6505, a microphone 6506, a camera 6507, and a light source 6508. The display portion 6502 has a touch panel function.

The display device of one embodiment of the present invention can be applied to the display portion 6502.

FIG. 41B is a schematic cross-sectional view including the end of the housing 6501 on the microphone 6506 side.

A translucent protective member 6510 is provided on the display surface side of the housing 6501, and a display panel 6511, optical members 6512, a touch sensor panel 6513, a printed circuit board 6517, a battery 6518, etc. are arranged in the space surrounded by the housing 6501 and the protective member 6510.

The display panel 6511, the optical member 6512, and the touch sensor panel 6513 are fixed to the protective member 6510 by an adhesive layer (not shown).

A part of the display panel 6511 is folded back in the area outside the display unit 6502, and the FPC 6515 is connected to the folded back part. An IC 6516 is mounted on the FPC 6515. The FPC 6515 is connected to a terminal provided on a printed circuit board 6517.

The display device of one embodiment of the present invention can be applied to the display panel 6511. Therefore, an extremely lightweight electronic device can be realized. In addition, since the display panel 6511 is extremely thin, a large-capacity battery 6518 can be mounted thereon while keeping the thickness of the electronic device small. In addition, by folding back a part of the display panel 6511 and arranging a connection portion with the FPC 6515 on the back side of the pixel portion, an electronic device with a narrow frame can be realized.

Figure 41C shows an example of a television device. In the television device 7100, a display unit 7000 is built into a housing 7101. In this example, the housing 7101 is supported by a stand 7103.

A display device according to one embodiment of the present invention can be applied to the display portion 7000.

The television device 7100 shown in FIG. 41C can be operated using operation switches provided on the housing 7101 and a separate remote control 7111. Alternatively, the display unit 7000 may be provided with a touch sensor, and the television device 7100 may be operated by touching the display unit 7000 with a finger or the like. The remote control 7111 may have a display unit that displays information output from the remote control 7111. The channel and volume can be operated using operation keys or a touch panel provided on the remote control 7111, and the image displayed on the display unit 7000 can be operated.

The television device 7100 is configured to include a receiver and a modem. The receiver can receive general television broadcasts. In addition, by connecting to a wired or wireless communication network via the modem, it is also possible to carry out one-way (from sender to receiver) or two-way (between sender and receiver, or between receivers, etc.) information communication.

Figure 41D shows an example of a notebook computer. The notebook computer 7200 has a housing 7211, a keyboard 7212, a pointing device 7213, an external connection port 7214, etc. The display unit 7000 is built into the housing 7211.

A display device according to one embodiment of the present invention can be applied to the display portion 7000.

Figures 41E and 41F show an example of digital signage.

The digital signage 7300 shown in FIG. 41E has a housing 7301, a display unit 7000, and a speaker 7303. It can also have LED lamps, operation keys (including a power switch or an operation switch), connection terminals, various sensors, a microphone, etc.

FIG. 41F shows digital signage 7400 attached to a cylindrical pole 7401. Digital signage 7400 has a display unit 7000 that is provided along the curved surface of pole 7401.

In Figures 41E and 41F, a display device according to one embodiment of the present invention can be applied to the display portion 7000.

The larger the display unit 7000, the more information can be provided at one time. Also, the larger the display unit 7000, the more easily it catches people's attention, which can increase the advertising effectiveness of an advertisement, for example.

By applying a touch panel to the display unit 7000, not only can images or videos be displayed on the display unit 7000, but the user can also intuitively operate it, which is preferable. Furthermore, when used to provide information such as route information or traffic information, the intuitive operation can improve usability.

As shown in Figures 41E and 41F, it is preferable that the digital signage 7300 or the digital signage 7400 can be linked via wireless communication with an information terminal 7311 or an information terminal 7411 such as a smartphone carried by a user. For example, advertising information displayed on the display unit 7000 can be displayed on the screen of the information terminal 7311 or the information terminal 7411. In addition, the display on the display unit 7000 can be switched by operating the information terminal 7311 or the information terminal 7411.

The digital signage 7300 or the digital signage 7400 can also be made to run a game using the screen of the information terminal 7311 or the information terminal 7411 as an operating means (controller). This allows an unspecified number of users to participate in and enjoy the game at the same time.

The electronic device shown in Figures 42A to 42G has a housing 9000, a display unit 9001, a speaker 9003, operation keys 9005 (including a power switch or an operation switch), a connection terminal 9006, a sensor 9007 (including a function to sense, detect, or measure force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared light), a microphone 9008, etc.

In Figures 42A to 42G, a display device of one embodiment of the present invention can be applied to the display portion 9001.

The electronic devices shown in Figures 42A to 42G have various functions. For example, they can have a function to display various information (still images, videos, text images, etc.) on the display unit, a touch panel function, a function to display a calendar, date or time, etc., a function to control processing by various software (programs), a wireless communication function, a function to read and process programs or data recorded on a recording medium, etc. Note that the functions of the electronic devices are not limited to these, and they can have various functions. The electronic devices may have multiple display units. In addition, the electronic devices may have a function to provide a camera or the like, capture still images or videos, and store them on a recording medium (external or built into the camera), a function to display the captured images on the display unit, etc.

The details of the electronic devices shown in Figures 42A to 42G are described below.

FIG. 42A is a perspective view showing a mobile information terminal 9101. The mobile information terminal 9101 can be used as a smartphone, for example. The mobile information terminal 9101 may be provided with a speaker 9003, a connection terminal 9006, a sensor 9007, and the like. The mobile information terminal 9101 can display text and image information on multiple surfaces. FIG. 42A shows an example in which three icons 9050 are displayed. Information 9051 shown in a dashed rectangle can also be displayed on another surface of the display unit 9001. Examples of the information 9051 include notifications of incoming e-mail, SNS, and telephone calls, the title of e-mail or SNS, the sender's name, the date and time, the remaining battery level, and radio wave strength. Alternatively, an icon 9050 or the like may be displayed at the position where the information 9051 is displayed.

Figure 42B is a perspective view showing a mobile information terminal 9102. The mobile information terminal 9102 has a function of displaying information on three or more sides of the display unit 9001. Here, an example is shown in which information 9052, information 9053, and information 9054 are each displayed on different sides. For example, a user can check information 9053 displayed in a position that can be observed from above the mobile information terminal 9102 while the mobile information terminal 9102 is stored in a breast pocket of clothes. The user can check the display without taking the mobile information terminal 9102 out of the pocket and decide, for example, whether or not to answer a call.

FIG. 42C is a perspective view showing a tablet terminal 9103. The tablet terminal 9103 is capable of executing various applications such as mobile phone calls, e-mail, text browsing and creation, music playback, internet communication, and computer games, for example. The tablet terminal 9103 has a display unit 9001, a camera 9002, a microphone 9008, and a speaker 9003 on the front side of the housing 9000, operation keys 9005 as operation buttons on the side of the housing 9000, and a connection terminal 9006 on the bottom.

FIG. 42D is a perspective view showing a wristwatch-type mobile information terminal 9200. The mobile information terminal 9200 can be used, for example, as a smart watch (registered trademark). The display surface of the display unit 9001 is curved, and display can be performed along the curved display surface. The mobile information terminal 9200 can also make hands-free calls by communicating with, for example, a headset capable of wireless communication. The mobile information terminal 9200 can also transmit data to and from other information terminals and charge itself via a connection terminal 9006. Charging may be performed by wireless power supply.

FIGS. 42E to 42G are perspective views showing a foldable mobile information terminal 9201. FIG. 42E is a perspective view of the mobile information terminal 9201 in an unfolded state, FIG. 42G is a perspective view of the mobile information terminal 9201 in a folded state, and FIG. 42F is a perspective view of a state in the middle of changing from one of FIG. 42E and FIG. 42G to the other. The mobile information terminal 9201 is highly portable when folded, and is highly viewable due to a seamless, wide display area when unfolded. The display unit 9001 of the mobile information terminal 9201 is supported by three housings 9000 connected by hinges 9055. For example, the display unit 9001 can be bent with a radius of curvature of 0.1 mm or more and 150 mm or less.

This embodiment can be combined with other embodiments as appropriate.

ANO: wiring, C11: capacitive element, C12: capacitive element, GL: wiring, M11: transistor, M12: transistor, M13: transistor, M14: transistor, M15: transistor, M16: transistor, SL: wiring, VCOM: wiring, 10: semiconductor device, 10A: semiconductor device, 10B: semiconductor device, 10C: semiconductor device, 10D: semiconductor device, 10E: semiconductor device, 10F: semiconductor device, 10G: semiconductor device, 20: semiconductor device, 20A: semiconductor device, 20B: semiconductor device, 20C: semiconductor device, 20D: semiconductor device, 50A: display device, 50B: display device, 50C: display device, 50D: display device, 50E: display device, 50F: display device, 50G: display device, 50H: display device, 50I: display device, 51: pixel circuit, 51A: pixel circuit, 51B: pixel circuit, 51C: pixel circuit, 51D: pixel circuit , 51E: pixel circuit, 51F: pixel circuit, 52A: transistor, 52B: transistor, 52C: transistor, 53: capacitance element, 60: liquid crystal element, 61: light emitting device, 62: liquid crystal device, 100: transistor, 100A: transistor, 100B: transistor, 100C: transistor, 100D: transistor, 100E: transistor, 100F: transistor, 100G: transistor , 100H: transistor, 100s: transistor, 102: substrate, 103: conductive layer, 104: conductive layer, 104A: conductive layer, 105: layer, 106: insulating layer, 106a: insulating layer, 106b: insulating layer, 108: layer, 108a: layer, 108b: layer, 108c: layer, 108Da: region, 108Db: region, 108Dc: region, 108f: film, 108M: region, 109: insulating layer, 110: insulating layer, 110a: insulating layer , 110af: insulating film, 110b: insulating layer, 110b_1: insulating layer, 110b_2: insulating layer, 110b_3: insulating layer, 110bf: insulating film, 110c: insulating layer, 110cf: insulating film, 110d: insulating layer, 110e: insulating layer, 110ef: insulating film, 111: pixel electrode, 111B: pixel electrode, 111G: pixel electrode, 111R: pixel electrode, 111S: pixel electrode, 112: conductive layer, 112_1: conductive layer, 112_2 : conductive layer, 112_3: conductive layer, 112A: conductive layer, 113: EL layer, 113B: EL layer, 113G: EL layer, 113R: EL layer, 113S: functional layer, 114: common layer, 115: common electrode, 116: insulating layer, 117: light shielding layer, 118B: sacrificial layer, 118G: sacrificial layer, 118R: sacrificial layer, 119B: sacrificial layer, 119G: sacrificial layer, 123: conductive layer, 124B: conductive layer, 124G: conductive layer, 124R: conductive layer, 1 25: insulating layer, 125f: insulating film, 126B: conductive layer, 126G: conductive layer, 126R: conductive layer, 127: insulating layer, 128: layer, 130B: light-emitting element, 130G: light-emitting element, 130R: light-emitting element, 130S: light-receiving element, 131: protective layer, 132B: colored layer, 132G: colored layer, 132R: colored layer, 133: layer, 133B: layer, 133Bf: film, 133G: layer, 133R: layer, 137: film, 139: film, 140 : Connection portion, 141: Opening, 141A: Opening, 142: Adhesive layer, 144: Adhesive layer, 145: Opening, 145A: Opening, 145B: Opening, 151: Substrate, 152: Substrate, 153: Insulating layer, 162: Display portion, 164: Circuit portion, 165: Conductive layer, 165a: Conductive layer, 165b: Conductive layer, 166: Conductive layer, 166a: Conductive layer, 166b: Conductive layer, 172: FPC, 173: IC, 181: Opening, 183: Opening opening, 185: resist mask, 187: impurity element, 193: conductive layer, 195: insulating layer, 197: connection portion, 200: transistor, 200A: transistor, 200B: transistor, 200C: transistor, 200D: transistor, 200E: transistor, 200F: transistor, 200G: transistor, 200H: transistor, 200s: transistor, 203: conductive layer, 204: conductive layer, 204A: conductive layer, 205: layer, 205B: transistor, 205G: transistor, 205R: transistor, 205S: transistor, 207B: transistor, 207D: transistor, 207G: transistor, 208: layer, 208A: layer, 208a: layer, 208b: layer, 208c: layer, 208Da: region, 208Db: region, 208Dc: region, 208Dd: region, 208M: region, 210 : pixel, 212a: conductive layer, 212a_1: conductive layer, 212a_2: conductive layer, 212a_3: conductive layer, 212aA: conductive layer, 212B: conductive layer, 212b: conductive layer, 212f: conductive film, 216: insulating layer, 223: connector, 224: spacer, 225: insulating layer, 230[1,1]: pixel, 230[m,n]: pixel, 230: pixel, 230B: pixel, 230G: pixel, 230R: pixel, 231: first drive circuit unit , 232: second driving circuit section, 235: insulating layer, 236: wiring, 237: insulating layer, 238: wiring, 241: opening, 241A: opening, 242: connection layer, 243: opening, 243A: opening, 260a: polarizing plate, 260b: polarizing plate, 261: insulating layer, 262: liquid crystal, 263: conductive layer, 264: conductive layer, 265: alignment film, 352: finger, 353: layer, 355: circuit layer, 357: layer, 700A: electronic device, 700B : Electronic device, 721: Housing, 723: Mounting section, 727: Earphone section, 750: Earphone, 751: Display panel, 753: Optical member, 756: Display area, 757: Frame, 758: Nose pad, 800A: Electronic device, 800B: Electronic device, 820: Display section, 821: Housing, 822: Communication section, 823: Mounting section, 824: Control section, 825: Imaging section, 827: Earphone section, 832: Lens, 6500: Electronic device device, 6501: housing, 6502: display unit, 6503: power button, 6504: button, 6505: speaker, 6506: microphone, 6507: camera, 6508: light source, 6510: protective member, 6511: display panel, 6512: optical member, 6513: touch sensor panel, 6515: FPC, 6516: IC, 6517: printed circuit board, 6518: battery, 7000: display unit, 7100: television device , 7101: housing, 7103: stand, 7111: remote control device, 7200: notebook computer, 7211: housing, 7212: keyboard, 7213: pointing device, 7214: external connection port, 7300: digital signage, 7301: housing, 7303: speaker, 7311: information terminal device, 7400: digital signage, 7401: pillar, 7411: information terminal device, 9000: housing, 9001: Display unit, 9002: Camera, 9003: Speaker, 9005: Operation keys, 9006: Connection terminal, 9007: Sensor, 9008: Microphone, 9050: Icon, 9051: Information, 9052: Information, 9053: Information, 9054: Information, 9055: Hinge, 9101: Portable information terminal, 9102: Portable information terminal, 9103: Tablet terminal, 9200: Portable information terminal, 9201: Portable information terminal

Claims (7)

a first transistor, a second transistor, and a first insulating layer;
the first transistor has a first conductive layer, a first metal oxide layer, a gate insulating layer, and a first gate electrode;
the second transistor includes a second conductive layer, a third conductive layer, a second metal oxide layer, the gate insulating layer, and a second gate electrode;
the first insulating layer overlies the first conductive layer and the second conductive layer;
the third conductive layer has a region overlapping with the second conductive layer via the first insulating layer;
the first insulating layer has a first opening reaching the first conductive layer;
the first insulating layer and the third conductive layer have a second opening reaching the second conductive layer;
the first metal oxide layer has a first region in contact with an upper surface of the first conductive layer at the first opening, a second region in contact with a side surface of the first insulating layer at the first opening, and a third region in contact with an upper surface of the first insulating layer;
the third region is in contact with the second region,
the second metal oxide layer has a fourth region in contact with an upper surface of the second conductive layer in the second opening, a fifth region in contact with a side surface of the first insulating layer in the second opening, and a sixth region in contact with a side surface of the third conductive layer in the second opening;
the first region, the third region, and the fourth region each have a first element;
the first element is boron or phosphorus;
the gate insulating layer is located on the first metal oxide layer and the second metal oxide layer and is in contact with the first metal oxide layer and the second metal oxide layer;
the first gate electrode has a region overlapping the first metal oxide layer through the gate insulating layer in the first opening,
the second gate electrode has a region overlapping with the second metal oxide layer through the gate insulating layer in the second opening. In claim 1,
the first region has a portion having a higher concentration of the first element than the second region;
the third region has a portion having a higher concentration of the first element than the second region,
The fourth region has a portion having a higher concentration of the first element than the fifth region. In claim 1,
the second metal oxide layer has a seventh region in contact with a top surface of the third conductive layer;
the seventh region has the first element;
The seventh region has a portion having a higher concentration of the first element than the fifth region. In claim 1,
The gate insulating layer comprises the first element. In claim 1,
a side surface of the first insulating layer in the first opening and a top surface of the first conductive layer form an angle of 65 degrees or more and 90 degrees or less. In any one of claims 1 to 5,
the first insulating layer includes a second insulating layer and a third insulating layer on the second insulating layer;
the second insulating layer comprises silicon and oxygen;
The third insulating layer comprises silicon and nitrogen. In any one of claims 1 to 5,
the first insulating layer includes a second insulating layer and a third insulating layer on the second insulating layer;
the second insulating layer comprises silicon and oxygen;
The third insulating layer comprises one or both of aluminum and hafnium, and oxygen.

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