WO2025079193A1 - Semiconductor light receiving element, optical line terminating device, multi-value intensity modulation transmitting/receiving device, digital coherent receiving device, radio-over-fiber system, spad sensor system, and lidar device - Google Patents

Abstract

A semiconductor light receiving element (100) according to the present disclosure comprises: an n-type InP substrate (1); an n-type semiconductor layer (2) formed on the n-type InP substrate (1); a multiplication layer (3) formed on the n-type semiconductor layer (2) and having an InAlAs digital alloy structure in which InAs layers having a layer thickness of 40-170 nm and AlAs layers are alternately laminated; a p-type field relaxation layer (4) formed on the multiplication layer (3) and composed of InP or InAlAs; and an InGaAs light absorption layer (5) formed on the p-type field relaxation layer (4).

Description

Semiconductor photodetector, optical line terminal, multilevel intensity modulation transmitter/receiver, digital coherent receiver, optical fiber radio system, SPAD sensor system, and lidar device

This disclosure relates to semiconductor photodetectors, optical line termination devices, multilevel intensity modulation transceivers, digital coherent receivers, radio-over-fiber systems, SPAD sensor systems, and lidar devices.

Along with the progress of digital transformation that utilizes digital information, there has been remarkable development of communication networks that communicate digital information with each other and data centers that store and process data. Optical communication is used for communication networks and communication within data centers. In recent years, optical communication has made remarkable progress in increasing speed and capacity. As optical communication advances, avalanche photodiodes (APDs), which provide high receiving sensitivity, are used as optical communication receivers.

In the access network that connects optical communication subscribers, the Passive Optical Network (PON) is the main system used. PON systems started with the G(E)-PON system that transmits signals of 1 to 2 Gbps, and in the future, 10G-EPON systems and XG-PON systems that transmit signals of 10 Gbps are expected to increase. Furthermore, the International Telecommunication Union Telecommunication Standardization Sector (ITU-T) is considering the 50G-PON system, a next-generation high-speed PON system, and it is expected that 50 Gbps-class transmission will also be put into practical use in access networks in the future.

APDs, which are semiconductor light receiving elements used in PON systems, have an element structure consisting of a light absorption layer (InGaAs), an electric field relaxation layer (InP or InAlAs), and a multiplication layer (InP or InAlAs). A high electric field of about 800 kV/cm is applied to the multiplication layer to multiply, or ionize, the electrons and holes generated in the light absorption layer. The electric field relaxation layer functions to weaken the electric field so that the high electric field of the multiplication layer is not applied to the light absorption layer. Incidentally, the ionization rate of electrons is expressed as α, and the ionization rate of holes as β.

In an APD, the greater the ratio of the ionization rates of electrons and holes, the smaller the excess noise generated during multiplication and the higher the receiving sensitivity. Furthermore, the greater the ratio of the ionization rates of electrons and holes, the shorter the multiplication time in the multiplication layer, resulting in a wider bandwidth.

The ionization rate ratio k of electrons and holes is defined as k = β/α. When electrons are injected into the multiplication layer, the smaller the ionization rate ratio k, the better the performance of the APD. Compound semiconductor materials such as InAlAs or InP are used for the multiplication layer of APDs for optical communications.

If InAlAs is selected as the material for the multiplication layer, the difference in the ionization rates of electrons and holes will be greater than in InP. Note that in InP, the ionization rate of holes is greater than that of electrons, and the ionization rate of holes is approximately twice that of electrons. On the other hand, if InAlAs is selected as the material for the multiplication layer, the ionization rate of electrons is greater than that of holes, and the ionization rate of electrons is approximately five times that of holes. Therefore, since the reception sensitivity is higher when InAlAs is used as the multiplication layer, InAlAs is more suitable than InP as the material for the multiplication layer of an APD.

As mentioned above, in a PON system, APDs, which are semiconductor light receiving elements, are required to have a wide response bandwidth and high receiving sensitivity. However, unlike PDs, APDs have a problem in that the time required for multiplication, that is, the multiplication time, becomes longer as the multiplication factor increases, resulting in a decrease in bandwidth at high multiplication factors. APDs with a multiplication layer made of InAlAs, which is used in optical communications, have a wider bandwidth than APDs made of other semiconductor materials, but when the multiplication factor is 6 or more, the bandwidth remains at around 20 GHz. In other words, there is a problem in that the bandwidth of around 37.5 GHz or more required for 50G-PON systems is difficult to achieve when conventional APDs are used.

US Patent Application Publication No. 2022/0099813

Jiyuan Zheng et. al, “Digital Alloy InAlAs Avalanche Photodiodes”, JOURNAL OF LIGHTWAVE TECHNOLOGY, VOL. 36, NO. 17, SEPTEMBER 1, pp. 3580-3585, 2018

In 50G-PON systems, the response bands of the semiconductor light-emitting elements and semiconductor light-receiving elements, the optical output of the semiconductor light-emitting elements, and the receiving sensitivity of the semiconductor light-receiving elements are insufficient. For this reason, it is being considered to provide a digital bandwidth compensation circuit using a digital signal processor (DSP) after the APD in the optical network unit (ONU), i.e., the receiving device on the subscriber's side.

In addition, the Optical Line Terminal (OLT), i.e. the receiving device on the central office side, requires a Semiconductor Optical Amplifier (SOA) to compensate for the lack of receiving sensitivity of the semiconductor light receiving element, and it is necessary to integrate an SOA into the electro-absorption modulated laser diode (EML) on the transmitting side of the ONU to increase the optical output. However, DSPs and SOAs consume very large amounts of power, which is a factor in increasing costs, and it is feared that the replacement of existing PON systems with 50G-PON systems will not progress.

Also, in existing PON systems other than the next-generation high-speed PON system, it is being considered to increase the number of branches of the optical signal output from the OLT in order to reduce costs. However, even in this case, it is necessary to integrate an SOA in the EML on the transmitting side of the OLT or ONU to increase the optical output, which causes problems such as increased power consumption of the transmitter and increased costs.

As described above, to compensate for the limitations of the receiving sensitivity and response bandwidth of semiconductor light receiving elements, transceivers are designed that incorporate expensive and power-hungry DSPs and SOAs into the ONU or OLT, but this creates problems such as increased power consumption and costs.

This disclosure has been made to resolve the above-mentioned problems, and aims to provide a semiconductor light-receiving element that has high reception sensitivity, a wide response band, and operates with low power consumption.

The semiconductor light receiving element according to the present disclosure comprises:
An InP substrate;
an n-type semiconductor layer formed on the InP substrate;
a multiplication layer formed on the n-type semiconductor layer and having a digital alloy structure with a layer thickness of 40 nm or more and 170 nm or less;
a p-type electric field buffer layer formed on the multiplication layer;
an InGaAs light absorption layer formed on the p-type electric field buffer layer;
Equipped with.

The optical line terminal according to the present disclosure comprises:
The semiconductor light receiving element described above,
an optical multiplexer/demultiplexer that inputs an optical signal to the semiconductor light receiving element;
an amplifier circuit for amplifying an electrical signal output from the semiconductor light receiving element;
a clock data recovery circuit connected to the amplifier circuit and configured to recover clock data from the amplified electrical signal;
a forward error correction circuit connected to the clock data recovery circuit for correcting an error in the clock data;
Equipped with.

A multi-level intensity modulation transmitting/receiving device according to the present disclosure comprises:
The semiconductor light receiving element described above for receiving an optical signal intensity-modulated into multiple values;
an amplifier circuit for amplifying an electrical signal output from the semiconductor light receiving element;
an analog/digital conversion circuit connected to the amplifier circuit and converting the amplified electrical signal into a digital signal;
a digital signal processing circuit connected to the analog/digital conversion circuit and processing the digital signal;
Equipped with.

The radio-over-fiber system according to the present disclosure comprises:
a light source that emits an analog modulated optical signal;
The semiconductor light receiving element described above for receiving the analog-modulated optical signal;
a transmission path for transmitting the analog electrical signal output from the semiconductor light receiving element to an antenna;
an antenna connected to the transmission line and configured to radiate the analog electrical signal as a radio wave signal;
Equipped with.

A digital coherent receiving device according to the present disclosure includes:
The semiconductor light receiving element described above,
a polarization splitter that splits the polarization of the intensity- and phase-modulated polarization multiplexed optical signal;
a 90-degree hybrid that splits and combines the optical signals output from the polarization splitter;
a digital signal processing circuit connected to the 90-degree hybrid device and processing a digital signal;
Equipped with.

The SPAD sensor system according to the present disclosure comprises:
A SPAD sensor constituted by the semiconductor light receiving element described above;
a quenching circuit for repeatedly applying a voltage equal to or greater than a breakdown voltage and a voltage equal to or less than the breakdown voltage to the SPAD sensor;
an optoelectronic measurement circuit for measuring an electrical signal output from the SPAD sensor;
Equipped with.

The LIDAR device according to the present disclosure comprises:
A light source that emits light in a pulsed manner;
the semiconductor light receiving element described above for receiving light emitted from the light source and reflected by an object;
an amplifier circuit for amplifying an electrical signal output from the semiconductor light receiving element;
a distance measuring circuit for calculating a distance based on the electrical signal amplified by the amplifier circuit;
Equipped with.

In the semiconductor light receiving element according to the present disclosure, the multiplication layer is configured with a digital alloy structure, and the thickness of the multiplication layer is set to be within a predetermined range, which has the effect of providing a semiconductor light receiving element with high reception sensitivity and a wide response band.

The optical line termination device, multilevel intensity modulation transceiver device, digital coherent receiver device, optical fiber radio system, SPAD sensor system, and LIDAR device disclosed herein use the semiconductor light receiving element disclosed herein as the semiconductor light receiving element, and therefore have the effect of providing devices and systems with excellent performance.

1 is a cross-sectional view showing an element structure of a front-illuminated APD, which is an example of a semiconductor light-receiving element according to a first embodiment. 1 is a cross-sectional view showing an element structure of an edge-illuminated APD, which is an example of a semiconductor light-receiving element according to a first embodiment. FIG. 13 is a diagram showing the electric field dependence of the electron dead space in an InAlAs multiplication layer. 4A to 4C are diagrams showing the ionization rates of electrons and holes. FIG. 13 is a graph showing the dependence of the ionization rate ratio and the tunnel current on the thickness of the multiplication layer. 6A to 6D are diagrams showing the ionization rates in the multiplication layer and the electric field relaxation layer, with FIG. 6A showing the ionization rate in the case of a random alloy structure multiplication layer, FIG. 6B showing the ionization rate in the case of a digital alloy structure multiplication layer, FIG. 6C showing the ionization rate in the case of a partially disordered digital alloy structure multiplication layer, and FIG. 6D showing the ionization rate in the case of a combination of a thick electric field relaxation layer and a digital alloy structure multiplication layer. FIG. 1 is a diagram illustrating the configuration of a comparative example of an optical line terminal (ONU and OLT) of a 50G-PON system. A diagram showing the configuration of an ONU in a 50G-PON system using a semiconductor photodetector according to the first embodiment. 1 is a diagram showing the configuration of an OLT in a 50G-PON system using a semiconductor photodetector according to a first embodiment. FIG. 1 is a diagram showing the configuration of a 50G-PON system and an OLT/ONU as a comparative example. A diagram showing the configuration of a multi-branch 50G-PON system and an OLT/ONU according to a first embodiment. A diagram showing the configuration of a 50G-PON system and an OLT/ONU relating to embodiment 1. 11 is a cross-sectional view showing the element structure of a front-illuminated APD, which is an example of a semiconductor light-receiving element according to a second embodiment. FIG. 11 is a cross-sectional view showing the element structure of a front-illuminated APD, which is an example of a semiconductor light-receiving element according to a second embodiment. FIG. 11 is a cross-sectional view showing the element structure of a front-illuminated APD, which is an example of a semiconductor light-receiving element according to a third embodiment. FIG. 11 is a cross-sectional view showing the element structure of a back-illuminated APD, which is an example of a semiconductor light-receiving element according to a fourth embodiment. 13 is a cross-sectional view showing the element structure of a front-illuminated APD, which is an example of a semiconductor light-receiving element according to a fifth embodiment. FIG. 13 is a cross-sectional view showing another element structure of a front-illuminated APD which is an example of a semiconductor light receiving element according to the fifth embodiment. FIG. 13 is a cross-sectional view showing the element structure of a front-illuminated APD, which is an example of a semiconductor light-receiving element according to a sixth embodiment. FIG. 13 is a cross-sectional view showing the element structure of a back-illuminated APD, which is an example of a semiconductor light-receiving element according to a seventh embodiment. FIG. 13 is a cross-sectional view showing the element structure of a back-illuminated APD, which is an example of a semiconductor light-receiving element according to an eighth embodiment. FIG. FIG. 13 is a diagram illustrating a configuration of a multilevel intensity modulation transmitting/receiving device according to a ninth embodiment. 23A and 23B are diagrams illustrating received waveforms of a multilevel intensity modulation transmitting/receiving device according to embodiment 9. FIG. 24A and 24B are diagrams for explaining the operation of a PD when a high optical input is applied. FIG. 1 is a diagram illustrating the operation of an APD when a high optical input is applied. FIG. 2 is a diagram showing the residence times of electrons and holes for each material constituting the multiplication layer. FIG. 13 is a diagram illustrating a configuration of a radio-on-fiber system according to a tenth embodiment. FIG. 1 illustrates a configuration of a radio-on-fiber system as a comparative example. A diagram showing the configuration of a digital coherent receiving device related to embodiment 11. FIG. 30A is a diagram illustrating waveforms of a digital coherent receiving device that is a comparative example, and FIG. 30B is a diagram illustrating waveforms of a digital coherent receiving device according to embodiment 11. FIG. 23 is a diagram showing the configuration of a SAPD sensor system according to a twelfth embodiment. FIG. 32A is a diagram showing waveforms of a SAPD sensor system which is a comparative example, and FIG. 32B is a diagram showing waveforms of a SAPD sensor system according to embodiment 12. FIG. 13 is a diagram showing the calculated difference between the quenching electric field and the Geiger mode electric field for each multiplication layer configuration. A diagram showing the configuration of a LIDAR device related to embodiment 13. FIG. 35A is a diagram showing a received waveform of an APD of a LIDAR device which is a comparative example, and FIG. 35B is a diagram showing a received waveform of an APD of a LIDAR device according to embodiment 13.

Embodiment 1.
<Element structure of semiconductor light receiving element according to the first embodiment>
Fig. 1 is a cross-sectional view showing the element structure of a front-illuminated APD, which is an example of a semiconductor light-receiving element 100 according to the first embodiment. Fig. 2 is a cross-sectional view showing the element structure of an edge-illuminated APD, which is an example of a semiconductor light-receiving element 110 according to the first embodiment.

<Element structure of semiconductor light receiving element according to the first embodiment>
The semiconductor light receiving element 100 according to the first embodiment comprises an n-type InP substrate 1, an n-type InAlAs buffer layer ² having a carrier concentration of 1 to 5× ¹⁰ cm and a layer thickness of 0.1 to 1.0 μm, which are successively formed on the n-type InP substrate 1, an InAlAs multiplication layer 3 (hereinafter referred to as an InAlAs digital alloy structure multiplication layer 3, and may also be abbreviated as a DA multiplication layer) having a digital alloy structure in which an i-type AlAs layer (for example, a layer thickness of two atomic layers, about 0.6 nm) and an i-type InAs layer (for example, a layer thickness of two atomic layers, about ^0.6 nm) are alternately laminated a plurality of times, and The n-type InP substrate ¹ is made up of a p-type InP electric field relaxation layer 4 having a thickness of 10 to 70 nm and a thickness of 300 nm, an i-type InGaAs light absorption layer 5 having a thickness of 0.1 to 2.0 μm, an i-type InAlGaAs/InAlAs graded layer 6, a p-type InP window layer 7 having a thickness of 0.1 to 3.0 μm, a p-type InGaAs contact layer 8, an n-type electrode 31 formed on the back surface side of the n-type InP substrate 1, and a p-type electrode 32 formed on the p-type InGaAs contact layer 8. The n-type InAlAs buffer layer 2 is also called an n-type semiconductor layer.

The semiconductor light receiving element 110 according to the first embodiment has a layer structure similar to that of the semiconductor light receiving element 100, but further includes an Fe-doped semi-insulating InP buried layer 20 formed at least on the end surface on which the incident light 90 is incident.

The n-type InAlAs buffer layer 2 may have either a random alloy structure or a digital alloy structure. Silicon (Si) is optimal as the n-type dopant for the n-type InAlAs buffer layer 2. This is to prevent n-type impurities from diffusing from the n-type InAlAs buffer layer 2 to the i-type InAlAs digital alloy structure multiplication layer 3, causing the digital alloy structure to become disordered. Here, disordering refers to the phenomenon in which the compositions of the layers of the digital alloy structure mix together, resulting in a random alloy structure with an average composition.

As described above, the InAlAs digital alloy structure multiplication layer 3 is composed of semiconductor layers in which AlAs layers (layer thickness: 2 atomic layers, approximately 0.6 nm) and InAs layers (layer thickness: 2 atomic layers, approximately 0.6 nm) are alternately stacked in this order. However, it is sufficient that the layer thicknesses of the AlAs layers and InAs layers are each in the range of 2 atomic layers to 6 atomic layers. The reason for using 6 atomic layers or less is that it is desirable for the stacked structure of the AlAs layers and InAs layers not to function as a quantum well structure.

Furthermore, the number of atomic layers in each layer of the InAlAs digital alloy structure multiplication layer 3 is preferably 2 to 4 atomic layers, with 2 atomic layers being optimal. The reason for this is that the thinner the atomic layer thickness of each layer is, the greater the effect of reducing the ionization rate ratio k due to the digital alloy structure.

In consideration of the affinity with InAlAs constituting the n-type InAlAs buffer layer 2, it is preferable to make only the first AlAs layer of the InAlAs digital alloy structure multiplication layer 3 thicker than three atomic layers. Alternatively, the InAlAs digital alloy structure multiplication layer 3 may be stacked by alternately forming InAs layers and AlAs layers in that order.

The InAlAs digital alloy structure multiplication layer 3 has an i-type conductivity and an example of a carrier concentration of 1×10 ¹⁷ cm ⁻³ or less. However, the InAlAs digital alloy structure multiplication layer 3 may have a p-type or n-type conductivity with a carrier concentration of 5×10 ¹⁸ cm ⁻³ or less.

In order to increase the dead space effect in the InAlAs digital alloy structure multiplication layer 3, the thickness of the InAlAs digital alloy structure multiplication layer 3 is preferably in the range of 40 nm to 170 nm. However, considering the typical degree of variation in layer thickness during the manufacture of the semiconductor light receiving element 100 of 20%, the thickness of the InAlAs digital alloy structure multiplication layer 3 is preferably in the range of 50 nm to 140 nm.

In addition to the multiplication layer composed of an InAlAs digital alloy structure, an InAlGaAs digital alloy structure in which InAlyGa(1-y)As (layer thickness of 2 to 6 atomic layers, Al composition ratio Y) and InAlzGa(1-z)As (layer thickness of 2 to 6 atomic layers, Al composition ratio Z) are alternately stacked can also be applied as the multiplication layer of this disclosure. Furthermore, a digital alloy structure made of InAlAsSb, a material system containing antimony (Sb), can also be applied as the multiplication layer of this disclosure.

As described above, the p-type InP electric field buffer layer 4 ^preferably has a carrier concentration of 0.1 to 50× ¹⁰ cm and a layer thickness in the range of 10 nm to 70 nm. Examples of p-type dopants for the p-type InP electric field buffer layer 4 include beryllium (Be), zinc (Zn), and carbon (C).

The electric field relaxation layer does not necessarily have to be made of p-type InP. In other words, the electric field relaxation layer may be a p-type InAlAs digital alloy structure or a p-type InAlAs random alloy structure. However, if the dopant contained in the p-type InP electric field relaxation layer 4 diffuses into the adjacent InAlAs digital alloy structure multiplication layer 3, the digital alloy structure may become disordered and may change to a random alloy structure of InAlAs. As described above, since the InAlAs digital alloy structure multiplication layer 3 has a thin layer thickness of about 100 nm, it may be significantly affected by disorder caused by dopant diffusion. Therefore, in the case of the p-type InP electric field relaxation layer 4, it is optimal to use Be as the p-type dopant, which is unlikely to diffuse. On the other hand, when p-type InAlAs is used as the constituent material of the electric field relaxation layer, Zn is optimal as the p-type dopant.

By providing a layer with a thickness of 0.1 μm or less between the p-type InP electric field relaxation layer 4 and the i-type InGaAs light absorption layer 5, which is made of InAlGaAs or InGaAsP, etc., and has an intermediate band gap value between the two, it is possible to prevent the accumulation of electrons and holes at the heterojunction interface. The conductivity type of the InGaAs light absorption layer may be n-type or p-type.

For the same purpose, a layer made of InAlGaAs or InGaAsP having an intermediate band gap between the i-type InGaAs light absorption layer 5 and the p-type InAlAs layer and having a thickness of 0.1 μm or less may be provided. The p-type InGaAs contact layer 8 has an outer periphery that is smaller in area than the multiplication layer.

In one example of the device structure of the semiconductor photodetector 100 shown in FIG. 1, two types of i-type InAlGaAs layers with different compositions are alternately stacked multiple times on an i-type InGaAs light absorption layer 5 to form an InAlGaAs/InAlAs graded layer 6. The conductivity type of the InAlGaAs/InAlAs graded layer 6 may be p-type or n-type. Also, instead of the p-type InP window layer 7, a p-type InAlAs window layer may be used.

<Operation Principle of Semiconductor Light-Receiving Element According to First Embodiment>
The operating principle of the semiconductor light receiving element 100 according to the first embodiment will be described below.
If a wideband APD of about 37.5 GHz or more can be realized, a next-generation high-speed PON system can be realized without using a DSP or an SOA. In the case of a PD, which is relatively easy to make into a wideband APD, the response bandwidth is as follows:
(1) RC time constant (R is the element resistance, C is the element capacitance)
(2) Carrier transit time (the time it takes for an electron or hole to travel through the depletion layer)
In APD, the
(3) It is also limited by the multiplication time (the time it takes for electrons and holes to multiply in a chain reaction in the multiplication layer, which increases in proportion to the multiplication factor).

Although a PD can realize the above-mentioned 37.5 GHz band, an APD requires a multiplication time, so if the multiplication factor is increased, it becomes difficult to realize the desired band. The multiplication time TM is expressed by the following equations (1) to (3).
Multiplication time TM = Multiplication rate M/GB product (1)
GB product = 1/(2πNkτav) (2)
In other words,
Multiplication time TM = 2πNkMτav (3)
It becomes.

Here, GB product is the product of the multiplication factor and the bandwidth, k is the ionization rate ratio, N is a coefficient that is loosely dependent on the ionization rate ratio k, and τav is the average time it takes for electrons and holes to travel through the multiplication layer. Therefore, by reducing the ionization rate ratio k, it is possible to shorten the multiplication time TM. In particular, to realize a high-speed PON system, it is necessary to make the multiplication time TM approach zero, in other words, to make the ionization rate ratio k approach zero.

In order to make the ionization rate ratio k zero, various compound semiconductors have been proposed as materials for the multiplication layer. In addition, in order to reduce the ionization rate ratio k, a digital alloy structure (also called ALSL: Atomic Layer Super Lattice) has been proposed in which semiconductor layers of different compositions are alternately stacked at a period of about 1 to 6 atomic layers. However, even with the digital alloy structure, it is difficult to make the ionization rate ratio k zero unless the structure is optimized. The digital alloy structure is described in Non-Patent Document 1.

The inventors therefore fabricated an APD with a digital alloy structure multiplication layer using a multiplication layer in which two-atom InAs layers and two-atom AlAs layers are alternately stacked in order to reduce the ionization rate ratio k of the digital alloy structure. As a result of analyzing the multiplication characteristics, they discovered that the distance that carriers travel in the multiplication layer until they are ionized is longer than that of an APD with a multiplication layer made of normal InAlAs made of bulk crystal, that is, an InAlAs random alloy structure multiplication layer. The distance that carriers travel in the multiplication layer until they are ionized is called the dead space.

The length of the dead space (hereinafter referred to as the dead space length) is longer for holes than for electrons, so in the case of an InAlAs random alloy structure made of a normal bulk crystal, if the thickness of the multiplication layer is thinned to about tens of nm, the ionization rate ratio k decreases because the holes cannot be ionized. However, when the thickness of the multiplication layer is thinned to about tens of nm, a new problem occurs in that leakage currents such as tunnel currents increase because a higher electric field must be applied to the multiplication layer to obtain the desired multiplication factor. In other words, an increase in the tunnel current increases the noise generated by the APD. On the other hand, the inventors' analysis discovered that the ionization rate ratio k = 0 in a digital alloy structure, even with a multiplication layer with a thickness of 100 nm or more, because the dead space is unusually large in the digital alloy structure compared to the random alloy structure.

In other words, the inventors have found for the first time that by constructing the multiplication layer of an APD with a digital alloy structure, it is possible to achieve an ionization rate ratio k = 0 while suppressing the tunnel current. Specifically, they have found that in a multiplication layer made of the digital alloy structure of the present disclosure, the ionization rate ratio k drops sharply at a layer thickness of 170 nm or less, and that the dead space effect improves dramatically when the multiplication layer has a layer thickness in the range of 60 to 130 nm. In other words, the inventors have demonstrated that the ionization rate ratio k = 0, which was impossible to achieve with a multiplication layer made of a random alloy structure or a multiplication layer made of a thick digital alloy structure, can be achieved by applying the multiplication layer made of the digital alloy structure of the present disclosure. At present, no research institute has reported that thinning the multiplication layer of an APD with a digital alloy structure has a greater effect of reducing the ionization rate ratio k than thinning the multiplication layer of an APD made of conventional materials.

<Method of Manufacturing Semiconductor Light-Receiving Element According to First Embodiment>
A front-illuminated APD, which is an example of the semiconductor light-receiving element 100 according to the first embodiment, can be realized by using metal organic vapor phase epitaxy (MOVPE) or molecular beam epitaxy (MBE) on an n-type InP substrate 1. A method for manufacturing the semiconductor light-receiving element 100 according to the first embodiment will be described below.

An n-type InAlAs buffer layer 2 having a thickness of 0.1 to 1 μm and a carrier concentration of 1 to 5×10 ¹⁸ cm ⁻³ is crystal-grown on an n-type InP substrate 1 by MOVPE or MBE.

The InAlAs digital alloy structure multiplication layer 3 is grown by crystal growth on the n-type InAlAs buffer layer 2. In other words, the InAlAs digital alloy structure multiplication layer 3 is formed by alternately growing crystals of an AlAs layer (layer thickness: 2 atomic layers, approximately 0.6 nm) and an InAs layer (layer thickness: 2 atomic layers, approximately 0.6 nm) from the n-type InAlAs buffer layer 2.

On the InAlAs digital alloy structure multiplication layer 3, a p-type InP field relaxation layer 4 having a thickness of 10 nm to 70 nm and a carrier concentration of 0.1 to 50×10 ¹⁷ cm ⁻³ is crystal-grown.

On the p-type InP electric field relaxation layer 4, an i-type InGaAs light absorption layer 5 having a thickness of 0.1 μm or more and 2 μm or less, an i-type InAlGaAs/InAlAs graded layer 6, a p-type InP window layer 7 having a thickness of 0.1 μm or more and 3 μm or less, and a p-type InGaAs contact layer 8 are successively crystal-grown. Note that the InAlGaAs/InAlAs graded layer may be n-type or p-type. Also, a p-type InAlAs window layer may be used instead of the p-type InP window layer 7.

After the crystal growth is completed, a p-type electrode 32 is formed on the surface of the p-type InGaAs contact layer 8, and an n-type electrode 31 is formed on the back surface of the n-type InP substrate 1.

In the case of the surface-illuminated APD shown in Figure 1, incident light 90 is incident perpendicularly to the i-type InGaAs light absorption layer 5. The diameter of the light receiving part of the APD is circular, or the size of the long side of the light receiving part of the APD is rectangular, is within the range of 5 μm to 1 mm. The incident surface of the APD is coated with an anti-reflective coating (not shown).

In the case of the edge-illuminated APD shown in FIG. 2, incident light 90 is incident from a direction parallel to the i-type InGaAs light absorption layer 5. From the viewpoint of reliability, the edge portion is covered with an insulating film, an organic film, or a semiconductor layer. In the edge-illuminated APD shown in FIG. 2, an Fe-doped semi-insulating InP buried layer 20 is formed on the edge. The layer thickness of the Fe-doped semi-insulating InP buried layer 20 is in the range of 100 nm to 5 μm in the incident direction.

In the APD according to the first embodiment, Ti and Au are used as the electrode materials for the p-type electrode 32. In the APD according to the first embodiment, the amount of electric field relaxation is adjusted so that tunnel breakdown does not occur at a voltage lower than avalanche breakdown. In the APD according to the first embodiment, the operating voltage is 15V to 90V, and the electric field in the multiplication layer during APD operation is 500kV/cm to 900kV/cm. In the APD according to the first embodiment, the electric field of the i-type InGaAs light absorption layer 5 is set to 300kV/cm or less. In the APD according to the first embodiment, the multiplication factor is used within the range of 3 to 30, but is 100 or more when operating in Geiger mode.

<Function of the semiconductor light receiving element according to the first embodiment>
The operation of the APD according to the first embodiment shown in Figures 1 and 2 will be described below. The inventors have found that the use of a digital alloy structure multiplication layer as in the APD according to the first embodiment enhances the dead space effect, that is, the effect of reducing the ionization rate ratio k. Figure 3 is a diagram showing the electric field dependence of the electron dead space in an InAlAs multiplication layer. As a result of analyzing the electron multiplication characteristics in a digital alloy structure multiplication layer, the inventors have clarified that, as shown in the graph of Figure 3, the InAlAs digital alloy structure multiplication layer of the present disclosure has a longer dead space than the conventional InAlAs random alloy structure multiplication layer.

Figures 4A to 4C show the ionization rates of electrons and holes, respectively, with Figure 4A showing the case of electron ionization, Figure 4B showing the case of hole ionization, and Figure 4C showing the ionization rate when the multiplication layer is thinned. In a conventional InAlAs random alloy structure multiplication layer, as shown in the graph in Figure 3, the dead space length is about 45 nm, so the thickness of the multiplication layer needs to be thinned to about 1.5 times the dead space (about 70 nm). However, thinning the multiplication layer to 70 nm increases the electric field in the multiplication layer, and a sudden increase in the tunnel current increases noise, making it difficult to obtain an APD with good reception sensitivity.

On the other hand, in the InAlAs digital alloy structure multiplication layer 3 of the APD of embodiment 1, as shown in the graph of FIG. 3, when the reciprocal of the applied electric field is 1.47×10 ⁻⁶ cm/V, the dead space length is about 85 nm, so that even if the thickness of the multiplication layer is about 1.5 times the dead space (about 130 nm), it is possible to make the ionization rate ratio k approach zero. Therefore, the effect of the tunnel current is small in the APD of embodiment 1.

Furthermore, in the InAlAs digital alloy structure multiplication layer, the dead space is highly dependent on the applied electric field, and when the reciprocal of the applied electric field is 1.27×10 ⁻⁶ cm/V, the dead space length is about 50 nm, as shown in the graph in Fig. 3, so the multiplication layer needs to be thinned to 75 nm. In other words, the thickness of the InAlAs digital alloy structure multiplication layer can be made thicker than the thickness of the InAlAs random alloy structure multiplication layer.

5 is a diagram showing the dependence of the ionization rate ratio and the tunnel current on the thickness of the multiplication layer. The inventors fabricated APDs having an InAlAs digital alloy structure multiplication layer and an InAlAs random alloy structure multiplication layer, respectively, measured the ionization rate ratio k, and further plotted the results in FIG. 5 together with the measurement results in References 1 and 2 described in FIG. 5.
In addition, documents 1 and 2 in FIG. 5 are as follows.
(1) Reference 1
Yuan Yuan, et al “Temperature dependence of the ionization coefficients of InAlAs and AlGaAs digital alloys”pp. 794, Vol. 6, No. 8/August 2018/Photonics Research
(2) Reference 2
Wenyang Wang, et al “Characteristics of thin InAlAs digital alloy avalanche photodiodes” pp. 3841, Vol. 46, No. 16/15 August 2021/Optics Letters

As shown in Figure 5, in an InAlAs random alloy structure multiplication layer, the effect of reducing the ionization rate ratio k due to the dead space does not appear unless the thickness of the multiplication layer is 80 nm or less. On the other hand, if the thickness of the multiplication layer is made thinner than 80 nm, the tunnel current increases sharply and tunnel breakdown occurs. When the multiplication layer is about 60 nm thick, it is barely possible to reduce the ionization rate ratio k and limit the tunnel current, but the margin for the layer thickness is only a few nm, making it extremely difficult to stably manufacture APDs. In addition, the ionization rate ratio k is also large at 0.12. In other words, with the conventional InAlAs random alloy structure multiplication layer, it is difficult to apply the effect of reducing the ionization rate ratio k by making the layer thinner to APDs.

On the other hand, in the InAlAs digital alloy structure multiplication layer disclosed herein, as discovered by the inventors, the dead space is large, and as shown in FIG. 5, as the multiplication layer is made thinner, the ionization rate ratio k starts to decrease to 0.1 or less at a layer thickness of 170 nm. Here, the ionization rate ratio k is determined from the measured value of the multiplication noise, and is the minimum value of the ionization rate ratio in the range of multiplication factors 1 to 10. For the same ionization rate ratio k, the layer thickness of the InAlAs digital alloy structure multiplication layer is more than twice as thick as that of the InAlAs random alloy structure multiplication layer.

As shown in the graph in Figure 5, in an APD with a pn junction diameter of 20 μm, if the thickness of the multiplication layer at which the tunnel current becomes 1 μA is limited to 40 nm, the optimal thickness range for an InAlAs digital alloy structure multiplication layer is 40 nm to 170 nm, and layer thicknesses within this range can be fabricated with sufficient reproducibility.

The thickness of the InAlAs digital alloy structure multiplication layer at which the dead space effect is sufficient to reduce the ionization rate ratio k is considered to be approximately twice the dead space length when the reciprocal of the applied electric field is 1.47 x ^10-6 cm/V. Considering that the dead space length is 85 nm as shown in Figure 3, therefore, 170 nm, which is twice the dead space length, is a suitable upper limit for the thickness of the InAlAs digital alloy structure multiplication layer.

Furthermore, in order to control the ionization rate ratio k in an InAlAs digital alloy structure multiplication layer to 0.05 or less, the graph in Figure 5 shows that the thickness of the multiplication layer is preferably 150 nm or less. Furthermore, in order to achieve a tunnel current of 1 μA or less and an ionization rate ratio k of approximately zero, the optimal thickness of the multiplication layer is in the range of 60 nm to 130 nm. If a margin of 10 nm is allowed when fabricating an APD, the thickness of the multiplication layer is preferably set in the range of 70 nm to 120 nm.

In addition, as shown in FIG. 3, the length of the dead space is preferably 50 nm to 90 nm. The ratio of the length of the dead space to the thickness of the multiplication layer is preferably 29% or more, which is the minimum dead space length of 50 nm divided by the maximum multiplication layer thickness of 170 nm. As the ratio increases, the ionization rate ratio k becomes smaller, but it cannot exceed 100%. This is because multiplication does not occur when the ionization rate ratio k exceeds 100%. Therefore, the ratio of the dead space length to the thickness of the multiplication layer is preferably 29% or more and less than 100%. Furthermore, when an example of the DA-APD disclosed herein with a multiplication layer thickness of 120 nm was produced, the optimal range of the ratio of the dead space length to the multiplication layer thickness experimentally confirmed to be 42% (= 50 nm/120 nm) to 75% (= 90 nm/120 nm).

The inventors have considered the reason why the ionization rate ratio k=0 could not be achieved with a conventional InAlAs random alloy structure multiplication layer, but the ionization rate ratio k=0 could be achieved with the InAlAs digital alloy structure multiplication layer of the present disclosure.
If the dead space length of electrons is De and the dead space length of holes is Dh, the conditions for achieving an ionization rate ratio k = 0 are expressed by the following formulas (4) and (5). Note that formula (4) represents the condition for the difference in the dead space lengths, and formula (5) represents the condition for the tunnel current.

Dhe=Dh-De>0 (4)

Dh>Tmin (5)

Here, Dhe is the difference in the dead space length between holes and electrons. Tmin is the minimum thickness of the multiplication layer at which the tunnel current becomes small enough that it does not affect noise, and the thicker the multiplication layer, the more the tunnel current decreases. As shown in Figure 4C, when the thickness of the multiplication layer becomes equal to or smaller than the dead space length of holes, holes are no longer multiplied and the ionization rate ratio k = 0, so the condition for the difference in dead space length is set as shown in formula (5) above.

In the case of an InAlAs random alloy structure multiplication layer, as can be seen from Figures 3 and 5, the value at which the ionization rate ratio k begins to decrease as the multiplication layer is made thinner is De ~ 40 nm, and Dh ~ 80 nm. When the pn junction diameter is 20 μm in diameter and the tunnel current is 100 nA or less, the minimum layer thickness Tmin = 90 nm, so the InAlAs random alloy structure does not satisfy the tunnel current conditions, and it is therefore impossible to achieve an ionization rate ratio k = 0.

On the other hand, in the case of an InAlAs digital alloy structure multiplication layer, the ionization rate ratio k starts to decrease when the multiplication layer is made thinner at values De ~ 80 nm and Dh ~ 170 nm, and when the pn junction diameter is 20 μm in diameter and the tunnel current is 100 nA or less, the minimum layer thickness Tmin = 90 nm, so there is a multiplication layer thickness that satisfies the condition of ionization rate ratio k = 0. Note that the minimum layer thickness Tmin is the same for the InAlAs digital alloy structure multiplication layer and the InAlAs random alloy structure multiplication layer because the band gap of both is the same.

Specifically, in the case of a random alloy structure, De is about 40 nm and Dh is about 80 nm. In contrast, the inventors found that in the case of a digital alloy structure, De is about 80 nm and Dh is about 170 nm.

In the InAlAs digital alloy structure multiplication layer, the difference in lattice constant between the InAs (lattice constant = 0.606 nm) and AlAs (lattice constant = 0.566 nm) that make up the superlattice is very large at 6.55%. For this reason, dopants in the electric field relaxation layer, that is, impurities, may diffuse into the InAlAs digital alloy structure multiplication layer during the manufacturing process, causing disorder within the multiplication layer.

Figures 6A to 6D show the ionization rates in the multiplication layer and the electric field relaxation layer. Figure 6A shows the ionization rate in the case of an InAlAs random alloy structure multiplication layer, Figure 6B shows the ionization rate in the case of an InAlAs digital alloy structure multiplication layer, Figure 6C shows the ionization rate in the case of a partially disordered InAlAs digital alloy structure multiplication layer, and Figure 6D shows the ionization rate in the case of a combination of a thick electric field relaxation layer and an InAlAs digital alloy structure multiplication layer. Compared to the InAlAs random alloy structure multiplication layer shown in Figure 6A, the dead space length of the InAlAs digital alloy structure multiplication layer shown in Figure 6B is longer, but due to dopant diffusion from the electric field relaxation layer, the dead space length is shorter in the partially disordered InAlAs digital alloy structure multiplication layer, as shown in Figure 6C.

In order to avoid the influence of disorder in the InAlAs digital alloy structure multiplication layer, the selection of the material and dopant of the electric field relaxation layer and the doping concentration are important. The impurity diffusion equation is expressed by the following equation (6).

dN/dt=D(d ² N/d ² x)-F (6)

In formula (6), N is the impurity concentration, t is time, D is the diffusion constant, x is position, and F is the external force acting on the diffusion. Examples of materials for the electric field buffer layer include InP, InAlAs random alloy structure, and InAlAs digital alloy structure. Examples of p-type dopants for the electric field buffer layer include Be and Zn. Considering the p-type dopant, a combination of a Be-doped p-type InP electric field buffer layer and an InAlAs digital alloy structure multiplication layer is preferable. This is because Be has a small diffusion constant D and also forms a potential barrier with the InAlAs digital alloy structure multiplication layer. The potential barrier corresponds to F in formula (6).

In order to prevent the variation in the amount of electric field relaxation, that is, the product of the layer thickness and the carrier concentration, from increasing when the thickness of the electric field relaxation layer varies, the carrier concentration of the electric field relaxation layer is preferably 2× ^{10 18 cm -3} or ^less . When InAlAs is used as the constituent material of the electric field relaxation layer, Zn doping is optimal, and the carrier concentration is optimally 2×10 18 cm -3 or less. Note that if the impurity concentration is higher than 2×10 ¹⁸ cm ^-3 , the amount of inactive impurities increases and diffusion is likely to occur, so the carrier concentration must be 5×10 ¹⁸ cm ^-3 or less.

The electric field relaxation amount ΔE is expressed by the following formula (7).

ΔE=W・q・N/ε (7)

When the electric field relaxation amount ΔE is constant, if the carrier concentration of the electric field relaxation layer is increased, the thickness of the electric field relaxation layer must be reduced in inverse proportion to the carrier concentration, where W is the layer thickness of the electric field relaxation layer, q is the elementary charge, N is the carrier concentration of the electric field relaxation layer, and ε is the dielectric constant.

When the carrier concentration N of the electric field relaxation layer is about 5×10 ¹⁸ cm ^-3 , the thickness of the electric field relaxation layer is about 10 nm. In order to prevent the shortening of the dead space length due to impurity diffusion into the multiplication layer, the carrier concentration of the electric field relaxation layer is controlled to be 5×10 ¹⁸ cm ^-3 or less. In addition, the electric field relaxation layer needs to have a thickness of 10 nm or more.

On the other hand, as shown in Figure 6D, when the electric field buffer layer becomes thicker than 1.5 times the dead space length of the electric field buffer layer, multiplication occurs in the electric field buffer layer. As shown in Figure 3, in the random alloy structure, the dead space length is 45 nm or less, so the layer thickness of the random alloy electric field buffer layer needs to be 70 nm or less. On the other hand, in the InAlAs digital alloy structure, the dead space length is 85 nm or less, so the layer thickness of the digital alloy electric field buffer layer needs to be 130 nm or less.

Note that the length of each dead space shown in Figures 6A to 6D has the following relationship: dead space (Figure 6A) < dead space (Figure 6D) < dead space (Figure 6C) < dead space (Figure 6B).

<Effects of the semiconductor light receiving element according to the first embodiment>
First, a first effect of the semiconductor light receiving element according to the first embodiment will be quantitatively described below.
The 3 dB bandwidth fc of a conventional APD is expressed by the following equation (8), where the bandwidth limit due to the RC time constant is frc, the bandwidth limited by the carrier transit time is ftr, and the bandwidth limit due to the multiplication time is fm.

fc=1/((1/frc) ² +(1/ftr) ² +(1/fm) ² ) ^0.5 (8)

On the other hand, the 3 dB bandwidth f c of the APD having the InAlAs digital alloy structure multiplication layer according to the first embodiment is limited only by the RC time constant and the carrier transit time according to equations (1), (2), and (3) because the ionization rate ratio k is close to zero, and therefore can be expressed by the following equation (9).

fc=1/((1/frc) ² +(1/ftr) ² ) ^0.5 (9)

In formula (9), the transit time ftr of a carrier includes the transit time through the light absorption layer plus the transit time through the multiplication layer.

Since the RC time constant is inversely proportional to the sum of the thickness of the light absorbing layer and the thickness of the multiplication layer, while the transit time is directly proportional, Equation (9) has a maximum value. That is, the maximum bandwidth occurs when frc=ftr. Substituting frc=ftr, Equation (9) is expressed as the following Equation (10).

fc=ftr/√2 (10)

Moreover, the 3 dB bandwidth ftr determined by the transit time is expressed by the following equation (11).

ftr=3.5Vav/(2πWt) (11)

In formula (11), Vav is the average saturation transit velocity of electrons and holes, and Wt is the total thickness of the light absorption layer and the multiplication layer. For example, in the case of InGaAs, Vav is 5.35×10 ⁶ cm/s. If the thickness of the multiplication layer is 100 nm and the thickness of the light absorption layer is 400 nm, then Wt=500 nm.

Substituting Vav=5.35×10 ⁶ cm/s and Wt=500 nm into formula (11) gives ftr=59.6 GHz. Substituting this into formula (10) gives the 3 dB bandwidth of the APD having the InAlAs digital alloy multiplication layer according to the first embodiment at 42.2 GHz. Therefore, it is clear from the above considerations that the APD having the InAlAs digital alloy multiplication layer 3 according to the first embodiment can meet the bandwidth of 37.5 GHz required for a 50G-PON system. In the following description of the device, system, etc., the APD having the InAlAs digital alloy multiplication layer according to the present disclosure is referred to as the DA-APD of the present disclosure.

Figure 7 is a configuration diagram showing an optical line terminal (OLT) 250 of a 50G-PON system as a comparative example. The optical line terminal 250 as a comparative example includes a forward error correction (FEC) circuit FEC251, a driver amplifier 252, a light source 253, an optical multiplexer/demultiplexer WDM254 (Wavelength Division Multiplexing: WDM), a digital signal processing circuit DSP255, an analog-to-digital converter (ADC256), an analog-to-digital conversion circuit ADC256, a burst TIA (Trans Impedance Amplifier) 257, and a conventional APD258.

FIG. 8 is a configuration diagram showing an optical line terminal (OLT) 260 of a 50G-PON system according to the first embodiment. The optical line terminal 260 includes an FEC 261, a driver amplifier 262, a light source 263, a WDM 264, a CDR 265 (Clock Data Recovery: CDR) which is a clock and data recovery circuit, a limiting amplifier 266, a burst TIA 267, and a DA-APD 268 according to the present disclosure.

FIG. 9 is a configuration diagram showing an optical line terminal (ONU) 270 of a 50G-PON system according to the first embodiment. The optical line terminal 270 includes a WDM 271, a light source 272, a driver amplifier 273, an FEC 274, a DA-APD 275 of the present disclosure, a TIA 276, a limiting amplifier 277, and a CDR 278.

As shown in the optical line terminal (OLT) 250 of the 50G-PON system in the comparative example shown in FIG. 7, the comparative 50G-PON system required digital bandwidth compensation, i.e., a DSP 255. On the other hand, in the 50G-PON system using the DA-APD disclosed herein, digital bandwidth compensation is not required. As a result, the DSP in each configuration of the optical line terminal 260 shown in FIG. 8 and the optical line terminal 270 shown in FIG. 9 can be omitted, making it possible to reduce power consumption and costs.

Next, a second effect of the semiconductor light receiving element according to the first embodiment will be described.
In order to increase the number of branches in a PON system and eliminate the need for an SOA, it is necessary to improve the signal-to-noise ratio of the receiver and increase the receiving sensitivity. For example, if an optical demultiplexer is added to increase the number of branches from the current level, the amount of light will be halved, so the signal-to-noise ratio must be improved by at least 3 dB. The signal-to-noise ratio of a receiver using an APD is expressed by the following equation (12).

SN ratio=Iph ²・M ² /(2q(Iph+Id)M ²・F・B
+4Kb・T・Ft・B/Rt) (12)

In equation (12), Iph is the photocurrent of the APD, M is the multiplication factor, q is the unit charge, Id is the dark current to be multiplied, F is the excess noise factor of the APD, B is the bandwidth, Kb is the Boltzmann constant, T is the absolute temperature, Ft is the noise figure of the amplifier, and Rt is the input resistance. The term on the left of the denominator represents the shot noise of the APD, and the term on the right of the denominator represents the thermal noise of the amplifier.

In order to simplify equation (12), it is assumed that Id is sufficiently smaller than Iph, and that the APD shot noise term and the amplifier thermal noise term are equal when the multiplication factor is set to maximize the SNR. If the amplifier thermal noise term is replaced with the APD shot noise term, the SNR can be expressed by the following equation (13).

SN ratio = Iph/(4q・F・B) (13)

Moreover, the excess noise factor F is given by the following equation (14).

F=M(1-(1-k)・((M-1) ² /M ² ))) (14)

In the case of conventional InAlAs random alloy structure multiplication layers, as mentioned above, it is difficult to thin the layer (up to 70 nm) to the point where the dead space effect appears due to the influence of tunnel current, so there are no examples of application to APDs. For this reason, the system is designed with the ionization rate ratio k for an unthinned InAlAs multiplication layer set to 0.2. When the ionization rate ratio k = 0.2 and the multiplication factor is 12 times, the excess noise factor F = 3.9.

On the other hand, in the 50G-PON system according to the first embodiment, an APD with an InAlAs digital alloy structure as a multiplication layer, that is, the DA-APD of the present disclosure, is applied as a semiconductor light receiving element. In the case of the InAlAs digital alloy structure multiplication layer of the present disclosure, the dead space effect works even with a layer thickness of 100 nm or more, so it can be applied to APDs. In this case, the ionization rate ratio k = 0, and when the multiplication factor is 12 times, the excess noise factor F = 1.9. Therefore, the excess noise is about half that of a conventional APD. As a result, the signal-to-noise ratio is improved by 3 dB when the DA-APD of the present disclosure is applied.

In general, in a 50G-PON system, inserting one stage of a 2-way splitter to increase the number of branches increases the loss by 3 dB. Therefore, by applying the DA-APD disclosed herein as a semiconductor light receiving element, it becomes possible to insert one more stage of splitter into a 50G-PON system.

FIG. 10 shows the configuration of a 50G-PON system 280 and OLT/ONU as a comparative example. The OLT of the 50G-PON system 280 includes an FEC 251, a driver amplifier 252, a light source 253, a WDM 254, a DSP 255, an ADC 256, a burst TIA 257, and a conventional APD 258. The ONU of the 50G-PON system 280 includes an FEC 251, a driver amplifier 252, a light source 253, a WDM 254, a DSP 255, an ADC 256, a TIA 257a, and a conventional APD 258.

FIG. 11 is a diagram showing the configuration of a 50G-PON system 282 and an OLT/ONU according to the first embodiment. The OLT of the 50G-PON system 282 includes an FEC 261, a driver amplifier 262, a light source 263, a WDM 264, a DSP 265a, an ADC 266a, a burst TIA 267, and a DA-APD 268 of the present disclosure. The OLT of the 50G-PON system 282 includes an FEC 261, a driver amplifier 262, a light source 263, a WDM 264, a DSP 265a, an ADC 266a, a TIA 267a, and a DA-APD 268 of the present disclosure.

By applying the DA-APD of the present disclosure, the number of branches, which is 32 in the 50G-PON system 280 shown in FIG. 10 as a comparative example, can be doubled to 64 branches as in the 50G-PON system 282 according to the first embodiment shown in FIG. 11, making it possible to achieve a dramatic improvement. Furthermore, since it is possible to double the number of branches in PON systems other than the 50G-PON system 282, it is also possible to reduce the driving current of the transmitter laser.

FIG. 12 shows the configuration of a 50G-PON system 284 and an OLT/ONU according to the first embodiment. The OLT of the 50G-PON system 284 includes a WDM 271, a light source 272, a driver amplifier 273, an FEC 274, a DA-APD 275 of the present disclosure, a burst TIA 276, a limiting amplifier 277, and a CDR 278. The ONU of the 50G-PON system 284 includes a WDM 271, a light source 272, a driver amplifier 273, an FEC 274, a DA-APD 275 of the present disclosure, a TIA 276a, a limiting amplifier 277, and a CDR 278.

In the comparative example 50G-PON system 280, the use of SOAs in the ONU and OLT, which are optical line terminals, is being considered to compensate for the lack of sensitivity, but it is possible to configure the ONU and OLT without using SOAs, as in the 50G-PON system 284 according to embodiment 1 shown in Figure 12.

The effects of the semiconductor light receiving element according to the present disclosure will be further described.
The DA-APD of the present disclosure has an InAlAs digital alloy structure multiplication layer, and by controlling the thickness of the multiplication layer within a predetermined range to make the ionization rate ratio k zero, the multiplication time in formula (1) becomes almost zero. As a result, the response band of the APD does not deteriorate even if the multiplication factor is increased. In other words, in the DA-APD of the present disclosure, the band is limited only by the RC time constant and the carrier travel time, as in the conventional PD. Therefore, the wide band required for the 50G-PON system is possible, and reception is possible without digital band compensation by a DSP.

In addition, when the ionization rate ratio k approaches zero, excess noise that deteriorates reception sensitivity is suppressed, making it unnecessary to amplify the optical signal using an SOA. Furthermore, even in PON systems other than 50G-PON systems, it becomes possible to achieve more branching than before. As a result, it is possible to achieve low cost and power saving for PON systems.

<Effects of First Embodiment>
As described above, the semiconductor photodetector according to the first embodiment has a digital alloy structure multiplication layer whose layer thickness is controlled within a predetermined range, and thus has the effect of providing a semiconductor photodetector that is highly reliable and has excellent broadband and low noise characteristics.

Embodiment 2.
Fig. 13 is a cross-sectional view showing the element structure of a front-illuminated APD, which is an example of the semiconductor light receiving element 120 according to the second embodiment. Also, Fig. 14 is a cross-sectional view showing the element structure of an edge-illuminated APD, which is an example of the semiconductor light receiving element 130 according to the second embodiment.

<Element structure of semiconductor light receiving element according to the second embodiment>
The semiconductor light receiving element 120 according to the second embodiment includes an n-type InP substrate 1, an n-type InAlAs buffer layer 2 having a carrier concentration of 1 to 5×10 ¹⁸ cm ⁻³ and a thickness of 0.1 to 1.0 μm, which are successively formed on the n-type InP substrate 1, an InAlAs digital alloy structure multiplication layer 3 in which an i-type AlAs layer (for example, a layer thickness of two atomic layers, about 0.6 nm) and an i-type InAs layer (for example, a layer thickness of two atomic layers, about 0.6 nm) are alternately laminated multiple times, a p-type InP electric field relaxation layer 4 having a carrier concentration of 0.1 to 50×10 ¹⁷ cm ⁻³ and a layer thickness of 10 to 70 nm, an i-type InGaAs light absorption layer 5 having a layer thickness of 0.1 to 2.0 μm, an i-type InAlGaAs/InAlAs graded layer 6, a layer thickness of 0.1 to 3.0 μm and a carrier concentration of 5×10 The n-type InAlAs buffer layer 2 is composed of an n-type InP window layer 11 having a density of ¹⁷ cm ^-3 or less, a p-type diffusion region 15 provided in the n-type InP window layer 11, a p-type InGaAs contact layer 8 provided on the p-type diffusion region 15, an n-type electrode 31 formed on the back surface side of the n-type InP substrate 1, and a p-type electrode 32 formed on the p-type InGaAs contact layer 8. The n-type InAlAs buffer layer 2 is also called an n-type semiconductor layer.

The semiconductor light receiving element 130 according to the second embodiment shown in FIG. 14 comprises an Fe-doped semi-insulating InP substrate 1a, an n-type InP conductive layer 2a successively formed on the Fe-doped semi-insulating InP substrate ^1a , an n-type InAlAs buffer layer 2 having a carrier concentration of 1 to 5× ¹⁰ cm and a layer thickness of 0.1 to 1.0 μm, an InAlAs digital alloy structure multiplication layer 3 in which an i-type AlAs layer (e.g., a layer thickness of two atomic layers, about 0.6 nm) and an i-type InAs layer (e.g., a layer thickness of two atomic layers, about 0.6 ^nm ) are alternately laminated multiple times, and The n-type InP conductive layer ^2a is made of a p-type InP electric field relaxation layer 4 having a thickness of 10 to 70 nm, an i-type InGaAs light absorption layer 5 having a thickness of 0.1 to 2.0 μm, an i-type InAlGaAs/InAlAs graded layer 6, an n-type InP window layer 11 having a thickness of 0.1 to 3.0 μm and a carrier concentration of 5×10 ¹⁷ cm ⁻³ or less, a p-type diffusion region 15 provided in the n-type InP window layer 11, a p-type InGaAs contact layer 8 provided on the p-type diffusion region 15, an n-type electrode 31a formed on the front side of the n-type InP conductive layer 2a, and a p-type electrode 32 formed on the p-type InGaAs contact layer 8. The n-type InP conductive layer 2a may be made of n-type InGaAs. The n-type InAlAs buffer layer 2 and the n-type InP conductive layer 2a are also called n-type semiconductor layers.

The semiconductor photodetector elements 120 and 130 according to the second embodiment differ from the semiconductor photodetector elements 100 and 110 according to the first embodiment in that the n-type InP constituting the n-type InP window layer 11 is undoped (i-type) or has a low carrier concentration, and in that a p-type diffusion region 15 is provided in the n-type InP window layer 11. The n-type InP window layer 11 of the semiconductor photodetector elements 120 and 130 has a layer thickness of 0.1 μm or more and 3 μm or less, and a carrier concentration of 5×10 ¹⁷ cm ^-3 or less. The n-type InP window layer 11 may be made of InAlAs instead of InP, or may have a laminated structure of InP and InAlAs.

The p-type diffusion region 15 is formed by partially selectively diffusing a p-type dopant such as Zn in a solid or gas phase. The carrier concentration of the p-type diffusion region 15 is 5×10 ¹⁷ cm ⁻³ or more. The tip of the p-type diffusion region 15 may be located at a depth up to the middle of the n-type InP window layer 11, at a depth reaching the i-type InAlGaAs/InAlAs graded layer 6, or at a depth reaching the i-type InGaAs light absorption layer 5. In the device structure shown in FIG. 13 and FIG. 14, the p-type diffusion region 15 has a depth reaching the i-type InAlGaAs/InAlAs graded layer 6. A p-type InGaAs contact layer 8 is provided on the p-type diffusion region 15.

In the front-illuminated APD, which is an example of the semiconductor light-receiving element 120 shown in FIG. 13, an n-type electrode 31 is provided on the back side. On the other hand, in the front-illuminated APD, which is an example of the semiconductor light-receiving element 130 shown in FIG. 14, an n-type electrode 31a is provided on the front side. That is, in the semiconductor light-receiving element 130, an n-type InP conductive layer 2a is provided on an Fe-doped semi-insulating InP substrate 1a, and after crystal growth, the semiconductor layers above the n-type InP conductive layer 2a are partially removed, and then an n-type electrode 31a is formed on the n-type InP conductive layer 2a. In the semiconductor light-receiving element 130, a p-type InP substrate or an n-type InP substrate may be used instead of the Fe-doped semi-insulating InP substrate 1a.

<Function of the semiconductor light receiving element according to the second embodiment>
In a mesa structure such as a front-illuminated APD, which is an example of the semiconductor light-receiving element 100 according to the first embodiment shown in Fig. 1, the side portion of the multiplication layer to which an electric field is applied is exposed to the outside and is therefore prone to deterioration. In particular, when the InAlAs digital alloy structure multiplication layer 3 is used as the multiplication layer, high strain is applied to each layer of the InAlAs digital alloy structure multiplication layer 3, so that dislocation defects and disorder are likely to occur from the exposed portion toward the inside, and as a result, there is a risk of a defect in which the dead space length becomes shorter.

Furthermore, in the case of a multiplication layer in which an InAlAs digital alloy structure is thinned, as in the semiconductor light receiving elements 100 and 110 according to the first embodiment, the electric field is several tens of percent higher than in the conventional InAlAs random alloy structure, and the effect of the side portions may shorten the life of the semiconductor light receiving element.

On the other hand, when a p-type diffusion region 15 is provided as in the semiconductor light receiving element 120 shown in FIG. 13, the portion of the InAlAs digital alloy structure multiplication layer 3 to which an electric field is applied, that is, the portion directly below the p-type diffusion region 15, is not exposed to the outside of the crystal layer, which has the effect of preventing deterioration of the dead space length in the InAlAs digital alloy structure multiplication layer 3 in which each layer is highly distorted.

However, when the p-type diffusion region 15 is formed by thermal diffusion as in the semiconductor light receiving element 120 shown in FIG. 13, the heat treatment temperature in the diffusion process reaches a high temperature of 400° C. or more, which makes it easy for disorder to occur in the InAlAs digital alloy structure multiplication layer 3. Furthermore, when Zn is diffused into the n-type InP window layer 11, components with a high diffusion rate and vacancies created by the Zn diffusion reach the InAlAs digital alloy structure multiplication layer 3, causing disorder. In particular, if mutual diffusion occurs with the p-type dopant in the p-type InP electric field relaxation layer 4, there is a risk that disordering of the InAlAs digital alloy structure multiplication layer 3 will be accelerated.

In the semiconductor light receiving elements 120 and 130 according to the second embodiment, the use of Be-doped p-type InP for the p-type InP electric field relaxation layer 4 suppresses the diffusion of Be into the InAlAs digital alloy structure multiplication layer 3, and prevents the intrusion of Zn and vacancies into the InAlAs digital alloy structure multiplication layer 3 due to interdiffusion, thereby preventing the InAlAs digital alloy structure multiplication layer 3 from becoming disordered.

Therefore, in the semiconductor light receiving elements 120 and 130 according to the second embodiment, even if a high-temperature heat treatment is performed to diffuse Zn in the diffusion step for forming the p-type diffusion region 15, the InAlAs digital alloy structure multiplication layer 3 can be prevented from becoming disordered, so that the dead space length does not shorten as shown in FIG. 6C, for example, and it is possible to maintain a long dead space length as shown in FIG. 6B. As a result, in the semiconductor light receiving elements 120 and 130 according to the second embodiment, it is possible to maintain the ionization rate ratio k at approximately zero, even though Zn diffusion is performed to form the p-type diffusion region 15.

<Effects of the Second Embodiment>
As described above, according to the semiconductor light-receiving element of the second embodiment, even though Zn diffusion is performed to form a p-type diffusion region during the formation of the element structure, disordering of the InAlAs digital alloy structure multiplication layer can be prevented, and the ionization rate ratio k can be maintained at approximately zero, thereby providing an effect of providing a semiconductor light-receiving element that is highly reliable and has excellent wideband and low-noise characteristics.

Embodiment 3.
FIG. 15 is a cross-sectional view showing the element structure of a front-illuminated APD, which is an example of a semiconductor light-receiving element 140 according to the third embodiment.

<Element structure of semiconductor light receiving element according to the third embodiment>
The front-illuminated APD, which is an example of the semiconductor photodetector 140 according to the third embodiment, is characterized in that, in addition to the element structure of the front-illuminated APD, which is an example of the semiconductor photodetector 120 according to the second embodiment, a separation groove 17 is provided along the outer periphery of the p-type diffusion region 15 formed in the n-type InP window layer 11.

The depth of the separation groove 17 is preferably in the range of 2 μm to 5 μm. The opening width of the separation groove 17 is preferably in the range of 0.5 μm to 100 μm. The bottom of the separation groove 17 reaches at least the InAlAs digital alloy structure multiplication layer 3. Note that FIG. 15 shows an example in which the bottom of the separation groove 17 reaches halfway through the n-type InAlAs buffer layer 2. Either dry etching or wet etching may be used to form the separation groove 17. However, it is preferable to add wet etching to remove the damaged layer caused by the dry etching after dry etching, which has excellent depth control.

The inside of the separation groove 17 and the surface of the n-type InP window layer 11 are protected by a surface protective film 18 made of an insulating film made of an oxide film such as SiN or _SiO2 . The surface protective film 18 also serves as an anti-reflective coating for the light receiving section. The thickness of the surface protective film 18 is preferably within a range of 50 nm to 5000 nm. The surface protective film 18 may also be an organic film such as benzocyclobutene (BCB).

<Function of the semiconductor light receiving element according to the third embodiment>
When the InAlAs digital alloy structure is used as the multiplication layer, each layer of the InAlAs digital alloy structure is highly strained, so that the InAlAs digital alloy structure is easily disordered when stress is applied from the outside. Therefore, as in the semiconductor light receiving element 140 according to the third embodiment, by providing the separation groove 17 along the outer periphery of the p-type diffusion region 15, the stress that affects the entire wafer during the manufacturing process can be alleviated. Even in the state of individual semiconductor light receiving elements 140, the stress is alleviated by the presence of the separation groove 17, so that the stress concentration in the light receiving part at the center of the semiconductor light receiving element 140 can be alleviated. Furthermore, since the InAlAs digital alloy structure multiplication layer 3 is exposed in the separation groove 17, it is desirable that the above-mentioned surface protection film 18 covers the surface of the separation groove 17. Note that a high electric field is not applied to the separation groove 17, so it does not become a starting point of deterioration.

As described above, in the semiconductor light receiving element 140 of the third embodiment, even if a high-temperature heat treatment is performed to diffuse Zn in the diffusion process for forming the p-type diffusion region 15, the InAlAs digital alloy structure multiplication layer 3 can be prevented from becoming disordered, so that it is possible to maintain a long dead space length as shown in FIG. 6B, for example, without the dead space length becoming shorter as shown in FIG. 6C. As a result, it is possible to maintain the ionization rate ratio k at approximately zero, even though Zn diffusion is performed in the manufacturing process.

Furthermore, because the stress is relieved by the separation groove 17 even when the semiconductor light receiving element 140 is in operation, no disorder occurs even if the semiconductor light receiving element 140 is used for a long period of time. In other words, the semiconductor light receiving element 140 of the third embodiment can achieve high reliability by maintaining a wide bandwidth and low noise for a long period of time.

<Effects of Third Embodiment>
As described above, according to the semiconductor light-receiving element of the third embodiment, even though Zn diffusion is performed to form the p-type diffusion region 15 during the formation of the element structure, the InAlAs digital alloy structure multiplication layer can be prevented from becoming disordered, so that it is possible to maintain the ionization rate ratio k at approximately zero. In addition, the presence of the separation groove can relieve stress, so that an effect is achieved in that a semiconductor light-receiving element that is highly reliable and has excellent wideband and low-noise characteristics can be obtained.

Embodiment 4.
FIG. 16 is a cross-sectional view showing the element structure of a back-illuminated APD, which is an example of a semiconductor light-receiving element 150 according to the fourth embodiment.

<Element structure of semiconductor light receiving element according to the fourth embodiment>
While the front-illuminated APD, which is an example of the semiconductor light-receiving element 140 according to the third embodiment, receives light from the front side, the back-illuminated APD, which is an example of the semiconductor light-receiving element 150 according to the fourth embodiment, is characterized in that it has an element structure in which a part of the n-type electrode 31b on the back side is removed to provide an opening 33, and light is made incident on the n-type InP substrate 1 exposed in the opening 33. In other words, the opening 33, which is an incidence region for the incident light 90, is provided on the back side of the n-type InP substrate 1 opposite the p-type electrode 32.

The back-illuminated APD, which is an example of the semiconductor light receiving element 150 according to the fourth embodiment, can prevent the InAlAs digital alloy structure multiplication layer 3 from becoming disordered, even if a high-temperature heat treatment is performed to diffuse Zn in the diffusion process for forming the p-type diffusion region 15, just like the semiconductor light receiving element 140 according to the third embodiment. Therefore, for example, the dead space length does not become shorter as shown in FIG. 6C, and it is possible to maintain a long dead space length as shown in FIG. 6B.

Furthermore, since the area of the p-type diffusion region 15 can be formed smaller in a back-illuminated APD such as the semiconductor light receiving element 150 than in a front-illuminated APD such as the semiconductor light receiving element 120, it is possible to further reduce the stress generated during p-type diffusion, and therefore it is possible to further prevent disordering of the InAlAs digital alloy structure multiplication layer 3. As a result, even though Zn diffusion is performed when forming the element structure, disordering of the InAlAs digital alloy structure multiplication layer 3 can be prevented, so it is possible to maintain the ionization rate ratio k at almost zero, and the stress can be further reduced, resulting in the effect of obtaining a semiconductor light receiving element that is highly reliable and has excellent wideband and low noise characteristics.

<Effects of the Fourth Embodiment>
As described above, according to the semiconductor light-receiving element of the fourth embodiment, the element structure is a back-illuminated APD, and therefore the area of the p-type diffusion region can be made smaller than that of a front-illuminated APD. This makes it possible to maintain the ionization rate ratio k at approximately zero, and further reduces stress, thereby providing an advantageous effect of providing a semiconductor light-receiving element that is highly reliable and has excellent broadband and low-noise characteristics.

Embodiment 5.
Fig. 17 is a cross-sectional view showing the element structure of a front-illuminated APD, which is an example of the semiconductor light receiving element 160 according to the fifth embodiment. Also, Fig. 18 is a cross-sectional view showing another element structure of a front-illuminated APD, which is an example of the semiconductor light receiving element 170 according to the fifth embodiment.

<Element structure of semiconductor light receiving element according to the fifth embodiment>
The semiconductor light receiving element 160 according to the fifth embodiment comprises an n-type InP substrate 1, an n-type InAlAs buffer layer ² having a carrier concentration of 1 to 5× ¹⁰ cm and a thickness of 0.1 to 1.0 μm, which are successively formed on the n-type InP substrate 1, an InAlAs digital alloy structure multiplication layer 3 in which an i-type AlAs layer (for example, a layer thickness of two atomic layers, about 0.6 nm) and an i-type InAs layer (for example, a layer thickness of two atomic layers, about 0.6 ^nm ) are alternately laminated multiple times, and The n-type InP substrate ¹ is made up of a p-type InP electric field relaxation layer 4 having a thickness of 10 to 70 nm and a thickness of 300 nm, an i-type InGaAs light absorption layer 5 having a thickness of 0.1 to 2.0 μm, an i-type InAlGaAs/InAlAs graded layer 6, an n-type InP window layer 11 having a thickness of 0.1 to 3.0 μm, a p-type InAlAs conductive layer 25, a p-type InGaAs contact layer 8, an n-type electrode 31 formed on the back surface side of the n-type InP substrate 1, and a p-type electrode 32 formed on the p-type InGaAs contact layer 8. The n-type InAlAs buffer layer 2 is also called an n-type semiconductor layer.

The semiconductor light receiving element 160 according to the fifth embodiment differs from the semiconductor light receiving element 100 according to the first embodiment in that the p-type InAlAs conductive layer 25 formed on the n-type InP window layer 11 is formed in a mesa shape, and a p-type InGaAs contact layer 8 and a p-type electrode 32 are provided on the p-type InAlAs conductive layer 25. The n-type InP window layer 11 may have a thickness of 50 nm or more, but a thickness of 200 nm or less is preferable in order not to lengthen the carrier travel time. The conductivity type of the n-type InP window layer 11 may be undoped instead of n-type. In the case of n-type, the carrier concentration is preferably 5.0×10 ¹⁷ cm ^-3 or less.

The manufacturing method of the semiconductor light receiving element 160 according to the fifth embodiment is characterized in that the p-type InAlAs conductive layer 25 is crystal-grown on the n-type InP window layer 11 by MOCVD or the like, and then the p-type InGaAs contact layer 8 is crystal-grown, after which the p-type InAlAs conductive layer 25 is removed, leaving the light receiving portion.

The thickness of the p-type InAlAs conductive layer 25 is preferably 100 nm or more and 3000 nm or less. The carrier concentration of the p-type InAlAs conductive layer 25 is preferably high, that is, 5.0×10 ¹⁷ cm ^-3 or more, in order to reduce the element resistance. The p-type InAlAs conductive layer 25 may be a laminated structure of p-type InP, p-type InGaAs, p-type InGaAsP, or p-type InAlGaAs instead of p-type InAlAs.

Also, while the semiconductor light receiving element 160 shown in FIG. 17 has an n-type electrode 31 on the back side, the semiconductor light receiving element 170 shown in FIG. 18 has an n-type electrode 31a on the front side. That is, in the semiconductor light receiving element 170, an n-type InP conductive layer 2a is provided on an Fe-doped semi-insulating InP substrate 1a, and after crystal growth, the layers above the n-type InP conductive layer 2a are partially removed, and then the n-type electrode 31a is formed on the n-type InP conductive layer 2a. Instead of the Fe-doped semi-insulating InP substrate 1a, a p-type InP substrate or an n-type InP substrate may be used.

<Function of the semiconductor light receiving element according to the fifth embodiment>
The operation of the semiconductor light receiving elements 160 and 170 according to the fifth embodiment will be described below.
When forming the p-type InAlAs conductive layer 25 to which a voltage is applied, a p-type diffusion step accompanied by a heat treatment at a high temperature of 400° C. or more is not performed, as compared with the semiconductor light receiving element 120 according to the second embodiment shown in Fig. 14, and therefore disordering of the InAlAs digital alloy structure multiplication layer 3 can be prevented, so that the dead space length does not become short as shown in Fig. 6C, and it becomes possible to maintain a state in which the dead space length is long as shown in Fig. 6B. As a result, it becomes possible to maintain the ionization rate ratio k at approximately zero.

<Effects of the Fifth Embodiment>
As described above, according to the semiconductor light receiving element of the fifth embodiment, as in the semiconductor light receiving element of the second embodiment, the region of the multiplication layer directly below the light receiving portion to which a high electric field is applied is separated from the side portion of the element, and therefore high reliability is obtained. As a result, a semiconductor light receiving element having high reliability, wide bandwidth, and low noise characteristics is obtained.

Embodiment 6.
FIG. 19 is a cross-sectional view showing the element structure of a front-illuminated APD, which is an example of a semiconductor light-receiving element 180 according to the sixth embodiment.

<Element structure of semiconductor light receiving element according to the sixth embodiment>
The front-illuminated APD, which is an example of the semiconductor light-receiving element 180 according to the sixth embodiment, is characterized in that a separation groove 17 is further provided along the outer periphery of the p-type InAlAs conductive layer 25 in addition to the element structure of the front-illuminated APD, which is an example of the semiconductor light-receiving element 160 according to the fifth embodiment.

The depth of the separation groove 17 is preferably within the range of 2 μm to 5 μm. The opening width of the separation groove 17 is preferably within the range of 0.5 μm to 100 μm. The bottom of the separation groove 17 reaches at least the InAlAs digital alloy structure multiplication layer 3. Note that FIG. 19 shows an example in which the bottom of the separation groove 17 reaches halfway through the n-type InAlAs buffer layer 2. Either dry etching or wet etching may be used to form the separation groove 17. However, it is preferable to add wet etching to remove the damaged layer caused by the dry etching after dry etching, which has excellent depth control.

The inside of the separation groove 17 and the surface of the n-type InP window layer 11 are protected by a surface protective film 18 made of an insulating film made of an oxide film such as SiN or _SiO2 . The surface protective film 18 also serves as an anti-reflective coating for the light receiving section. The thickness of the surface protective film 18 is preferably within a range of 50 nm to 5000 nm. The surface protective film 18 may also be an organic film such as BCB.

<Function of the semiconductor light receiving element according to the sixth embodiment>
When the InAlAs digital alloy structure is used as the multiplication layer, each layer of the InAlAs digital alloy structure is highly strained, so that when stress is applied from the outside, disordering is likely to occur. Therefore, as in the semiconductor light receiving element 180 according to the sixth embodiment, by providing the separation groove 17 along the outer periphery of the p-type InAlAs conductive layer 25, the stress that affects the entire wafer during the manufacturing process can be alleviated. Even in the state of individual semiconductor light receiving elements 180, the stress is alleviated by the presence of the separation groove 17, so that the stress concentration in the light receiving part at the center of the semiconductor light receiving element 180 can be alleviated. In addition, since the InAlAs digital alloy structure multiplication layer 3 is exposed in the separation groove 17, it is desirable that the above-mentioned surface protection film 18 covers the surface of the separation groove 17. Note that a high electric field is not applied to the separation groove 17, so that it does not become a starting point of deterioration.

<Effects of Sixth Embodiment>
As described above, according to the semiconductor photodetector of the sixth embodiment, the separation groove can relieve stress due to heat treatment or the like in the manufacturing process, and therefore disordering of the digital alloy structure multiplication layer can be prevented. This makes it possible to maintain the ionization rate ratio k at approximately zero, and provides the effect of providing a semiconductor photodetector that is highly reliable and has excellent broadband and low noise characteristics.

Embodiment 7.
FIG. 20 is a cross-sectional view showing the element structure of a back-illuminated APD, which is an example of a semiconductor light-receiving element 190 according to the seventh embodiment.

<Element structure of semiconductor light receiving element according to seventh embodiment>
While a front-illuminated APD, which is an example of a semiconductor light-receiving element 180 according to the sixth embodiment, receives light from the front side as shown in Fig. 19, a back-illuminated APD, which is an example of a semiconductor light-receiving element 190 according to the seventh embodiment, is characterized in that, as shown in Fig. 20, a part of the n-type electrode 31b on the back side is removed to provide an opening 33, and light is made incident on the n-type InP substrate 1 exposed in the opening 33. In other words, the opening 33, which is an incident region for incident light 90, is provided on the back side of the n-type InP substrate 1 opposite the p-type electrode 32.

The back-illuminated APD, which is an example of the semiconductor light receiving element 190 according to the seventh embodiment, can relieve stress due to heat treatment during the manufacturing process by using a separation groove, similar to the semiconductor light receiving element 180 according to the sixth embodiment, and therefore can prevent the InAlAs digital alloy structure multiplication layer 3 from becoming disordered. As a result, the dead space length does not become shorter as shown in FIG. 6C, but rather it is possible to maintain a long dead space length as shown in FIG. 6B.

Furthermore, since the area of the p-type InAlAs conductive layer 25 can be made smaller in a back-illuminated APD such as the semiconductor light receiving element 190 than in a front-illuminated APD, it is possible to further reduce stress due to heat treatment in the manufacturing process, and therefore it is possible to further prevent disordering of the InAlAs digital alloy structure multiplication layer 3. As a result, even though a heat treatment process is performed when forming the element structure, disordering of the InAlAs digital alloy structure multiplication layer 3 can be prevented, so it is possible to maintain the ionization rate ratio k at almost zero, and stress can be further reduced, resulting in the effect of obtaining a semiconductor light receiving element that is highly reliable and has excellent wideband and low noise characteristics.

In addition, in a back-illuminated APD such as the semiconductor photodetector 190, the area of the mesa-shaped p-type InAlAs conductive layer 25 can be reduced compared to that of a front-illuminated APD, so the effect of stress from the mesa portion of the p-type InAlAs conductive layer 25 is reduced, and the InAlAs digital alloy structure multiplication layer 3 does not become disordered. In addition, because stress is relaxed even during operation of the semiconductor photodetector 190, the InAlAs digital alloy structure multiplication layer does not become disordered even after a long period of time. In other words, the semiconductor photodetector 190 according to the seventh embodiment can maintain a wide bandwidth and low noise for a long period of time.

<Effects of the Seventh Embodiment>
As described above, according to the semiconductor light-receiving element of the seventh embodiment, since the area of the p-type conductive layer can be made small, it is possible to further reduce the stress generated in the heat treatment process, and therefore it is possible to further prevent disordering of the InAlAs digital alloy structure multiplication layer 3, so that it is possible to maintain the ionization rate ratio k at approximately zero, and since the stress can be further reduced, it is possible to obtain a semiconductor light-receiving element that is highly reliable and has excellent wide band and low noise characteristics.

Embodiment 8.
FIG. 21 is a cross-sectional view showing the element structure of a back-illuminated APD, which is an example of a semiconductor light-receiving element 200 according to the eighth embodiment.

<Element structure of semiconductor light receiving element according to the eighth embodiment>
The semiconductor light receiving element 200 according to the eighth embodiment comprises an Fe-doped semi-insulating InP substrate 1a, and a p-type InGaAlAs contact layer 40 having a carrier concentration of 1 to 5× ¹⁰ cm ⁻³ and a layer thickness of 0.1 to 1 μm, which are successively formed on the Fe-doped semi-insulating InP substrate 1a, a p-type InGaAlAs contact layer 40 having a carrier concentration of 1 to 5× ¹⁰ cm ⁻³ and a layer thickness of 0.1 to 1 μm, a p-type InP conductive layer 41 having a carrier concentration of 1 to 5×10 cm −3 and a layer thickness of 0.1 to 1 μm, a p-type or low carrier concentration (5×10 ¹⁷ cm ⁻³ or less) n-type or i-type InAlGaAs/InAlAs graded layer 42, an i-type InGaAs light absorbing layer 43 having a layer thickness of 0.1 to 2.0 μm, and a p-type InGaAs/InAlAs layer 44 having a layer thickness of 10 to 100 nm and a carrier concentration of 1 to 50×10 ¹⁷ cm a p-type InP field relaxation layer 44 having a thickness of 1000 nm; an InAlAs digital alloy structure multiplication layer ⁴⁵ having a digital alloy structure in which an i-type AlAs layer (for example, a layer thickness of two atomic layers, about 0.6 nm) and an i-type InAs layer (for example, a layer thickness of two atomic layers, about 0.6 nm) are alternately laminated a plurality of times; an n-type InAlAs field adjustment layer 46 having a thickness of 10 to 50 nm; an n-type InP window layer 47 having a thickness of ^0.1 to ² μm ^; an n-type InAlAs conductive layer 48 having a thickness of 0.1 to 2 μm and a carrier concentration of 5×10 ¹⁷ to 8×10 ¹⁸ cm ⁻³ , an n-type electrode 50 formed on the n-type InGaAs contact layer 49, a p-type electrode 51 formed on the p-type InGaAlAs contact layer 40, and a metal film 53 formed on the back side of the Fe-doped semi-insulating InP substrate 1a. The p-type InP conductive layer 41 is also called a p-type semiconductor layer.

<Method of Manufacturing Semiconductor Light-Receiving Element According to Eighth Embodiment>
A method for manufacturing the semiconductor light receiving element 200 according to the eighth embodiment will be described below.
Using MOVPE or MBE, a p-type InGaAlAs contact layer 40 having a carrier concentration of 1 to 5×10 ¹⁸ cm ^-3 is crystal-grown to a thickness of 0.1 to 1 μm on an Fe-doped semi-insulating InP substrate 1a. An n-type InP substrate may be used instead of the Fe-doped semi-insulating InP substrate 1a. Also, the p-type InGaAs contact layer 40 may be made of p-type InP, p-type InGaAsP, or p-type InGaAs instead of p-type InGaAlAs.

A p-type InP conductive layer 41 having a carrier concentration of 1 to 5×10 ¹⁸ cm ⁻³ and a thickness of 0.1 to 1 μm is grown by crystal growth on the p-type InGaAlAs contact layer 40. Here, the p-type InP conductive layer 41 may be p-type InGaAsP or p-type InAlGaAs instead of p-type InP.

Next, an i-type, n-type or p-type InAlAs layer with a small barrier against holes may be provided on the p-type InP conductive layer 41. Furthermore, after the p-type or low carrier concentration (5×10 ¹⁷ cm ^-3 or less) n-type or i-type InAlGaAs/InAlAs graded layer 42 is crystal-grown, the i-type InGaAs light absorbing layer 43 is crystal-grown to a thickness of 0.1 to 2 μm. The i-type InGaAs light absorbing layer 43 may be an n-type or p-type with a low carrier concentration (5×10 ¹⁷ cm ^-3 or less) instead of an i-type. Here, either or both of the p-type InP conductive layer 41 and the n-type InAlGaAs/InAlAs graded layer 42 are not necessarily required.

Next, the p-type InP electric field buffer layer 44 having a carrier concentration of 1 to 50×10 ¹⁷ cm ^-3 is crystal-grown to a thickness of 10 to 100 nm. Examples of p-type dopants for the p-type InP electric field buffer layer 44 include Be, Zn, and C. The p-type InP electric field buffer layer 44 does not necessarily have to be p-type InP, and may be p-type InAlAs or a p-type InAlAs digital alloy structure.

If the dopants in the p-type InP electric field buffer layer 44 diffuse into the adjacent InAlAs digital alloy structure multiplication layer 45, the InAlAs digital alloy structure becomes disordered and changes to an InAlAs random alloy structure. In particular, since the thickness of the InAlAs digital alloy structure multiplication layer 45 is thin at about 100 nm, the effect of disordering due to dopant diffusion is large. Therefore, the optimal p-type dopant for the p-type InP electric field buffer layer 44 is Be, which is less likely to diffuse. On the other hand, when using a p-type InAlAs electric field buffer layer, Zn is the optimal p-type dopant.

Also, between the i-type InGaAs light absorption layer 43 and the p-type InP electric field relaxation layer 44, an InAlGaAs/InAlAs graded layer with a thickness of 10 to 100 nm, which has an intermediate band gap value, such as InAlGaAs or InGaAsP, may be provided.

The InAlAs digital alloy structure multiplication layer 45 is crystal-grown as a multiplication layer on the p-type InP electric field relaxation layer 44. The InAlAs digital alloy structure multiplication layer 45 is composed of semiconductor layers that are alternately stacked in the order of an AlAs layer (layer thickness of two atomic layers, approximately 0.6 nm) and an InAs layer (layer thickness of two atomic layers, approximately 0.6 nm) from the side of the Fe-doped semi-insulating InP substrate 1a. The InAlAs digital alloy structure multiplication layer 45 may be formed in the order of an InAs layer and an AlAs layer.

The number of atomic layers in each layer of the InAlAs digital alloy structure multiplication layer 45 is preferably 2 to 4 atomic layers, with 2 atomic layers being optimal. The reason for this is that the thinner the atomic layer thickness of each layer, the greater the effect of reducing the ionization rate ratio k due to the digital alloy structure.

The InAlAs digital alloy structure multiplication layer 45 may have an i-type conductivity with a carrier concentration of 1×10 ¹⁷ cm ⁻³ or less, but may also have a p-type or n-type conductivity with a carrier concentration of 5×10 ¹⁸ cm ⁻³ or less.

In order to increase the dead space effect in the InAlAs digital alloy structure multiplication layer 45, the thickness of the InAlAs digital alloy structure multiplication layer 45 is preferably in the range of 40 nm to 170 nm. However, considering the typical variation of 20% in the layer thickness during the fabrication of the semiconductor light receiving element 190, the thickness of the InAlAs digital alloy structure multiplication layer 45 is preferably in the range of 50 nm to 140 nm.

Next, the n-type InAlAs field adjustment layer 46 is crystal-grown to a thickness of 10 to 50 nm, and then the n-type InP window layer 47 is crystal-grown to a thickness of 0.1 to 2 μm. Here, the n-type InP window layer 47 also functions as a field adjustment layer and an electron transit layer, but is not necessarily required. The n-type InAlAs field adjustment layer 46 and the n-type InP window layer 47 are layers for adjusting the electric field at the outermost surface, and preferably have a carrier concentration in the range of 1 to 500×10 ¹⁶ cm ^-3 . Weakening the electric field at the outermost surface has the effect of suppressing local breakdown and improving reliability.

An n-type InAlAs conductive layer 48 is grown as an n-type conductive layer, and an n-type InGaAs contact layer 49 is grown as an n-type contact layer, on the n-type InP window layer 47. The n-type InAlAs conductive layer 48 and the n-type InGaAs contact layer 49 each have a thickness of 0.1 to 2 μm and a carrier concentration of 5× ¹⁰ cm ⁻³ to 8× ¹⁰ cm ⁻³ .

After the crystal growth of the n-type InGaAs contact layer 49, the n-type InAlAs conductive layer 48 and the n-type InGaAs contact layer 49 are etched into a mesa shape to form a first mesa. Then, the second mesa is formed by etching the p-type InGaAs contact layer 40 so as to include the first mesa outside the first mesa. The second mesa does not need to reach the p-type InGaAs contact layer 40 as long as the i-type InGaAs light absorption layer 43 can be electrically isolated. It is preferable that the distance between the first mesa and the second mesa is 1 μm or more. The first mesa may be formed after the second mesa is formed.

The p-type electrode 51 is formed on the p-type InGaAs contact layer 40, and the n-type electrode 50 is formed on the n-type InGaAs contact layer 49. Since the ohmic resistance of an n-type semiconductor is one order of magnitude smaller than that of a p-type semiconductor, it is not necessarily necessary to use the n-type InGaAs contact layer 49, which has a small band gap, and n-type InP, n-type InGaAlAs, or n-type InGaAsP may also be used. Alternatively, a direct contact may be made with the n-type InAlAs conductive layer 48.
Through the above steps, the semiconductor light receiving element 200 according to the eighth embodiment is completed.

<Functions and Effects of Semiconductor Light-Receiving Element According to Eighth Embodiment>
The semiconductor light receiving element 200 of the eighth embodiment is characterized in that the conductivity type of the semiconductor light receiving element 180 of the seventh embodiment is inverted from n type to p type and from p type to n type, and the conductivity type of the upper surface side is made n type.

A first function and effect of the semiconductor light receiving element 200 according to the eighth embodiment will be described below.
If the InAlAs digital alloy structure multiplication layer 45 is held at a high temperature for a long time during epitaxial crystal growth, it may become disordered and become an InAlAs random alloy structure. In the semiconductor light receiving element 200 according to the eighth embodiment, the total layer thickness of each semiconductor layer above the InAlAs digital alloy structure multiplication layer 45 is about one-third thinner than that of the semiconductor light receiving element 190 according to the seventh embodiment. That is, in the semiconductor light receiving element 200 according to the eighth embodiment, the crystal growth time required for epitaxially growing each remaining semiconductor layer after the InAlAs digital alloy structure multiplication layer 45 is crystal grown is about one-third shorter than that of the semiconductor light receiving element 190 according to the seventh embodiment, so that the InAlAs digital alloy structure multiplication layer 45 is less likely to become disordered. As a result, the dead space length is increased, and the state in which the ionization rate ratio k is zero can be more reliably realized.

A second function and effect of the semiconductor light receiving element 200 according to the eighth embodiment will be described below.
The upper electrode of the semiconductor light receiving element, that is, the electrode on the front side, is a p-type electrode 32 in the back-illuminated APD shown in Fig. 20, and an n-type electrode 50 in the back-illuminated APD shown in Fig. 21. To increase the speed, it is necessary to reduce the electrode area of the front side electrode and reduce the electric capacitance. However, when the electrode area of the upper electrode is reduced, the contact resistance between the electrode and the semiconductor layer increases, which causes a problem that the RC time constant increases and the response band becomes narrower.

In the semiconductor light receiving element 200 according to the eighth embodiment, the upper electrode, i.e., the n-type electrode 50, is in contact with an n-type semiconductor, so the ohmic resistance is reduced to one tenth compared to contact with a p-type semiconductor. This allows the area of the n-type electrode 50 to be reduced, which has the effect of reducing stress from the electrode and making disorder less likely to occur in the InAlAs digital alloy structure multiplication layer 45. As a result, in the semiconductor light receiving element 200 according to the eighth embodiment, a state in which the ionization rate ratio k is zero can be more easily achieved, which has the effect of reducing the bandwidth compensation circuit in the PON system, doubling the number of branches, omitting the SOA, and reducing the operating current of the transmitter laser.

<Effects of the Eighth Embodiment>
As described above, according to the semiconductor photodetector of the eighth embodiment, the crystal growth time required for epitaxial crystal growth of the remaining semiconductor layers after the InAlAs digital alloy structure multiplication layer is crystal grown is about one-third shorter than that of the semiconductor photodetector of the seventh embodiment, so that disordering of the InAlAs digital alloy structure multiplication layer is less likely to occur. This makes it possible to more reliably realize a state in which the dead space length is longer and the ionization rate ratio k is zero, and also makes it possible to further reduce stress, thereby providing an advantageous effect of providing a semiconductor photodetector that is highly reliable and has excellent wideband and low noise characteristics.

Embodiment 9.
Fig. 22 is a diagram showing a configuration of a multi-level intensity modulation transmitting/receiving apparatus 300 according to embodiment 9. Fig. 23A and Fig. 23B are diagrams showing received waveforms of the multi-level intensity modulation transmitting/receiving apparatus 300 according to embodiment 9.

The multilevel intensity modulation transmitter/receiver 300 is a multilevel intensity modulation transmitter/receiver using the PAM (Pulse Amplitude Modulation) method, which is a multilevel intensity modulation method. In the transmitter, the digital signal generated in the DSP 301 is converted to analog in the DAC 302a, amplified in the driver amplifier 303, and drives the light source 304 consisting of a DFB laser or EML to emit an optical signal to the optical fiber cable 310.

Meanwhile, in the receiving section, the light passes through the optical fiber cable 310 and the optical system and enters the DA-APD 305, which is the semiconductor light receiving element disclosed herein, where the optical signal is converted to a current and multiplied. It is then amplified in the Linear-TIA 306, converted to a digital signal in the ADC 302b, and signal processing is performed by the DSP 301.

<Functions and Effects of the Multilevel Intensity Modulation Transmitter/Receiver According to the Ninth Embodiment>
In the PAM type multi-level intensity modulation transmitting/receiving device 300, not only binary signals of 1 and 0 such as NRZ (None Return to Zero) and RZ (Return to Zero), but also, for example, in PAM4 (Pulse Amplitude Modulation-4), it is necessary to receive four values with different optical signal intensities. An example of a PAM4 received waveform is shown in FIG. 23A. An index called TDECQ (Transmitter Dispersion and Eye Closure Quaternary) is used to determine whether the received waveform in PAM4 is good or bad. TDECQ is calculated by the following formula (15).

TDECQ (dB) = 10log (OMA/(6・Qt・R)) (15)

In formula (15), the optical modulation amplitude (OMA) is the total amplitude from level 0 to level 3, Qt is a value dependent on the SER (Symbol Error Rate) defined by the IEEE (Institute of Electrical and Electronics Engineers), and R is the additional noise value required to achieve the SER value. TDECQ (dB) is defined as, for example, 3 dB or less. In order to reduce TDECQ (dB),
(1) The eye opening at each level must be uniform. (2) The noise at each level must be low.

In order for the eye opening at each of the four levels, which have different optical signal strengths, to be uniform, the semiconductor light receiving element must have excellent linearity. Here, a semiconductor light receiving element has good linearity when the photocurrent Iph increases in proportion to the optical input power Pin. In other words, even if the optical input power Pin changes, if Iph/Pin is constant, it can be said to have good linearity.

Also, since PAM needs to receive signals with a wide range of strengths, from low to high, it needs to have an excellent dynamic range. In other words, even if the optical input power Pin increases, if the drop in Iph/Pin is small, the dynamic range can be said to be good. As in the received waveform in Figure 23B, if the linearity and dynamic range deteriorate, the eye opening formed between levels 2 and 3 deteriorates.

In the case of APDs, one of the reasons for the degradation of linearity is that when the photocurrent increases with an increase in optical input, the number of holes and electrons traveling in the multiplication layer and the light absorption layer increases, causing a change in the electric field distribution in the multiplication layer and the light absorption layer. This phenomenon is called the space charge effect.

The inventors have studied a model of degradation of the linearity of an APD. Figures 24A and 24B are diagrams for explaining the operation of a PD when a high optical input is applied. As shown in Figure 24A, when the optical input increases and the photocurrent increases, a space charge effect acts as if a voltage drop occurs due to the series resistance and no voltage is applied to the pn junction. This voltage drop reduces the multiplication factor. This is because the generated electrons and holes affect the electric field distribution as shown in Figure 24B. The series resistance Rli that degrades the linearity of an APD is expressed by the following formula (16).

Rli=Rsc+Rd+Rlo (16)

In equation (16), Rsc is the resistance due to the space charge effect, Rd is the element resistance, and Rlo is the load resistance. Rd and the load resistance are usually several tens of ohms, but Rsc can be several hundreds of ohms or more.

It has been found that, when the time it takes for electrons and holes generated by light absorption to pass through the depletion layer is Td, Rsc can be expressed by the following formula (17).

Rsc=W・Td/(2εS) (17)

In equation (17), W is the thickness of the depletion layer, ε is the dielectric constant, and S is the pn junction area.

Next, the operation of the APD at high light input will be described. FIG. 25 is a diagram for explaining the operation of the APD at high light input. When a large number of electrons and holes are generated in the multiplication layer, the electric field in the multiplication layer of the APD changes, that is, the so-called space charge effect occurs. Due to the occurrence of this space charge effect, the multiplication factor of the APD decreases and the linearity deteriorates. As described above, since the deterioration of the linearity of the APD is caused by the series resistance Rsc, it is necessary to reduce the residence time Td of the electrons and holes in the depletion layer. In particular, when the multiplication factor increases, the residence time Tdm in the multiplication layer increases. Tdm is the same as the so-called multiplication time, and is expressed by the following formula (18).

Residence time Tdm = Multiplication time = 2π・N・k・M・τav (18)

In equation (18), N is the Emmons coefficient (which depends gently on the ionization rate ratio k), M is the multiplication factor, and τav is the time it takes for the carrier to travel through the multiplication layer. The residence time Tdm excludes the one-way transit time it takes for the carrier to cross the multiplication layer. The multiplication factor N is 0.55, 0.83, 1.1, and 2.0 when the ionization rate ratio k = 0.5 (InP), 0.2 (InAlAs), 0.1 (Si), and 0 to 0.001 (InAlAs digital alloy structure), respectively.

Figure 26 shows the residence time Tdm of electrons and holes for each material that makes up the multiplication layer. In the InAlAs digital alloy structure multiplication layer, the residence time Tdm within the multiplication layer is dramatically reduced. In other words, electrons and holes are quickly discharged from the multiplication layer, suppressing the space charge effect in the multiplication layer, resulting in improved linearity and dynamic range in the InAlAs digital alloy structure multiplication layer.

As a result, with a conventional APD, the eye opening of PAM4 was non-uniform as shown in FIG. 23B, but with the DA-APD disclosed herein, the eye opening is uniform as shown in FIG. 23A, making it possible for TDECQ to satisfy the specified value. Therefore, when the DA-APD disclosed herein is used, an APD can be used in a PAM transceiver, which makes it possible to increase the transmission distance of optical signals and reduce the drive current of the transmitting laser.

<Effects of the 9th embodiment>
As described above, the multi-level intensity modulation transmitting/receiving device according to the ninth embodiment uses the DA-APD of the present disclosure as the semiconductor light receiving element, and thus has the effect of providing a multi-level intensity modulation transmitting/receiving device that can increase the transmission distance of an optical signal and reduce power consumption.

Embodiment 10.
Fig. 27 is a schematic diagram showing the configuration of a radio on fiber system 400 (Radio on fiber: RoF) according to a tenth embodiment. Fig. 28 is a schematic diagram showing the configuration of a radio on fiber system 450, which is a comparative example. The radio on fiber system 400 includes a light source 401, a transmission line 402 such as an optical fiber cable, a DA-APD 403 of the present disclosure, and an antenna 404.

In a radio-on-fiber system 400 according to the tenth embodiment, an analog electrical amplitude signal is input to a light source 401 such as an LD and converted into an optical amplitude signal. The converted optical amplitude signal is transmitted through an optical fiber cable, i.e., a transmission path 402. The transmitted optical amplitude signal is multiplied and converted into an electrical amplitude signal using a DA-APD 403 of the present disclosure. The converted electrical amplitude signal is transmitted to an antenna 404 and radiated as a radio wave signal.

The radio-on-fiber system 400 according to the tenth embodiment is capable of efficiently supplying signals to an antenna 404 that is located at a distance from an electrical signal source. In addition, since no analog-to-digital or digital-to-analog conversion is performed during transmission, the system has the advantage of being simple in configuration and consuming little power.

<Functions and Effects of Radio-on-Fiber System According to Tenth Embodiment>
In the comparative example radio-on-fiber system 450 shown in FIG. 28, if a signal is attenuated during transmission through the optical fiber cable, the signal cannot be amplified by the PD 406, and therefore a sufficient radio signal cannot be emitted from the antenna.

Furthermore, when a conventional APD is used, as shown in Figures 24A and 24B, an increase in the number of electrons and holes in the multiplication layer changes the electric field distribution, causing the multiplication factor to saturate and making it impossible to ensure the dynamic range. This causes problems not only in that a sufficient amplitude of the electrical signal cannot be obtained, but also in that the analog signal is distorted. As a result, it is difficult to apply a conventional APD to a radio-on-fiber system 450 such as the comparative example.

On the other hand, in the DA-APD 403 disclosed herein used in the radio-on-fiber system 400 according to embodiment 10, as shown in FIG. 26, the residence time Tdm of electrons and holes in the multiplication layer is short, so changes in the electric field distribution in the multiplication layer are suppressed. As a result, a response with excellent linearity is obtained over a wide dynamic range. In other words, since the DA-APD 403 disclosed herein multiplies the signal, the original signal can be reproduced and a large current amplitude can be obtained.

The multiplication factor of the DA-APD403 disclosed herein can be in the range of 1.2 to 10 times. However, as the multiplication factor increases, the signal becomes distorted, so it is desirable to use a multiplication factor in the range of 1.2 to 5 times. Also, considering that the multiplication factor is about 80% and not 100% due to the loss of the optical fiber, it is optimal to use a multiplication factor of 2 to 3 times to compensate for such losses.

<Effects of the Tenth Embodiment>
As described above, according to the radio-on-fiber system of the tenth embodiment, the DA-APD of the present disclosure is used to configure the radio-on-fiber system, which has the effect of making it possible to output a strong radio signal even if the optical transmission distance is long.

Embodiment 11.
29 is a schematic diagram illustrating a configuration of a digital coherent receiving apparatus 500 according to an eleventh embodiment. The digital coherent receiving apparatus 500 according to the eleventh embodiment is characterized in that it uses the DA-APD 505a of the present disclosure.

In digital coherent communication, optical signals with both phase and intensity modulated are polarization multiplexed and transmitted through optical fiber. In digital coherent receiving device 500, the optical signal input from optical fiber cable 501 is first polarized and separated by polarization separator 502. After polarization separation, each polarized signal light is input to 90-degree hybrid device 503a and 90-degree hybrid device 503b, respectively. Meanwhile, the laser light locally emitted from semiconductor laser 504 is separated into two signals with a phase shift of 90 degrees from each other.

The signal light and the laser light are multiplexed, and the signal light is further separated into orthogonal components (I, Q) and output. The four optical signals, i.e., the orthogonal I and Q components for each polarization, totaling four optical signals, are each incident on four balanced detectors 505 arranged in 90-degree hybrid devices 503a, 503b, each of which is made up of two DA-APDs 505a of the present disclosure connected in series as a pair. The electrical signal output from the balanced detector 505 is input to the DSP 506. The digital coherent receiving device 500 according to the eleventh embodiment has the above configuration.

<Operation of the digital coherent receiving device according to the eleventh embodiment>
FIG. 30A is a diagram illustrating waveforms of a digital coherent receiving device that is a comparative example, and FIG. 30B is a diagram illustrating waveforms of a digital coherent receiving device according to embodiment 11.

In conventional balanced detectors, a PD was used as a semiconductor light receiving element that receives signal light. On the other hand, when the DA-APD 505a disclosed herein is used, it is possible to multiply the signal, making it possible to suppress the local light. Furthermore, when a conventional APD is used, as shown in FIG. 25, an increase in the number of electrons and holes in the multiplication layer changes the electric field distribution, causing the multiplication factor to saturate and making it impossible to ensure a dynamic range. This causes problems not only in that a sufficient amplitude of the electrical signal cannot be obtained, but also in that the analog signal is distorted. As a result, as shown in FIG. 30A, in the comparative example, the interval between waveforms A1 and B1 becomes narrow, and the intensity signal of the constellation waveform is distorted, making it difficult to apply an APD.

On the other hand, in the DA-APD 505a disclosed herein, as shown in FIG. 26, the residence time Tdm of electrons and holes in the multiplication layer is short, so changes in the electric field distribution in the multiplication layer are suppressed. As a result, as shown in FIG. 30B, when the DA-APD 505a disclosed herein is used, the interval between waveform A and waveform B becomes wider, and a constellation waveform with excellent linearity over a wide dynamic range is obtained. In other words, even if the signal is multiplied by the APD, the original signal can be reproduced, and a large current amplitude can be obtained.

The multiplication factor of the DA-APD505a disclosed herein can be within the range of 1.2 to 10 times. However, as the signal becomes distorted as the multiplication factor increases, it is preferable to use a multiplication factor within the range of 1.2 to 5 times.

<Effects of Eleventh Embodiment>
As described above, according to the digital coherent receiving device of embodiment 11, the DA-APD of the present disclosure is applied as a semiconductor photodetector for receiving an optical signal, and therefore it is possible to reduce the drive current of the local light (laser), that is, to reduce the power consumption of the digital coherent receiving device.

Embodiment 12.
31 is a schematic diagram showing the configuration of a SPAD sensor (Single Photon Avalanche Diode) system according to embodiment 12. The SPAD sensor system 600 includes a photoelectron measurement circuit 601, a SPAD sensor 602 including the DA-APD of the present disclosure, and a quenching circuit 603.

The SPAD sensor system 600 uses the DA-APD of the present disclosure. Photons incident on the SPAD sensor system 600 are absorbed in the light absorption layer of the SPAD sensor 602, which is made of the DA-APD of the present disclosure, generating pairs of electrons and holes, and the electrons flow into the multiplication layer. An electric field about 10% higher than the avalanche breakdown electric field is applied to the multiplication layer.

This state is called the Geiger mode. In the Geiger mode, the electrons are multiplied by approximately ^106. The generated electrons flow as a current and flow into the photoelectron measurement circuit 601. If the current generated by one photon is known in advance, it is possible to count the number of photons incident on the SPAD sensor system 600.

FIG. 32A shows the waveform of a SAPD sensor system as a comparative example, and FIG. 32B shows the waveform of a SAPD sensor system according to embodiment 12. If an electric field equal to or greater than the avalanche breakdown electric field is continuously applied to the multiplication layer, excessive current will flow, so the voltage applied to the SPAD sensor 602 after detecting a photon is quickly reduced to weaken the electric field in the multiplication layer. This is called quenching. In other words, as shown in the comparison of the multiplication characteristics of the SPAD sensor in FIG. 32A and FIG. 32B, the voltage is reduced from B: Geiger mode voltage to A: quenching voltage to stop the chain multiplication, and then the voltage is increased again from A: quenching voltage to B: Geiger mode voltage to make it possible to receive incident photons with high sensitivity.

The quenching circuit 603 that controls the voltage is classified into a passive circuit and an active circuit. In a passive circuit, when a current flows due to photons incident on the SPAD sensor 602, a voltage drop occurs in the resistor connected in series to the SPAD sensor 602, and the voltage applied to the SPAD sensor 602 decreases. In other words, the quenching circuit 603 operates to repeatedly apply a voltage equal to or greater than the breakdown voltage and a voltage less than the breakdown voltage to the SPAD sensor 602.

<Actions and Effects of the SPAD Sensor System According to the Twelfth Embodiment>
The SPAD sensor system 600 according to the twelfth embodiment can be used not only for counting the number of photons but also as a highly sensitive semiconductor light receiving element. However, it is necessary to constantly repeat the voltage from B: Geiger mode voltage to A: quenching voltage. The repetition period is on the order of nanoseconds to microseconds. If the difference between A: quenching voltage and B: Geiger mode voltage can be reduced, the repetition period can be shortened and the response speed of the SPAD sensor system 600 can be increased.

In the passive quenching circuit 603, it is possible to reduce the resistance value connected in series to the SPAD sensor 602, which increases the response speed of the SPAD sensor 602. In addition, in the active quenching circuit 603, the voltage amplitude is reduced, which allows for simplification of the drive circuit and power saving, and also makes it possible to widen the response band.

The effect of using the InAlAs digital alloy structure of the present disclosure as a multiplication layer will be described below.
In the InAlAs digital alloy structure multiplication layer of the present disclosure, as shown in Figures 4A and 6B, the dead space length is long, so multiplication does not occur at low electric fields. However, as the electric field is increased, the dead space length becomes shorter, so the multiplication factor increases rapidly and leads to breakdown. In the APD of the InAlAs random alloy multiplication layer and the APD having the digital alloy InAlAs multiplication layer with a thick multiplication layer, if the voltage at which the dark current exceeds 10 μA is set as the breakdown voltage, the multiplication factor at 90% of the breakdown voltage exceeds 10 times. On the other hand, in the InAlAs digital alloy structure multiplication layer of the present disclosure, the multiplication factor at a voltage of 90% of the breakdown voltage is 10 times or less.

The voltage required for breakdown depends on the device structure, such as the thickness of the light absorption layer and the carrier concentration of the electric field buffer layer, so here we verify the effect using the quantifiable electric field of the multiplication layer. Note that above the reach-through voltage (up to 12 V), the voltage applied to the SPAD sensor 602 is proportional to the electric field of the multiplication layer.

Figure 33 shows the calculated difference between the quenching electric field and the Geiger mode electric field for each material constituting the multiplication layer. It can be seen that in the InAlAs digital alloy structure multiplication layer disclosed herein, the difference between the quenching electric field and the Geiger mode electric field for each multiplication layer is 170 kV/cm, which is exceptionally low. The electric field is 120 kV/cm lower than that of an InAlAs digital alloy structure multiplication layer having a superlattice structure similar to the InAlAs digital alloy structure multiplication layer disclosed herein but a layer thickness of 200 nm or more that has not been thinned.

<Effects of the twelfth embodiment>
As described above, according to the SPAD sensor system of the twelfth embodiment, the DA-APD of the present disclosure is used in the SPAD sensor, and therefore the difference between the quenching electric field and the Geiger mode electric field, that is, the applied voltage difference, can be reduced, thereby achieving the effect of obtaining a SPAD sensor system that enables an improved response band, a simplified quenching circuit, and reduced power consumption.

Embodiment 13.
Fig. 34 is a diagram showing the configuration of a LIDAR (Light Detection and Ranging: LiDAR) device according to embodiment 13. Fig. 35A is a diagram showing the received waveform of the APD of the LIDAR device which is a comparative example, and Fig. 35B is a diagram showing the received waveform of the APD of the LIDAR device according to embodiment 13.

The LIDAR device 700 includes a light source 701, a DA-APD 702 of the present disclosure, a TIA 703, and a ranging circuit 704.

The LIDAR device 700 calculates the distance to the object 705 by measuring the time it takes for the pulsed light emitted from the light source to hit the object 705 and return to the semiconductor light receiving element. An LD or the like is used as the light source 701. To measure long distances, the amount of light from the LD needs to be increased, but for eye safety reasons, there is an upper limit to the amount of light emitted from the LD. For this reason, it is necessary to increase the sensitivity of the semiconductor light receiving element. Therefore, in the LIDAR device 700 according to embodiment 13, the DA-APD 702 disclosed herein is used with high multiplication as the semiconductor light receiving element.

The detected light pulse is multiplied by the DA-APD 702 of the present disclosure and converted into a current pulse. It is then amplified by the TIA 703 and input to the distance measurement circuit 704, and the time when the intensity of the pulse signal exceeds a preset discrimination line is determined to be the arrival time, as shown in Figures 35A and 35B. The timing at which the light pulse is emitted from the light source 701 is input as a signal to the distance measurement circuit 704, and the distance to the object 705 can be calculated by multiplying the time difference between the two by the speed of light and dividing the result by 2.

<Actions and Effects of the LIDAR Device According to the Thirteenth Embodiment>
Since the reflectance of the object 705 is not necessarily high and the reflection direction varies, it is necessary to detect weak light with an APD. In a conventional APD, as shown in Fig. 35A, when a voltage is set to achieve high multiplication, the multiplication time becomes long and the current pulse width output from the APD becomes wide. In addition, the tunnel current increases, making it difficult to distinguish the light pulse.

On the other hand, in the multiplication layer of the DA-APD702 disclosed herein, as described in the explanation of the operation of embodiment 1, even at high multiplication of 20 times or more, the tunnel current does not increase, making it easy to identify weak light. Also, as shown in FIG. 26, the residence time in the multiplication layer is short, and therefore, as shown in FIG. 35B, a current pulse with a large peak intensity is obtained, resulting in high identification sensitivity. As a result, not only is it possible to measure the distance to distant objects, but the light output of the light source can be reduced, thereby saving power and further improving safety for the eyes.

<Effects of Thirteenth Embodiment>
As described above, according to the LIDAR device of embodiment 13, the reflected light from an object is received by the DA-APD of the present disclosure, which makes it possible to measure the distance to a distant object, reduces the power consumption of the light source, and provides a LIDAR device that is also safer for the eyes.

Although this disclosure describes various exemplary embodiments and examples, the various features, aspects, and functions described in one or more embodiments are not limited to application to a particular embodiment, but may be applied to the embodiments alone or in various combinations.

Therefore, countless variations not illustrated are contemplated within the scope of the technology of this disclosure. For example, this includes modifying, adding, or omitting at least one component, and even extracting at least one component and combining it with a component of another embodiment.

1 n-type InP substrate, 1a Fe-doped semi-insulating InP substrate, 2 n-type InAlAs buffer layer, 2a n-type InP conductive layer, 3, 45 InAlAs digital alloy structure multiplication layer, 4, 44 p-type InP field relaxation layer, 5, 43 i-type InGaAs light absorption layer, 6 i-type InAlGaAs/InAlAs graded layer, 7 p-type InP window layer, 8 p-type InGaAs contact layer, 11, 47 n-type InP window layer, 15 p-type diffusion region, 17 isolation groove, 18 surface protection film, 20 Fe-doped semi-insulating InP buried layer, 25 p-type InAlAs conductive layer, 31, 31a, 31 b, 50 n-type electrode, 32, 51 p-type electrode, 33 opening, 40 p-type InGaAlAs contact layer, 41 p-type InP conductive layer, 42 n-type InAlGaAs/InAlAs graded layer, 46 n-type InAlAs field adjustment layer, 48 n-type InAlAs conductive layer, 49 n-type InGaAs contact layer, 53 metal film, 90 incident light, 100, 110, 120, 130, 140, 150, 160, 170, 180, 190, 200 semiconductor light receiving element, 250, 260, 270 optical line termination device, 251, 261, 274 FEC, 252, 262, 273 ,303 Driver amplifier,253,263,272,304,401,701 Light source,254,264,271 WDM,255,265a,301,506 DSP,256,266a,302b ADC,258 APD,257,267,276 Burst TIA,265,278 CDR,266,277 Limiting amplifier,257a,267a,276a,703 TIA,268,275,305,403,505a,702 DA-APD,280,282,284 50G-PON system,302a DAC,310,501 Optical fiber cable cable, 306 Linear-TIA, 400, 450 Radio-on-fiber system, 402 Transmission line, 404 Antenna, 406 PD, 300 Multi-level intensity modulation transmitter/receiver, 500 Digital coherent receiver, 501 Optical fiber cable, 502 Polarization separator, 503a, 503b 90-degree hybrid, 504 Semiconductor laser, 505 Balanced detector, 600 SPAD sensor system, 601 Photoelectron measurement circuit, 602 SPAD sensor, 603 Quenching circuit, 700 Lidar device, 704 Distance measurement circuit, 705 Object

Claims (26)

An InP substrate;
an n-type semiconductor layer formed on the InP substrate;
a multiplication layer formed on the n-type semiconductor layer and having a digital alloy structure with a layer thickness of 40 nm or more and 170 nm or less;
a p-type electric field buffer layer formed on the multiplication layer;
an InGaAs light absorption layer formed on the p-type electric field buffer layer;
A semiconductor light receiving element comprising: An InP substrate;
a p-type semiconductor layer formed on the InP substrate;
an InGaAs light absorption layer formed on the p-type semiconductor layer;
a p-type electric field relaxation layer formed on the InGaAs light absorption layer;
a multiplication layer having a digital alloy structure formed on the p-type electric field buffer layer and having a layer thickness of 40 nm or more and 170 nm or less;
A semiconductor light receiving element comprising: The semiconductor light receiving element according to claim 1 or 2, characterized in that the multiplication layer has a digital alloy structure in which InAl layers and AlAs layers are alternately stacked. The semiconductor light receiving element according to any one of claims 1 to 3, characterized in that the thickness of the multiplication layer is 60 nm or more and 130 nm or less. The semiconductor light receiving element according to any one of claims 1 to 4, characterized in that the p-type electric field relaxation layer has a random alloy structure with a layer thickness of 10 nm or more and 70 nm or less. The semiconductor light receiving element according to claim 5, characterized in that the p-type electric field relaxation layer is made of InP or InAlAs. The semiconductor light receiving element according to any one of claims 1 to 4, characterized in that the p-type electric field relaxation layer has a digital alloy structure with a layer thickness of 10 nm or more and 130 nm or less. The semiconductor light receiving element according to claim 7, characterized in that the p-type electric field relaxation layer is made of an InAlAs digital alloy structure in which InAs layers and AlAs layers are alternately stacked. The semiconductor light receiving element according to any one of claims 1 to 8, characterized in that the p-type electric field buffer layer is doped with beryllium or zinc as a p-type impurity. The semiconductor light receiving element according to claim 1, characterized in that the n-type semiconductor layer is doped with silicon as an n-type impurity. The semiconductor light receiving element according to claim 1, characterized in that an i-type or n-type window layer is formed on the InGaAs light absorption layer, a p-type impurity diffusion region is formed in the window layer, and a p-type electrode is provided on the p-type impurity diffusion region. The semiconductor light receiving element according to claim 11, characterized in that the n-type semiconductor layer is an n-type conductive layer, and an n-type electrode is provided on a portion of the n-type conductive layer formed on the InP substrate that is partially exposed. The semiconductor light receiving element according to claim 12, characterized in that a separation groove is provided on the outer periphery of the p-type impurity diffusion region, the separation groove reaching the n-type conductive layer. The semiconductor light receiving element according to claim 11, characterized in that a light incidence area is provided on the back surface of the InP substrate opposite the p-type electrode. The semiconductor light receiving element according to claim 1, characterized in that a p-type contact layer having an outer periphery with an area smaller than that of the multiplication layer is formed on the InGaAs light absorption layer, and a p-type electrode is provided on the p-type contact layer. The semiconductor light receiving element according to any one of claims 1 to 15, characterized in that the dead space length is 50 nm or more and 90 nm or less. The semiconductor light receiving element according to any one of claims 1 to 15, characterized in that the ratio of the dead space length to the thickness of the multiplication layer is 29% or more and less than 100%. The semiconductor light receiving element according to any one of claims 1 to 15, characterized in that the ionization rate ratio k is 0.1 or less. A semiconductor light receiving element according to any one of claims 1 to 15, characterized in that the multiplication factor at a voltage that is 90% of the breakdown voltage is 10 times or less. A semiconductor light receiving element according to any one of claims 1 to 19,
an optical multiplexer/demultiplexer that inputs an optical signal to the semiconductor light receiving element;
an amplifier circuit for amplifying an electrical signal output from the semiconductor light receiving element;
a clock data recovery circuit connected to the amplifier circuit and configured to recover clock data from the amplified electrical signal;
a forward error correction circuit connected to the clock data recovery circuit for correcting an error in the clock data;
An optical line terminal comprising: A semiconductor light receiving element according to any one of claims 1 to 19,
an optical multiplexer/demultiplexer that inputs an optical signal to the semiconductor light receiving element;
an amplifier circuit for amplifying an electrical signal output from the semiconductor light receiving element;
an analog/digital conversion circuit connected to the amplifier circuit and converting the amplified electrical signal into a digital signal;
a digital signal processing circuit connected to the analog/digital conversion circuit and processing the digital signal;
a forward error correction circuit connected to the digital signal processing circuit for correcting errors in the digital signal;
An optical line terminal comprising: a light source that emits an analog modulated optical signal;
A semiconductor light receiving element according to any one of claims 1 to 19, which receives the optical signal that has been analog-modulated;
a transmission path for transmitting an analog electrical signal output from the semiconductor light receiving element to an antenna;
an antenna connected to the transmission line and configured to radiate the analog electrical signal as a radio wave signal;
A radio-on-fiber system comprising: A semiconductor light receiving element according to any one of claims 1 to 19, which receives a multi-level intensity modulated optical signal;
an amplifier circuit for amplifying an electrical signal output from the semiconductor light receiving element;
an analog/digital conversion circuit connected to the amplifier circuit and converting the amplified electrical signal into a digital signal;
a digital signal processing circuit connected to the analog/digital conversion circuit and processing the digital signal;
A multilevel intensity modulation transmitting/receiving device comprising: A semiconductor light receiving element according to any one of claims 1 to 19,
a polarization splitter that splits the polarization of the intensity- and phase-modulated polarization multiplexed optical signal;
a 90-degree hybrid that splits and combines the optical signals output from the polarization splitter;
a digital signal processing circuit connected to the 90-degree hybrid device and processing a digital signal;
A digital coherent receiving device comprising: A SPAD sensor constituted by the semiconductor light receiving element according to any one of claims 1 to 19;
a quenching circuit for repeatedly applying a voltage equal to or greater than a breakdown voltage and a voltage equal to or less than the breakdown voltage to the SPAD sensor;
an optoelectronic measurement circuit for measuring an electrical signal output from the SPAD sensor;
A SPAD sensor system comprising: A light source that emits light in a pulsed manner;
a semiconductor light receiving element according to claim 1 , which receives light emitted from the light source and reflected by an object;
an amplifier circuit for amplifying an electrical signal output from the semiconductor light receiving element;
a distance measuring circuit for calculating a distance based on the electrical signal amplified by the amplifier circuit;
A lidar device comprising:

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