WO2025074426A1 - System and method for improving linearity of a power amplifier - Google Patents

Abstract

The present disclosure relates to a system (108) and a method (700) for improving linearity of a power amplifier (PA) (312). The system (108) includes a processing engine (210) connected to an inverse coefficient estimation (ICE) module (212). The ICE module (212) is designed to capture one or more output data samples of the power amplifier (PA) (312), process the one or more output data samples to generate an error signal indicating power amplifier non-linearity, and estimate one or more parameters of a pre-distorter using a periodic prognostic error convergence (PPEC) technique based on the error signal. The estimation of pre-distorter one or more parameters involves estimating inverse coefficients using a time-varying forgetting factor λ. The ICE module (212) generates a pre-distorted input signal using the estimated one or more parameters and applies the pre-distorted input signal to the PA (312) for improving linearity of the power amplifier (PA) (312).

Description

SYSTEM AND METHOD FOR IMPROVING LINEARITY OF A POWER

AMPLIFIER

RESERVATION OF RIGHTS

[0001] A portion of the disclosure of this patent document contains material, which is subject to intellectual property rights such as, but are not limited to, copyright, design, trademark, Integrated Circuit (IC) layout design, and/or trade dress protection, belonging to Jio Platforms Limited (JPL) or its affiliates (hereinafter referred as owner). The owner has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure, as it appears in the Patent and Trademark Office patent files or records, but otherwise reserves all rights whatsoever. All rights to such intellectual property are fully reserved by the owner.

FIELD OF DISCLOSURE

The present disclosure relates generally to the field of wireless communication systems. More particularly, the present disclosure relates to systems and methods for improving linearity of a power amplifier (PA).

DEFINITIONS

[0002] As used in the present disclosure, the following terms are generally intended to have the meaning as set forth below, except to the extent that the context in which they are used to indicate otherwise.

[0003] The expression “Power Amplifier (PA)” refers to an electronic device that increases power of a signal, typically used in radio frequency (RF) transmission systems to amplify signals for broadcast or communication purposes.

[0004] The expression “Analog-to-Digital Converter (ADC)” refers to a device that converts an analog signal, such as a radio frequency or baseband signal, into a digital signal that can be processed by digital systems like FPGAs or microcontrollers.

[0005] The expression “Digital Pre-Distortion (DPD)” refers to a signal processing technique used to compensate for the non-linearities in power amplifiers (PAs). It involves pre-distorting an input signal to the PA to counteract the distortions that the PA introduces, resulting in a more linear output.

[0006] The expression “Pre-distorter” refers to a component in the DPD that applies a calculated distortion to the input signal before it reaches the power amplifier to counteract the amplifier’s inherent non-linearities.

[0007] The expression “Indirect Learning Architecture (ILA)” refers to a method used in digital pre-distortion where a pre-distorter is trained indirectly by comparing the input and output of the power amplifier. The architecture allows for adaptive adjustments of different parameters of PA based on feedback from the output of the PA.

[0008] The expression “Periodic Prognostic Error Convergence (PPEC)” refers to a technique/algorithm used within digital pre-distortion systems to periodically adjust the pre-distorter’ s parameters to minimize error and improve convergence, leading to more accurate compensation of the PA non-linearities.

[0009] The expression “Inverse Coefficient Estimation (ICE) Module” refers to a component within a digital pre-distortion system responsible for estimating inverse coefficients needed to linearize the output of the power amplifier.

[0010] The expression “Least Mean Square (LMS) Algorithm” refers to an adaptive filtering algorithm that minimizes the mean square error between the desired and actual output. It iteratively updates the filter coefficients to reduce the error, making it useful in applications like DPD.

[0011] The expression “Recursive Least Square (RLS) Algorithm” refers to an adaptive filtering algorithm that minimizes a weighted sum of the squared errors between the desired and actual output.

[0012] The expression “Forgetting Factor ( )” refers to a parameter used in recursive algorithms like RLS that determines how quickly past data is “forgotten” or de-emphasized. A smaller forgetting factor allows the algorithm to respond more quickly to changes in the system being modelled. [0013] The expression “Error Signal” refers to the difference between the desired output and the actual output of a system.

[0014] The expression “Baseband Signal” refers to the original signal that carries the information to be transmitted, typically at a lower frequency before being modulated to a higher frequency for transmission.

[0015] The expression “Post-distorter” refers to a component in the DPD that models the inverse of the PA’ s transfer function to identify the distortion caused by the amplifier, aiding in the adjustment of the pre-distorter.

[0016] The expression “Mean Squared Error (MSE)” refers to a measure of the average squared difference between the estimated and actual values. It is used in optimization algorithms to minimize error in prediction or estimation.

[0017] The expression “Normalized Output” refers to the output signal of a power amplifier after it has been adjusted by a linear gain to have a standard or reference amplitude, facilitating the comparison with other signals.

[0018] The expression “Adjacent Channel Leakage Ratio (ACER)” refers to signal power leaking from one channel into adjacent channels. It is critical in wireless communications to prevent interference with adjacent channels.

[0019] The expression “Error Vector Magnitude (EVM)” refers to a metric used to quantify the performance of a communication system by measuring the difference between the actual transmitted signal and the ideal signal. Lower EVM indicates better signal quality.

[0020] The expression “MIMO (Multiple Input Multiple Output)” refers to an advanced antenna technology used in wireless communications, particularly in 5G systems, where many antennas are employed at the base station to improve capacity, coverage, and energy efficiency.

[0021] The expression “Feedback Sample Power (FB Threshold)” refers to a predetermined power level used to evaluate the power of the feedback signal in the DPD system, ensuring that the feedback signal is within an acceptable range for accurate processing. [0022] The expression “Input Sample Power (IN Threshold)” refers to a predefined power level used to assess the input signal’s power in the DPD, ensuring that the input is within a suitable range for processing and comparison with the feedback signal.

[0023] The expression “Prediction Error” refers to the discrepancy between the predicted output of a model or system and the actual observed output.

[0024] The expression “FPGA (Field Programmable Gate Array)” refers to a type of digital integrated circuit that can be programmed after manufacturing to perform specific logical functions, making it versatile for various applications, including digital signal processing.

[0025] The expression “Out-of-Band (OOB) Emissions” refers to unwanted emissions or interference that occur outside the allocated bandwidth for a communication channel, potentially causing interference with adjacent channels.

[0026] The expression “Adaptive Convergence” refers to the process by which an adaptive algorithm iteratively adjusts its parameters to minimize the error signal, leading to the convergence of the system to an optimal or near-optimal state.

[0027] The expression “Delay Alignment” refers to the process of ensuring that the timing of signals, such as input and feedback signals in the DPD, is synchronized to allow for accurate error calculation and correction. The message “Delay alignment: passed” indicates successful alignment.

[0028] The expression “ACPR (Adjacent Channel Power Ratio)” refers to a metric used to measure the amount of power that leaks into adjacent channels relative to the power in the main channel of a communication signal. It is an important parameter in evaluating the performance of communication systems, especially in terms of spectral efficiency and interference.

[0029] The expression “EVM (Error Vector Magnitude)” refers to a key performance metric used to measure the quality of digital communication systems. It quantifies the deviation of the received signal from the ideal or expected signal. EVM is particularly important in evaluating the accuracy of the signal transmission and reception in digital communication systems. [0030] The expression “Root Mean Square (RMS) algorithm” refers to an approach used to estimate system parameters by minimizing the mean square error between desired and actual signal outputs.

[0031] The expression “corresponding sample points” refers to the specific instances in time at which both the input signal to the power amplifier and the output signal from the power amplifier are sampled. These points are aligned in time so that each input sample has a directly related output sample, enabling accurate comparison or error calculation between the two signals.

[0032] The expression “output data samples” refers to discrete values representing the amplified signal produced by the PA after passing through the predistorter. These samples are used to evaluate the effectiveness of the pre-distortion process and to identify any remaining non-linear distortions.

[0033] The expression “power amplifier non-linearity” refers to the deviation of the output power of the PA from a linear relationship with its input power. This non-linearity can introduce distortion in the transmitted signal, reducing signal quality and interference with other users.

[0034] The expression “parameters of a pre-distorter” refers to the numerical values that define the behaviour and performance of the pre-distortion module.

[0035] These definitions are in addition to those expressed in the art.

BACKGROUND OF DISCLOSURE

[0036] The following description of related art is intended to provide background information pertaining to the field of the disclosure. This section may include certain aspects of the art that may be related to various features of the present disclosure. However, it should be appreciated that this section be used only to enhance the understanding of the reader with respect to the present disclosure, and not as admissions of prior art.

[0037] Power amplifiers (PAs) are known to cause non-linear distortion in electronic applications. These PAs are also among power hungry devices in numerous industrial electronic applications, for example, in magnetic bearing, digital video-broadcasting, radio frequency (RF) transceivers, and dual- band/wideband wireless communications. Specifically, in wireless communications, to enhance the spectral efficiency in modem high-speed wireless communication systems, different non-constant envelope modulation schemes, such as orthogonal frequency division multiple access in 3rd Generation Partnership Project (3GPP) long-term evolution (LTE), wideband code division multiple access (WCDMA) and 5th Generation New Radio (5G NR), are normally employed. However, these signals usually have a high Peak-to -Average Power Ratio (PAPR). It becomes more severe for 5G NR standard where instantaneous bandwidth increases up to 100MHz.

[0038] High PAPR leads to a requirement of a higher power rating of PA. Consequently, it raises cost and heat dissipation requirements in PA. To reduce it, a crest factor reduction (CFR) technique is used which reduces crest factor from 11- 12 dB to 7-8 dB to operate the PA near saturation point and consequently enhances an average efficiency of the PA. This requires a large level of power back-off to maintain a high linearity of the transmitted signals, ultimately degrading the power efficiency of the PA. However, due to lower back-off operation, the nonlinearity is drastically degraded and various analog and digital techniques are employed such that feed-forward, envelope tracking, LINC, analog distortion, etc. to compensate it. But out of all these techniques, the digital pre-distortion technique has been widely accepted by many designers due to its ease of adaptation in changing operating conditions such as process, voltage, and thermal (PVT) variation, low to high power, and aging. to compensate it, digital pre-distortion (DPD) is employed in the system. The DPD is implemented before the PA as a baseband non-linear component that is the inverse of the nonlinearity of the PA.

[0039] The DPD is a technique to increase linearity or compensate for nonlinearity in power amplifiers. DPD is a cost-effective linearization technique which provides improved linearity, better efficiency, and complements with power amplifiers. The DPD applies inverse distortion, using a pre-distorter, at an input signal of the PA to cancel distortion generated by the PA. The inverse coefficients are generated by a Volterra Model. The coefficients may have to be updated according to the changes in the PA characteristics such as power, ambient temperature, etc. For a system with high bandwidths such as in 5G NR system, indirect learning architecture (ILA) is used in generating the inverse coefficients. The coefficients are generated in an iterative manner. There are different types of ILA adaptive algorithms present. The effectiveness of the DPD is based on how fast the system can realize the coefficients. In systems with higher bandwidths and low latency processing, the errors due to nonlinearity are very high, which needs to be effectively tackled.

[0040] There is, therefore, a need in the art to provide a method and a system that can overcome the shortcomings of the existing prior arts.

OBJECTS OF THE PRESENT DISCLOSURE

[0041] Some of the objects of the present disclosure, which at least one embodiment herein satisfies are as listed herein below.

[0042] An object of the present disclosure is to provide a system and a method for an indirect learning architecture (ILA) based digital pre-distortion (DPD) with a faster and more effective error convergence algorithm.

[0043] The object of the present disclosure is to provide the system and the method that provide faster error convergence, leading to a reduction in non-linear distortions due to power amplifiers.

[0044] Another object of the present disclosure is to provide the system and the method that leads to the rapid convergence of the non-linear distortion by using the estimated inverse coefficients.

[0045] Yet another object of the present disclosure is to implement the ILA- based DPD system for a power amplifier having an inverse coefficient estimation module comprising the PPEC unit in Field-Programmable Gate Arrays (FPGA), which is part of the 5G New Radio (NR) transmitter chain design.

[0046] Other objects and advantages of the present disclosure will be more apparent from the following description, which is not intended to limit the scope of the present disclosure.

SUMMARY [0047] In an exemplary embodiment, the present invention discloses a system for improving linearity of a power amplifier (PA), the system comprising a processing engine coupled to an inverse coefficient estimation (ICE) module configured to capture, by the ICE module, one or more output data samples from the PA, process, by the ICE module, the one or more output data samples to generate an error signal indicative of power amplifier non-linearity, estimate, by the ICE module, one or more parameters of a pre-distorter using a periodic prognostic error convergence (PPEC) technique based on the error signal, wherein estimating the one or more parameters of a pre-distorter comprises estimating inverse coefficients using a time -varying forgetting factor X, generate, by the ICE module, a predistorted input signal using the estimated one or more parameters and apply, by the ICE module, the pre-distorted input signal to the PA.

[0048] In some embodiments, the one or more output data samples of the PA are captured using an Analog-to-Digital Converter (ADC)

[0049] In some embodiments, the error signal is generated by calculating a difference between a desired output signal and the one or more output data samples of the PA at one or more corresponding sample points.

[0050] In some embodiments, the time- varying forgetting factor Z. is defined between 0 = 0.98 and X (0) = 0.94.

[0051] In some embodiments, the inverse coefficients are provided to a post inverse unit to generate the pre-distorted input signal.

[0052] In some embodiments, the pre-distorted input signal is an input signal provided to the ICE module.

[0053] In an exemplary embodiment, a method for improving linearity of a power amplifier (PA), the method includes capturing, by an inverse coefficient estimation (ICE) module, one or more output data samples from the PA, processing, by the ICE module, the one or more output data samples to generate an error signal indicative of power amplifier non-linearity, estimating, by the ICE module, one or more parameters of a pre-distorter using a periodic prognostic error convergence (PPEC) technique based on the error signal, wherein estimating the one or more parameters of a pre-distorter comprises estimating inverse coefficients using a time- varying forgetting factor , generating, by the ICE module, a pre-distorted input signal using the estimated one or more parameters and applying, by the ICE module, the pre-distorted input signal to the PA.

[0054] In an exemplary embodiment, user equipment (UE) communicatively coupled with a network is disclosed. The UE includes capturing, by an inverse coefficient estimation (ICE) module, one or more output data samples from the PA, processing, by the ICE module, the one or more output data samples to generate an error signal indicative of power amplifier non-linearity, estimating, by the ICE module, one or more parameters of a pre-distorter using a periodic prognostic error convergence (PPEC) technique based on the error signal, wherein estimating the one or more parameters of a pre-distorter comprises estimating inverse coefficients using a time- varying forgetting factor , generating, by the ICE module, a pre-distorted input signal using the estimated one or more parameters and applying, by the ICE module, the pre-distorted input signal to the PA.

[0055] In an exemplary embodiment, a computer program product comprising a non-transitory computer-readable medium comprising instructions that, when executed by one or more processors, cause the one or more processors to perform a method for improving linearity of a power amplifier (PA), the method comprises of capturing, by an inverse coefficient estimation (ICE) module, one or more output data samples from the PA, processing, by the ICE module, the one or more output data samples to generate an error signal indicative of power amplifier non-linearity, estimating, by the ICE module, one or more parameters of a pre- distorter using a periodic prognostic error convergence (PPEC) technique based on the error signal, wherein estimating the one or more parameters of a pre-distorter comprises estimating inverse coefficients using a time -varying forgetting factor , generating, by the ICE module, a pre-distorted input signal using the estimated one or more parameters and applying, by the ICE module, the pre-distorted input signal to the PA.

[0056] The foregoing general description of the illustrative embodiments and the following detailed description thereof are merely exemplary aspects of the teachings of this disclosure and are not restrictive.

BRIEF DESCRIPTION OF DRAWINGS [0057] The accompanying drawings, which are incorporated herein, and constitute a part of this disclosure, illustrate exemplary embodiments of the disclosed methods and systems in which like reference numerals refer to the same parts throughout the different drawings. Components in the drawings are not necessarily to scale, emphasis instead being placed upon clearly illustrating the principles of the present disclosure. Some drawings may indicate the components using block diagrams and may not represent the internal circuitry of each component. It will be appreciated by those skilled in the art that disclosure of such drawings includes the disclosure of electrical components, electronic components or circuitry commonly used to implement such components.

[0058] FIG. 1 illustrates an exemplary architecture for improving the linearity of a power amplifier (PA) in accordance with embodiments of the present disclosure.

[0059] FIG. 2 illustrates an exemplary block diagram of a system for improving linearity of the PA, in accordance with embodiments of the present disclosure.

[0060] FIG. 3 illustrates an exemplary architecture of a DFE of a 5G NR transmitter lineup, in accordance with embodiments of a prior art.

[0061] FIG. 4 shows a detailed schematic of a conventional adaptive DPD, in accordance with embodiments of the prior art.

[0062] FIG. 5 is an exemplary implementation of a system architecture for improving linearity of the PA, in accordance with embodiments of the present disclosure.

[0063] FIG. 6A - FIG. 6B illustrates a flow chart illustrating data and control flow, according to one embodiment of the present disclosure.

[0064] FIG. 7 is an exemplary implementation of a method for improving linearity of the PA, in accordance with embodiments of the present disclosure.

[0065] FIG. 8 is a plot illustrating error convergence of conventional recursive least square algorithm (RLS) algorithm, in accordance with embodiments of the present disclosure. [0066] FIG. 9 is a plot illustrating error convergence of PPEC technique, according to one embodiment of the present disclosure.

[0067] FIG. 10 is a plot illustrating an Adjacent Channel Power Ratio (ACPR) comparison without DPD, PPEC technique and RLS Algorithm after a single iteration of the 8K samples, according to one embodiment of the present disclosure.

[0068] FIG. 11 illustrates an exemplary computer system in which or with which the system may be implemented, in accordance with an embodiment of the present disclosure.

[0069] The foregoing shall be more apparent from the following more detailed description of the disclosure.

LIST OF REFERENCE NUMERALS

100 - Network Architecture

102-1, 102-2... 102-N - Users

104-1, 104-2. . . 104-N, User equipments

106 - Network

108 - System

202 - One or more processor(s)

204 - Memory

206 - Interface

210 - Processing engine

212, 410 - Inverse coefficient estimation (ICE) module

220 - Database

300 - System architecture of prior art

302 - Physical layer output (PHY out)

304 - Digital up converter

306 - Crest factor reduction (CFR) module

308 - Digital pre-distorter

310 - Radio frequency digital-to-analog converter (RFDAC)

312 - Power amplifier (PA)

316 - Bandpass filter (BPF) 14 - Radio frequency analog-to-digital converter (RFADC) 00 - Flow diagram of prior art 04 - Pre-distorter 06 - Post-distorter 08 - Linear gain (GO) 00 - Digital pre-distortion (DPD) architecture 02 - Programmable logic (PL) section

504 - Processing system (PS) section

506 - Pre-inverse unit

508 - Data collection unit

510 - Inverse coefficient updation and mapping unit

512 - Power measurement unit

513 - Control interface

514 - Post inverse unit

516 - Data acceptance and alignment unit

520 - Adaptive control unit

522 - Control debug and monitor unit

550 - Digital pre-distortion (DPD)

600 - Flow diagram

700 - Flow diagram

800 - Plot

900 - Plot

1000 - Plot

1100 - Exemplary computer system

1110 - External storage device

1120 - Bus

1130 - Main memory

1140 - Read only memory

1150 - Mass storage device

1160 - Communication port

1170 - Processor

DETAILED DESCRIPTION OF DISCLOSURE [0070] In the following description, for the purposes of explanation, various specific details are set forth in order to provide a thorough understanding of embodiments of the present disclosure. It will be apparent, however, that embodiments of the present disclosure may be practiced without these specific details. Several features described hereafter can each be used independently of one another or with any combination of other features. An individual feature may not address all of the problems discussed above or might address only some of the problems discussed above. Some of the problems discussed above might not be fully addressed by any of the features described herein.

[0071] The ensuing description provides exemplary embodiments only, and is not intended to limit the scope, applicability, or configuration of the disclosure. Rather, the ensuing description of the exemplary embodiments will provide those skilled in the art with an enabling description for implementing an exemplary embodiment. It should be understood that various changes may be made in the function and arrangement of elements without departing from the spirit and scope of the disclosure as set forth.

[0072] Specific details are given in the following description to provide a thorough understanding of the embodiments. However, it will be understood by one of ordinary skill in the art that the embodiments may be practiced without these specific details. For example, circuits, systems, networks, processes, and other components may be shown as components in block diagram form in order not to obscure the embodiments in unnecessary detail. In other instances, well-known circuits, processes, algorithms, structures, and techniques may be shown without unnecessary detail in order to avoid obscuring the embodiments.

[0073] Also, it is noted that individual embodiments may be described as a process which is depicted as a flowchart, a flow diagram, a data flow diagram, a structure diagram, or a block diagram. Although a flowchart may describe the operations as a sequential process, many of the operations can be performed in parallel or concurrently. In addition, the order of the operations may be re-arranged. A process is terminated when its operations are completed but could have additional steps not included in a figure. A process may correspond to a method, a function, a procedure, a subroutine, a subprogram, etc. When a process corresponds to a function, its termination can correspond to a return of the function to the calling function or the main function.

[0074] The word “exemplary” and/or “demonstrative” is used herein to mean serving as an example, instance, or illustration. For the avoidance of doubt, the subject matter disclosed herein is not limited by such examples. In addition, any aspect or design described herein as “exemplary” and/or “demonstrative” is not necessarily to be construed as preferred or advantageous over other aspects or designs, nor is it meant to preclude equivalent exemplary structures and techniques known to those of ordinary skill in the art. Furthermore, to the extent that the terms “includes,” “has,” “contains,” and other similar words are used in either the detailed description or the claims, such terms are intended to be inclusive in a manner similar to the term “comprising” as an open transition word without precluding any additional or other elements.

[0075] Reference throughout this specification to “one embodiment” or “an embodiment” or “an instance” or “one instance” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure. Thus, the appearances of the phrases “in one embodiment” or “in an embodiment” in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0076] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. [0077] Unless the context otherwise requires any other specific meaning in the entire description, the term “release” and their grammatical variants may also indicate, but not limited to, the activity of clearing, deleting, erasing, cancelling, discarding, freeing, removing, overriding, omitting, aborting, relinquishing, overwriting, or renouncing the unused application context for new upcoming procedure(s) in a network and specifically an IMS network.

[0078] Power amplifiers (PAs) are known to cause non-linear distortion in electronic applications. The PAs are also among devices in numerous industrial electronic applications e.g., in magnetic bearing, digital video-broadcasting, radio frequency (RF) transceivers, and dual-band/wideband wireless communications. The PA characteristics change with time due to process, supply voltage, and temperature (PVT) variations. To track time- varying changes in the PA characteristics, an adaptive digital pre-distortion (DPD) technique with cost- effective learning architectures has become one of the most preferred choices. Commonly and widely used learning architecture for pre-distortion (PD) parameter identification is indirect learning architecture (ILA). An adaptive ILA is often used to identify the PD parameters in RF PAs. The existing DPD systems are mainly used for scenarios where the PAs operate under relatively stable conditions, e.g., the PA characteristics remain almost constant over time. As the PA characteristics change over time, researchers developed the adaptive ILA using least mean squares (LMS) for linearizing PAs. The main advantage of LMS is its simple implementation. However, it provides inaccurate estimation and has slow convergence since increasing the step size parameter leads to instability problems. Moreover, it is also sensitive to the scaling of the input signal, making it very hard to choose a proper step size.

[0079] To obtain faster convergence of the adaptation, the adaptive ILA using recursive least squares (RLS) was proposed. It is worth noting that the choice of forgetting factor is often essential to make a good trade-off between convergence and accuracy. For the RLS, a decrease in the forgetting factor leads to its sensitivity to noise and a larger fluctuation of parameter estimates, resulting in inefficient linearization performance. With the continuous development of wideband communication systems, more efficient linearization methods for RF PAs are desired to meet the emerging requirement of highly linear PAs in these systems. [0080] The DPD is a technique to increase linearity or compensate for nonlinearity in Power Amplifiers (PAs). The PAs are critical in communication systems, and it is crucial to improve their efficiency and overall performance. The DPD is a cost-effective linearization technique that provides improved linearity and better efficiency and enables the full advantages of the PA.

[0081] The DPD applies inverse distortion, using a pre-distorter, to the predistorted input signal of the PA to cancel the distortion generated by the power amplifier. For successful DPD functioning, the PA’s characteristics must be accurately known and effectively implemented. Studies have shown improvements of up to 40% in PA efficiency used in wireless base stations.

[0082] To increase the linearity of the PAs, the DPD generates the inverse coefficients that can suppress the non-linear effect of the PA. The inverse coefficients are generated by a Volterra Model. The Volterra models are used to represent the non-linear and memory-based PA models. In dynamic DPDs, the coefficients needed to be updated according to the changes in the PA characteristics such as power, ambient temperature, etc. For a system with high bandwidths, such as in a 5G NR system, the realization of the coefficients should be efficient.

[0083] In some aspects, indirect learning architecture (ILA) generates the inverse coefficients. The coefficients are generated iteratively. Different types of ILA adaptive algorithms are known. The effectiveness of the DPD depends on how fast the system can realize the coefficients. Developing an algorithm with faster error convergence and stability is critical in DPD development.

[0084] Accordingly, there is a need for systems and methods to provide faster error convergence and stability in the DPDs.

[0085] The present disclosure aims to overcome the above-mentioned problems in this field of technology by providing a system and a method for indirect learning architecture (ILA) based Digital Pre-Distortion (DPD).

[0086] The various embodiments throughout the disclosure will be explained in more detail with reference to FIG. 1- FIG. 11. [0087] Referring to FIG. 1, the architecture (100) may include one or more computing devices or user equipments (104-1, 104-2. . . 104-N) associated with one or more users (102-1, 102-2. . . 102-N) in an environment. A person of ordinary skill in the art will understand that one or more users (102-1, 102-2... 102-N) may be individually referred to as the user (102) and collectively referred to as the users (102). Similarly, a person of ordinary skill in the art will understand that one or more user equipments (104-1, 104-2. .. 104-N) may be individually referred to as the user equipment (104) and collectively referred to as the user equipment (104). A person of ordinary skill in the art will appreciate that the terms “computing device(s)” and “user equipment” may be used interchangeably throughout the disclosure. Although at least three user equipments (104) are depicted in FIG. 1, however any number of the user equipments (104) may be included without departing from the scope of the ongoing description.

[0088] In an embodiment, the user equipment (104) may include, but is not limited to, a handheld wireless communication device (e.g., a mobile phone, a smart phone, a phablet device, and so on), a wearable computer device(e.g., a headmounted display computer device, a head-mounted camera device, a wristwatch computer device, and so on), a global positioning system (GPS) device, a laptop computer, a tablet computer, or another type of portable computer, a media playing device, a portable gaming system, and/or any other type of computer device with wireless communication capabilities, and the like. In an embodiment, the user equipment (104) may include but is not limited to, any electrical, electronic, electromechanical, or an equipment, or a combination of one or more of the above devices such as virtual reality (VR) devices, augmented reality (AR) devices, laptop, a general-purpose computer, desktop, personal digital assistant, tablet computer, mainframe computer, or any other computing device, where the user equipment (104) may include one or more in-built or externally coupled accessories including, but not limited to, a visual aid device such as a camera, an audio aid, a microphone, a keyboard, and input devices for receiving input from the user (102) or the entity such as a touchpad, touch-enabled screen, electronic pen, and the like. A person of ordinary skill in the art will appreciate that the user equipment (104) may not be restricted to the mentioned devices and various other devices may be used. [0089] In an embodiment, the user equipment (104) may include smart devices operating in a smart environment, for example, an internet of things (loT) system. In such an embodiment, the user equipment (104) may include but is not limited to, smartphones, smart watches, smart sensors (e.g., mechanical, thermal, electrical, magnetic, etc.), networked appliances, networked peripheral devices, networked lighting system, communication devices, networked vehicle accessories, networked vehicular devices, smart accessories, tablets, smart television (TV), computers, smart security system, smart home system, other devices for monitoring or interacting with or for the users (102) and/or entities, or any combination thereof. A person of ordinary skill in the art will appreciate that the user equipment (104) may include, but is not limited to, intelligent, multi-sensing, network-connected devices that can integrate seamlessly with each other and/or with a central server or a cloud-computing system or any other device that is network-connected.

[0090] Referring to FIG. 1, the user equipment (104) may communicate with a system (108) through a network (106). In an embodiment, the network (106) may include at least one of a Fifth Generation (5G) network, 6G network, or the like. The network (106) may enable the user equipment (104) to communicate with other devices in the architecture (100) and/or with the system (108). The network (106) may include a wireless card or some other transceiver connection to facilitate this communication. In another embodiment, the network (106) may be implemented as or include any of a variety of different communication technologies such as a wide area network (WAN), a local area network (LAN), a wireless network, a mobile network, a Virtual Private Network (VPN), the Internet, the Public Switched Telephone Network (PSTN), or the like. In an embodiment, each of the UE (104) may have a unique identifier attribute associated therewith. In an embodiment, the unique identifier attribute may be indicative of Mobile Station International Subscriber Directory Number (MSISDN), International Mobile Equipment Identity (IMEI) number, International Mobile Subscriber Identity (IMSI), Subscriber Permanent Identifier (SUPI) and the like.

[0091] FIG. 2 illustrates a block diagram (200) of the system (108) for improving linearity of the PA in accordance with embodiments of the present disclosure. [0092] In an aspect, the system (108) may include one or more processor(s) (202). The one or more processor(s) (202) may be implemented as one or more microprocessors, microcomputers, microcontrollers, edge or fog microcontrollers, digital signal processors, central processing units, logic circuitries, and/or any devices that process data based on operational instructions. Among other capabilities, the one or more processor(s) (202) may be configured to fetch and execute computer-readable instructions stored in a memory (204) of the system (108). The memory (204) may be configured to store one or more computer- readable instructions or routines in a non-transitory computer-readable storage medium, which may be fetched and executed to create or share data packets over a network service. The memory (204) may include any non-transitory storage device including, for example, volatile memory such as Random Access Memory (RAM), or non-volatile memory such as Erasable Programmable Read-Only Memory (EPROM), flash memory, and the like.

[0093] Referring to FIG. 2, the system (108) may include an interface(s) (206). The interface(s) (206) may include a variety of interfaces, for example, interfaces for data input and output devices, referred to as VO devices, storage devices, and the like. The interface(s) (206) may facilitate communication to/from the system (108). The interface(s) (206) may also provide a communication pathway for one or more components of the system (108). Examples of such components include but are not limited to, processing unit/engine(s) (210) and a database (220).

[0094] In an embodiment, the processing unit/engine(s) (210) may be implemented as a combination of hardware and programming (for example, programmable instructions) to implement one or more functionalities of the processing engine(s) (210). In the examples described herein, such combinations of hardware and programming may be implemented in several different ways. For example, the programming for the processing engine(s) (210) may be processorexecutable instructions stored on a non-transitory machine-readable storage medium, and the hardware for the processing engine(s) (210) may include a processing resource (for example, one or more processors), to execute such instructions. In the present examples, the machine-readable storage medium may store instructions that, when executed by the processing resource, implement the processing engine(s) (210). In such examples, the system (108) may include the machine-readable storage medium storing the instructions and the processing resource to execute the instructions, or the machine-readable storage medium may be separate but accessible to the system (108) and the processing resource. In other examples, the processing engine(s) (210) may be implemented by electronic circuitry.

[0095] In an embodiment, the database (220) may include data that may be either stored or generated as a result of functionalities implemented by any of the components of the processor (202) or the processing engines (210). In an embodiment, the database (220) may be separate from the system (108). In an embodiment, the database (220) may be indicative of including, but not limited to, a relational database, a distributed database, a cloud-based database, or the like.

[0096] In an embodiment, the processing engine (210) may include an ICE module (212). The ICE module (212) may receive an output from a DPD and an output from a PA as feedback dataset and processes the outputs using an inverse coefficient estimation algorithm. The ICE module (212) may use a periodic prognostic error convergence (PPEC) technique. This PPEC technique derives DPD coefficients. The ICE module (212) may trigger and execute the PPEC technique for deriving and fine-tuning of the DPD coefficients.

[0097] In an embodiment, for single-band FR2 radios, the application of DPD may not be critical compared to that of the FR1 counterpart. On one hand, the contribution of PAs to the total DC power consumption in a FR2 BS is much reduced. This is because more antenna elements are added to increase the directivity of the antenna array to combat against the high path loss occurred at FR2, which in turn requires smaller power to feed each antenna element, and thus small-power PA per Tx is sufficient. On the other hand, the requirement on ACER for FR2 BSs is not as large, i.e. 24 - 28dBc (by means of OTA measurement), compared to that applied to FR1 BSs, i.e. 45dBc due to the beamforming and propagation environment. This somewhat alleviates the essential need of high-linearity PAs on meeting required ACLR. Therefore, the DPD in single -band FR2 BSs is expected to provide a little gain in terms of improving power efficiency and meeting the ACLR requirement. Furthermore, the analog and hybrid beamforming, which are predominantly used in FR2 radios, also pose challenges for DPD implementation. With hundreds to thousands of PAs and higher operating bandwidths for FR2 radio, simply utilizing a similar DPD architecture as in FR1 would cost extra for RF hardware design and power consumption, while it may be infeasible to deploy single DPD for every PA in the analog/hybrid beamforming phased array since several or all analog chains essentially share one digital path. The DPD algorithms would also have more demands on the bandwidth of feedback receiver/ ADC and BB signal processing resources, which are scaled with the size of bandwidth to be linearized. These limited-gain and implementation-challenge factors make the similar DPD implementations as in FR1 less attractive to the FR2 single-band BS.

[0098] In an embodiment, any individual variation in PA would affect the performance of the linearization so the peak linearization performance is likely to be lower than that of a one-DPD-per-PA system. Whilst the design of PA is likely to be identical there are a number of factors which could change their performance:

• Temperature - the location of each PA in the array (and the silicon) may mean different transistors are at different temperature (depending on the number of neighbouring devices for example) so the temperature of each junction may be different.

• Unit to unit variation - whilst some transistors may all be on a single piece of silicon and variation on a single bit of silicon may be small if multiple devices are used (8 or 16 per device may be more usual) so there will be unit to unit variation across the potential 128 paths

• Output match variation - PA performance is very dependent on the load it is working into, again all output match circuits are likely to be designed identically but will vary based on a number of factors:

• Unit to unit of components

• Antenna unit to unit

Antenna isolation and load pulling from nearby antenna (and signals) Despite these issues useful linearization of an FR2 systems can be achieved and may become more common as technology improves.

[0099] In an embodiment, antenna array and TRXs in FR2 radios are desired to be tightly integrated in which RF filter is preferably omitted after the PA. Since a multi-band. RIB essentially needs to transmit multiple -band signals concurrently, the nonlinearity of PAs will likely cause intermodulation (IM) distortion. It would be highly challenging to manage the PAs in multiband RIB not to operate in the nonlinearity power region. Particularly, the varying nonlinearity behaviours of the PAs, which causes by the nonlinear interaction between antenna array and the PAs as discussed above, also inherit to the FR2 multi-band RIB. Such issues would be expected to be more complicated in the multiband use cases than in single -band ones due to higher requirements on matching load impedance of PAs covering multiband/wideband.

[00100] FIG. 3 illustrates an exemplary architecture (300) of a downlink digital front end (DFE) of a 5G New Radio (NR) transmitter lineup, known in the art.

[00101] The architecture (300) includes a PHY output (302), a digital up converter (304), a crest factor reduction (CFR) module (306), a digital pre-distorter (308), an RF digital to analog converter (RFDAC) (310), a power amplifier (PA) (312), a feedback RF analog to digital converter (RFADC) (114) and a bandpass filter (316). A detailed description of the DFE is not provided herein as the functioning of DFE is well-known in the art. The digital up converter (304) receives signal input from the PHY output (302) and performs digital up conversion (DUC), which includes converting baseband samples into intermediate frequency (IF) samples. The converted samples are provided to the CFR module (306) which reduces a peak-to-average power ratio (PAPR) of the samples. As described, high PAPR is undesirable for communication systems. The samples are provided to the digital pre-distorter (308), which applies the digital pre-distortion (DPD) technique to increase linearity or compensate for nonlinearity in the PA (312). The digital pre- distorter (308) applies feedback from the PA (312) based on the non-linear distortion identified at the output at the PA (312) by increasing the linearity by compensating the nonlinearity of the PA (312). The RFADC (314) converts analog signals to digital ones. The RFDAC (310) receives the output from the digital predistorter (308) and converts the digital samples to analog samples to be fed to the PA (312). The output of the PA (312) is received by the BPF (316) for transmission.

[00102] FIG. 4 shows a detailed schematic of an adaptive DPD (400). The DPD (400) includes a pre-distorter (404), a post-distorter (406), a linear gain (408), and an Inverse Coefficient Estimation (ICE) module (410). The pre-distorter (404) is input with a baseband signal U(n), which generates a signal X(n) that is provided as an input to the PA (312). An output Y(n) from the PA (312) is normalized by the linear gain (GO) (408), producing a normalized output z(n), i.e., z(n) = Y(n) /GO. The linear gain (408) is a constant multiplier applied to the output Y (n) to normalize it or bring it to a desired amplitude level and scale the output Y(n) to ensure that it matches a predefined linear behaviour. The purpose of applying the linear gain (408) is to compensate for any variations in signal amplitude due to non-linearities in the PA (312). For example, in an audio amplifier system, suppose the output is measured to be 2 volts when it should ideally be 1 volt for the given input. To correct this, the linear gain G0=2 would be applied to reduce the amplitude by half, bringing the output back to the desired 1-volt level. The post distorter (406) (also referred to as a training block) is configured to identify an inverse transfer function of the PA (312). The post distorter (406) receives z(n) and generates an output Z_p(n). One or more parameters for the post-distorter (PD) (406) are identified by minimizing error signal E(n) = X(n) - Zp(n) using the ICE module (410). The ICE module (410) includes adaptive convergence techniques to minimize errors and to obtain one or more estimation parameters that may be referred to as inverse coefficient parameters. In some examples, the pre-distorter (404) and the postdistorter (406) are substantially similar. Thus, when the post-distorter (406) coefficients are identified, they are implemented in the pre-distorter (404). In implementations, the process above is continuously performed till indirect learning architecture (ILA) linearization has converged. The cascaded pre-distorter (404) and PA (312) behave linearly at convergence. The aforementioned DPD can be implemented through various means.

[00103] An exemplary implementation of the ILA based DPD in a Field Programmable Gate Arrays (FPGAs) is explained in FIG. 5, which is a part of the 5G NR transmitter chain design. [00104] FIG. 5 shows an exemplary implementation of a system architecture (500) for improving the linearity of the PA (312). The system architecture (500) is implemented in a programmable logic (PL) section (502) and a processing subsystem (PS) section (504) of the FPGA. In the digital front end (DFE), an output of CFR/DUC (corresponding to CFR module (306) and DUC) is provided as an input to a Digital pre-distortion (DPD) (550) at an input port, and a generated output of the DPD (550) is an input to a DAC and further to the PA (312). The feedback of the PA (312) is down converted and connected to ADC (not shown). The ADC output is input to DPD feedback input port. The sample rate at data input and feedback input ports are maintained the same for the DPD operation.

[00105] The PL section (502) includes a pre-inverse unit (506), a data collection unit (508), an inverse coefficient updation and mapping unit (510), a power measurement unit (512), and a control interface (513). The PS section (504) includes a post inverse unit (514), a data acceptance and alignment (DAA) unit (516), an ICE module (212), an adaptive control unit (520), a control, and a debug and monitor unit (522).

[00106] The pre-inverse unit (506) is configured to implement the predistorter (404) using a pre-inverse function in the FPGA to obtain a pre-distorted input signal before communicating the pre-distorted input signal to the PA (312). One or more estimated parameters that may be referred to as coefficients of the preinverse function are derived from the DPD coefficient estimation algorithm applied by the pre-inverse unit (506). The one or more estimated parameters are the output of the ICE module (212). The one or more estimated parameters are fed to the post inverse unit (514). The post inverse unit (514) generates pre-distorted input signal using the one or more estimated parameters. The pre-distorted input signal will be one of the inputs of the ICE module (212). The data collection unit (508) is configured to implement data buffers that store a plurality of one or more output data samples of the DPD output and feedback obtained from the PA (312). For example, the data collection unit (508) may use 4K/8K and 16K memory per the system requirement. The data collection unit (508) may be configured to be triggered from the control interface (513) for every ten of microseconds within a slot for data collection. The inverse coefficient updation and mapping unit (510) includes a parameter buffer and a mapping table for the one or more estimated parameters. The mapping table may include, for example, three sets of DPD coefficients for three power ranges (low/mid and high) which are communicated to one or more parameters initially once the input data power range is decided. Later the one or more parameters are updated as ICE module (212) triggers for fine tuning of the DPD coefficients or any significant changes sensed at input/feedback sample characteristic which is measured in terms of mean squared error (MSE). The estimated parameters are the Inverse coefficients. These coefficients are the output of the ICE module (212). these coefficients are fed to the post inverse unit (514), the post inverse unit (514) generates PD distorted signal using the PA input and the inverse coefficients, this PD will be one of the input of the ICE module (212). The same PD signal (pre distorted PA signal) and DPD input will used to generate the error signal and using this error signal it will generate the inverse coefficients again.

[00107] The power measurement unit (512) includes units for, inter alia, power calculation for input data samples, one or more output data samples and feedback data samples. The power measurement unit (512) is configured to calculate a mean and peak power of the collected data that is stored in the data collection unit (508). The control interface (513) implements data_ctrl and user_ctrl interface between the PL section (502) and the PS section (504). A user host application interface may run on a different clock (for e.g., user_clk) from a clock used for other control accesses (for e.g., ctrl_clk) to allow connection to a separate host system. The measured power information is communicated to the control interface (513), which determines the activities, including DPD correction ON/OFF or selecting the default coefficient data set from the coefficient mapping table.

[00108] The post inverse unit (514) is configured to implement a post distorter (406) using a pre-inverse function in the FPGA circuitry to perform a post inverse function of the DPD (550). The post inverse unit (514) includes a polynomial-based model and is substantially similar to pre-inverse unit (506) implemented in the PL section (502). The DPD coefficients determined in PL section (502) are applied to the post inverse unit (514) for each updation event. The DAA unit (516) applies a selection criterion on the collected samples of DPD output and the feedback output collected by the data collection unit (508) in the PL section (502). The dataset of input, DPD output and the PA (312) feedback output are amplitude- aligned and delay-aligned before feeding to the ICE module (212). The data and control flow are elaborated in FIG. 6 A- FIG. 6B.

[00109] The control, debug and monitor unit (522) is configured to perform aspects of controlling, debugging and monitoring mechanism of all units of the PS section (504) of the DPD (550). The DPD (550) host application is implemented in the control debug and monitor unit (522) that includes basic debugging and monitoring functions such as read power, read PAPR, capture input/PA feedback output data to generate PSD (power spectral density), read DPD coefficients, monitoring alignment status, single step correction, adaptive loop correction, enable/disable DPD output, DPD ON/OFF etc. The control debug and monitor unit (522) continuously monitors the interrupt generated by the DPD (550) from the PL section (502) and manages capturing feedback data out for different antenna ports in, for example, round robin manner for multiple-input multiple-output (MIMO) instances. In some aspects, the control debug and monitor unit (522) senses the time division duplexing (TDD) ON and OFF behavior for capturing right input data for DPD estimation process.

[00110] The adaptive control unit (520) is configured to provide adaptive control to ICE module (212). The adaptive control unit (520) generates a trigger, for example, for each 20ms to recapture the data by the data collection unit (508) and pass to the DAA unit (516) and the ICE module (212) for DPD coefficient estimation. If the adaptive control unit (520) senses any change in characteristic of dataset such as power level changes, increased nonlinearity etc., the adaptive control unit (520) may re-run the ICE module (212) for updating the DPD coefficient.

[00111] The ICE module (212) receives the output from the DPD (550) and the one or more output data samples from the PA (312) as feedback dataset and processes the output using an inverse coefficient estimation algorithm. The ICE module (212) uses a Periodic Prognostic Error Convergence (PPEC) technique. The PPEC technique derives the DPD coefficients. The ICE module (212) triggers and executes the PPEC technique for fine-tuning the DPD coefficients or any significant changes sensed at input/feedback sample characteristics. The PPEC technique is elaborated below. [00112] To make the parameter estimations more consistent and accurate in the steady state region, an adaptive ILA based DPD technique is applied using PPEC with the time-varying forgetting factor, which can improve the transient behavior of the algorithm.

[00113] The coefficient vector co of the pre-distorter (404) is estimated by using a modified version of Gauss-Newton recursive prediction error minimization (RPEM) algorithm that minimizes the following cost function. The RPEM is an algorithm used in adaptive systems for estimating the parameters of a model based on minimizing the prediction error.

where e (1, co) is given as in Gauss-Newton algorithm, 1 represents the number of samples and co will be the coefficients The formulation of the RPEM algorithm is derived, which requires the negative gradient of e (1, co) with respect to co. The negative gradient is given by:

When applying the PPEC algorithm for PA linearization, the adaptive ILA-based DPD using PPEC algorithm is described below:

Proposed PPEC algorithm for adaptive ILA DPD:

where p also is a positive constant and X(n) is a time-varying forgetting factor that tends exponentially to 1 as n — > co. In this algorithm, O, X (0) and P (0) are initial variables designed by users. Typically chosen values are X0 = 0.98 and X (0) = 0.94. The error convergence of the PPEC algorithm is shown as a plot 800 in FIG. 8.

[00114] In an embodiment, the PPEC algorithm estimates the inverse coefficients required for effective pre-distortion. The PPEC algorithm ensures that the pre-distorter (404) can accurately compensate for the non-linearity of the PA (312), leading to significant improvements in signal quality and reduced distortion. The primary output of the algorithm is the set of estimated inverse coefficients. These coefficients are then used by the pre-distorter (404) to modify the input signal to the PA (312), effectively cancelling out the non-linear effects of the PA (312). This results in a transmitted signal closer to the desired linear amplification, leading to improved signal-to-noise ratio (SNR), enhanced power efficiency, and improved system performance.

[00115] FIG. 6A - FIG. 6B illustrate a flow chart illustrating data and control flow, according to one embodiment of the present invention.

[00116] At step (602) of the flow diagram (600), the data collection unit (508) is configured to obtain data samples that include an output of the DPD (550) and an output from the Power Amplifier (PA) (312).

[00117] At step (604) of the flow diagram (600), the power measurement unit

(512) is configured to perform power calculations of input data samples, one or more output data samples and the PA feedback data samples.

[00118] At step (606) of the flow diagram (600), the power measurement unit

(512) defines input sample power IN threshold to be -30 dBFS and feedback sample power FB threshold to be -33 dBFS. The “input sample power IN threshold” refers to a predefined power level at which the input signal to the power amplifier is within an acceptable range for processing. This threshold is expressed in decibels relative to full scale (dBFS), a unit that measures the amplitude of the signal relative to the maximum possible digital signal level. The “feedback sample power FB threshold” refers to a predefined power level for the feedback signal, which is the signal returned from the power amplifier after it has been processed. Similar to the input threshold, this is also measured in decibels relative to full scale (dBFS).

[00119] At step (608) of the flow diagram (600), the power measurement unit (512) determines if the input sample power is greater than or equal to IN threshold. If the power is lesser than the IN threshold, then an error message is generated in step (610) that indicates that the power is “low input power” and that the DPD (550) is to be turned off. Further, the flow moves to step (612) where the data samples are collected, including the output of the DPD (550) and the output from the PA (312). The collected data samples are stored in the data collection unit (508) in step (602). Otherwise, if the power is greater than or equal to IN, at step (614), the power measurement unit (512) determines if the feedback sample power is greater than or equal to the FB threshold. If the power is less than the FB threshold, then an error message is generated in step (616) that indicates that the power is “low Feedback power” and that the DPD (550) should be turned off. Further, the flow moves to step (612) where the data samples are collected. The collected data samples are stored in the data collection unit (508) in step (602). If the power is greater than or equal to FB threshold, at step (618), the power measurement unit (512) generates a message “sufficient data power criterion: passed”.

[00120] Step (620) to Step (628) are flow steps for amplitude alignment. At step (620) of the flow diagram (600), DATAOUT samples (representing output of the DPD (550)) are normalized and mean power is determined.

[00121] At step (622) of the flow diagram (600), DATAFB samples (representing feedback from the PA (312)) are normalized and mean power is determined.

[00122] At step (624) of the flow diagram (600), the difference between the DATAOUT mean power and a DATAFB mean power is determined.

[00123] At step (626) of the flow diagram (600), either the DATAOUT samples or the DATAFB SAMPLES is aligned (considering whichever the samples are low) with the mean power difference, and the DATAOUT samples or the DATAFB SAMPLES are made equal.

[00124] At step (628) of the flow diagram (600), a message “amplitude alignment: passed” is generated.

[00125] Step (630) to Step (638) are flow steps for delay alignment. The delay alignment is performed when the program starts, initiated by the user (102), or the initial delay value is to be decided and used every time, followed by amplitude alignment.

[00126] At step (630) of the flow diagram (600), a cross-correlation is obtained between DATAOUT and DATAFB amplitude-aligned datasets.

[00127] At step (632) of the flow diagram (600), sample lag or delay for the DATAFB dataset is determined.

[00128] At step (634) of the flow diagram (600), the delayed samples may be removed from the start of DATAFB dataset and the end of DATAOUT dataset.

[00129] At step (636), a message, “Delay alignment: passed” is generated. The phrase “Delay alignment: passed” refers to a successful verification that the timing between different signal paths within the system (108) has been properly synchronized.

[00130] At step (638), the aligned DATAOUT dataset and DATAFB dataset are transferred to ICE module (212).

[00131] Comparison of the PPEC with other algorithms is used in the ICE module (212).

Conventional Least Mean Square algorithm (LMS).

[00132] The least mean squares (LMS) algorithm was developed by Widrow and Hoff in 1960 and has since become very popular as an error minimization technique in a wide variety of applications. It is a relatively simple algorithm, easy to implement, and is very robust, delivering consistent and reliable results. LMS is a stochastic gradient algorithm, which works by finding the gradient of the means square error to update the coefficients at each step. The LMS algorithm is derived by minimizing the mean square error (MSE) E {e2(n, co)}, where E denotes the expected values,

1 6e²(n, w) w^l(n) = w^l(n - 1) - - /r - - -

2 ow

= w^f(n — 1) + /re(n)z^t(n) where: n: Discrete time index or iteration step in the LMS algorithm. co: Filter coefficient vector that is updated at each iteration “n” to minimize the mean square error.

The LMS algorithm can be applied on a sample -by-sample basis or in block form, as shown above. The step-size parameter is used to control the convergence rate and stability of the algorithm. However, it usually converges slowly since increasing the step size parameter leads to instability problems. Moreover, it is also sensitive to the scaling of the input signal, making it very hard to choose a proper step size of the parameter.

Conventional Recursive Least Square algorithm (RLS)

The main disadvantage of the LMS algorithm is slow convergence. To speed up the convergence of the adaptation, the RLS algorithm is developed for predistortion. The RLS algorithm is derived by minimizing a weighted sum of the magnitude- squared errors.

where e (1, co) is the prediction error and 0 < X < 1 is the forgetting factor (or weighting factor) that gives exponentially less weight to the previous error. The prediction error refers to the difference between the actual output of the system (108) (e.g., the output of a PA (314)) and the expected or predicted output based on the current model or filter coefficients. The forgetting factor, denoted by 0 < < 1, is a weighting parameter that determines how much weight is given to past errors in the adaptation process. It is a value between 0 and 1. The choice of plays an essential role to track the variation of PA characteristics effectively. The smaller value of X, the quicker the information in previous data will be forgotten. In other words, if is small and less than 1, the RLS algorithm becomes more sensitive and the oscillation of the parameter estimations changes quickly and become bigger, which linearizes the non-linear behavior of PAs ineffectively. The error convergence of RLS algorithm is shown as a plot 800 in FIG. 8, which shows output estimation error vs. iteration number.

[00133] FIG. 7 illustrates an exemplary flow diagram of a method (700) for for improving linearity of a power amplifier (PA) (312), in accordance with embodiments of the present disclosure.

[00134] At step 702, the method (700) is configured to capture one or more output data samples from the Power Amplifier (PA) (312) using an ICE module (212). This step involves collecting the real-time output signals produced by the PA (312), which are typically analog in nature. These signals are then converted into digital data samples, often using an Analog-to-Digital Converter (ADC) (314). The captured one or more output data samples are crucial for subsequent processing and analysis, as they provide a representation of the behavior of the PA (312) in response to the input signal.

[00135] In an aspect, the one or more output data samples of the PA (312) are captured by an analog-to-digital converter (ADC) (314). This ensures that the analog signals produced by the PA (312) are accurately converted into digital data samples for processing.

[00136] At step 704, the method (700) processes the captured one or more output data samples using the ICE module (212) to generate an error signal indicative of non-linearity in the power amplifier. In this context, the error signal is calculated as the difference between the desired output signal (what the PA (312) should ideally produce) and the one or more output data samples (what the PA produces). This step is essential for identifying the discrepancies caused by nonlinear distortions in the PA (312)

[00137] At step 706, the method (700) estimates one or more parameters of a pre-distorter (404) using a periodic prognostic error convergence (PPEC) technique based on the error signal. The pre-distorter (404) is designed to compensate for the non-linearities in the PA (312). Estimating the one or more parameters involves calculating inverse coefficients, which are adjusted dynamically using a time-varying forgetting factor X. This forgetting factor X is critical in the adaptation process, as it determines how quickly the algorithm adapts to changes in the characteristics of the PA (312) over time. The range of X (from 0.98 to 0.94) provides a balance between sensitivity to new data and stability in parameter estimation.

[00138] In an aspect, the time- varying forgetting factor X is defined to range between Xo = 0.98 and X (0) = 0.94. This range is selected to optimize the balance between rapid adaptation and stable parameter estimation.

[00139] one or more The ICE module (212) uses the one or more parameters to modify the original input signal so that, when passed through the non-linear PA (312), the resulting output signal will be closer to the desired linear output. This pre-distortion process is crucial for correcting the distortions introduced by the PA (312).

[00140] At step 710, the method (700) applies the pre-distorted input signal to the PA (312). By feeding the modified signal into the PA (312), the method (700) ensures that the final output signal from the PA (312) is linearized, thereby improving the overall performance and efficiency of the amplification process. This step completes the correction loop, with the system now producing a more accurate and desirable output signal.

[00141] In an exemplary embodiment, user equipment (UE) communicatively coupled with a network is disclosed. The UE includes capturing, by an inverse coefficient estimation (ICE) module, one or more output data samples from the PA, processing, by the ICE module, the one or more output data samples to generate an error signal indicative of power amplifier non-linearity, estimating, by the ICE module, one or more parameters of a pre-distorter using a periodic prognostic error convergence (PPEC) technique based on the error signal, wherein estimating the one or more parameters of a pre-distorter comprises estimating inverse coefficients using a time- varying forgetting factor X, generating, by the ICE module, a pre-distorted input signal using the estimated one or more parameters and applying, by the ICE module, the pre-distorted input signal to the PA. [00142] In an exemplary embodiment, a computer program product comprising a non-transitory computer-readable medium comprising instructions that, when executed by one or more processors, cause the one or more processors to perform a method for improving linearity of a power amplifier (PA), the method comprises of capturing, by an inverse coefficient estimation (ICE) module, one or more output data samples from the PA, processing, by the ICE module, the one or more output data samples to generate an error signal indicative of power amplifier non-linearity, estimating, by the ICE module, one or more parameters of a predistorter using a periodic prognostic error convergence (PPEC) technique based on the error signal, wherein estimating the one or more parameters of a pre-distorter comprises estimating inverse coefficients using a time-varying forgetting factor X, generating, by the ICE module, a pre-distorted input signal using the estimated one or more parameters and applying, by the ICE module, the pre-distorted input signal to the PA.

[00143] FIG. 11 illustrates an exemplary computer system (1100) in which or with which embodiments of the present disclosure may be implemented. As shown in FIG. 11, the system (108) may include an external storage device (1110), a bus (1120), a main memory (1130), a read-only memory (1140), a mass storage device (1150), a communication port (1160), and a processor (1170). A person skilled in the art will appreciate that the system (108) may include more than one processor (1170) and communication ports (1160). Processor (1170) may include various modules associated with embodiments of the present disclosure.

[00144] In an embodiment, the communication port (1160) is any of an RS- 232 port for use with a modem-based dialup connection, a 10/100 Ethernet port, a Gigabit or 10 Gigabit port using copper or fiber, a serial port, a parallel port, or other existing or future ports. The communication port (1160) is chosen depending on a network, such a Local Area Network (LAN), Wide Area Network (WAN), or any network to which the system (108) connects.

[00145] In an embodiment, the memory (1130) is Random Access Memory (RAM), or any other dynamic storage device commonly known in the art. Readonly memory (1140) is any static storage device(s) e.g., but not limited to, a Programmable Read Only Memory (PROM) chips for storing static information e.g., start-up or Basic Input/Output System (BIOS) instructions for the processor (1170).

[00146] In an embodiment, the mass storage (1150) is any current or future mass storage solution, which is used to store information and/or instructions. Exemplary mass storage solutions include, but are not limited to, Parallel Advanced Technology Attachment (PATA) or Serial Advanced Technology Attachment (SATA) hard disk drives or solid-state drives (internal or external, e.g., having Universal Serial Bus (USB) and/or Firewire interfaces), one or more optical discs, Redundant Array of Independent Disks (RAID) storage, e.g., an array of disks (e.g., SATA arrays).

[00147] In an embodiment, the bus (1120) communicatively couples the processor(s) (1170) with the other memory, storage, and communication blocks. The bus (1120) is, e.g., a Peripheral Component Interconnect (PCI)/PCI Extended (PCI-X) bus, Small Computer System Interface (SCSI), Universal Serial Bus (USB) or the like, for connecting expansion cards, drives and other subsystems as well as other buses, such a Front Side Bus (FSB), which connects the processor (1170) to the system (108).

[00148] Optionally, operator and administrative interfaces, e.g., a display, keyboard, joystick, and a cursor control device, may also be coupled to the bus (1120) to support direct operator interaction with the system (108). Other operators and administrative interfaces are provided through network connections connected through the communication port (1160). The components described above are meant only to exemplify various possibilities. In no way should the aforementioned exemplary illustration (1100) limit the scope of the present disclosure.

[00149] While considerable emphasis has been placed herein on the preferred embodiments, it will be appreciated that many embodiments can be made, and many changes can be made in the preferred embodiments without departing from the principles of the disclosure. These and other changes in the preferred embodiments of the disclosure will be apparent to those skilled in the art from the disclosure herein, whereby it is to be distinctly understood that the foregoing descriptive matter is to be implemented merely as illustrative of the disclosure and not as a limitation. [00150] The present disclosure provides a technically advanced solution by providing a system and a method that enables faster and effective error convergence in power amplifiers through ILA-based DPD with PPEC design. The present disclosure is technically advance and accurate than known convergence algorithms including the RLS and PPEC algorithms as shown in FIG. 8 and FIG. 9, respectively. The PPEC in DPD of the present disclosure provides better ACER corrections compared to LMS and RLS algorithms. FIG. 10 shows adjacent channel power ratio (ACPR) comparison without DPD, PPEC technique and RLS Algorithm after single iteration of the 8K samples. From FIG. 10, performance of PPEC technique surpasses other known algorithms. The PPEC in DPD of disclosure provides faster correction of the ACLR with minimum number of samples captured. In RLS algorithm, a minimum of 8K samples is required for proper ACLR corrections, while PPEC in DPD, the ACLR corrections are achieved with a mere 2K samples. Furthermore, the PPEC in DPD of the present disclosure reduces the resource utilization in the FPGA block RAM (BRAM). In known algorithms such as RLS minimum of 8K samples needed to be captured and stored in the BRAM for inverse coefficient estimation. With the use of PPEC technique only 2K samples needed to be stored reducing the FPGA resource utilization. Table 1 below compares root mean square (RMS) algorithm with the PPEC technique. From the table it is very clear that error vector magnitude (EVM) is significantly less compared to algorithms that do not use DPD and RMS algorithms.

Table 1: ACPR comparison of the RMS algorithm and PPEC algorithm

[00151] The disclosed ILA based DPD design may be used for any 3G, 4G and 5G radio’s digital front-end design as it is defined to support from lower bandwidth to 100MHz bandwidth. Due to its property of faster error convergence, a smaller number of samples needed to be captured this gives faster processing time and less utilization of the FPGA resources. Better ACLR performance is also observed, thus reducing out-of-band (OOB emissions). This disclosed ILA based DPD design is very effective in 5G NR with the MIMO due to its ease of implementation, negligible computational complexity, effective ACLR reduction performance, controlled in-band and out-of-band distortion and full bandwidth utilization.

ADVANTAGES OF THE PRESENT DISCLOSURE

[00152] The present disclosure described herein is versatile and applicable to various radio front-end systems, supporting bandwidths from lower frequencies up to 100 MHz, making it suitable for 3G, 4G, and 5G technologies.

[00153] The present disclosure described herein ensures quicker convergence of errors, reducing the number of samples needed, which translates to faster processing times and less Field-Programmable Gate Arrays (FPGA) resource usage.

[00154] The present disclosure described herein provides enhanced Adjacent Channel Leakage Ratio (ACLR) performance, effectively reducing out-of-band (OOB) emissions and controlling both in-band and out-of-band distortions.

[00155] The present disclosure described herein is highly effective in 5G New Radio (NR) systems with massive Multiple -Input Multiple- Output (MIMO) due to its ease of implementation, low computational complexity, and full bandwidth utilization.

Claims

CLAIMS We claim:

1. A system (108) for improving linearity of a power amplifier (PA) (312), the system (108) comprising: a processing engine (210) coupled to an inverse coefficient estimation (ICE) module (212) to: capture, by the ICE module (212), one or more output data samples from the PA (312); process, by the ICE module (212), the one or more output data samples to generate an error signal indicative of power amplifier non-linearity; estimate, by the ICE module (212), one or more parameters of a pre-distorter using a periodic prognostic error convergence (PPEC) technique based on the error signal, wherein estimating the one or more parameters of a pre-distorter comprises estimating inverse coefficients using a time- varying forgetting factor X; generate, by the ICE module (212), a pre-distorted input signal using the estimated one or more parameters; and apply, by the ICE module (212), the pre-distorted input signal to the PA (312).

2. The system (108), as claimed in claim 1, wherein the one or more output data samples of the PA (312) are captured using an Analog-to-Digital Converter (ADC).

3. The system (108) as claimed in claim 1, wherein the error signal is generated by calculating a difference between a desired output signal and the one or more output data samples of the PA (312) at one or more corresponding sample points.

4. The system (108) as claimed in claim 1 , wherein the time-varying forgetting factor X is defined between X (0) = 0.98 and X (0) = 0.94.

5. The system (108), as claimed in claim 1, wherein the inverse coefficients are provided to a post inverse unit (514) to generate the pre-distorted input signal.

6. The system (108), as claimed in claim 1, wherein the pre-distorted input signal is an input signal provided to the ICE module (212).

7. A method (700) for improving linearity of a power amplifier (PA) (312), the method (700) comprising: capturing (702), by an inverse coefficient estimation (ICE) module (212), one or more output data samples from the PA (312); processing (704), by the ICE module (212), the one or more output data samples to generate an error signal indicative of power amplifier non-linearity; estimating (706), by the ICE module (212), one or more parameters of a pre-distorter using a periodic prognostic error convergence (PPEC) technique based on the error signal, wherein estimating the one or more parameters of a pre-distorter comprises estimating inverse coefficients using a time-varying forgetting factor X; generating (708), by the ICE module (212), a pre-distorted input signal using the estimated one or more parameters; and applying (710), by the ICE module (212), the pre-distorted input signal to the PA (312).

8. The method (700) as claimed in claim 7, wherein the one or more output data samples of the PA (312) are captured using an analog-to-digital converter (ADC).

9. The method (700) as claimed in claim 7, wherein the error signal is generated by calculating a difference between a desired output signal and the one or more output data samples of the PA (312) at one or more corresponding sample points.

10. The method (700) as claimed in claim 7, wherein a desired output signal is generated based on a mathematical model of the PA (312).

11. The method (700) as claimed in claim 7, wherein the time-varying forgetting factor X is defined between 0 = 0.98 and X (0) = 0.94.

12. The method (700) as claimed in claim 7, wherein the inverse coefficients are provided to a post inverse unit (514) to generate the pre-distorted input signal.

13. The method (700) as claimed in claim 7, wherein the pre-distorted input signal is an input signal provided to the ICE module (212).

14. A user equipment (UE) (104) communicatively coupled with a network (106), the coupling comprises steps of: receiving, by the network (106), a connection request from the UE (104); sending, by the network (106), an acknowledgment of the connection request to the UE (104); and transmitting a plurality of signals in response to the connection request, wherein the communication network (104) is configured for performing a method (700) for improving linearity of a power amplifier (PA) (312), as claimed in claim 7.

15. A computer program product comprising a non-transitory computer- readable medium comprising instructions that, when executed by one or more processors, cause the one or more processors to perform a method (500) for improving linearity of a power amplifier (PA) (312), the method (500) comprising: capturing (702), by an inverse coefficient estimation (ICE) module (212), one or more output data samples from the PA (312); processing (704), by the ICE module (212), the one or more output data samples to generate an error signal indicative of power amplifier non-linearity; estimating (706), by the ICE module (212), one or more parameters of a pre-distorter using a periodic prognostic error convergence (PPEC) technique based on the error signal, wherein estimating the one or more parameters of a pre-distorter comprises estimating inverse coefficients using a time-varying forgetting factor X; generating (708), by the ICE module (212), a pre-distorted input signal using the estimated one or more parameters; and applying (710), by the ICE module (212), the pre-distorted input signal to the PA (312).