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WO2024218430A1 - Composant électrique - Google Patents

Composant électrique Download PDF

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Publication number
WO2024218430A1
WO2024218430A1 PCT/FI2024/050140 FI2024050140W WO2024218430A1 WO 2024218430 A1 WO2024218430 A1 WO 2024218430A1 FI 2024050140 W FI2024050140 W FI 2024050140W WO 2024218430 A1 WO2024218430 A1 WO 2024218430A1
Authority
WO
WIPO (PCT)
Prior art keywords
substrate
electrical component
capacitor
capacitor electrode
junction
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
PCT/FI2024/050140
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English (en)
Inventor
Vladimir MILCHAKOV
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
IQM Finland Oy
Original Assignee
IQM Finland Oy
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by IQM Finland Oy filed Critical IQM Finland Oy
Publication of WO2024218430A1 publication Critical patent/WO2024218430A1/fr
Anticipated expiration legal-status Critical
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N69/00—Integrated devices, or assemblies of multiple devices, comprising at least one superconducting element covered by group H10N60/00
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N60/00—Superconducting devices
    • H10N60/10—Junction-based devices
    • H10N60/12—Josephson-effect devices

Definitions

  • the present disclosure relates to electrical, and particularly to components which contain nonlinear inductors.
  • the present disclosure further concerns components formed between two adjacent substrates.
  • Electrodes containing nonlinear inductors and capacitors can, in some circumstances, exhibit quantized and non-equidistant energy levels. Such elements can be used as quantum two-level systems and utilized for example as qubits in quantum computers.
  • TLS two-level systems
  • Such undesired TLS-influences can arise from metal-oxide or silicon-oxide layers in the qubit’s electrical environment, or from material impurities in the substrate - that is, in any conducting, semiconducting or insulating layers which lie adjacent to the qubit on the same substrate.
  • the material impurities may include residuals of photoresist materials that were used in lithographic processes for patterning the circuit elements. Such residuals may remain on the substrate if the removal of the photoresist was incomplete.
  • An object of the present disclosure is to provide an apparatus which meets the design objective stated above.
  • the object of the disclosure is achieved by an arrangement which is characterized by what is stated in the independent claim.
  • the preferred embodiments of the disclosure are disclosed in the dependent claims.
  • the disclosure is based on the idea of utilizing the gap between the two adjacent substrates as the capacitor in a quantum two-level system. TLS-disturbances are thereby reduced in the gap.
  • Figure 1 illustrates an electrical component
  • Figures 2a - 2e illustrate a first embodiment.
  • Figures 3a - 3g illustrate a second embodiment.
  • This disclosure describes an electrical component comprising a first substrate and a second substrate.
  • the electrical component also comprises a first capacitor electrode on the first substrate and a second capacitor electrode on the second substrate.
  • the second substrate is attached to the first substrate so that a gap is formed between the first and second capacitor electrodes.
  • the first capacitor electrode faces the second capacitor electrode across the gap so that the first and second capacitor electrodes form a capacitor in a capacitor region between the first substrate and the second substrate.
  • the electrical component also comprises a nonlinear inductor coupled in parallel with the capacitor.
  • the first substrate is bonded to the second substrate.
  • the first substrate may have a top surface and the second substrate may have a bottom surface. These surfaces may also be called the main top surface and the main bottom surface, to distinguish them from other surfaces which may be formed by protrusions or recesses in the first and second substrate.
  • the first capacitor electrode may be on the top surface of the first substrate.
  • the second capacitor electrode may be on the bottom surface of the second substrate.
  • these capacitor electrodes may be on recessed surfaces in the first and second substrates, respectively.
  • the first substrate may for example be a circuit board or a top part of an electronic chip.
  • the second substrate may a circuit board or a bottom part of an electronic chip.
  • the surfaces between which the capacitor is formed can for example be the surfaces of two circuit boards that are attached to each other, or the surfaces of a circuit board and an electronic chip which is attached to the circuit board, or the surfaces of two chips attached to each other.
  • Any substrate discussed in this disclosure may comprise an insulating body, conductive patterns deposited on the surface of the insulating body and optionally also conductive patterns embedded in the insulating body.
  • the conductive patterns may form an electric circuit in the substrate.
  • the first substrate may be attached to the second substrate by bonding.
  • the bonding process may for example be a flip-chip bonding process, but other processes can also be used.
  • the interconnections may for example be made of indium.
  • the interconnections may be connected to electric circuits in the first substrate and in the second substrate. In other words, the interconnections may connect an electric circuit in the first substrate to an electric circuit in the second substrate.
  • the first substrate may define an xy-plane and a z-direction which is perpendicular to the xy-plane.
  • top surface and bottom surface refer in this disclosure to surfaces which are parallel to the xy-plane and face in the positive z-direction (top surface) or negative z-direction (bottom surface).
  • top surface and bottom are used only as convenient references to surfaces facing in two opposite z-directions. “Top surface” therefore simply means a surface which faces in a first z-direction, and “bottom surface means a surface which faces in a second z-direction which is opposite to the first.
  • top and bottom and related words such as “above” and “below”, do not imply anything about how the device should be oriented in relation to the Earth’s gravitational field when it is being manufactured or operated.
  • the z-direction could for example be perpendicular to the gravitational field when the device is in use.
  • the capacitor and the nonlinear inductor may be coupled to an external electrical circuit.
  • This external electrical circuit may for example comprise microwave resonators.
  • the resonance frequency of the microwave resonators may be substantially equal to the electrical resonance frequency of the system containing the capacitor and the nonlinear inductor.
  • the external electrical circuit may additionally, or alternatively, also comprise flux lines, drivelines, and other circuit elements which can be used to control and read the state of the qubit.
  • Figure 1 illustrates schematically the electrical component discussed in this disclosure. It comprises a first substrate 14 and a second substrate 15.
  • the first substrate 14 has a top surface 141 .
  • the second substrate has a bottom surface 151 .
  • the second substrate 15 is attached to the first substrate 14 so that a gap 19 is formed between the bottom surface 151 of the second substrate 15 and the top surface 141 of the first substrate 14.
  • the means of attachment are not illustrated in figure 1 .
  • the electrical component comprises a capacitor region 18.
  • a first capacitor electrode 11 lies on the top surface 141 of the first substrate 14 in the capacitor region 18.
  • a second capacitor electrode 12 lies on the bottom surface 151 of the second substrate 15 in the capacitor region 18.
  • the capacitor region is therefore the region where the first capacitor electrode 11 faces the second capacitor electrode 12.
  • the first and second capacitor electrodes may form a parallel-plate capacitor.
  • An electric field, illustrated by grey arrows, may exist between the capacitor plates when the electrical component is in use.
  • the space between the two capacitor electrodes may, but does not have to, be a vacuum.
  • the electro-magnetic field between the capacitor electrodes will then be present only in vacuum and at the metal-vacuum interface at each electrode. This makes the device tolerant to impurities lying under the electrode (substrate-metal interface), around the device (substrate - air or substrate - vacuum) and even the TLSs that lie deep inside the substrate.
  • the first and second substrates 14 and 15 may be insulating.
  • the first and second capacitor electrodes 11 and 12 may be metallic.
  • the first and second capacitor electrodes 11 and 12 may be for example be made of aluminium, tantalum, niobium, or titanium nitride.
  • the capacitor electrodes may also comprise a superconductive coating of nanometer thickness which improves the metal - air or metal - vacuum interface at the electrodes in terms of TLS.
  • the electrical component in figure 1 also comprises a nonlinear inductor 13. Parallel coupling between the nonlinear inductor 13 and the capacitor is illustrated schematically in figure 1.
  • the electrical component comprises a first electrical connection 171 which extends from the first capacitor electrode 11 to the nonlinear inductor 13 and a second electrical connection 172 which extends from the second capacitor electrode 12 to the nonlinear inductor 13. More detailed examples of these electrical connections will be given below.
  • the nonlinear inductor 13 may for example be a Josephson junction or a kinetic inductor.
  • the term "Josephson junction" may refer to a quantum mechanical device made of a first junction electrode which is separated from a second junction electrode by a barrier, for example a thin insulating tunnel barrier.
  • the first junction electrode is superconducting.
  • the second junction electrode may also be superconducting (which creates an SIS- junction), or it may be a normal metal (NIS- junction).
  • the insulating layer of a Josephson junction may be formed by any tunnel barrier. It may for example be formed by a vacuum gap, or a point-like contact. The gap may be called a junction gap.
  • Josephson junction may alternatively refer to a quantum mechanical device made of a superconducting first junction electrode which is separated from a superconducting second junction electrode by a normal metal layer (SNS), a ferromagnetic layer (SFS-junction) or a semiconductor layer.
  • SNS normal metal layer
  • S-junction ferromagnetic layer
  • a kinetic inductor may be a non-linear superconducting inductor whose inductance arises mostly from the inertia of charge carriers in the inductor.
  • a kinetic inductor may for example be made of one or more nanowires. Any electrical component described in this disclosure may comprise a vacuum between the first and second substrates.
  • the first and/or the second substrate may comprise stopper regions (which are not illustrated in the figures).
  • a spacer may be placed in each stopper region.
  • a spacer may be a solid body which fixes the gap 39 between the first and second substrates 34 and 35 to a specific value with high precision, while ensuring that physical contact across the junction gap is avoided.
  • the spacer is placed in intentional physical contact with the first and/or the second substrates in the stopper regions when the substrates attached to each other.
  • a spacer may be formed from electrically inactive parts on the first and/or the second substrate.
  • a spacer may be an additional material block, which may for example be deposited on the first or the second substrates before they are bonded to each other.
  • any component described in this disclosure may be a part of a qubit, so that the qubit comprises the electrical component.
  • any component described in this disclosure may be a part of a quantum computer, so that the quantum computer comprises the electrical component.
  • Figure 2a illustrates an electrical component where reference numbers 21 - 25, 241 , 251 and 29 correspond to reference numbers 11 - 15, 141 , 151 and 19, respectively, in figure 1.
  • the nonlinear inductor 23 is on the top surface 241 of the first substrate 24.
  • the nonlinear inductor 23 is coupled to the first capacitor electrode 21 with a first electrical connection 242 on the top surface 241 of the first substrate 24.
  • the nonlinear inductor 23 is coupled to the second capacitor electrode 22 with a second electrical connection which extends across the gap 29 to the second substrate 25 and to the second capacitor electrode 22.
  • the first electrical connection 242 may comprise a conducting or superconducting element.
  • the second electrical connection on the other side of the nonlinear inductor 23, may comprise a vertical conductor 261 which extends between the first substrate and the second substrate.
  • This vertical conductor may for example be made of indium. It may be formed in the bonding process by placing a solder bump between the first and second substrates 24 and 25.
  • the vertical conductor 261 may be electrically connected to a conductor 243 on the first substrate 24 which extends to the nonlinear inductor 23.
  • the first electrical connection 242 and the conductor 243 are on opposite sides of the nonlinear inductor.
  • the vertical conductor 261 may also be electrically connected to a conductor 262 on the bottom surface 251 of the second substrate, so that the vertical conductor 261 and the conductor 243 and 262 together form the second electrical connection. This has been illustrated in figure 2a.
  • the conductors 243 and 262 may comprise conducting or superconducting elements.
  • the vertical conductor 261 may extend across the gap directly to the second capacitor electrode 22, as figure 2b illustrates.
  • the capacitor can have different geometries in the xy-plane.
  • Figure 2c illustrates a geometry where the first capacitor electrode 21 forms an annulus around the vertical conductor 261 .
  • Figure 2d illustrates a geometry where the first capacitor electrode forms a rectangular frame around the vertical conductor 261. Many other shapes are also possible.
  • the second capacitor electrode 22 may have the same shape as the first capacitor electrode 21 in the xy-plane. Alternatively, the second capacitor electrode 22 may have a larger area than the first capacitor electrode 21 . If the first capacitor electrode surrounds the vertical conductor 261 as in figures 2c and 2d, then the second capacitor electrode 22 may extend across the central region where the vertical conductor 261 is located, as figure 2e illustrates.
  • Figure 3a illustrates an electrical component where reference numbers 31 - 35, 341 , 351 39 correspond to reference numbers 11 - 15, 141 and 15119, respectively, in figure 1 .
  • This component comprises a first superconducting junction element 371 on the top surface 341 of the first substrate 34.
  • the first superconducting junction element 371 is electrically connected to the first capacitor electrode 31 with a first non-dissipative electrical connection 342.
  • the connection 342 may be superconducting.
  • the electrical component comprises a second conducting junction element 372 on the bottom surface 351 of the second substrate 351.
  • the second conducting junction element 372 is electrically connected to the second capacitor electrode 32 with a non-dissipative second electrical connection 352, which may be superconducting.
  • the first superconducting junction element 371 faces the second conducting junction element 372 across a junction gap 39 in a junction region 38, so that the first superconducting junction element 371 and the second conducting junction element 372 together with the gap form the nonlinear inductor 33 in the junction region 38.
  • the second conducting junction element 372 may be made of a normal metal.
  • the Josephson junction will then be an NIS-junction.
  • the second conducting junction element 372 may be made of superconducting material.
  • the Josephson junction will then be an SIS-junction.
  • the junction gap 39 forms the insulating layer in an SIS or NIS Josephson junction.
  • both the capacitor gap and the junction gap 39 in the nonlinear inductor 33 are effectively equal to the gap between the substrates.
  • the first substrate 34 may have a main top surface, and the component may comprise one or more first protrusions which extend from the main top surface of the first substrate toward the second substrate 35 in the junction region 33.
  • the first protrusion can make the junction gap narrower than the capacitor gap when the first capacitor electrode 31 lies on the main top surface of the first substrate 34.
  • Figure 3b illustrates an example where the first superconducting junction element 371 forms the one or more first protrusions.
  • the element 371 extends from the main top surface 341 toward the second substrate 35 so that the junction gap 391 becomes narrower than the capacitor gap 392.
  • One superconducting element is illustrated, but one or more first protrusions could alternatively comprise an array of superconducting junction elements, all of which extend toward the second substrate 35 in the junction region.
  • the junction gap can be zero if the tip of the protrusion is sharp enough.
  • the element 371 which forms the first protrusion may be in direct physical contact with the second conducting junction element 372.
  • a tunnelling barrier may be formed between the tip of the protrusion and the second conducting junction element because the tip is so narrow in the x- and y-dimensions.
  • each first protrusion 371 may be greater at its base than at its tip.
  • the base is the part of the first protrusion which is attached to the first substrate 34 and the tip is the part of the first protrusion which is closest to the second substrate 35.
  • the crosssection is a cross-section in the xy-plane which is parallel to the first and second substrates 34 and 35.
  • the first superconducting junction element 371 may for example have the shape of a cone.
  • the first superconducting element may comprise a base element and a wire (not illustrated) which extends from the base element toward the second substrate. The wire then forms the tip of the superconducting element.
  • An elevated surface 349 on the first substrate 34 is a surface with a z-coordinate which is greater than the z-coordinate of the main top surface 341 .
  • the superconducting junction element which is placed on the elevated surface 349 may be a further protrusion which extends further toward the second substrate
  • the relative widths of the junction gap 391 and the capacitor gap 392 can optionally be adjusted also by forming protrusions on the second substrate 35.
  • the second substrate 35 may have a main bottom surface 351
  • the component may comprise one or more second protrusions which extend from the main bottom surface 351 of the second substrate 35 toward the first substrate 34 in the junction region 33.
  • the first and second protrusions may then extend toward each other in the junction region 33.
  • the second conducting junction element 372 forms the one or more second protrusions.
  • the cross-section of each second protrusion 372 may be greater at its base than at its tip. Again, the base is the part of the second protrusion 372 which is attached to the second substrate 35 and the tip is the part of the second protrusion 372 which is closest to the first substrate 34.
  • Figure 3e shows an alternative where one or more second elevated surfaces 348 on the second substrate 35 form the one or more second protrusions, and the second conducting junction element 372 is below said one or more second elevated surfaces 348.
  • An elevated surface 348 on the second substrate 35 is a surface with a z-coordinate which is smaller than the z-coordinate of the main bottom surface 351 .
  • the first substrate may have a main top surface
  • the component may comprise a first recessed cavity in the first substrate
  • the first capacitor electrode may be located on the bottom of the first recessed cavity.
  • FIG. 3f This has been illustrated in figure 3f, where the reference numbers 31 - 32, 34 - 35, 341 - 342, 351 - 352, 371 and 372 refer to the same elements as in figure 3a. But unlike in figures 3b - 3e, a recess has been formed in the main top surface 341 . This creates a first recessed cavity 369 with a cavity bottom surface 347 which is further away from the second substrate 35 than the main top surface 341 . The first capacitor electrode is placed on the cavity bottom surface 347, while the first superconducting junction element 371 is on the main top surface 341 . The capacitor gap will therefore be greater than the junction gap.
  • the second substrate may also have a main bottom surface, and the component may comprise a second recessed cavity in the second substrate.
  • the second capacitor electrode may be located on the top of the second recessed cavity. This option has been illustrated in figure 3g, where 368 designates the second recessed cavity.
  • Figure 3g also illustrates an additional option.
  • a spacer (which is not illustrated in the figure) may fix the distance between the first and second substrates 34 and 35 when they are bonded to each other.
  • the main top surface 341 of the first substrate 34 and the main bottom surface 351 of the second substrate 351 have been bonded directly to each other.
  • the component comprises an additional recessed surface 346 in the first substrate 34, and the first superconducting junction element 371 is located on the additional recessed surface 346 in the first substrate 34.
  • the component also comprises an additional recessed surface 357 in the second substrate 35, and the second conducting junction element 372 is located on the additional recessed surface 356 in the second substrate 35.
  • junction region may then form a central region in the electrical component, and the capacitor may surround this central region.

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  • Semiconductor Integrated Circuits (AREA)

Abstract

L'invention concerne un composant électrique comprenant un premier substrat (14) et un second substrat (15). Le composant électrique comprend également une première électrode de condensateur (11) sur le premier substrat et une seconde électrode de condensateur (12) sur le second substrat. La première électrode de condensateur fait face à la seconde électrode de condensateur à travers un espace (19) de telle sorte que les première et seconde électrodes de condensateur forment un condensateur. Le composant électrique comprend également un inducteur non linéaire (13) couplé en parallèle avec le condensateur.
PCT/FI2024/050140 2023-04-17 2024-03-22 Composant électrique Pending WO2024218430A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FI20235431 2023-04-17
FI20235431 2023-04-17

Publications (1)

Publication Number Publication Date
WO2024218430A1 true WO2024218430A1 (fr) 2024-10-24

Family

ID=90718402

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/FI2024/050140 Pending WO2024218430A1 (fr) 2023-04-17 2024-03-22 Composant électrique

Country Status (1)

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WO (1) WO2024218430A1 (fr)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08306972A (ja) * 1995-05-11 1996-11-22 Canon Inc ジョセフソン接合素子
US20190044046A1 (en) * 2018-06-19 2019-02-07 Intel Corporation Quantum circuit assemblies with vertically-stacked parallel-plate capacitors
US20190385673A1 (en) * 2017-01-27 2019-12-19 Technische Universiteit Delft A qubit apparatus and a qubit system

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08306972A (ja) * 1995-05-11 1996-11-22 Canon Inc ジョセフソン接合素子
US20190385673A1 (en) * 2017-01-27 2019-12-19 Technische Universiteit Delft A qubit apparatus and a qubit system
US20190044046A1 (en) * 2018-06-19 2019-02-07 Intel Corporation Quantum circuit assemblies with vertically-stacked parallel-plate capacitors

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