WO2024259834A1 - Cmos storage array and compute-in-memory circuit - Google Patents

Abstract

Provided in the present disclosure is a CMOS storage array, comprising storage units distributed in a matrix array, each storage unit comprising a memory, and a P-channel field effect transistor and an N-channel field effect transistor, which are connected in series, wherein a source electrode of the P-channel field effect transistor is connected to a drain electrode of the N-channel field effect transistor, a drain electrode of the P-channel field effect transistor is connected to a source electrode of the N-channel field effect transistor, and one end of the memory is connected to the drain electrode of the P-channel field effect transistor. By using the disclosure, the density of the storage array can be increased, and the requirement for a driving capability of a field effect transistor can be reduced.

Description

CMOS semiconductor storage array and in-memory computing circuit

This application claims priority to a patent application filed on June 20, 2023, entitled “CMOS semiconductor memory array and in-memory computing circuit” with application number 202310735553.0.

Technical Field

The present disclosure relates to the technical field of resistive random access memory (RRAM) and CMOS hybrid integrated circuits, and in particular to a RRAM storage unit using CMOS and a storage array circuit thereof.

Background Art

With the continuous development of artificial intelligence and deep learning technology, artificial neural networks have been widely used in natural language processing, image recognition, autonomous driving, graph neural networks and other fields. However, the increasing size of the network has led to a large amount of energy consumption in the transfer of data between memory and traditional computing devices such as CPU and GPU, which is called the von Neumann bottleneck. The most important calculation in the artificial neural network algorithm is the vector matrix multiplication calculation (Vector Matrix Multiplication). Compute-In-Memory based on non-volatile memory (Non-volatile Memory, or non-volatile memory) stores weights in non-volatile memory units and performs simulated vector matrix multiplication calculations in the array, avoiding the frequent transfer of data between memory and computing units, and is considered to be a promising way to solve the von Neumann bottleneck.

At present, non-volatile memory devices such as RRAM, PCRAM, MRAM, FeRAM, FeFET, etc. store weights on the conductivity of the device after the weights are written. The devices are organized in the form of an array, and the input voltage from one end is used as the input of the vector-matrix multiplication. The array is calculated by Ohm's law and Kirchhoff's law, and the current obtained at the other end of the array is the summation result of the vector-matrix multiplication, and the summation result is usually read out using an analog-to-digital converter (ADC).

Among the various new non-volatile memories mentioned above, two-terminal non-volatile memories have attracted extensive attention and research due to their higher theoretical density and reduced process cost brought by simple structure. In practical applications, two-terminal memories need to form a storage array to achieve high-density structure and high-speed reading and writing. The existing methods mainly form a 1-transistor-1 memory (1T1R) array. The transistors in the mainstream method are connected to the memory array. N-type is often used. However, in actual use, on the one hand, due to the low power supply Vdd at advanced nodes, the maximum gate voltage that can be applied by the transistor is limited. On the other hand, when the N-type transistor has a source resistor, the non-zero source voltage will further reduce the gate-source voltage of the transistor. Therefore, there is a problem of insufficient driving current during the operation of the two-terminal memory at advanced nodes, which limits the further reduction of the device size and the improvement of the storage array density.

Summary of the invention

In view of the above problems, the purpose of the present invention is to provide a CMOS semiconductor memory array and an in-memory computing circuit to solve the problems of voltage limitation in existing memory circuits, resulting in insufficient driving current, limiting the miniaturization of devices and increasing the density of memory arrays, and so on.

The CMOS semiconductor storage array provided by the present disclosure includes storage units distributed in a matrix array, wherein the storage unit includes a memory and a P-channel field effect transistor and an N-channel field effect transistor connected in series; wherein the source of the P-channel field effect transistor is connected to the drain of the N-channel field effect transistor; the drain of the P-channel field effect transistor is connected to the source of the N-channel field effect transistor; and one end of the memory is connected to the drain of the P-channel field effect transistor.

In addition, an optional technical solution is that the gate of the N-channel field effect transistor and the gate of the P-channel field effect transistor are respectively connected to different word lines; the source of the P-channel field effect transistor is connected to the source line, and the other end of the memory is connected to the bit line.

In addition, an optional technical solution is that the source line is connected to the positive voltage VDD, and the saturation current of the P-channel field effect transistor is:

Where, _Vsg = _Vs < VDD, and V _tp represent intrinsic parameters of the P-channel field effect transistor, V _sg represents the source-gate voltage of the P-channel field effect transistor, and V _s represents the source voltage of the P-channel field effect transistor.

In addition, an optional technical solution is to include M×N storage cells, where M represents the number of rows, N represents the number of columns, and the word lines include a word line N connected to the gate of an N-channel field effect transistor, and a word line P connected to the gate of a P-channel field effect transistor; wherein the word lines N and P of the storage cells in the same column are shared, and the bit lines and source lines of the storage cells in the same row are shared.

In addition, the optional technical solution includes a save mode, a write 1 mode, a write 0 mode and a read mode; wherein, in the save mode, each storage unit does not work and saves its original data; in the write 1 mode, each storage unit does not work and saves its original data; In the write mode and write 0 mode, the specified storage cell is in the state representing 1 and 0 respectively, and the voltage of the specified storage cell is less than the preset voltage VDD; in the read mode, the source line of the storage cell is connected to the read voltage, so that the read current passes through the storage cell to the bit line, and the corresponding state of the storage cell is read from the bit line.

In addition, an optional technical solution is that in the storage mode, all word lines N, bit lines and source lines are connected to GND, and the word line P is connected to a preset voltage VDD; the P-channel field effect transistor and the N-channel field effect transistor are both in the off state.

In addition, an optional technical solution is that, in write 1 mode, word line N is connected to a preset voltage VDD, and word line P is connected to GND; after the target memory cell is selected, the source line of the target memory cell is connected to a preset write 1 voltage, and the remaining lines remain in the state in the save mode, and the current of the target memory cell flows from the source line through the memory to the bit line, and the target memory cell is written to state 1.

In addition, an optional technical solution is that, in write 0 mode, word line N is connected to a preset voltage VDD, word line P and source line are connected to GND; after the target memory cell is selected, the bit line of the target memory cell is connected to a preset write 0 voltage, and the remaining lines maintain the state in the save mode, the current of the target memory cell flows from the bit line through the memory to the source line, and the target memory cell is written to state 0.

In addition, an optional technical solution is that in the read mode, the word line N is connected to the preset voltage VDD; after the target memory cell is selected, the source line is connected to the read voltage, and the remaining lines maintain the state in the save mode. The read current flows from the source line through the memory to the bit line, and the corresponding state of the memory cell is read from the bit line.

On the other hand, the present disclosure also provides an in-memory computing circuit, including the above-mentioned CMOS semiconductor storage array.

Utilizing the above-mentioned CMOS semiconductor storage array and in-memory computing circuit, the storage unit includes a memory and a P-channel field effect transistor and an N-channel field effect transistor connected in series; wherein the source of the P-channel field effect transistor is connected to the drain of the N-channel field effect transistor; the drain of the P-channel field effect transistor is connected to the source of the N-channel field effect transistor, and PMOS is introduced to form a CMOS transmission gate structure, thereby significantly reducing the operating voltage, alleviating the problem of insufficient driving capability in the traditional storage structure, and being conducive to improving the density of the storage array and realizing the miniaturization of the device.

In order to achieve the above and related purposes, one or more aspects of the present disclosure include features that will be described in detail later. The following description and the accompanying drawings describe some exemplary aspects of the present disclosure in detail. However, these aspects indicate only some of the various ways in which the principles of the present disclosure can be used. In addition, the present disclosure is intended to include all these aspects and their equivalents.

BRIEF DESCRIPTION OF THE DRAWINGS

By referring to the following description in conjunction with the accompanying drawings, and with a more comprehensive understanding of the present disclosure, other objects and results of the present disclosure will become more apparent and easier to understand. In the accompanying drawings:

FIG1 is a schematic diagram of the structure of a storage unit of a CMOS semiconductor storage array according to an embodiment of the present disclosure;

FIG2 is a schematic structural diagram of a matrix array of a CMOS semiconductor storage array according to an embodiment of the present disclosure;

FIG. 3 is a schematic diagram of operating voltages of a CMOS semiconductor memory array according to an embodiment of the present disclosure.

DETAILED DESCRIPTION

In the following description, for the purpose of illustration, in order to provide a comprehensive understanding of one or more embodiments, many specific details are set forth. However, it is apparent that these embodiments may also be implemented without these specific details. In other examples, for ease of describing one or more embodiments, known structures and devices are shown in the form of block diagrams.

The maximum gate voltage that can be applied to the transistors in the current N-type transistor storage array is limited, and when the N-type transistor has a source resistor, the non-zero source voltage will further reduce the gate-source voltage of the transistor, so there is a problem of insufficient driving current during the operation of the two-terminal memory at the advanced node. To solve the above problems, the present invention provides a CMOS semiconductor storage array and an in-memory computing circuit, wherein the storage unit includes a memory and a P-channel field effect transistor and an N-channel field effect transistor connected in series; wherein the source of the P-channel field effect transistor is connected to the drain of the N-channel field effect transistor; the drain of the P-channel field effect transistor is connected to the source of the N-channel field effect transistor, and a PMOS is introduced to form a CMOS transmission gate structure, thereby significantly reducing the operating voltage, alleviating the problem of insufficient driving capability in the traditional storage structure, and is conducive to further improving the density of the storage array and realizing the miniaturization of the device.

In the following description of the present disclosure, the line connecting the gate of the transistor is called the word line (Word Line, WL), the line connecting the source of the transistor is called the source line (Source Line, SL), and the line connecting one end of the device is called the bit line (Bit Line, BL).

To describe the CMOS semiconductor memory array in the present disclosure in detail, specific embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

1 and 2 respectively show a schematic structure of a memory cell and a matrix array structure of a CMOS semiconductor memory array according to an embodiment of the present disclosure.

As shown in both FIG. 1 and FIG. 2 , the CMOS semiconductor memory array of the embodiment of the present disclosure includes a plurality of memory cells distributed in a matrix array, each memory cell further including a memory and a P-channel field effect transistor (PMOS for short) and an N-channel field effect transistor (NMOS for short) connected in series; wherein the source of the P-channel field effect transistor is connected to the drain of the N-channel field effect transistor; the drain of the P-channel field effect transistor is connected to the source of the N-channel field effect transistor; and one end of the memory is connected to the drain of the P-channel field effect transistor.

Specifically, in the structure described in FIG1 , the gate of the N-channel field effect transistor and the gate of the P-channel field effect transistor are respectively connected to different word lines, and the word lines include a word line N connected to the gate of the N-channel field effect transistor and a word line P connected to the gate of the P-channel field effect transistor; the source of the P-channel field effect transistor is connected to the source line, and the other end of the memory is connected to the bit line. It can be seen that in this memory cell, a CMOS transmission gate is connected in series with an RRAM to form a memory cell with a gating function. The conduction of the transistor can be controlled by the signals on WL0 and WL1, and the corresponding operating voltages can be applied to SL and BL to operate or read the memory in the cell.

Among them, the PMOS as a gating device is connected to the positive voltage VDD at the source line, and the saturation current of the P-channel field effect transistor is:

Where, _Vsg = _Vs < VDD, and V _tp represent intrinsic parameters of the P-channel field effect transistor, V _sg represents the source-gate voltage of the P-channel field effect transistor, and V _s represents the source voltage of the P-channel field effect transistor.

It can be seen that when the above-mentioned PMOS transmits a positive voltage, since its Vsg is not affected by the voltage at the other end, the gate-source voltage drop of the PMOS can reach the voltage VDD, while for the NMOS, the maximum is only VDD-I*R, where the typical value of I*R is 0.7V. In this case, the saturation current of the PMOS device will be significantly greater than that of the NMOS device of the same size. In other words, if the same current driving capability is required, the gate width W required by the PMOS is smaller, which is more conducive to improving the density of the storage array.

FIG2 shows a typical memory array structure formed by the memory cells of FIG1 , wherein the same row shares SL and BL, and the same column shares WLP (word line P) and WLN (word line N). The figure shows the specific connection relationship between two rows and two columns; wherein, in the application process, the specific memory array structure may also include M×N memory cells, wherein M represents the number of rows, and N represents the number of columns, wherein the memory cells in the same row share word lines SL0 and SL1; and the memory cells in the same column share word lines P and N.

In a specific embodiment of the present disclosure, the storage array has four working modes, namely, a save mode, a write 1 mode, a write 0 mode and a read mode; wherein, in the save mode, each storage unit does not work and saves its own original data; in the write 1 mode and the write 0 mode, the designated storage unit is in a state representing 1 and 0, respectively, and the voltage of the designated storage unit is less than a preset voltage VDD; in the read mode, the source line of the storage unit is connected to the read voltage, so that the read current passes through the storage unit to the bit line, and the corresponding state of the storage unit is read from the bit line.

Specifically, in the save mode, all word lines N, bit lines and source lines are connected to GND, and word line P is connected to a preset voltage VDD; P-channel field effect transistors and N-channel field effect transistors are both in the off state; in the write 1 mode, word line N is connected to a preset voltage VDD, and word line P is connected to GND; after the target memory cell is selected, the source line of the target memory cell is connected to a preset write 1 voltage, and the remaining lines maintain the state in the save mode, and the current of the target memory cell flows from the source line through the memory to the bit line, and the target memory cell is written to state 1; in the write 0 mode, word line N is connected to a preset voltage VDD, and word line P is connected to GND; after the target memory cell is selected, the source line of the target memory cell is connected to a preset write 1 voltage, and the remaining lines maintain the state in the save mode, and the current of the target memory cell flows from the source line through the memory to the bit line, and the target memory cell is written to state 1; Connected to the preset voltage VDD, the word line P and the source line are connected to GND; after the target memory cell is selected, the bit line of the target memory cell is connected to the preset write 0 voltage, and the other lines remain in the state in the storage mode, and the current of the target memory cell flows from the bit line through the memory to the source line, and the target memory cell is written to state 0; in the read mode, the word line N is connected to the preset voltage VDD; after the target memory cell is selected, the source line is connected to the read voltage, and the other lines remain in the state in the storage mode, and the read current flows from the source line through the memory to the bit line, and the corresponding state of the memory cell is read from the bit line.

As a specific example, FIG. 3 shows a schematic structure of an operating voltage of a memory array according to an embodiment of the present disclosure.

As shown in FIG. 1 to FIG. 3, there are four working modes of the storage array, namely, the save mode, the write 1 mode, the write 0 mode and the read mode; assuming that the memory writes 1 when a positive voltage is applied to SL, and the memory writes 0 when a positive voltage is applied to BL, VDD and GND are used below to represent the high level and ground in the circuit respectively. Specifically, assuming that the target device of the current operation is the storage cell (1, 1) in the lower right corner of FIG. 2, the operation flow shown in FIG. 3 is performed. First, the array is in an inoperative state, and all cells save data. Then, the operations of write 1, read, and write 0 are successively performed on the specified cells.

Specifically, in the non-working state, all WLN, BL, and SL are connected to GND, and all WLP are connected to VDD. At this time, all transistors are in the off state and the array does not work;

Write 1 mode: WLN1 is connected to VDD, WLP1 is connected to GND, SL1 is connected to the write 1 voltage, and the connection method of the other lines is the same as the non-working state. At this time, the transistor corresponding to the (1, 1) unit is turned on, and current will flow from SL1 through the memory to BL1, and the device is written to 1.

Read mode: WLN1 is connected to VDD, WLP1 is connected to GND, SL1 is connected to the read voltage, and the connection method of the other lines is the same as the non-working state. At this time, the transistor corresponding to the (1, 1) unit is turned on, and the read current flows from SL1 through the memory to BL1. The current corresponding to the device can be read from BL1.

Write 0 mode: WLN1 is connected to VDD, WLP1 is connected to GND, BL1 is connected to the write 0 voltage, and the connection method of the other lines is consistent with the non-working state. At this time, the transistor corresponding to the (1, 1) unit is turned on, and current will flow from BL1 through the memory to SL, and the device is written to 0.

It should be noted that the present disclosure above only explains a method for operating a single storage cell in an array at a time, selecting only one row and one column at a time, and a person with ordinary knowledge in the technical field should understand that the operation method can be easily extended to the selection of multiple rows and columns, so that the cells of multiple rows and columns can be read and written in parallel, thereby increasing the data throughput of the array.

Corresponding to the above-mentioned CMOS semiconductor storage array, the present disclosure also provides an in-memory computing circuit, including the CMOS semiconductor storage array as described above. For specific embodiments of the in-memory computing circuit, reference may be made to the description in the CMOS semiconductor storage array embodiment, which will not be described one by one here.

According to the CMOS semiconductor memory array and in-memory computing circuit disclosed above, the memory unit includes a memory and a P-channel field effect transistor and an N-channel field effect transistor connected in series; wherein the source of the P-channel field effect transistor is connected to the drain of the N-channel field effect transistor; the drain of the P-channel field effect transistor is connected to the source of the N-channel field effect transistor, and the PMOS is introduced to form a CMOS transmission gate structure, thereby significantly reducing the operating voltage, alleviating the problem of insufficient driving capability in the traditional memory structure, and facilitating further improving the density of the memory array and realizing the miniaturization of the device.

It should also be noted that, in this specification, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprise", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the statement "comprises a ..." does not exclude the presence of other identical elements in the process, method, article or device including the element.

The above description of the disclosed embodiments enables professionals in the field to implement or use the present disclosure. Various modifications to these embodiments will be obvious to professionals in the field. It is apparent that the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present disclosure. Therefore, the present disclosure will not be limited to the embodiments shown herein, but will conform to the broadest scope consistent with the principles and novel features disclosed herein.

Claims (10)

A CMOS semiconductor storage array, characterized in that it includes storage units distributed in a matrix array, wherein the storage units include a memory and a P-channel field effect transistor and an N-channel field effect transistor connected in series; wherein: The source of the P-channel field effect transistor is connected to the drain of the N-channel field effect transistor; The drain of the P-channel field effect transistor is connected to the source of the N-channel field effect transistor; One end of the memory is connected to the drain of the P-channel field effect transistor. The CMOS semiconductor memory array according to claim 1, wherein: The gate of the N-channel field effect transistor and the gate of the P-channel field effect transistor are respectively connected to different word lines; A source of the P-channel field effect transistor is connected to a source line, and the other end of the memory is connected to a bit line. The CMOS semiconductor memory array according to claim 2, characterized in that The source line is connected to the positive voltage VDD, and the saturation current of the P-channel field effect transistor is:
Where, _Vsg = _Vs < VDD, and V _tp represent intrinsic parameters of the P-channel field effect transistor, V _sg represents the source-gate voltage of the P-channel field effect transistor, and V _s represents the source voltage of the P-channel field effect transistor. The CMOS semiconductor memory array as shown in claim 2, characterized in that it comprises M×N memory cells, wherein M represents the number of rows, N represents the number of columns, and the word lines comprise a word line N connected to the gate of the N-channel field effect transistor, and a word line P connected to the gate of the P-channel field effect transistor; wherein, The memory cells located in the same column share a word line N and a word line P, and the memory cells located in the same row share a bit line and a source line. The CMOS semiconductor storage array as shown in claim 4, characterized in that it includes a save mode, a write 1 mode, a write 0 mode and a read mode; wherein, In the saving mode, each storage unit does not work and saves its own original data; In the write 1 mode and the write 0 mode, the designated storage cell is in a state representing 1 and 0, respectively, and the voltage of the designated storage cell is less than a preset voltage VDD; In the read mode, the source line of the memory cell is connected to a read voltage, so that a read current passes through the memory cell to reach the bit line, and the corresponding state of the memory cell is read from the bit line. The CMOS semiconductor memory array according to claim 5, characterized in that In the storage mode, all word lines N, bit lines and source lines are connected to GND, and the word line P is connected to a preset voltage VDD; The P-channel field effect transistor and the N-channel field effect transistor are both in an off state. The CMOS semiconductor memory array according to claim 5, characterized in that In the write 1 mode, the word line N is connected to a preset voltage VDD, and the word line P is connected to GND; After the target memory cell is selected, the source line of the target memory cell is connected to a preset write 1 voltage, and the remaining lines maintain the state in the storage mode. The current of the target memory cell flows from the source line through the memory to the bit line, and the target memory cell is written to state 1. The CMOS semiconductor memory array according to claim 5, characterized in that In the write 0 mode, the word line N is connected to a preset voltage VDD, and the word line P and the source line are connected to GND; After the target memory cell is selected, the bit line of the target memory cell is connected to a preset write 0 voltage, and the other lines maintain the state in the storage mode. The current of the target memory cell flows from the bit line through the memory to the source line, and the target memory cell is written to state 0. The CMOS semiconductor memory array according to claim 5, characterized in that In the read mode, the word line N is connected to a preset voltage VDD; After the target memory cell is selected, the source line is connected to the read voltage, and the other lines remain in the state in the storage mode. The read current flows from the source line through the memory to the bit line, and the data is read from the bit line. The corresponding state of the storage unit. An in-memory computing circuit, characterized by comprising a CMOS semiconductor storage array as described in any one of claims 1 to 9.