WO2024087083A1

WO2024087083A1 - Semiconductor packaged device and method for manufacturing the same

Info

Publication number: WO2024087083A1
Application number: PCT/CN2022/127854
Authority: WO
Inventors: Jianping Zhang; Kai Cao; Lei Zhang; Chunhua Zhou
Original assignee: Innoscience Zhuhai Technology Co Ltd
Current assignee: Innoscience Zhuhai Technology Co Ltd
Priority date: 2022-10-27
Filing date: 2022-10-27
Publication date: 2024-05-02
Anticipated expiration: 2025-04-27
Also published as: CN118302852A

Abstract

A semiconductor packaged device includes a semiconductor die, a plurality of first conductive pads, a conductive layer, a first heat dissipation structure, and a second heat dissipation structure. The semiconductor die has a top surface, a bottom surface, and an inclined side surface connecting the top surface to the bottom surface. The conductive layer is electrically connected with the semiconductor die through one of the first conductive pads, in which the conductive layer extends laterally and downward along the inclined side surface of the semiconductor die. The first heat dissipation structure is disposed over the top surface of the semiconductor die and thermally coupled to the semiconductor die through the first conductive pads. The second heat dissipation structure is disposed under the bottom surface of the semiconductor die and thermally coupled to the semiconductor die.

Description

SEMICONDUCTOR PACKAGED DEVICE AND METHOD FOR MANUFACTURING THE SAME

Inventors: Jianping ZHANG; Kai CAO; Lei ZHANG; Chunhua ZHOU

Field of the Disclosure:

The present disclosure generally relates to a nitride-based semiconductor packaged device. More specifically, the present disclosure relates to a nitride-based semiconductor packaged device having a dual-side cooled nitride-based semiconductor die.

Background of the Disclosure:

In recent years, intense research on high-electron-mobility transistors (HEMTs) has been prevalent, particularly for high power switching and high frequency applications. III-nitride-based HEMTs utilize a heterojunction interface between two materials with different bandgaps to form a quantum well-like structure, which accommodates a two-dimensional electron gas (2DEG) region, satisfying demands of high power/frequency devices. In addition to HEMTs, examples of devices having heterostructures further include heterojunction bipolar transistors (HBT) , heterojunction field effect transistor (HFET) , and modulation-doped FETs (MODFET) . III-nitride-based devices have unique packaging needs that take into account the requirement for enhanced thermal dissipation and overcome the potential for packaging degradation caused by III-nitride device heat output. Thus, there is a need in the art for improved III-nitride-based device.

Summary of the Disclosure:

In accordance with one aspect of the present disclosure, a semiconductor packaged device is provided. The semiconductor packaged device includes a semiconductor die, a plurality of first conductive pads, a conductive layer, a first heat dissipation structure, and a second heat dissipation structure. The semiconductor die has a top surface, a bottom surface, and an inclined side surface connecting the top surface to the bottom surface. The first conductive pads are disposed over the top surface of the semiconductor die. The conductive layer is electrically connected with the semiconductor die through one of the first conductive pads, in which the conductive layer extends laterally and downward along the inclined side surface of the semiconductor die. The first heat dissipation structure is disposed over the top surface of the semiconductor die and thermally coupled to the semiconductor die through the first conductive pads. The second heat dissipation structure is disposed under the bottom surface of the semiconductor die and thermally coupled to the semiconductor die.

In accordance with one aspect of the present disclosure, a method for manufacturing a semiconductor packaging device is provided. The method includes steps as follows. A semiconductor die is formed to have an inclined side surface. A plurality of first conductive pads are formed over a top surface of the semiconductor die, in which the first conductive pads are electrically coupled to the semiconductor die. A conductive layer is formed to be electrically connected to one of the first conductive pads. The conductive layer is formed to extend from a top of the semiconductor die to a side of the semiconductor die along the inclined side surface. A heat dissipation structure is formed under the bottom surface of the semiconductor die. Another heat dissipation structure is formed over the top surface of the semiconductor die.

In accordance with one aspect of the present disclosure, a semiconductor packaged device is provided. The semiconductor packaged device includes a semiconductor die, a first circuit structure, a plurality of conductive members, and a second circuit structure. The first circuit structure is disposed over a top surface of the semiconductor die. The conductive members are disposed between the semiconductor die and the first circuit structure, and the semiconductor die is electrically coupled to first circuit structure through the conductive members. The second circuit structure makes contact with a side surface of a first conductive member of the conductive members to be electrically coupled to the semiconductor die. The second circuit structure extends inclinedly and downward, such that the second circuit structure is substantially parallel to an inclined side surface of the semiconductor die.

By the above configuration, in the present disclosure, different heat dissipation structures are disposed/formed at a top and a bottom of the semiconductor die respectively, and the semiconductor die is thermally coupled to the two dissipation structures. Thus, the heat dissipation efficiency of the semiconductor packaged device can be improved.

Brief Description of the Drawings:

Aspects of the present disclosure are readily understood from the following detailed description when read with the accompanying figures. It should be noted that various features may not be drawn to scale. That is, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. Embodiments of the present disclosure are described in more detail hereinafter with reference to the drawings, in which:

FIG. 1A is a vertical cross-sectional view of a semiconductor packaged device according to some embodiments of the present disclosure;

FIG. 1B is a vertical cross-sectional view of a semiconductor die in the semiconductor packaged device of the FIG. 1A;

FIG. 2A, FIG. 2B, FIG. 2C, FIG. 2D, FIG. 2E, FIG. 2F, FIG. 2G, FIG. 2H, FIG. 2I, and FIG. 2J show different stages of a method for manufacturing a semiconductor packaged device according to some embodiments of the present disclosure;

FIG. 3 is a vertical cross-sectional view of a semiconductor packaged device according to some embodiments of the present disclosure

FIG. 4 is a vertical cross-sectional view of a semiconductor packaged device according to some embodiments of the present disclosure

FIG. 5 is a vertical cross-sectional view of a semiconductor packaged device according to some embodiments of the present disclosure;

FIG. 6 is a vertical cross-sectional view of a semiconductor packaged device according to some embodiments of the present disclosure; and

FIG. 7 is a vertical cross-sectional view of a semiconductor packaged device according to some embodiments of the present disclosure.

Detailed Description:

Common reference numerals are used throughout the drawings and the detailed description to indicate the same or similar components. Embodiments of the present disclosure will be readily understood from the following detailed description taken in conjunction with the accompanying drawings.

Spatial descriptions, such as "on, " "above, " "below, " "up, " "left, " "right, " "down, " "top, " "bottom, " "vertical, " "horizontal, " "side, " "higher, " "lower, " "upper, " "over, " "under, " and so forth, are specified with respect to a certain component or group of components, or a certain plane of a component or group of components, for the orientation of the component (s) as shown in the associated figure. It should be understood that the spatial descriptions used herein are for purposes of illustration only, and that practical implementations of the structures described herein can be spatially arranged in any orientation or manner, provided that the merits of embodiments of this disclosure are not deviated from by such arrangement.

Further, it is noted that the actual shapes of the various structures depicted as approximately rectangular may, in actual device, be curved, have rounded edges, have somewhat uneven thicknesses, etc. due to device fabrication conditions. The straight lines and right angles are used solely for convenience of representation of layers and features.

In the following description, semiconductor packaged devices/dies/packages, methods for manufacturing the same, and the likes are set forth as preferred examples. It will be apparent to those skilled in the art that modifications, including additions and/or substitutions may be made without departing from the scope and spirit of the present disclosure. Specific details may be omitted so as not to obscure the present disclosure; however, the disclosure is written to enable one skilled in the art to practice the teachings herein without undue experimentation.

To satisfy market demands toward increased miniaturization and functionality, the electronic device is developed to be more compact, and the circuit therein is designed to be fine-pitch. However, when the electronic device is operated, it generates a great quantity of heat. If the heat is not released timely, that can jeopardize performance of the device and operating life. Hence, for ensuring reliability, it is necessary to improve the device's heat dissipation.

At least for avoiding the aforesaid issues, the present disclosure provides a novel structure/arrangement for the semiconductor packaged device.

FIG. 1A is a vertical cross-sectional view of the semiconductor packaged device 1A according to some embodiments of the present disclosure. FIG. 1B is a vertical cross-sectional view of a semiconductor die 10 in the semiconductor packaged device 1A of the FIG. 1A.

Referring to FIGS. 1A and 1B, a semiconductor packaged device 1A includes a semiconductor die 10, a heat dissipation structure 20, a plurality of conductive pads 22, a passivation layer 30, a plurality of conductive pads 40, a conductive structure CS (including a dielectric layer 50, a conductive layer 52, and a dielectric layer 54) , a heat dissipation structure 60, and a plurality of conductive bumps 92.

The semiconductor die 10 has a top surface TS, a bottom surface BS, a pair of side surfaces SS. The top surface TS is opposite to the back surface BS. Each of the side surfaces SS connects the top surface TS to the back surface BS. In the embodiments, the side surfaces SS can be inclined side surfaces, and the semiconductor die 10 can have a trapezoid profile.

The top surface TS of the semiconductor die 10 can contain analog or digital circuits implemented as active devices, passive devices, conductive layers, and dielectric layers formed within the die and electrically interconnected according to the electrical design and function of the die. For example, the circuit may include one or more transistors, diodes, or other circuit elements formed within top surface TS to implement analog circuits or digital circuits, and thus the top surface TS can be an active surface of the semiconductor die 10.

In some embodiments, the semiconductor die 10 can include a transistor. The transistor can be formed adjacent to the top surface TS of the semiconductor die 10. In some embodiments, the transistor is a GaN-based transistor. FIG. 1B is a vertical cross-sectional view of a semiconductor die 10 in the semiconductor packaged device 1A of the FIG. 1A. The transistor 10 includes a substrate 102, a nitride-based semiconductor layer 103, a nitride-based semiconductor layer 104,

electrodes

105, 106, a doped nitride-based semiconductor layer 107, and a gate electrode 108. The detailed configuration of the transistor 1A is fully depicted as shown in FIG. 1B.

Referring to FIG. 1B, the substrate 102 may be a semiconductor substrate. The exemplary materials of the substrate 102 can include, for example but are not limited to, Si, SiGe, SiC, gallium arsenide, p-doped Si, n-doped Si, sapphire, semiconductor on insulator, such as silicon on insulator (SOI) , or other suitable substrate materials. In some embodiments, the substrate 102 can include, for example, but is not limited to, group III elements, group IV elements, group V elements, or combinations thereof (e.g., III-V compounds) . In other embodiments, the substrate 102 can include, for example but is not limited to, one or more other features, such as a doped region, a buried layer, an epitaxial (epi) layer, or combinations thereof.

In some embodiments, the transistor can include a buffer layer (not shown) . The buffer layer (not shown) can be disposed on/over/above the substrate 102. The buffer layer can be disposed between the substrate 102 and the nitride-based semiconductor layer 103. The buffer layer can be configured to reduce lattice and thermal mismatches between the substrate 102 and the nitride-based semiconductor layer 103, thereby curing defects due to the mismatches/difference. The buffer layer may include a III-V compound. The III-V compound can include, for example but are not limited to, aluminum, gallium, indium, nitrogen, or combinations thereof. Accordingly, the exemplary materials of the buffer layer can further include, for example but are not limited to, GaN, AlN, AlGaN, InAlGaN, or combinations thereof.

In some embodiments, the transistor may further include a nucleation layer (not shown) . The nucleation layer may be formed between the substrate 102 and the buffer layer. The nucleation layer can be configured to provide a transition to accommodate a mismatch/difference between the substrate 102 and a III-nitride layer of the buffer layer. The exemplary material of the nucleation layer can include, for example but is not limited to AlN or any of its alloys.

The nitride-based semiconductor layer 103 is disposed on/over/above the substrate 102. The nitride-based semiconductor layer 104 is disposed on/over/above the nitride-based semiconductor layer 103. The exemplary materials of the nitride-based semiconductor layer 103 can include, for example but are not limited to, nitrides or group III-V compounds, such as GaN, AlN, InN, In _xAl _yGa _(1–x–y) N where x+y ≤ 1, Al _xGa _(1–x) N where x ≤ 1. The exemplary materials of the nitride-based semiconductor layer 104 can include, for example but are not limited to, nitrides or group III-V compounds, such as GaN, AlN, InN, In _xAl _yGa _(1–x–y) N where x+y ≤ 1, Al _yGa _(1–y) N where y ≤ 1.

The exemplary materials of the nitride-based semiconductor layers 103 and 104 are selected such that the nitride-based semiconductor layer 104 has a bandgap (i.e., forbidden band width) greater than a bandgap of the nitride-based semiconductor layer 103, which causes electron affinities thereof different from each other and forms a heterojunction therebetween. For example, when the nitride-based semiconductor layer 103 is an undoped GaN layer having a bandgap of approximately 3.4 eV, the nitride-based semiconductor layer 104 can be selected as an AlGaN layer having bandgap of approximately 4.0 eV. As such, the nitride-based semiconductor layers 103 and 104 can serve as a channel layer and a barrier layer, respectively. A triangular well potential is generated at a bonded interface between the channel and barrier layers, so that electrons accumulate in the triangular well, thereby generating a two-dimensional electron gas (2DEG) region adjacent to the heterojunction. Accordingly, the transistor is available to include at least one GaN-based high-electron-mobility transistor (HEMT) .

The

electrodes

105 and 106 are disposed on/over/above the nitride-based semiconductor layer 104. The

electrodes

105 and 106 can make contact with the nitride-based semiconductor layer 104. In some embodiments, the electrode 105 can serve as a source electrode. In some embodiments, the electrode 105 can serve as a drain electrode. In some embodiments, the electrode 106 can serve as a source electrode. In some embodiments, the electrode 106 can serve as a drain electrode. The role of the

electrodes

105 and 106 depends on the device design.

In some embodiments, the

electrodes

105 and 106 can include, for example but are not limited to, metals, alloys, doped semiconductor materials (such as doped crystalline silicon) , compounds such as silicides and nitrides, other conductor materials, or combinations thereof. The exemplary materials of the

electrodes

105 and 106 can include, for example but are not limited to, Ti, AlSi, TiN, or combinations thereof. Each of the electrodes 1024 and 1025 may be a single layer, or plural layers of the same or different composition. The

electrodes

105 and 106 form ohmic contacts with the nitride-based semiconductor layer 104. Furthermore, the ohmic contacts can be achieved by applying Ti, Al, or other suitable materials to the

electrodes

105 and 106.

In some embodiments, each of the

electrodes

105 and 106 is formed by at least one conformal layer and a conductive filling. The conformal layer can wrap the conductive filling. The exemplary materials of the conformal layer can include, for example but are not limited to, Ti, Ta, TiN, Al, Au, AlSi, Ni, Pt, or combinations thereof. The exemplary materials of the conductive filling can include, for example but are not limited to, AlSi, AlCu, or combinations thereof.

The doped nitride-based semiconductor layer 107 is disposed on/over/above the nitride-based semiconductor layer 104. The gate electrode 108 is disposed/stacked on the doped nitride-based semiconductor layer 107. The doped nitride-based semiconductor layer 107 and the gate electrode 1027 are disposed between the

electrodes

105 and 106.

A width of the doped nitride-based semiconductor layer 107 is greater than that of the gate electrode 108. In some embodiments, a width of the doped nitride-based semiconductor layer 107 is substantially the same as a width of the gate electrode 108. The relationship of the widths of the doped nitride-based semiconductor layer 107 and the gate electrode 108 can depend on the device design.

In the exemplary illustration of FIG. 1B, the transistor is an enhancement mode device, which is in a normally-off state when the gate electrode 108 is at approximately zero bias. Specifically, the doped nitride-based semiconductor layer 107 may create at least one p-n junction with the nitride-based semiconductor layer 104 to deplete the 2DEG region, such that at least one zone of the 2DEG region corresponding to a position below the corresponding the gate electrode 108 has different characteristics (e.g., different electron concentrations) than the remain of the 2DEG region and thus is blocked.

Due to such mechanism, the transistor has a normally-off characteristic. In other words, when no voltage is applied to the gate electrode 108 or a voltage applied to the gate electrode 108 is less than a threshold voltage (i.e., a minimum voltage required to form an inversion layer below the gate electrode 108) , the zone of the 2DEG region below the gate electrode 108 is kept blocked, and thus no current flows therethrough.

In some embodiments, the doped nitride-based semiconductor layer 107 can be omitted, such that the transistor is a depletion-mode device, which means the transistor in a normally-on state at zero gate-source voltage.

The doped nitride-based semiconductor layer 107 can be a p-type doped III-V semiconductor layer. The exemplary materials of the doped nitride-based semiconductor layer 107 can include, for example but are not limited to, p-doped group III-V nitride semiconductor materials, such as p-type GaN, p-type AlGaN, p-type InN, p-type AlInN, p-type InGaN, p-type AlInGaN, or combinations thereof. In some embodiments, the p-doped materials are achieved by using a p-type impurity, such as Be, Zn, Cd, and Mg. In some embodiments, the nitride-based semiconductor layer 103 includes undoped GaN and the nitride-based semiconductor layer 104 includes AlGaN, and the doped nitride-based semiconductor layer 107 is a p-type GaN layer which can bend the underlying band structure upwards and to deplete the corresponding zone of the 2DEG region, so as to place the transistor into an off-state condition.

The exemplary materials of the gate electrode 108 may include metals or metal compounds. The gate electrode 108 may be formed as a single layer, or plural layers of the same or different compositions. The exemplary materials of the metals or metal compounds can include, for example but are not limited to, W, Au, Pd, Ti, Ta, Co, Ni, Pt, Mo, TiN, TaN, metal alloys or compounds thereof, or other metallic compounds.

Referring back to FIG. 1A, the heat dissipation structure 20 can be disposed under the semiconductor die 10. The heat dissipation structure 20 makes contact with the bottom surface BS of the semiconductor die 10, and thus the semiconductor die 10 is thermally coupled to the heat dissipation structure 20. In the present disclosure, the heat dissipation structure includes a material with high thermal conductivity, such as metal. The heat dissipation structure 20 can be, for example, planar structure/thin film structure. The heat dissipation structure 20 makes contact with an entirety of the bottom surface BS of the semiconductor die 10. Thus, a thermal conductive path, from the back surface BS of the semiconductor die 10 through the heat dissipation structure 20 to an underside region of the semiconductor packaged device 1A, is formed.

The conductive pads 22 (i.e., conductive member) are disposed on/over/above the top surface TS of the semiconductor die 10. The conductive pads 22 makes contact with the top surface TS of the semiconductor die 10. The exemplary materials of the conductive pads 22 can include, for example but are not limited to, metal, metal alloys or compounds thereof, or other metallic compounds.

The passivation layer 30 is disposed on/over/above the top surface TS of the semiconductor die 10. The passivation layer 30 makes contact with the top surface TS of the semiconductor die 10. The conductive pads 22 and the passivation layer 30 collectively cover an entirety of the top surface TS of the semiconductor die 10. The conductive pads 22 are separated by the passivation layer 30. Side surfaces/walls of the conductive pads 22 make contact with the passivation layer 30. Each of the conductive pads 22 is confined by the passivation layer 30.

The exemplary materials of the passivation layer 30 can include, for example but are not limited to, dielectric materials. For example, the passivation layer 50 can include, for example but are not limited to, SiN _x, SiO _x, Si ₃N ₄, SiON, SiC, SiBN, SiCBN, oxides, nitrides, plasma enhanced oxide (PEOX) , or combinations thereof. In some embodiments, the passivation layer 30 can be a multi-layered structure, such as a composite dielectric layer of Al ₂O ₃/SiN, Al ₂O ₃/SiO ₂, AlN/SiN, AlN/SiO ₂, or combinations thereof. Thus, by such a material selection, the passivation layer 30 can serve as an insulation layer.

The conductive pads 40 (i.e., conductive member) are disposed on/over/above the conductive pads 22. The conductive pads 40 cover/make contact with top surfaces of the conductive pads 22, respectively. The conductive pad 20 has a width greater than that of the conductive pad 40, and thus a part of the top surface of the conductive pad 20 is covered by the conductive pad 40. The conductive pads 22 are located directly under the conductive pads 40, respectively, such that each of the conductive pads 22 is sandwiched between the conductive pad 40 and the semiconductor die 10. The exemplary materials of the conductive pads 40 can include, for example but are not limited to, metal, metal alloys or compounds thereof, or other metallic compounds.

The conductive structure CS covers the top surface TS and side surfaces SS of the semiconductor die 10, and

conductive pads

22, 40. The conductive structure CS includes a dielectric layer 50, a conductive layer 52, and a dielectric layer 54.

The dielectric layer 50 (e.g., bottom dielectric layer) includes a side portion and a main portion (e.g., middle portion) . The main portion of the dielectric layer 50 covers a top surface of the conductive pad 22 and a top surface of the passivation layer 30. The side portion of the dielectric layer 50 makes contact with/covers a top surface of the conductive pad 22, a top and a side surfaces of the passivation layer 30, the inclined side surface SS of the semiconductor die 10, and a side surface 20SS of the heat dissipation structure 20A. The side portion of the dielectric layer 50 is conformally disposed with the passivation layer 30 and the semiconductor die 10. The side portion of the dielectric layer 50 extends from a position (e.g., a side surface of the conductive pad 401) over the top surface of the conductive pad 22 to a position having a height level substantially the same as the bottom surface BS of the semiconductor die 10 (or a position adjacent to a side surface SS of the heat dissipation structure 20) along the inclined side surface SS of the semiconductor die 10, in which the conductive pad 401 is the closest conductive pad to an edge of the semiconductor die 10 among the conductive pads 40.

The exemplary materials of the dielectric layer 50 can include, for example but are not limited to, dielectric materials. For example, the dielectric layer 50 can include, for example but are not limited to, SiN _x, SiO _x, Si ₃N ₄, SiON, SiC, SiBN, SiCBN, oxides, nitrides, plasma enhanced oxide (PEOX) , or combinations thereof. In some embodiments, the dielectric layer 50 can be a multi-layered structure, such as a composite dielectric layer of Al ₂O ₃/SiN, Al ₂O ₃/SiO ₂, AlN/SiN, AlN/SiO ₂, or combinations thereof. Thus, by such a material selection, the dielectric layer 50 can serve as an insulation layer.

The conductive layer 52 is disposed on/over/above the side portion of the dielectric layer 50. The conductive layer 52 is conformally disposed with the side portion of the dielectric layer 50. The conductive layer 52 covers/makes contact with the side portion of the dielectric layer 50. The conductive layer 52 extends from a position over the top surface of the conductive pad 22 to a position having a height level substantially the same as the bottom surface BS of the semiconductor die 10 along a top and a side surface of the dielectric layer 50. The conductive layer 52 extends laterally first, and then extends inclinedly and downward to a position having a height level substantially the same as the bottom surface BS of the semiconductor die 10, such that the conductive layer 52 is substantially parallel to the inclined side surface SS of the semiconductor die 10. An end portion of the conductive layer 52 makes contact with a side surface of the conductive pad 401, such that the conductive layer 52 can be electrically coupled to the semiconductor die 10 through the

conductive pads

401, 22. The conductive layer 52 and the dielectric layer 50 collectively cover a side surface of the conductive pad 401. The conductive layer 52 is separated/spaced apart from the heat dissipation structure 20 by the dielectric layer 50. In some embodiments, the conductive layer 52 may have metal lines, pads, traces, or combinations thereof, such that the conductive layer 52 can form at least one circuit. Hence, the conductive layer 52 can serve as a circuit structure. An external electronic device can send at least one electronic signal to the semiconductor die 1A by the conductive layer 52, and vice versa.

The exemplary materials of the conductive layer 52 can be, for example, metal materials. The metal materials can include, for example but are not limited to, Ag, Cu, Au, Al, Mo, W, Zn or metal alloy.

The dielectric layer 54 (e.g., upper dielectric layer) includes a side portion and a main portion. The main portion of the dielectric layer 54 covers a top surface of the passivation layer 30 and a top surface of the main portion of the dielectric layer 50. The main portion of the dielectric layer 54 makes contact with the main portion of the dielectric layer 50, such that the two main portions of the

dielectric layers

50 and 54 can be merged as a thicker dielectric layer. The merged dielectric layer MD can include a plurality of portions, and each of the portions thereof extending between two of corresponding adjacent conductive pads 40 to provide an insulation function therebetween. The side portion of the dielectric layer 54 extends from a position over the top surface of the conductive pad 40 to a position having a height level substantially the same as the bottom surface BS of the semiconductor die 10. Thus, end surfaces of the

dielectric layers

50, 54, an end surface of the conductive layer 52, and the bottom surface BS of the heat dissipation structure 20 are substantially coplanar with each other. The side portion of the dielectric layer 54 covers a top surface of the conductive pad 401 and the conductive layer 52, such that the conductive layer 52 can be protected. The conductive layer 52 extends in a region between the

dielectric layers

50, 54. Thus, the dielectric layer 54 can serve as a protection layer.

The exemplary materials of the dielectric layer 54 can include, for example but are not limited to, dielectric materials. For example, the dielectric layer 54 can include, for example but are not limited to, SiN _x, SiO _x, Si ₃N ₄, SiON, SiC, SiBN, SiCBN, oxides, nitrides, plasma enhanced oxide (PEOX) , or combinations thereof. In some embodiments, the dielectric layer 54 can be a multi-layered structure, such as a composite dielectric layer of Al ₂O ₃/SiN, Al ₂O ₃/SiO ₂, AlN/SiN, AlN/SiO ₂, or combinations thereof. Thus, by such a material selection, the dielectric layer 54 can serve as an insulation layer.

The heat dissipation structure 60 is disposed on/over/above the top surface TS of the semiconductor die. The heat dissipation structure 60 is vertically separated from the semiconductor die 10 by the conductive bumps 92. The heat dissipation structure 60 includes a dielectric body 62, a conductive layer 64, and a plurality of conductive vias 66.

The dielectric body 62 has a plurality through holes. Each of the conductive vias 66 penetrates the dielectric body 62 via the corresponding through hole of the dielectric body 62. The conductive layer 64 is disposed on/over/above a top surface of the dielectric body 62 and top surfaces of the conductive vias 66.

The exemplary materials of the dielectric body 62 can include, for example but are not limited to, dielectric materials. For example, the dielectric body 62 can include, for example but are not limited to, SiN _x, SiO _x, Si ₃N ₄, SiON, SiC, SiBN, SiCBN, oxides, nitrides, plasma enhanced oxide (PEOX) , or combinations thereof. In some embodiments, the dielectric body 62 can be a multi-layered structure, such as a composite dielectric layer of Al ₂O ₃/SiN, Al ₂O ₃/SiO ₂, AlN/SiN, AlN/SiO ₂, or combinations thereof. Thus, by such a material selection, the dielectric body 60 can serve as an insulation layer.

The exemplary materials of the conductive layer 64 and the conductive vias 66 can be, for example, metal materials. The metal materials can include, for example but are not limited to, Ag, Cu, Au, Al, Mo, W, Zn or metal alloy.

The conductive bumps 92 (e.g., solder bumps/conductive member) are disposed between the heat dissipation structure 60 and the semiconductor die 10. Each of the conductive bumps 92 makes contact with the dielectric body 62 and the conductive via 66. Each of the conductive bumps 92 penetrates the dielectric layer 54 to make contact with/align with the corresponding conductive pad 40. The conductive vias 66 are disposed within the dielectric body 62 and extend vertically to make contact with the conductive layer 62 and the conductive bumps 92, and thus the heat dissipation structure 60 can be thermally/electrically coupled to the semiconductor die 10 through the conductive bumps 92, and

conductive pads

40, 22.

The exemplary materials of the conductive bumps 92 can include, for example but are not limited to, Al, Cu, Sn, Ni, Au, Ag or a combination thereof.

By such a configuration, an additional thermal conductive path, from the top surface TS of the semiconductor die 10 through the heat dissipation structure 60 to an upperside region of the semiconductor packaged device 1A, is formed. Thus, heat generated during the operation of the semiconductor packaged device 1A can be dissipated by the

heat dissipation structures

20, 60; and therefore, a dual-side cooled semiconductor die 10 can be achieved. In the embodiment, the conductive layer 64 makes contact with an entirety of the top surface of the dielectric body 62, a large heat dissipation area can be achieved by such a configuration.

In some embodiments, the conductive layer 64 of the heat dissipation structure 60 may have metal lines, pads, traces, or combinations thereof, such that the conductive layer 64 can form at least one circuit. That is to say, the conductive layer 64 can serve as a circuit layer. Hence, the heat dissipation structure 60 can serve as a circuit structure. An external electronic device can send at least one electronic signal to the semiconductor die 10 by the conductive layer 64, and vice versa.

In some embodiments, the conductive layer 52 of the conducive structure CS is designed to have a width different from that of the conductive via 66 of the heat dissipation structure 60. For example, the conductive layer 52 is designed to have a width greater than the conductive via 66. Thus, the conductive layer 64 and conductive vias 66 of the heat dissipation structure 60, and the conductive layer 52 of the circuit structure CS can achieve different circuit functions. In other words, the semiconductor packaged device 1A can achieve multiple circuit functions in a small volume, which means the semiconductor packaged device 1A can meet a high-density circuit requirement. For example, the electrical connection path from an external device to the semiconductor packaged device 1A can be constituted via either the conductive layer 52 or the conductive layer 64, which makes the design more flexible.

In addition, since the circuit structure CS and the heat dissipation structure 60 are disposed at different positions (e.g., the circuit structure CS is disposed at an inclined side surface SS of the semiconductor die 10 and the heat dissipation structure 60 is disposed on a top of the semiconductor die) , a signal interference issue therebetween can be further reduced.

Different stages of a method for manufacturing the semiconductor packaged device 1A are shown in FIG. 2A, FIG. 2B, FIG. 2C, FIG 2D, FIG 2E, FIG. 2F, FIG. 2G, FIG. 2H, FIG. 2I, and FIG. 2J described below. In the following, deposition techniques can include, for example but are not limited to, atomic layer deposition (ALD) , physical vapor deposition (PVD) , chemical vapor deposition (CVD) , metal organic CVD (MOCVD) , plasma enhanced CVD (PECVD) , low-pressure CVD (LPCVD) , plasma-assisted vapor deposition, epitaxial growth, or other suitable processes.

Referring to FIG. 2A, an intermediate semiconductor die 1 is provided, in which the intermediate semiconductor die 1 has, for example, a rectangular profile. A plurality of conductive pads 22 and an intermediate passivation layer 7 are collectively formed on/over/above a top surface of the intermediate semiconductor die 1.

Referring to FIG. 2B, a heat dissipation structure 20 is formed under a bottom surface of the intermediate semiconductor die 1, in which the heat dissipation structure 20 can be a metal layer. The formation of the heat dissipation structure 20 can include a metallization process. Then, a temporary substrate TS is provided. The resulted structure in the FIG. 2A is attached on the temporary substrate TS through the heat dissipation structure 20, in which the heat dissipation structure 20 can serve as an attached layer.

In some embodiments, a cutting process can be performed on the intermediate semiconductor die 1 and the intermediate passivation layer 7 with a cutting tool C, such that side portions of the intermediate semiconductor die 1 and side portions/edge portions of the intermediate passivation layer 7 are removed, thereby forming a passivation layer 30 having inclined surfaces and a semiconductor die 10 having inclined surfaces SS. Thus, a semiconductor die 10 having inclined side surfaces SS is formed. In some embodiments, a plasma treatment can be performed on the intermediate semiconductor die 1 and the intermediate passivation layer 7, thereby forming the passivation layer 30 and the semiconductor die 10, and the present disclosure is not limited thereto.

Referring to FIG. 2C, a dielectric layer 50 is formed to cover the passivation layer 30, the semiconductor die 10, in which the dielectric layer 50 is formed to have a plurality of through holes to expose the conductive pads 22, respectively.

Referring to FIG. 2D, a plurality of conductive pads 40 are formed on/over/above a top surface TS of the semiconductor die 10. The conductive pads 40 are formed on/over/above the conductive pads 22, respectively. The plurality of conductive pads 40 are formed in the through holes of the dielectric layer 50 to make contact with the conductive pads 22, respectively, such that the conductive pads 40 are electrically coupled to the semiconductor die 10. A conductive layer 52 is formed to cover a side portion of the dielectric layer 50. The conductive layer 52 is formed to extend from a top of the semiconductor die 10 to a side of the semiconductor die along the inclined side surface SS. The conductive layer 52 is formed to make contact with the conductive pad 401. The conductive layer 52 is formed to extend from a top of the semiconductor die 10 to a side of the semiconductor die 10 along the inclined side surface SS.

Referring to FIG. 2E, a dielectric layer 54 is formed to cover the dielectric layer 50, a plurality of conductive pads 40, and the conductive layer 52. The conductive layer 52 is sandwiched between the formed

dielectric layers

50, 54.

Referring to FIG. 2F, an intermediate dielectric body DB is provided. A patterning process is performed on the intermediate dielectric body DB, such that a plurality of holes H are formed therein. Then, a conductive material CM is formed to fill up the holes H and cover a top surface of the intermediate dielectric body DB.

Referring to FIG. 2G, a thinning process is performed on the intermediate dielectric body DB to remove a bottom portion of the intermediate dielectric body DB, and the bottom surfaces of the conductive material CM are exposed. The remaining portion of the intermediate dielectric body DB can serve as the aforesaid dielectric body 62 of the heat dissipation structure 60. A top portion of the conductive material CM can serve as the aforesaid conductive layer 64 of the heat dissipation structure 60. The portions of the conductive material CM in the holes H can serve as a plurality of conductive vias 66 of the heat dissipation structure 60. Thus, a heat dissipation structure 60 is formed.

Referring to FIG. 2H, a plurality of conductive bumps 92 are formed/mounted under the heat dissipation structure 60 to make contact with the bottom surfaces of the conductive vias 66.

Referring to FIG. 2I, the heat dissipation structure 60 is brought/placed on a top of the semiconductor die 10, such that the conductive bumps 92 can make contact with the conductive pads 40, respectively. Thus, the heat dissipation structure 60 can be thermally and electrically connected/coupled to the semiconductor die 10 through the

conductive pads

22, 40 and the conductive bumps 92.

Referring to FIG. 2J, the temporary substrate TS is removed, such that end surfaces of the

dielectric layers

50, 54 and end surface of the conductive layer 52 are exposed. The end surfaces of the

dielectric layers

50, 54 and end surface of the conductive layer 52 are substantially coplanar with each other. Thus, a semiconductor device 1A in the FIG. 1A can be obtained.

FIG. 3 is a vertical cross-sectional view of a semiconductor packaged device 1B according to some embodiments of the present disclosure. The semiconductor packaged device 1B is similar to the semiconductor packaged device 1A as described and illustrated with reference to FIG. 1A, except that the heat dissipation structure 20B is an island-shaped structure. The heat dissipation structure 20B can include separated portions under the bottom surface BS of the semiconductor die 10; and thus at least a part of the back surface BS of the semiconductor die 10 is exposed. Such a configuration can meet a specific design requirement.

FIG. 4 is a vertical cross-sectional view of a semiconductor packaged device 1C according to some embodiments of the present disclosure. The semiconductor packaged device 1C is similar to the semiconductor packaged device 1A as described and illustrated with reference to FIG. 1A, except that the semiconductor packaged device 1C further includes a plurality of conductive pads P. Each of the conductive pads P makes contact with an end surface of the conductive layer 52. In one aspect, these conductive pads P can serve as extending portions of the conductive layer 52, such that the conductive layer 52 can protrude out end surfaces of the

dielectric layers

50, 54. Such a configuration can make the semiconductor packaged device 1C to be electrically connected/coupled with an external electronic device (not shown) easier.

The exemplary materials of the conductive layer P can be, for example, metal materials. The metal materials can include, for example but are not limited to, Ag, Cu, Au, Al, Mo, W, Zn or metal alloy.

FIG. 5 is a vertical cross-sectional view of a semiconductor packaged device 1D according to some embodiments of the present disclosure. The semiconductor packaged device 1D is similar to the semiconductor packaged device 1A as described and illustrated with reference to FIG. 1A, except that the semiconductor packaged device 1D further includes a plurality of the under-bump-metallurgy (UBM) layers 94. Each of the UBM layer 94, for example, can include a pad portion 94a and a retaining wall portion 94b surrounding the pad portion 94a. The conductive bump 92 can be mounted on the corresponding pad portion 94a.

In some embodiments, a reflow process may be applied to adhere the conductive bump 92 to the UBM layer 94. The conductive bump 92 may not flow outside of the UBM layer 94 to damage other elements of the semiconductor packaged device 1D, thereby improving manufacturing yield.

The exemplary materials of the UBM layer can include, for example but not limited thereto, Cu, Cu/Ni, Ti, W, Ni/Au, Ti/W or TiWN.

FIG. 6 is a vertical cross-sectional view of a semiconductor packaged device 1E according to some embodiments of the present disclosure. The semiconductor packaged device 1E is similar to the semiconductor packaged device 1D as described and illustrated with reference to FIG. 5, except that the semiconductor packaged device 1E includes a plurality of conductive members CM located between the heat dissipation structure 60 and the semiconductor die 10. Each of the conductive members CM includes a UBM layer 94, a conductive pillar 96, and a top conductive layer 98. The UBM layer 94 is located between the conductive pillar 96 and the conductive pad 40. The UBM layer 94 makes contact with the conductive pillar 96 and the conductive pad 40. The conductive pillar 96 is located between the conductive pad 98 and the conductive layer 98. The conductive pillar 96 makes contact with the top conductive layer 98 and the UBM layer 94. The top conductive layer 98 is located between the conductive via 66 and the conductive pillar 96. The top conductive layer 98 makes contact with the conductive via 66 and the conductive pillar 96. By such a configuration, the heat dissipation structure 60 can be thermally coupled to the semiconductor die 10 through the conductive members CM having the conductive pillars 96. In addition, by the configuration of conductive pillars 96, the semiconductor packaged device 1E can achieve a fine-pitch requirement.

FIG. 7 is a vertical cross-sectional view of a semiconductor packaged device 1F according to some embodiments of the present disclosure. The semiconductor packaged device 1F is similar to the semiconductor packaged device 1A as described and illustrated with reference to FIG. 1, except that the semiconductor packaged device 1F includes a heat dissipation structure 20F, in which the heat dissipation structure 20F includes a plurality of protruding portions (e.g., fin structure) extending downward. By such a configuration, heat dissipation area of the heat dissipation structure 20F can be further increased; and therefore, the heat dissipation ability of the semiconductor packaged device 1F can be further improved.

In some embodiments, the conductive layer 64 may have the protruding portions extending upward. Thus, heat dissipation area of the conductive layer 64 can be further increased.

Based on above, in the present disclosure, a semiconductor die is formed to have an inclined side surface. The semiconductor die is packaged with and thermally coupled to two heat dissipation structures. One of the heat dissipation structures is disposed over a top of the semiconductor die, and the other one is disposed under a bottom of the semiconductor die. Thus, the semiconductor packaged device can have good heat dissipation ability.

On the other hand, the circuit structure can be formed at the inclined side surface of the semiconductor die, and is electrically coupled to the semiconductor die. A circuit layer can be formed in the heat dissipation structure over the semiconductor die, and thus the heat dissipation structure over the semiconductor die can serve as another circuit structure. By such a configuration, the semiconductor packaging device can realize high integrated circuits in a small volume.

The embodiments were chosen and described in order to best explain the principles of the disclosure and its practical application, thereby enabling others skilled in the art to understand the disclosure for various embodiments and with various modifications that are suited to the particular use contemplated.

As used herein and not otherwise defined, the terms "substantially, " "substantial, " "approximately" and "about" are used to describe and account for small variations. When used in conjunction with an event or circumstance, the terms can encompass instances in which the event or circumstance occurs precisely as well as instances in which the event or circumstance occurs to a close approximation. For example, when used in conjunction with a numerical value, the terms can encompass a range of variation of less than or equal to ±10%of that numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. The term “substantially coplanar” can refer to two surfaces within micrometers of lying along a same plane, such as within 40 μm, within 30 μm, within 20 μm, within 10 μm, or within 1 μm of lying along the same plane.

As used herein, the singular terms “a, ” “an, ” and “the” may include plural referents unless the context clearly dictates otherwise. In the description of some embodiments, a component provided “on” or “over” another component can encompass cases where the former component is directly on (e.g., in physical contact with) the latter component, as well as cases where one or more intervening components are located between the former component and the latter component.

While the present disclosure has been described and illustrated with reference to specific embodiments thereof, these descriptions and illustrations are not limiting. It should be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the true spirit and scope of the present disclosure as defined by the appended claims. The illustrations may not necessarily be drawn to scale. There may be distinctions between the artistic renditions in the present disclosure and the actual apparatus due to manufacturing processes and tolerances. Further, it is understood that actual devices and layers may deviate from the rectangular layer depictions of the FIGS. and may include angles surfaces or edges, rounded corners, etc. due to manufacturing processes such as conformal deposition, etching, etc. There may be other embodiments of the present disclosure which are not specifically illustrated. The specification and the drawings are to be regarded as illustrative rather than restrictive. Modifications may be made to adapt a particular situation, material, composition of matter, method, or process to the objective, spirit and scope of the present disclosure. All such modifications are intended to be within the scope of the claims appended hereto. While the methods disclosed herein have been described with reference to particular operations performed in a particular order, it will be understood that these operations may be combined, sub-divided, or re-ordered to form an equivalent method without departing from the teachings of the present disclosure. Accordingly, unless specifically indicated herein, the order and grouping of the operations are not limitations.

Claims

A semiconductor packaged device, comprising:

a semiconductor die having a top surface, a bottom surface, and an inclined side surface connecting the top surface to the bottom surface;

a plurality of first conductive pads disposed over the top surface of the semiconductor die;

a conductive layer electrically connected with the semiconductor die through one of the first conductive pads, wherein the conductive layer extends laterally and downward along the inclined side surface of the semiconductor die;

a first heat dissipation structure disposed over the top surface of the semiconductor die and thermally coupled to the semiconductor die through the first conductive pads; and

a second heat dissipation structure disposed under the bottom surface of the semiconductor die and thermally coupled to the semiconductor die.
The semiconductor packaged device of any one of the proceeding claims, further comprising a plurality of second conductive pads and a passivation layer collectively covering the top surface of the semiconductor die, wherein the conductive layer is electrically connected to the semiconductor die through the first and second conductive pads.
The semiconductor packaged device of any one of the proceeding claims, wherein the second conductive pads are located directly under the first conductive pads, respectively.
The semiconductor packaged device of any one of the proceeding claims, wherein the second conductive pad has a width greater than that of the first conductive pad.
The semiconductor packaged device of any one of the proceeding claims, further comprising a first and a second dielectric layers, wherein the first dielectric layer covers the passivation layer and the second conductive pads, and the second dielectric layer covers the first conducive pads and the conductive layer.
The semiconductor packaged device of any one of the proceeding claims, wherein the conductive layer is sandwiched between the first and the second dielectric layers.
The semiconductor packaged device of any one of the proceeding claims, wherein the first dielectric layer has a portion making contact with the inclined side surface of the semiconductor die, such that the conductive layer is separated from the semiconductor die by the first dielectric layer.
The semiconductor packaged device of any one of the proceeding claims, wherein end surfaces of the first and second dielectric layer, an end surface of the conductive layer, and a bottom surface of the second heat dissipation structure are substantially coplanar with each other.
The semiconductor packaged device of any one of the proceeding claims, further comprising a plurality of conductive bumps, wherein each of the conductive bumps is located between the first heat dissipation structure and the first conductive pad, and the first heat dissipation structure is thermally coupled to the semiconductor die through the conductive bumps and the first conductive pads.
The semiconductor packaged device of any one of the proceeding claims, wherein the first heat dissipation structure is separated from the semiconductor die by the conductive bumps.
The semiconductor packaged device of any one of the proceeding claims, wherein the first heat dissipation structure further comprises:

a dielectric body;

a second conductive layer disposed over a top surface of the dielectric body; and

a plurality of conductive vias disposed within the dielectric body and extend vertically to make contact with the second conductive layer and the conductive bumps.
The semiconductor packaged device of any one of the proceeding claims, wherein a width of the conductive via is greater than that of the conductive layer.
The semiconductor packaged device of any one of the proceeding claims, wherein each of the conductive bumps makes contact with the dielectric body and the conductive via.
The semiconductor packaged device of any one of the proceeding claims, wherein the second heat dissipation structure comprises a planar structure.
The semiconductor packaged device of any one of the proceeding claims, wherein the second heat dissipation structure makes contact with an entirety of the bottom surface of the semiconductor die.
A manufacturing method of the semiconductor packaged device, comprising:

forming a semiconductor die having an inclined side surface;

forming a heat dissipation structure under a bottom surface of the semiconductor die;

forming a plurality of first conductive pads over a top surface of the semiconductor die, wherein the first conductive pads are electrically coupled to the semiconductor die;

forming a conductive layer to be electrically connected to one of the first conductive pads, wherein the conductive layer is formed to extend from a top of the semiconductor die to a side of the semiconductor die along the inclined side surface; and

forming another heat dissipation structure over the top surface of the semiconductor die.
The manufacturing method of any one of the proceeding claims, wherein the step of forming the semiconductor die further comprises:

removing at least one side portion of an intermediate semiconductor die, such that the inclined side surface of the semiconductor die is formed.
The manufacturing method of any one of the proceeding claims, wherein prior the step of removing at least one side portion of the intermediate semiconductor die, the method further comprises:

forming a plurality of second conductive pads and a passivation layer to collectively cover a top surface of the intermediate semiconductor die.
The manufacturing method of any one of the proceeding claims, wherein the step of forming the another heat dissipation structure further comprises:

forming a dielectric body with a plurality of holes;

forming a conductive material to fill up the holes and cover a top surface of the intermediate dielectric body; and

thinning the intermediate dielectric body to expose bottom surfaces of the conductive material.
The manufacturing method of any one of the proceeding claims, wherein after the step of forming the another heat dissipation structure, the method further comprises:

forming a plurality of conductive bumps under the another heat dissipation structure.
A semiconductor packaged device, comprising:

a semiconductor die;

a first circuit structure disposed over a top surface of the semiconductor die;

a plurality of conductive members disposed between the semiconductor die and the first circuit structure, and the semiconductor die is electrically coupled to first circuit structure through the conductive members; and

a second circuit structure making contact with a side surface of a first conductive member of the conductive members to be electrically coupled to the semiconductor die, wherein the second circuit structure extends inclinedly and downward, such that the second circuit structure is substantially parallel to an inclined side surface of the semiconductor die.
The semiconductor packaged device of any one of the proceeding claims, wherein the first conductive member is one of the conductive members closest to an edge of the semiconductor die.
The semiconductor packaged device of any one of the proceeding claims, wherein the conductive member comprises a conductive pillar and an under-bump-metallurgy (UBM) layer, wherein the UBM layer is located between the conductive pillar and the semiconductor die, and the conductive pillar is located between the first circuit structure and the UBM layer.
The semiconductor packaged device of any one of the proceeding claims, further comprising a heat dissipation structure disposed under a bottom surface of the semiconductor die opposite to the top surface thereof.
The semiconductor packaged device of any one of the proceeding claims, further comprising an insulation layer conformally disposed with the inclined side surface of the semiconductor die, wherein the second circuit structure is spaced apart from the semiconductor die by the insulation layer.