WO2023201697A1

WO2023201697A1 - Semiconductor packaged device and method for manufacturing the same

Info

Publication number: WO2023201697A1
Application number: PCT/CN2022/088445
Authority: WO
Inventors: Ergang Xu; Kai Cao; Lei Zhang
Original assignee: Innoscience Suzhou Semiconductor Co Ltd
Current assignee: Innoscience Suzhou Semiconductor Co Ltd
Priority date: 2022-04-22
Filing date: 2022-04-22
Publication date: 2023-10-26
Anticipated expiration: 2024-10-22
Also published as: CN116097429A

Abstract

A semiconductor device includes a first semiconductor die, a second semiconductor die, and an encapsulant. The first semiconductor die includes a first transistor. The second semiconductor die is disposed above the first semiconductor die and includes a second transistor. The encapsulant encapsulates the first semiconductor die. The first semiconductor die is fully embedded in the encapsulant with an active surface and a back surface of the first semiconductor die covered by the encapsulant. The second semiconductor die has an active surface free from coverage of the encapsulant and a back surface covered by the encapsulant and facing toward the active surface of the first semiconductor die.

Description

SEMICONDUCTOR PACKAGED DEVICE AND METHOD FOR MANUFACTURING THE SAME

Inventors: Ergang XU, Kai CAO, Lei ZHANG

Field of the Disclosure:

The present disclosure generally relates to a nitride-based semiconductor packaged device. More specifically, the present disclosure relates to a fan-out nitride-based semiconductor packaged device.

Background of the Disclosure:

In recent years, intense research on high-electron-mobility transistors (HEMTs) has been prevalent, particularly for high power switching and high frequency applications. III-nitride-based HEMTs utilize a heterojunction interface between two materials with different bandgaps to form a quantum well-like structure, which accommodates a two-dimensional electron gas (2DEG) region, satisfying demands of high power/frequency devices. In addition to HEMTs, examples of devices having heterostructures further include heterojunction bipolar transistors (HBT) , heterojunction field effect transistor (HFET) , and modulation-doped FETs (MODFET) .

Summary of the Disclosure:

In accordance with one aspect of the present disclosure, a semiconductor packaging device is provided. A semiconductor device includes a first semiconductor die, a second semiconductor die, and an encapsulant. The first semiconductor die includes a first transistor. The second semiconductor die is disposed above the first semiconductor die and includes a second transistor. The encapsulant encapsulates the first semiconductor die. The first semiconductor die is fully embedded in the encapsulant with an active surface and a back surface of the first semiconductor die covered by the encapsulant. The second semiconductor die has an active surface free from coverage of the encapsulant and a back surface covered by the encapsulant and facing toward the active surface of the first semiconductor die.

In accordance with one aspect of the present disclosure, a method for manufacturing a semiconductor device is provided. The method includes steps as follows. A first semiconductor die is disposed on a substrate. A conductive layer is formed on the first semiconductor die. A second semiconductor die is disposed over the first semiconductor die with the second semiconductor die electrically coupling with the conductive layer. An encapsulant encapsulates the first and second semiconductor dies and covers the substrate. The first semiconductor die is debonded from the substrate such that the first semiconductor die has an active surface exposed from the encapsulant.

In accordance with one aspect of the present disclosure, a semiconductor device is provided. A semiconductor packaged device includes a first semiconductor die, a second semiconductor die, and an encapsulant. The first semiconductor die includes a first transistor. The second semiconductor die is disposed above the first semiconductor die and includes a second transistor. The encapsulant encapsulates the first semiconductor die and receives the second semiconductor die. The first semiconductor die and the second semiconductor die have back surfaces facing away from a top surface of the encapsulant, and the back surface of the first semiconductor die is deeper than the back surface of the second semiconductor die with respect to the top surface of the encapsulant.

By the above configuration, in the semiconductor packaged device, first and second semiconductor dies are encapsulated by the encapsulant according to their operation voltage range. Hence, the aforesaid arrangement provides a good thermal management to the semiconductor packaged device, such that the thermal dissipation ability and reliability of the semiconductor packaged device can be improved.

Brief Description of the Drawings:

Aspects of the present disclosure are readily understood from the following detailed description when read with the accompanying figures. It should be noted that various features may not be drawn to scale. That is, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. Embodiments of the present disclosure are described in more detail hereinafter with reference to the drawings, in which:

FIG. 1 is a vertical cross-sectional view of a semiconductor packaged device according to some embodiments of the present disclosure;

FIG. 2A is a partial enlargement of the structure in the semiconductor die according to some embodiments of the present disclosure;

FIG. 2B is a partial enlargement of the structure in the semiconductor die according to some embodiments of the present disclosure; and

FIG. 3A, FIG. 3B, FIG. 3C, FIG. 3D, FIG. 3E, FIG. 3F, FIG. 3G, FIG. 3H, FIG. 3I, and FIG. 3J show different stages of a method for manufacturing a semiconductor packaged device according to some embodiments of the present disclosure.

Detailed Description:

Common reference numerals are used throughout the drawings and the detailed description to indicate the same or similar components. Embodiments of the present disclosure will be readily understood from the following detailed description taken in conjunction with the accompanying drawings.

Spatial descriptions, such as "on, " "above, " "below, " "up, " "left, " "right, " "down, " "top, " "bottom, " "vertical, " "horizontal, " "side, " "higher, " "lower, " "upper, " "over, " "under, " and so forth, are specified with respect to a certain component or group of components, or a certain plane of a component or group of components, for the orientation of the component (s) as shown in the associated figure. It should be understood that the spatial descriptions used herein are for purposes of illustration only, and that practical implementations of the structures described herein can be spatially arranged in any orientation or manner, provided that the merits of embodiments of this disclosure are not deviated from by such arrangement.

Further, it is noted that the actual shapes of the various structures depicted as approximately rectangular may, in actual device, be curved, have rounded edges, have somewhat uneven thicknesses, etc. due to device fabrication conditions. The straight lines and right angles are used solely for convenience of representation of layers and features.

In the following description, semiconductor devices/dies/packages, methods for manufacturing the same, and the likes are set forth as preferred examples. It will be apparent to those skilled in the art that modifications, including additions and/or substitutions may be made without departing from the scope and spirit of the present disclosure. Specific details may be omitted so as not to obscure the present disclosure; however, the disclosure is written to enable one skilled in the art to practice the teachings herein without undue experimentation.

FIG. 1 is a vertical cross-sectional view of a semiconductor packaged device 1A according to some embodiments of the present disclosure. In order to meet variety of needs of consumers and achieve the purpose of light, thin and short electronic devices, the electronic devices become more densely populated. Currently, the mainstream of manufacturing a semiconductor device is to encapsulate multiple semiconductor dies with different functions in a small volume. At least for a purpose of achieving different functions in a semiconductor packaged device 1A, the semiconductor packaged device 1A at least includes two semiconductor dies 10, 12 with different functions, which means that the semiconductor packaged device 1A is a dual-die package.

Specifically, the semiconductor packaged device 1A includes semiconductor dies 10, 12, a circuit structure CS1, a plurality of conductive bumps 38 (i.e., solder bumps) , a dielectric layer 40, a conductive layer 42, an encapsulant 44, a circuit structure CS2, and a plurality of conductive bumps 54. The circuit structure CS1 includes a dielectric layer 30, a redistribution layer 32, a dielectric layer 34, and a plurality of bonding pads 36. The circuit structure CS2 includes a dielectric layer 46, a redistribution layer 48, a dielectric layer 50, a plurality of bonding pads 52.

The semiconductor die 12 can be disposed on/over/above the semiconductor die 10. The semiconductor die 12 can be stacked directly on/over/above the semiconductor die 10. The semiconductor die 12 vertically overlaps with the semiconductor die 10. Hence, a width of the semiconductor device 1A in a horizontal direction HD can be confined in a fixed range, thereby achieving a small footprint/high integration.

The semiconductor die 10 has an active surface 104 (i.e., a top surface) , a back surface 106 (i.e., a bottom surface/non-active surface) , and a pair of side surfaces 108. The active surface 104 is opposite to the back surface 106. The side surface 108 connects the active surface 104 to the back surface 106. In some embodiments, the active surface 104, the back surface 106, and the side surfaces 108 can constitute a rectangular profile of the semiconductor die 10.

The semiconductor die 12 has an active surface 124 (i.e., a top surface) , a back surface 126 (i.e., a bottom surface/non-active surface) and a pair of inclined side surfaces 128. The inclined side surface 128 connects the back surface 126 to the active surface 124. In some embodiments, the active surface 124, the back surface 126, and the inclined side surfaces 128 can constitute a trapezoid profile of the semiconductor die 12. The active surface 104 of the semiconductor die 10 faces toward the back surface 126 of the semiconductor die 12.

In some embodiments, the

active surfaces

104, 124 of the semiconductor dies 10, 12 can contain analog or digital circuits implemented as active devices, passive devices, conductive layers, and dielectric layers formed within the die and electrically interconnected according to the electrical design and function of the die. For example, the circuit may include one or more transistors, diodes, or other circuit elements formed within

active surfaces

104, 124 to implement analog circuits or digital circuits. As such, the active surface 104/124 is the main heating surface of the semiconductor device 10/12.

In some embodiments, the semiconductor die 10 can include a transistor 102, and the semiconductor die 12 can include a transistor 122. The

transistors

102, 122 can be formed adjacent with the

active surfaces

104, 124 of the semiconductor dies 10, 12, respectively. The detailed configuration of the

transistors

102, 122 are depicted as in FIGS. 2A and 2B.

FIG. 2A is a partial enlargement of the structure in the semiconductor die 10 according to some embodiments of the present disclosure. The semiconductor die 10 includes a substrate 1021, a nitride- based semiconductor layer 1022, a nitride-based semiconductor layer 1023,

electrodes

1024, 1025, a doped nitride-based semiconductor layer 1026, and a gate electrode 1027.

The substrate 1021 may be a semiconductor substrate. The exemplary materials of the substrate 1021 can include, for example but are not limited to, Si, SiGe, SiC, gallium arsenide, p-doped Si, n-doped Si, sapphire, semiconductor on insulator, such as silicon on insulator (SOI) , or other suitable substrate materials. In some embodiments, the substrate 1021 can include, for example, but is not limited to, group III elements, group IV elements, group V elements, or combinations thereof (e.g., III-V compounds) . In other embodiments, the substrate 1021 can include, for example but is not limited to, one or more other features, such as a doped region, a buried layer, an epitaxial (epi) layer, or combinations thereof.

In some embodiments, the semiconductor die 10 can include a buffer layer (not shown) . The buffer layer (not shown) can be disposed on/over/above the substrate 1021. The buffer layer can be disposed between the substrate 1021 and the nitride-based semiconductor layer 1022. The buffer layer can be configured to reduce lattice and thermal mismatches between the substrate 1021 and the nitride-based semiconductor layer 1022, thereby curing defects due to the mismatches/difference. The buffer layer may include a III-V compound. The III-V compound can include, for example but are not limited to, aluminum, gallium, indium, nitrogen, or combinations thereof. Accordingly, the exemplary materials of the buffer layer can further include, for example but are not limited to, GaN, AlN, AlGaN, InAlGaN, or combinations thereof.

In some embodiments, the semiconductor die 10 may further include a nucleation layer (not shown) . The nucleation layer may be formed between the substrate 1021 and the buffer layer. The nucleation layer can be configured to provide a transition to accommodate a mismatch/difference between the substrate 1021 and a III-nitride layer of the buffer layer. The exemplary material of the nucleation layer can include, for example but is not limited to AlN or any of its alloys.

The nitride-based semiconductor layer 1022 is disposed on/over/above the substrate 1021. The nitride-based semiconductor layer 1023 is disposed on/over/above the nitride-based semiconductor layer 1022. The exemplary materials of the nitride-based semiconductor layer 1022 can include, for example but are not limited to, nitrides or group III-V compounds, such as GaN, AlN, InN, In _xAl _yGa _(1–x–y) N where x+y ≤ 1, Al _yGa _(1–y) N where y ≤ 1. The exemplary materials of the nitride-based semiconductor layer 1023 can include, for example but are not limited to, nitrides or group III-V compounds, such as GaN, AlN, InN, In _xAl _yGa _(1–x–y) N where x+y ≤ 1, Al _yGa _(1–y) N where y ≤ 1.

The exemplary materials of the nitride-based

semiconductor layers

1022 and 1023 are selected such that the nitride-based semiconductor layer 1023 has a bandgap (i.e., forbidden band width) greater than a bandgap of the nitride-based semiconductor layer 1022, which causes electron affinities thereof different from each other and forms a heterojunction therebetween. For example, when the nitride-based semiconductor layer 1022 is an undoped GaN layer having a bandgap of approximately 3.4 eV, the nitride-based semiconductor layer 1023 can be selected as an AlGaN layer having bandgap of approximately 4.0 eV. As such, the nitride-based

semiconductor layers

1022 and 1023 can serve as a channel layer and a barrier layer, respectively. A triangular well potential is generated at a bonded interface between the channel and barrier layers, so that electrons accumulate in the triangular well, thereby generating a two-dimensional electron gas (2DEG) region adjacent to the heterojunction. Accordingly, the transistor 102 is available to include at least one GaN-based high-electron-mobility transistor (HEMT) .

The

electrodes

1024 and 1025 are disposed on/over/above the nitride-based semiconductor layer 1023. The

electrodes

1024 and 1025 can make contact with the nitride-based semiconductor layer 1023. In some embodiments, the electrode 1024 can serve as a source electrode. In some embodiments, the electrode 1025 can serve as a drain electrode. In some embodiments, the electrode 1024 can serve as a source electrode. In some embodiments, the electrode 1025 can serve as a drain electrode. The role of the

electrodes

1024 and 1025 depends on the device design.

In some embodiments, the

electrodes

1024 and 1025 can include, for example but are not limited to, metals, alloys, doped semiconductor materials (such as doped crystalline silicon) , compounds such as silicides and nitrides, other conductor materials, or combinations thereof. The exemplary materials of the

electrodes

1024 and 1025 can include, for example but are not limited to, Ti, AlSi, TiN, or combinations thereof. Each of the

electrodes

1024 and 1025 may be a single layer, or plural layers of the same or different composition. The

electrodes

1024 and 1025 form ohmic contacts with the nitride-based semiconductor layer 1023. Furthermore, the ohmic contacts can be achieved by applying Ti, Al, or other suitable materials to the

electrodes

1024 and 1025.

In some embodiments, each of the

electrodes

1024 and 1025 is formed by at least one conformal layer and a conductive filling. The conformal layer can wrap the conductive filling. The exemplary materials of the conformal layer can include, for example but are not limited to, Ti, Ta, TiN, Al, Au, AlSi, Ni, Pt, or combinations thereof. The exemplary materials of the conductive filling can include, for example but are not limited to, AlSi, AlCu, or combinations thereof.

The doped nitride-based semiconductor layer 1026 is disposed on/above the nitride-based semiconductor layer 1023. The gate electrode 1027 is disposed/stacked on the doped nitride-based semiconductor layer 1026. The doped nitride-based semiconductor layer 1026 and the gate electrode 1027 are disposed between the

electrodes

1024 and 1025. The

electrodes

1024 and 1025, the gate electrode 1027, and the 2DEG region can serve as components of the transistor 102.

A width of the doped nitride-based semiconductor layer 1026 is greater than that of the gate electrode 1027. In some embodiments, a width of the doped nitride-based semiconductor layer 1026 is substantially the same as a width of the gate electrode 1027. The relationship of the widths of the doped nitride-based semiconductor layer 1026 and the gate electrode 1027 can depend on the device design.

In the exemplary illustration of FIG. 2A, the transistor 102 is an enhancement mode device, which is in a normally-off state when the gate electrode 1027 is at approximately zero bias. Specifically, the doped nitride-based semiconductor layer 1026 may create at least one p-n junction with the nitride-based semiconductor layer 1023 to deplete the 2DEG region, such that at least one zone of the 2DEG region corresponding to a position below the corresponding the gate electrode 1027 has different characteristics (e.g., different electron concentrations) than the remain of the 2DEG region and thus is blocked.

Due to such mechanism, the transistor 102 has a normally-off characteristic. In other words, when no voltage is applied to the gate electrode 1027 or a voltage applied to the gate electrode 1027 is less than a threshold voltage (i.e., a minimum voltage required to form an inversion layer below the gate electrode 1027) , the zone of the 2DEG region below the gate electrode 1027 is kept blocked, and thus no current flows therethrough.

In some embodiments, the doped nitride-based semiconductor layer 1026 can be omitted, such that the transistor 102 is a depletion-mode device, which means the transistor 102 in a normally-on state at zero gate-source voltage.

The doped nitride-based semiconductor layer 1026 can be a p-type doped III-V semiconductor layer. The exemplary materials of the doped nitride-based semiconductor layer 1026 can include, for example but are not limited to, p-doped group III-V nitride semiconductor materials, such as p-type GaN, p-type AlGaN, p-type InN, p-type AlInN, p-type InGaN, p-type AlInGaN, or combinations thereof. In some embodiments, the p-doped materials are achieved by using a p-type impurity, such as Be, Mg, Zn, Cd, and Mg. In some embodiments, the nitride-based semiconductor layer 1022 includes undoped GaN and the nitride-based semiconductor layer 1023 includes AlGaN, and the doped nitride-based semiconductor layer 1027 is a p-type GaN layer which can bend the underlying band structure upwards and to deplete the corresponding zone of the 2DEG region, so as to place the transistor 102 into an off-state condition.

The exemplary materials of the gate electrode 1027 may include metals or metal compounds. The gate electrode 1027 may be formed as a single layer, or plural layers of the same or different compositions. The exemplary materials of the metals or metal compounds can include, for example but are not limited to, W, Au, Pd, Ti, Ta, Co, Ni, Pt, Mo, TiN, TaN, metal alloys or compounds thereof, or other metallic compounds.

FIG. 2B is a partial enlargement of the structure in the semiconductor die 12 according to some embodiments of the present disclosure. The semiconductor die 12 includes a substrate 1221, a nitride-based semiconductor layer 1222, a nitride-based semiconductor layer 1223,

electrodes

1224, 1225, a doped nitride-based semiconductor layer 1226, and a gate electrode 1227.

The

electrodes

1224 and 1225, the gate electrode 1227, and the 2DEG region can serve as components of the transistor 122. The configuration of the transistor 122 can be similar to that of the transistor 102, except to that a distance L2 between the electrode 1225 and the gate electrode 1227 is greater than a distance L1 between the electrode 1025 and the gate electrode 1027.

In some embodiments, the electrode 1225 of semiconductor die 12 and the electrode 1025 of the semiconductor die 10 can be drain electrodes, and thus the distance L1/L2 can be referred to as drain to gate edge spacing, which governs the breakdown voltage of the transistor 102/122. Since the distance L2 of the transistor 122 is greater than the distance L1 of the transistor 102, the breakdown voltage of the transistor 122 is higher than that of the transistor 102. Due to above configuration, the transistor 122 can be configured by a high-voltage GaN-based transistor for high voltage application, and the transistor 102 can be configured by a low-voltage GaN-based transistor for low voltage application. Therefore, an operation voltage of the transistor 122 can be higher than an operation voltage of the transistor 102. In some embodiments, an operation voltage of the low-voltage transistor 102 is in a range from about 5V to about 100V. In some embodiments, an operation voltage of the high-voltage transistor 122 is in a range from about 150V to about 1250V.

Compared to the transistor 102, the transistor 122 generates a relatively large amount of heat due to its high operation voltage. Thus, the transistor 122/semiconductor die 12 also can be referred to as a high-power consuming transistor/semiconductor die, and the transistor 102/semiconductor die 10 also can be referred to as a low power consuming transistor/semiconductor die.

As transistor density per volume and operating speed increase, so does heat generation. Excessive heat may accumulate in the semiconductor device, resulting in malfunction of the semiconductor device. Moreover, the increased heat output of the semiconductor device results in thermal cycling that can weaken the bond between the encapsulant and the semiconductor dies leading to delamination. Furthermore, the quality of the encapsulant will worsen due to excessive heat. The reliability and performance of the packaged semiconductor device is decreased as the temperature increases. In addition, in the semiconductor packaged device, a through gan via (TGV) process is usually performed to achieve connection between layers. However, the TGV process is complex, which results in a higher manufacturing cost of the semiconductor packaged device. Therefore, there is a need in the art for improved semiconductor device packages.

At least to avoid the aforesaid issue, the present disclosure is to develop a novel structure for semiconductor packaged device. The detailed structure/arrangement will be fully described as follows.

Referring to the FIG. 1 again, the circuit structure CS1 is disposed between the semiconductor dies 10, 12. The dielectric layer 30 of the circuit structure CS1 is disposed on/over/above the semiconductor die 10. The dielectric layer 30 of the circuit structure CS1 covers the active surface 104 of the semiconductor die 10. The redistribution layer 32 of the circuit structure CS1 is disposed/sandwiched between the

dielectric layers

30, 34. The redistribution layer 32 penetrates through holes TH1 of the dielectric layer 30, such that an end portion of the redistribution layer 32 makes contact with an electrode of the transistor 102. The redistribution layer 32 extends horizontally/laterally, such that another end portion of the redistribution layer 32 makes contact with the bonding pad 36. Due to aforesaid configuration, the transistor 102 can be electrically connected to the bonding pads 36 through the redistribution layer 32.

The dielectric layer 34 of the circuit structure CS1 is disposed on/over/above the dielectric layer 30. The dielectric layer 34 covers the redistribution layer 32 and the dielectric layer 30. The bonding pads 36 of the circuit structure CS1 are disposed on/over/above the redistribution layer 32. The dielectric layer 34 covers side surfaces of the bonding pads 36. Top surfaces of the bonding pads 36 are free from coverage of the dielectric layer 34. The conductive bumps 38 are disposed on/over/above the bonding pads 36 of the circuit structure CS1, respectively. Each of the conductive bumps 38 makes contact with the corresponding bonding pad 36.

The dielectric layer 40 is located/disposed between the back surface 126 (or inclined side surfaces 128) of the semiconductor die 12 and the conductive layer 42 to provide a good insulation between the semiconductor die 12 and the conductive layer 42. The dielectric layer 40 covers the back surface 126 and the inclined side surface 128 of the semiconductor die 12. The dielectric layer 40 makes contact with the back surface 126 and the inclined side surfaces 128 of the semiconductor die 12. The dielectric layer 40 is conformal with the back surface 126 and the inclined surfaces 128 of the semiconductor die 12.

The conductive layer 42 is disposed between the semiconductor dies 10, 12. The conductive layer 42 is disposed under the dielectric layer 40. The conductive layer 42 is conformal with the dielectric layer 40. The conductive layer 42 extends from a position directly under the back surface 126 of the semiconductor die 12 to a position out of the active surface 124 of the semiconductor die 12. The conductive bumps 38 are disposed between the redistribution layer 32 and the conductive layer 42. The conductive bumps 38 electrically connect the redistribution layer 32 to the conductive layer 42.

During the operation period of the semiconductor device 1A, heat generated from the semiconductor die 10 having a low-voltage GaN-based transistor 102 is lower than that of the semiconductor die 12 having a high-voltage GaN-based transistor 122 because of their different operation voltages. During a package stage of the present disclosure, the

semiconductor diess

10, 12 are encapsulated in the encapsulant 44 in consideration of the aforesaid heating generating factor in the following manner.

In this regard, the encapsulant 44 encapsulates the semiconductor dies 10, 12, such that the semiconductor die 10 is fully embedded in the encapsulant 44 and the active surface 124 of the semiconductor die 12 is free from coverage of the encapsulant 44. A bottom portion of the encapsulant 44 covers an entirety of the active surface 104, the back surface 106, and the side surfaces 108 of the semiconductor die 10. The bottom portion of the encapsulant 44 make contact with the back surface 106 and the side surfaces 108. A top portion of the encapsulant 44 covers the back surface 126 and the inclined side surfaces 128 of the semiconductor die 12, and the active surface 124 of the semiconductor die 12 is free from coverage of the top portion of the encapsulant 44. The encapsulant 44 can provide a good protection to the semiconductor dies 10, 12 for preventing moisture and particles from contaminating the semiconductor dies 10, 12.

The encapsulant 44 has a top-most surface TS and a bottom-most surface BS opposite to each other. The back surfaces 106, 126 of the semiconductor dies 10, 12 face away from the top-most surface TS of the encapsulant 44. By above configuration, the semiconductor dies 10, 12 are encapsulated by the encapsulant 44, such that the back surface 106 of the semiconductor die 10 is deeper than the back surface 126 of the semiconductor die 12 with respect to the top-most surface TS of the encapsulant 44. That is to say, the active surface 106 (i.e., main heating surface) of the semiconductor die 10 is shallower than the active surface 126 (i.e., main heating surface) of the semiconductor die 12 with respect to the top-most surface TS of the encapsulant 44.

Due to the above configuration, since the semiconductor die 10 having the low-voltage GaN-based transistor/low power consuming transistor 102 generates a relatively small amount of heat during its operation, the semiconductor die 10 is selected to be encapsulated/embedded inside the encapsulant 44 during the package stage of the present disclosure, in order to reduce the negative impact of heat on the encapsulant 44 as much as possible.

Since the semiconductor die 12 having the high-voltage GaN-based transistor/high power consuming transistor 122 generates a relative high amount of heat during its operation, the semiconductor die 12 is selected to be encapsulated/received by the encapsulant 44 during the package stage of the present disclosure, such that the active surface 124 (i.e., main heating surface) thereof is free from coverage of the encapsulant 44. Thus, heat generated from the high-voltage GaN-based transistor 122 of the semiconductor die 12 would not accumulate in the encapsulant 44 and can thermally dissipate rapidly.

In brief, the package stage of the present disclosure takes into account heating generating/power consumption difference between the semiconductor dies 10, 12 to encapsulate the semiconductor dies 10, 12. Such a configuration can provide a good thermal management to the semiconductor device 1A. Thus, the quality of the encapsulant 44 can be ensured and the delamination issue can also be avoided, and the reliability and performance of the semiconductor device 1A can be well improved.

The semiconductor die 10, the circuit structure CS1, and the conductive bumps 38 are located/disposed between the top-most surface TS and the bottom-most surface BS of the encapsulant 44. The end surface ES1 of the conductive layer 42 and the end surfaces ES3 of the dielectric layer 40 are substantially coplanar with the active surface of the semiconductor die 12 and the top-most surface TS of the encapsulant 44.

The dielectric layer 30, the redistribution layer 34, the dielectric layer 34, the bonding pads 34, and the conductive bumps 38 are embedded into the encapsulant 44. The conductive layer 42 and the dielectric layer 40 are received by the encapsulant 44. An end surface ES1 of the conductive layer 38 is covered by the encapsulant 44. Another end surface ES2 of the conductive layer 38 is free from coverage of the encapsulant 44. A pair of end surfaces ES3 of the dielectric layer 40 are free from coverage of the encapsulant 44.

The circuit structure CS2 is disposed on/over/above the semiconductor dies 12, the dielectric layer 40, the conductive layer 42, and the encapsulant 44. To be more specific, the dielectric layer 46 of the circuit structure CS2 covers the active surface 124 of the semiconductor die 12, end surfaces ES3 of the dielectric layer 40, and the top-most surface TS of the encapsulant 44. The redistribution layer 48 is disposed on/over/above the active surface 124 of the semiconductor die 12 and the conductive layer 42. A portion of the redistribution layer 48 penetrates a portion of the through holes TH2 of the dielectric layer 46 to make contact with the conductive layer 38. Another portion of the of the redistribution layer 48 penetrates another portion of the through holes TH2 of the dielectric layer 46 to make contact with the transistor 122 of the semiconductor die 12.

The dielectric layer 50 covers the redistribution layer 48 and the dielectric layer 46. The bonding pads 50 are disposed on/over/above the redistribution layer 48. The dielectric layer 50 covers side surfaces of the bonding pads 52. Top surfaces of the bonding pads 52 are free from coverage of the dielectric layer 50. The conductive bumps 54 are disposed on/over/above the bonding pads 52, respectively. Each of the conductive bumps 54 makes contact with the corresponding bonding pad 52. A spacing between two adjacent conductive bumps 54 is greater than a spacing between two adjacent conductive bumps 38.

Due to the aforesaid configuration, the semiconductor die 10 is electrically connected/coupled to a group of the conductive bumps 54 through the conductive layer 42, the redistribution layer 48 and the bonding pads 52. The semiconductor die 12 is electrically connected/coupled to another group of the conductive bumps 54 through the redistribution layer 48 and the bonding pads 52. In some embodiments, an external electronic device can be electrically connected/coupled to the semiconductor dies 10, 12 of the semiconductor device 1A through the conductive bumps 54. Therefore, at least one signal from the electronic device can be transferred to the semiconductor dies 10, 12, and vice versa.

The present disclosure adopts the configuration of the redistribution layer 32, the conductive bumps 38, and the conductive layer 42 to achieve connection between the layers instead of using TGV process; and therefore, the manufacturing process complexity and the manufacturing cost of the semiconductor device 1A can be further reduced.

The material of the

dielectric layers

30, 34, 40, 46, and 50 can include, for example but are not limited to, dielectric materials. For example, the

dielectric layer

30, 34, 40, 46, and 50 can include, for example but are not limited to, SiN _x, SiO _x, Si ₃N ₄, SiON, SiC, SiBN, SiCBN, oxides, nitrides, plasma enhanced oxide (PEOX) , or combinations thereof. In some embodiments, the dielectric layer 120 can be a multi-layered structure, such as a composite dielectric layer of Al ₂O ₃/SiN, Al ₂O ₃/SiO ₂, AlN/SiN, AlN/SiO ₂, or combinations thereof.

In some embodiments, the optional dielectric layer can be formed by a single layer or more layers of dielectric materials. The exemplary dielectric materials can include, for example but are not limited to, one or more oxide layers, a SiO _x layer, a SiN _x layer, a high-k dielectric material (e.g., HfO ₂, Al ₂O ₃, TiO ₂, HfZrO, Ta ₂O ₃, HfSiO ₄, ZrO ₂, ZrSiO ₂, etc) , or combinations thereof.

The exemplary materials of the redistribution layers 32, 48 can include, for example but are not limited to, conductive materials, such as metals or alloys.

The exemplary materials of the

bonding pads

36, 52, and the

conductive bumps

38, 54 can include, for example but are not limited to, Sn, Au, Ni, Pd, Cu, or an alloy of any two or more of these metals, such as Au-Sn metal alloy.

The exemplary material of the encapsulant 44 can include, for example but are not limited to, epoxy resins.

Different stages of a method for manufacturing the semiconductor packaged device 1A are shown in FIG. 3A, FIG. 3B, FIG. 3C, FIG. 3D, FIG. 3E, FIG. 3F, FIG. 3G, FIG. 3H, FIG. 3I, and FIG. 3J described below. In the following, deposition techniques can include, for example but are not limited to, atomic layer deposition (ALD) , physical vapor deposition (PVD) , chemical vapor deposition (CVD) , metal organic CVD (MOCVD) , plasma enhanced CVD (PECVD) , low-pressure CVD (LPCVD) , plasma-assisted vapor deposition, epitaxial growth, or other suitable processes.

Referring to FIG. 3A, a semiconductor wafer W1 is provided. A plurality of transistors 122 are formed in the semiconductor wafer W1, in which each of the transistors 122 includes a low-voltage GaN-based transistor.

Referring to FIG. 3B, a temporary carrier substrate/intermediate substrate TW1 is provided. A bonding layer BL1 (i.e., adhesive layer) is provided to be disposed/glued on a top surface of the temporary carrier wafer TW1. The semiconductor wafer W1 is flipped upside down to be bonded to the temporary carrier substrate TW1 through the bonding layer BL1, such that the transistors 122 can be disposed/bonded on the temporary carrier substrate TW1.

Referring to FIG. 3C, a wafer thinning process is performed on the semiconductor wafer W1. The wafer thinning process includes a grinding process to grind a back surface BS of the semiconductor wafer W1 to a predetermined thickness. Then, a sawing process is performed on the thinned and etched semiconductor wafer (not shown) by using a sawing blade or a laser cutting process to cut through the thinned semiconductor wafer, such that two separated semiconductor dies 12 are formed and a portion of the bonding layer BL1 is exposed. Each of the semiconductor dies 12 is sawed to have a pair of inclined side surfaces 128.

Referring to FIG. 3D, a blanket dielectric layer (not shown) is formed on the resulted structure of the FIG. 3C, such that a portion of the blanket dielectric layer is conformal with the semiconductor die 12. A patterning process is performed on the blanket dielectric layer, so as to form two separated dielectric layers 42 on the two semiconductor dies 12, respectively. Each of the semiconductor dies 12, for example, can include two transistors 122. The present disclosure is not limited thereto.

Then, a blanket conductive layer is formed on the aforesaid resulted structure, such that a portion of the blanket conductive layer is conformal with the dielectric layers 42. After that, a patterning process is performed on the blanket conductive layer to form two separated conductive layer layers 40 on the two separated dielectric layers 42, respectively. It should be noted that each of the conductive layer layers 40 is patterned to have a through hole TH to expose a portion of the dielectric layer 40 after the patterning process.

Referring to FIG. 3D, a blanket dielectric layer (not shown) is formed on the resulted structure of the FIG. 3C, such that a portion of the blanket dielectric layer is conformal with the semiconductor die 12. A patterning process is performed on the blanket dielectric layer, so as to form two separated dielectric layers 42 on the two semiconductor dies 12, respectively.

Referring to FIG. 3E, a temporary carrier substrate/intermediate substrate TW2 is provided. A bonding layer BL2 is provided to be disposed on a top surface of the temporary carrier wafer TW2. The semiconductor dies 12, the dielectric layer 40 and the conductive layer 42 are debonded from the temporary carrier substrate TW1 in the FIG. 3D. Then, the semiconductor dies 12, the dielectric layer 40 and the conductive layer 42 are bonded to the temporary carrier substrate TW2 through the bonding layer BL2, such that the transistors 122 can be disposed on the temporary carrier substrate TW2.

Referring to FIG. 3F, a plurality semiconductor dies 10 are formed. Each of the semiconductor die 10 is formed to have a plurality of the transistors 102. Each of the transistors 102 is a high-voltage GaN-based transistor.

A circuit structure CS1 is formed on the active surface 104 of the semiconductor die 10. Specifically, a dielectric layer 30 of the circuit structure CS1 with a plurality through holes is formed to cover the active surface 104, in which the through holes of the dielectric layer 30 expose the transistors 102. A redistribution layer 32 is formed to cover and extend into the through holes of the dielectric layer 30 to make contact with the transistors 102. A dielectric layer 34 with a plurality of through holes is formed to cover the dielectric layer 30 and the redistribution layer 32, in which the through holes of the dielectric layer 34 expose the redistribution layer 32. A plurality of the bonding pads 36 are formed to fill up the through holes of the dielectric layer 34, such that the bonding pads 36 make contact with the redistribution layer 32. A plurality of conductive bumps 38 are formed on the bonding pads 34, such that the conductive bumps 38 make contact with the bonding pads 34, respectively.

The formation of the dielectric layer 30, the redistribution layer 32, the dielectric layer 34, and the bonding pads 36 includes deposition techniques and a patterning process. In some embodiments, the deposition techniques can be performed for forming a blanket layer, and the patterning process can be performed for removing excess portions thereof. In some embodiments, the patterning process can include photolithography, exposure and development, etching, other suitable processes, or combinations thereof.

Then, the semiconductor dies 10 with circuit structures CS1 and the conductive bumps 38 are disposed on/over/above the semiconductor dies 12, respectively, such that the conductive bumps 38 can make contact with the conductive layer 42. As such, the semiconductor dies 10 can be electrically coupled with the conductive layer 42 through the redistribution layer 32, the bonding pads 36, and the conductive bumps 38.

Referring to FIG. 3G, an encapsulant 44 is formed to encapsulate the semiconductor dies 10, 12, the circuit structure CS1, and the conductive bumps 38. The encapsulant 44 is formed to cover the bonding layer BL2 and the temporary carrier substrate TW2.

Referring to FIG. 3H, the semiconductor die 12 is debonded from the bonding layer BL2 on the temporary carrier substrate TW2, such that semiconductor die 12 has an active surface 124 exposed from the encapsulant 44 and the conductive layer 42 has an end surface ES1 exposed from the encapsulant 44.

Referring to FIG. 3I, a circuit structure CS2 is formed on the active surface 124 of the semiconductor die 12. Specifically, a dielectric layer 46 of the circuit structure CS2 with a plurality through holes is formed to cover the active surface 124, in which the through holes of the dielectric layer 46 expose the transistors 122. A redistribution layer 48 is formed to cover the and extend into the through holes of the dielectric layer 46 to make contact with the conductive layer 42. The redistribution layer 48 is formed to be indirectly connected to the active surface 124 of the semiconductor die 10 through the conductive layer 42. A dielectric layer 50 with plurality through holes is formed to cover the dielectric layer 46 and the redistribution layer 48, in which the through holes of the dielectric layer 46 expose the redistribution layer 48. A plurality of the bonding pads 52 are formed to fill up the through holes of the dielectric layer 50, such that the bonding pads 52 make contact with the redistribution layer 48.

The formation of the dielectric layer 30, the redistribution layer 32, the dielectric layer 34, and the bonding pads 36 includes deposition techniques and a patterning process.

Referring to FIG. 3J, a plurality of the conductive bumps 54 are disposed on the bonding pads 52, such that the conductive bumps 54 can make contact with the bonding pads 52, respectively. Thus, the conductive bumps 54 can be electrically connected to the redistribution layer 48 through the bonding pads 52. The semiconductor die 10 is electrically connected to a group of the conductive bumps 54 through the conductive layer 42, a portion of the redistribution layer 48, and a portion of the bonding pads 52. The semiconductor die 12 is electrically connected to another group of the conductive bumps 54 through another portion of the redistribution layer 48. Then, a sawing process is performed on the resulted structure; and therefore, a plurality of the semiconductor devices 1A can be obtained.

Based on the above descriptions, in the present disclosure, two semiconductor dies are vertically stacked on each other, so integration of the semiconductor packaged device can be improved.

Then, the two semiconductor dies are encapsulated by the encapsulant according to their power consumption/operation voltage. Specifically, a low-voltage/low power consuming semiconductor die is fully embedded in the encapsulant, and thus the encapsulant is not easy to be affected due to low heat generated from the low-voltage/low power consuming semiconductor die. On the other hand, an active surface of a high-voltage/high power consuming semiconductor die is exposed by the encapsulant, such that high heat generated from the high-voltage/high power consuming semiconductor die can dissipate rapidly by the redistribution layer of the circuit structure instead of directly affecting the encapsulant. Hence, the aforesaid arrangement provides a good thermal management to the semiconductor device, such that the thermal dissipation ability and reliability of the semiconductor packaged device can be improved.

The embodiments were chosen and described in order to best explain the principles of the disclosure and its practical application, thereby enabling others skilled in the art to understand the disclosure for various embodiments and with various modifications that are suited to the particular use contemplated.

As used herein and not otherwise defined, the terms "substantially, " "substantial, " "approximately" and "about" are used to describe and account for small variations. When used in conjunction with an event or circumstance, the terms can encompass instances in which the event or circumstance occurs precisely as well as instances in which the event or circumstance occurs to a close approximation. For example, when used in conjunction with a numerical value, the terms can encompass a range of variation of less than or equal to ±10%of that numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. The term “substantially coplanar” can refer to two surfaces within micrometers of lying along a same plane, such as within 40 μm, within 30 μm, within 20 μm, within 10 μm, or within 1 μm of lying along the same plane.

As used herein, the singular terms “a, ” “an, ” and “the” may include plural referents unless the context clearly dictates otherwise. In the description of some embodiments, a component provided “on” or “over” another component can encompass cases where the former component is directly on (e.g., in physical contact with) the latter component, as well as cases where one or more intervening components are located between the former component and the latter component.

While the present disclosure has been described and illustrated with reference to specific embodiments thereof, these descriptions and illustrations are not limiting. It should be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the true spirit and scope of the present disclosure as defined by the appended claims. The illustrations may not necessarily be drawn to scale. There may be distinctions between the artistic renditions in the present disclosure and the actual apparatus due to manufacturing processes and tolerances. Further, it is understood that actual devices and layers may deviate from the rectangular layer depictions of the FIGS. and may include angles surfaces or edges, rounded corners, etc. due to manufacturing processes such as conformal deposition, etching, etc. There may be other embodiments of the present disclosure which are not specifically illustrated. The specification and the drawings are to be regarded as illustrative rather than restrictive. Modifications may be made to adapt a particular situation, material, composition of matter, method, or process to the objective, spirit and scope of the present disclosure. All such modifications are intended to be within the scope of the claims appended hereto. While the methods disclosed herein have been described with reference to particular operations performed in a particular order, it will be understood that these operations may be combined, sub-divided, or re-ordered to form an equivalent method without departing from the teachings of the present disclosure. Accordingly, unless specifically indicated herein, the order and grouping of the operations are not limitations.

Claims

A semiconductor packaged device, comprising:

a first semiconductor die comprising a first transistor;

a second semiconductor die disposed above the first semiconductor die and comprising a second transistor; and

an encapsulant encapsulating the first semiconductor die, wherein the first semiconductor die is fully embedded in the encapsulant with an active surface and a back surface of the first semiconductor die covered by the encapsulant, wherein the second semiconductor die has an active surface free from coverage of the encapsulant and a back surface covered by the encapsulant and facing toward the active surface of the first semiconductor die.
The semiconductor packaged device of any one of the preceding claims, wherein the first transistor and the second transistor are respectively configured by GaN-based transistors that are adapted to different voltage ranges.
The semiconductor packaged device of any one of the preceding claims, wherein the first transistor is configured by a low-voltage GaN-based transistor, and the second transistor is configured by a high-voltage GaN-based transistor.
The semiconductor packaged device of any one of the preceding claims, wherein a distance between a drain electrode and a gate electrode of the high-voltage GaN-based transistor is greater than a distance between a drain electrode and a gate electrode of the low-voltage GaN-based transistor.
The semiconductor packaged device of any one of the preceding claims, wherein the encapsulant has a bottom covering an entirety of the back surface of the first semiconductor die.
The semiconductor packaged device of any one of the preceding claims, wherein the encapsulant has a top-most surface and a bottom-most surface which are opposite to each other, and the first semiconductor die is located between the top-most surface and the bottom-most surface of the encapsulant.
The semiconductor packaged device of any one of the preceding claims, wherein the active surface of the first semiconductor die faces the back surface of the second semiconductor die.
The semiconductor packaged device of any one of the preceding claims, further comprising:

a conductive layer disposed between the first and second semiconductor dies, wherein the conductive layer has an end surface covered by the encapsulant and another end surface free from coverage of the encapsulant.
The semiconductor packaged device of any one of the preceding claims, further comprising a dielectric layer covering the back surface of the second semiconductor die and located between the back surface of the second semiconductor die and the conductive layer.
The semiconductor packaged device of any one of the preceding claims, wherein the dielectric layer has a pair of end surfaces free from coverage of the encapsulant.
The semiconductor packaged device of any one of the preceding claims, wherein the second semiconductor die has an inclined surface connecting the back surface to the active surface of the second semiconductor die.
The semiconductor packaged device of any one of the preceding claims, wherein the dielectric layer is conformal with the inclined surface and the back surface of the second semiconductor die.
The semiconductor packaged device of any one of the preceding claims, further comprising:

a first redistribution layer disposed between the first semiconductor die and the conductive layer; and

a plurality of first conductive bumps disposed between the first redistribution layer and the conductive layer and electrically connecting the first redistribution layer to the conductive layer, wherein the first redistribution layer and the first conductive bumps are embedded into the encapsulant.
The semiconductor packaged device of any one of the preceding claims, further comprising:

a second redistribution layer disposed above the active surface of the second semiconductor die; and

a plurality of second conductive bumps disposed above the second redistribution layer and connected to the second semiconductor die through the second redistribution layer.
The semiconductor packaged device of any one of the preceding claims, wherein the first semiconductor die is electrically connected to a first group of the second conductive bumps through the conductive layer, and the second semiconductor die is electrically connected to a second group of the second conductive bumps.
A method for manufacturing a semiconductor packaged device, comprising:

disposing a first semiconductor die on a substrate;

forming a conductive layer on the first semiconductor die;

disposing a second semiconductor die over the first semiconductor die with the second semiconductor die electrically coupling with the conductive layer;

forming an encapsulant encapsulating the first and second semiconductor dies and covering the substrate; and

debonding the first semiconductor die from the substrate such that the first semiconductor die has an active surface exposed from the encapsulant.
The method of any one of the preceding claims, further comprising:

forming a redistribution layer connected to the active surface of the first semiconductor die and the conductive layer.
The method of any one of the preceding claims, further comprising:

forming a plurality of conductive bumps connected to the redistribution layer such that the first semiconductor die is electrically connected to a first group of the conductive bumps, and the second semiconductor die is electrically connected to a second group of the conductive bumps through the conductive layer.
The method of any one of the preceding claims, wherein the debonding the first semiconductor die from the substrate is performed such that the conductive layer has an end surface exposed from the encapsulant.
The method of any one of the preceding claims, further comprising:

forming a high-voltage GaN-based transistor in the first semiconductor die; and

forming a low-voltage GaN-based transistor in the second semiconductor die.
A semiconductor packaged device, comprises

a first semiconductor die comprising a first transistor;

a second semiconductor die disposed above the first semiconductor die and comprising a second transistor; and

an encapsulant encapsulating the first semiconductor die and receiving the second semiconductor die, wherein the first semiconductor die and the second semiconductor die have back surfaces facing away from a top surface of the encapsulant, and the back surface of the first semiconductor die is deeper than the back surface of the second semiconductor die with respect to the top surface of the encapsulant.
The semiconductor packaged device of any one of the preceding claims, wherein the first transistor and the second transistor are respectively configured by GaN-based transistors that are adapted to different voltage ranges.
The semiconductor packaged device of any one of the preceding claims, wherein the first transistor is configured by a low-voltage GaN-based transistor, and the second transistor is configured by a high-voltage GaN-based transistor.
The semiconductor packaged device of any one of the preceding claims, wherein a distance between a drain electrode and a gate electrode of the high-voltage GaN-based transistor is greater than a distance between a drain electrode and a gate electrode of the low-voltage GaN-based transistor.
The semiconductor packaged device of any one of the preceding claims, wherein an operation voltage of the low-voltage die is in a range from about 5V to about 100V, and an operation voltage of the high-voltage die is in a range from about 150V to about 1250V.