WO2023106913A1

WO2023106913A1 - Integration of inductors on silicon-based solar cells

Info

Publication number: WO2023106913A1
Application number: PCT/NL2022/050677
Authority: WO
Inventors: VAN David Auke NIJEN; Patrizio Manganiello; Olindo ISABELLA
Original assignee: Technische Universiteit Delft
Current assignee: Technische Universiteit Delft
Priority date: 2021-12-09
Filing date: 2022-11-24
Publication date: 2023-06-15
Anticipated expiration: 2024-06-09
Also published as: NL2030089B1; EP4445430A1

Abstract

The present invention is in the field of a solar cell, or photovoltaic (PV) cell, for the conversion of light into electrical energy, a process for making such a solar cells, and a PV-module comprising said solar cells. In particular the invention relates to a silicon-based solar cell comprising at least one p-n junction, a substrate, wherein the substrate comprises Si and dopants, and at least one electrical contact layer. Examples thereof are a back-contacted solar cell, such as an interdigitated back-contacted solar cell, and a back and front contacted solar cell.

Description

Integration of inductors on silicon-based solar cells

FIELD OF THE INVENTION

BACKGROUND OF THE INVENTION

A solar cell, or photovoltaic (PV) cell, is an electrical device that converts energy of light, typically sun light (hence “solar”), directly into electricity by the so-called photovoltaic effect. The solar cell may be considered a photoelectric cell, having electrical characteristics, such as current, voltage, resistance, and fill factor, which vary when exposed to light and which vary from type of cell to type.

Solar cells are described as being photovoltaic irrespective of whether the source is sunlight or an artificial light. They may also be used as photo detector.

When a solar cell absorbs light it may generate either electron-hole pairs or excitons. In order to obtain an electrical current charge carriers of opposite types are separated. The separated charge carriers are “extracted” to an external circuit, typically providing a DC-current. For practical use a DC-current may be transformed into an AC-current, e.g. by using an inverter. Typically solar cells are grouped into an array of elements. Various elements may form a panel, also referred to as module, and various panels may form a system.

Wafer based c-Si solar cells contribute to more than 90% of the total PV market. According to recent predictions, this trend will remain for the upcoming years towards 2025 and many years beyond. Due to their simplified process, conventional c-Si solar cells dominate a large part of the market. As alternative to the industry to improve the power to cost ratio, the silicon heterojunction approach has become increasingly attractive for PV industry, even though the relatively complicated process to deploy the proper front layers, such as a transparent conductive oxide (TCO) and an inherent low thermal budget of the cells limiting usage of existing production lines and thus result in a negligible market share so far. A heterojunction is the interface that occurs between two layers or regions of dissimilar crystalline semiconductors. These semiconducting materials have unequal band gaps as opposed to a homojunction. A homojunction relates to a semiconductor interface formed by typically two layers of similar semiconductor material, wherein these semiconductor materials have equal band gaps and typically have a different doping (either in concentration, in type, or both). A common example is a homojunction at the interface between an n-type layer and a p-type layer, which is referred to as a p-n junction. In heterojunctions advanced techniques are used to precisely control a deposition thickness of layers involved and to create a lattice-matched abrupt interface. Three types of heterojunctions can be distinguished, a straddling gap, a staggered gap, and a broken gap. The conversion efficiencies of wafer-based c-Si solar cells typically lie in the range of 20%. Theoretically a single p-n junction crystalline silicon device has a maximum power efficiency of 33.7%. An infinite number of layers may reach a maximum power efficiency of 86%. The highest ratio achieved for a solar cell per se at present is about 44%. For commercial silicon solar cells the record is about 25.6%. In view of efficiency the front contacts may be moved to a rear or back side, eliminating shaded areas. In addition thin silicon films were applied to the wafer. Solar cells also suffer from various imperfections, such as recombination losses, reflectance losses, heating during use, thermodynamic losses, shadow, internal resistance, such as shunt and series resistance, leakage, etc. A qualification of performance of a solar cell is the fill factor (FF). The fill factor may be defined as a ratio of an actual maximum obtainable power to the product of the open circuit voltage and short circuit current. It is considered to be a key parameter in evaluating performance. A typical advanced commercial solar cell has a fill factor > 0.75, whereas less advanced cells have a fill factor between 0.4 and 0.7. Cells with a high fill factor typically have a low equivalent series resistance and a high equivalent shunt resistance; in other words less internal losses occur. Efficiency is nevertheless improving gradually, so every relatively small improvement is welcomed and of significant importance.

At present a solar cell having a full area front passivating contact is not attractive, such as due to highly absorptive materials used to build such a structure. That is the case of heavily doped poly-silicon and a-Si layers. In a poly-silicon case, the process requires a very thin polysilicon film for minimizing parasitic absorption loss, and in case of a-Si, the process requires e.g. an extra transparent conductive oxide (TCO) layer for supporting the carrier lateral transport.

Photovoltaic (PV) module designs with increasing granularity of power electronics are gaining attention. For example, performing sub-module maximum power point tracking - to separately control smaller group of cells and extract the maximum power from each group - or applying a reconfiguration strategy - to dynamically adapt the electrical interconnection of (groups of) cells in function of their operating conditions - can increase the energy yield of PV modules significantly in case of non-uniform illumination. Currently, power electronics for module or sub-module purposes is typically attached to the back of the PV-module or to the PV module frame, installed in the PV junction box, or embedded into the PV laminate. It is worth to note that this last approach has been only tested by researchers when it comes to integration of submodule power converters. In current c-Si solar cell designs the main focus is to achieve a high efficiency. Module-level and sub-module-level power converters require passive components (inductors and capacitors) that are often expensive and bulky - especially the inductors - and sometimes limit reliability and lifetime of the converters themselves - especially the capacitors. In many converter topologies, such as boost converters, these passive components are located at the input of the converter, therefore they connect the PV cells to the converter’s switching devices (MOSFETs or diodes).

Incidentally reference can be made to US 2017/162735 Al, EP 2 725 624 Al, and US 2013/038268 Al. US 2017/162735 Al recites a solar cell structure for wireless charging includes a substrate and at least one thin film solar cell disposed on a surface of the substrate, wherein the thin film solar cell has a winding coil structure. Accordingly, in the thin film solar cell, the electrode which is the winding coil structure may be used as electromagnetic induction coil or millimeter-wave radio wave receiving radiator. EP 2 725 624 Al recites a solar cell and a portable electronic device are provided. The solar cell includes a semiconductor material configured to absorb light for generating a current. The solar cell further includes a positive contact and a negative contact. In addition, the negative contact is configured to couple with an external interface. The portable electronic device includes an energy storage unit. The portable electronic device also includes a semiconductor material configured to absorb light for generating a current, a positive contact, and a negative contact. The negative contact of the portable electronic device is configured to couple with an external interface. US 2013/038268 Al recites a photovoltaic cell arrangement having a front surface and a rear surface, and first and second conductor patterns formed on different ones of the front and rear surfaces. The first conductor pattern comprises at least one loop, and the apparatus comprises at least a first terminal connected to the second conductor pattern, and second and third terminals connected to different ends of the at least one loop of the first conductor pattern. A transducer arrangement comprises a transducer body having a front surface and a rear surface, and first and second conductor patterns formed on different ones of the front and rear surfaces. The first conductor pattern comprises at least one loop. The transducer arrangement comprises at least a first terminal connected to the second conductor pattern, and second and third terminals connected to different ends of the at least one spiral loop of the first conductor pattern. The transducer body and the first and second conductor patterns together form a photovoltaic transducer arrangement and the second conductor pattern constitutes an induction transducer.

The present invention relates to an improved silicon-based solar cell and various aspects thereof and a simple process for manufacturing said solar cell which overcomes one or more of the above disadvantages, without jeopardizing functionality and advantages.

SUMMARY OF THE INVENTION

The present invention relates in a first aspect to a front and rear contacted solar cell, in a second aspect to a process for making such a solar cell, and in a third aspect to a PV-module comprising said solar cells.

Inventors have now found that it is actually possible to replace part of these external power electronics by integrating passive components onto crystalline silicon (c-Si) solar cells. The passive components are typically provided as layers, or parts thereof. In semiconductor industry, as in solar cell fabrication, a layer is considered to relate to the provision, such as by deposition, of some material in the form of atoms or molecules on a substantially flat surface, such as on a substrate or base or further layer. It is noted in this respect that self-inductance of regular solar cells is small compared to the solar cell resistance. For instance, the inductance of a 2 cm x 4 cm c-Si PV cell was found to be 0.28 pH. Inventors have re-designed crystalline silicon solar cells with the goal of integration of passive components. As such, more useful values of inductance and likewise capacitance are obtained than those commonly exhibited by regular cell designs. For example, an approach is to form spiral-like patterns onto the device. These spiral-like patterns can be either the metal contacts of the solar cells themselves, or planar inductors fabricated on the solar cells, typically provided at a back side, or both. Furthermore, spiral-like patterns can be created using electrically conducting materials that are different from metals, such as Transparent Conductive Oxide (TCO) layers. Creating spiral-like patterns onto solar cells not only affects their inductance, but also their resistive and capacitive effects. As such, re-design possibilities affect the impedance as a whole. Thus, by integration of passive components in solar cells, more practically useful inductances are obtained compared to prior art cell designs. As such, the improved Si-based solar cells enable new power converter’s designs that make use of the adapted solar cell impedance. Novel, more compact and less expensive converters for PV module (and sub-module) applications are the result of this invention. So, by re-designing the cells to manipulate their impedance, the desired impedance is more accurately obtained and part of the power electronics that is normally connected to the cells externally is replaced. In an example of a boost converter (even though similar discussion could be made for the generic buck and buck/boost converters), the converters’ input capacitor and inductor is replaced by the PV cell’s capacitance and inductance; therefore, only the switching devices (and the output capacitor) is required as external components, leading to a more compact and less expensive power converter’s architecture. To a certain extent, also reliability is positively affected since the passive components are part of the solar cells and these are well protected as part of the PV module laminate, that has been extensively proven to properly protect the solar cells for 25+ years. In summary, advantages of the present invention are that for instance external power electronic components are replaced, and as such can be left out of the system. More compact and less expensive power converters could be designed when the solar cell impedance is manipulated properly. Thus, PV module designs with increasing power electronics granularity are cheaper and new designs are enabled. Also a wider range of locations can now be considered for applying solar cells. Also power transfer from solar cell to a DC-grid may be simplified. A possibly somewhat lower efficiency is balanced and compensated by better performance under partial shading, which often occurs for prolonged periods of times, or put different, solar cells can now simply be implemented at locations with in time varying illumination and shading. So a higher total energy yield is expected.

The present silicon based solar cell 1 comprises at least one p-n junction, a positive PV- generator terminal 31 in electrical contact with the p-n junction, a negative PV-generator terminal 32 in electrical contact with the p-n junction, wherein the terminals may be in direct or indirect electrical contact with the respective side of the p-n junction, wherein the terminal provide a contact opportunity to connect external components, such as other solar cells, a converter, electronics, and the like, a substrate 10, wherein the substrate comprises Si and dopants, at least one electrical contact layer 21,22,18, wherein the electrical contact layer, or part thereof can function as a terminal 31,32, wherein the at least one electrical contact layer covers < 99% of a surface of the solar cell at a respective front-side and/or respective back-side, in particular < 70%, more in particular <50%, wherein the coverage for the front-side contact typically is smaller (e.g. smaller than 50%) than for the back-side (e.g. 75%), characterized in that at least one passive component is provided, the at least one passive component each individually provided at the respective front-side and/or respective back-side of the solar cell, which passive component stores energy in a magnetic field when an electrical current flows through, wherein the at least one passive component covers < 99% of a surface of the solar cell at a respective front-side and/or respective back-side, that is the passive component is directly on top of or directly below the solar cell itself, respectively, in particular < 70%, more in particular <50%, wherein the at least one passive component each individually has a first passive component terminal and a second passive component terminal, wherein a passive component terminal may be shared or may be the same as the PV-generator terminal, or may be the end of the passive component, such as an end of a coil, wherein the passive component has an inductance of 0.1 pH-lH, or likewise 0.1 nH-0. IH/mm², wherein at least one of the two passive component terminals is [when in use or not in use, depending on the configuration] in direct or indirect electro-magnetic contact with the respective PV-generator terminal, in particular in direct or indirect electric contact, typically indirect electrical contact, that is with at least one further electric component in between said terminals, and the other of the two passive component terminals is in contact with an external terminal. The passive component is typically in the form of a layer or layer-like structure, such as an etched layer, in particular an etched layer providing the inductance, such as a spiral like layer forming at least one planar coil. It is preferred that the passive component does not have too many turns, preferably 1-6 turns, more preferably 1.25-4 turns, even more preferably 1.5-2 turns. The term “turn” refers to a loop in a coil or spiral. It is noted that the electrical contact layer 21,22 can be used as electron or hole transport layer, such as an n-type doped Si or p-type doped Si layer. These may have a high dopant concentration, such as 5*1O¹⁴-O.5*1O²⁰ n- or p-type dopants/cm³, In general a terminal may be considered as a point at which an external circuit can be connected, or a point where a first part of the present solar cell electro-magnetically overlaps with another part of the present solar cell. The external terminal typically provides the DC-current of the solar cell. The term “terminal” relates to a part that forms an end, e.g. of the passive component, or of the p-n-junction, that is a physical termination of said part. The terminals provide a point of contact, which may be used as such, or may not be used.

Thereby the present invention provides a solution to one or more of the above mentioned problems.

The present invention is also topic of a scientific article, submitted for publication, with title “Exploring the benefits, challenges, feasibility and progress of integrating power electronics into c-Si solar cells”, by the present inventors.

Advantages of the present description are detailed throughout the description. References to the figures are not limiting, and are only intended to guide the person skilled in the art through details of the present invention. DETAILED DESCRIPTION OF THE INVENTION

The present invention relates in a first aspect to a silicon based solar cell, and in a second aspect to a PV-module comprising said solar cell, in a third aspect to a power supply unit comprising various of said PV-modules, and to a method of producing said solar cell.

The present thin film inductors are typically made of a metal, such as copper, and TCO, and can be fabricated in various layouts, such as square, hexagonal, circular, and octagonal patterns. A thin film is a layer of material with a thickness ranging from fractions of a nanometer (monolayer) to several micrometers. A dependence of the inductance on the number of turns is usually quadratic. It is found that a main drawback of increasing the number of turns on a given area is that this causes the series resistance of the conductor to increase as well. An important figure of merit for inductors that quantifies the trade-off between inductance and resistance considered is the quality factor Q = L/ R. In general, Q needs to be greater than one for the device to act more like an inductor than a resistor. Apart from the quality factor, one of the main figures of merit for on-chip applications is the inductance density. A high inductance density is found to minimize the required surface area of the inductor. For air core inductors with reasonable quality factors, inductance densities up to 200 nH/ mm² can be achieved. It is worth noting that both the Q and the inductance density can be increased by enclosing the conductor with a magnetic material. Using this approach, a thin film inductor with an inductance density of 1.3 pH/ mm² and a quality factor above one is fabricated. Although magnetic materials can significantly increase the inductance density and quality factor, they bring along fundamental loss mechanisms; hysteresis and Eddy-currents, and are therefore less preferred. The core losses are found to become increasingly dominant for operation at higher frequencies, and are found to have a significant effect on the watt-hour efficiency of DC-DC power converters. Thus, air core inductors are more suitable for very high frequency (VHF) applications (30-300 MHZ). However, it must be noted that most designs are not suited for the higher current levels being common and present in PV modules. To quantify what inductance values may need to be achieved with planar coils supporting such current levels, inductances achieved with planar coils on PCBs in the field of Wireless Power Transfer (WPT) are studied. For such planar coils with an outer diameter of 10 cm (comparable to solar cell sizes), inductances between 1 pH and 4 pH (corresponding to inductance densities between 12 and 50 nH/cm²) have been reported; for diameters up to 20 cm, inductance values from several tens of pH up to 80 pH (corresponding to an inductance density of 250 nH/cm²) are found. Such inductance values are suited as they are in the same order of magnitude as inductors that are used in module-level power optimizers. For example, the inductor of an exemplary module-level power optimizer is equal to 22 pH. Inventors have re-designed the metallization patterns that are already present in prior art PV cell designs. It offers an ease of integration into existing manufacturing processes, since it can be realized without any additional fabrication steps in view of standard c-Si cell flowcharts. Since the prior art metal grid pattern on the front surface involves a careful optimization in the trade-off between resistive and shading losses, there is not much room to create spiral-like metallization patterns here. Typically, there is more space available to form patterns on the backside, where the absence of shading losses (at least in non-bifacial cells) gives more room to make alterations to the metallization pattern. On the backside of an FBC solar cell, the metal contacts with underlying point contacts are re-designed into a spiral-like shape, as presented in Figure 4a, b. A similar approach could be used for IBC solar cells, as presented in Figure 2a, b. The two-diode equivalent circuit of a solar cell with increased selfinductance is presented in Figure 5. It is noted that analytical formulas developed for inductors may not be directly applicable for a solar cell-integrated approach, as the current through the metal layer may increase towards the outer side of the spiral. Furthermore, the spiral-like metallization patterns on the back of solar cells are considered to affect the series resistance and thus the fill factor with respect to standard c-Si solar cell designs. Finally, it is worth noting that the addition of a magnetic material is considered to increase the self-inductance without increasing the number of turns. Deposition of a magnetic material on one side of the inductor can increase the inductance up to 100%. Including such magnetic materials would increase fabrication costs and require additional processing steps using atypical materials, such as Ni, Co, Zr, Gd, Fe, Ni-Fe, Co-Zr-Ta, and Fe-Al-O. In an alternative, referred to as the decoupled approach, the inductor may be electrically separated from the charge carrier collection layers by an insulator layer, as presented in Figure 3. This method is found to offer more flexibility in the inductor design, as it allows the charge carrier collection layers and the planar coil to be optimized separately. Thus, the process of increasing the self-inductance without causing a too large loss in fill factor is simplified. Furthermore, the decoupled approach allows configurations where the cell is transformed into a so-called 4-terminal device. As such, it enables integrated designs where the inductor is not directly connected to the PV generator, such as the buck converter. A further advantage of this approach is the reduced probability that the addition of magnetic materials may affect the solar cell negatively, as it is separated by said insulating layer. The structure also allows for designs where the magnetic material is present on both sides of the inductor, also known as sandwich structure.

In an exemplary embodiment of the present solar cell at least one of the two passive component terminals coincides with the respective positive PV-generator terminal or negative PV-generator terminal. The term “coincide” is used to reflect that the passive component terminal corresponds in position with the respective PV-generator terminal, that is, overlap with one and another.

In an exemplary embodiment of the present solar cell the at least one passive component forms an at least one first electrical contact layer and wherein said first electrical contact layer is in electrical contact with the respective p-n junction of the solar cell [both are 2T variant]. In an exemplary embodiment of the present solar cell the at least one of the two passive component terminals coincides with the respective positive PV-generator terminal or negative PV-generator terminal and wherein at least one other of the two passive component terminals does not coincide with the respective positive PV-generator terminal or negative PV-genera- tor terminal .

In an exemplary embodiment of the present solar cell the at least one passive component forms at least one second electrical contact layer and wherein said electrical second contact layer is in electric contact with the respective first electrical contact layer, wherein said first electrical contact layer is in electrical contact with the respective p-n junction of the solar cell [both are 3T variant].

In an exemplary embodiment of the present solar cell none of the two passive component terminals coincides with the respective p-n junction of the solar cell.

In an exemplary embodiment of the present solar cell the at least one passive component forms at least one second electrical contact layer and wherein said electrical second contact layer is in direct or indirect electro-magnetic contact with the respective first electrical contact layer, and wherein in particular said at least one first electrical contact layer and said at least one second electrical contact layer are electrically separated from one and another by an electrical insulation material, such as a SiCh layer, wherein said first electrical contact layer is in electrical contact with the respective p-n junction of the solar cell [both are 4T variant].

In an exemplary embodiment of the present solar cell the silicon of the substrate is selected from crystalline silicon, polycrystalline silicon, nano-crystalline silicon, and combinations thereof, and/or wherein the substrate (10) is a single sided or double-sided flat substrate (10) surface, and/or wherein the substrate (10) is a single sided or double-sided textured substrate (10) surface (ISO 4287: 1997), in particular textured with a surface roughness Ra of 1-20 pm, such as 2-10 pm, and/or wherein the textured surface has an aspect ratio (height: depth of a textured structure) of 2-10, and/or wherein the substrate (10) comprises l*10¹²-0.5*10¹⁹ n- or p-type dopants/cm³, in particular 2*10¹⁴-10¹⁷ dopants/cm³, more in particular 5*10¹⁴-10¹⁶ dopants/cm³, such as 8*10¹⁴-3*10¹⁵ dopants/cm³, and/or wherein the substrate (10) has a resistivity of 0.1-1000 ohm*cm at 300K, more in particular 1- 100 ohm* cm, such as 5-10 ohm* cm, and/or wherein a doping concentration is spatially constant, or wherein a doping concentration varies spatially, and/or wherein n-type dopants are selected from P, As, Bi, Sb and Li, and/or wherein p-type dopants are selected from B, Ga, and In, and/or wherein a dopant concentration is 5*10¹⁴-0.5*10¹⁹ n- or p-type dopants/cm³, and/or wherein the solar cell is selected from a hetero-j unction solar cell, a back-contacted solar cell, such as an interdigitated back-contacted solar cell, and a back and front contacted solar cell.

In an exemplary embodiment of the present solar cell at least one of the at least two passive component terminals is in electrical contact with at least one further electrical component, such as a switch, a capacitor, a diode, and a resistor.

In an exemplary embodiment of the present solar cell the at least one passive component is part of a circuit selected from a DC-DC circuit, such as a DC-DC boost circuit, a DC-DC buck boost circuit, a DC-DC buck circuit, and a DC-AC circuit.

In an exemplary embodiment of the present solar cell the at least one electrical contact layer comprises a spiral shaped conducting material.

In an exemplary embodiment of the present solar cell the at least one passive component each individually has an inductance of 0.1 pH-lOH, in particular 1 pH-lH, more in particular 2 pH-50 pH, such as 5-20 pH, and/or wherein the at least one passive component each individually is adapted to provide a high-power low frequency output, in particular < 500 kHz, more in particular <100kHz, such as < 10 kHz, and typically > 100 Hz, and/or wherein the at least one passive component each individually has a resistance (end-to-end) of < 30 Q, as measured using a four-point probe technique at a temperature of 300K, in particular a resistance of < 1 Q, more in particular a resistance of < 0.1 Q, even more in particular a resistance of < 5mQ, and/or wherein at least one passive component is provided with at least one magnetic material, in particular at least one layer of magnetic material, and/or wherein at least one passive component is provided with at least one void, in particular air, wherein the at least one electrical contact layer and/or at least one passive component has a thickness of 0.1-100 pm, in particular a thickness of 1-50 pm, more in particular a thickness of 2-20 pm, and/or wherein the at least one electrical contact layer and/or at least one passive component has a width of 20-10000 pm, in particular 100-1000 pm, such as 180-220 pm, and/or wherein the at least one electrical contact layer and/or at least one passive component comprises a material selected from metals, in particular from Cu, W, Al, and Ag, from semi-conducting materials, such as n-doped Si and p-doped Si, from transparent conductive oxides, such as ITO, and combinations thereof, and/or in particular wherein the metal of the metal contacts (13) independently comprises at least one of Cu, Al, W, Ti, Ni, Cr, Ag, and/or wherein a thickness of said metal contacts (13) is 200 nm-50 pm, in particular 1-25 pm, and/or wherein the metal contact (13) is selected from a metal layer, a metal grid, a metal line, or a combination thereof, and/or wherein the metal contact (13f) at a front side covers <20% of a surface area of the front side, preferably <10% thereof, such as <5% thereof.

In an exemplary embodiment the present solar cell comprises two or more passive components, in particular three or more passive components, such as 4-6 passive components.

In an exemplary embodiment of the present solar cell the at least one electrical contact layer is a charge carrier connecting layer.

In an exemplary embodiment of the present solar cell the solar cell has a size of 1*1 cm² - 20*20 cm².

In an exemplary embodiment of the present solar cell the at least one passive component is provided on the backside and/or wherein the at least one passive component is provided on the front side.

In an exemplary embodiment the present solar cell comprises directly on the substrate, at least one intrinsic layer (11), and/or directly on the intrinsic layer a transparent conductive oxide (TCO)-layer (12), wherein the at least one intrinsic layer (11) and transparent conductive oxide (TCO)-layer (12) provide electron transport or hole transport, respectively, and a metal contact (13) in electrical contact with the TCO-layer, in particular wherein the at least one intrinsic layer (11) is selected from intrinsic Si, such as (i)a- Si:H and (i)nc-Si:H, from intrinsic Si-dielectrics, such as (i)a-SiO_x:H, (i)a-SiC_x:H, and (i)a- SiNx:H, or dielectric metal oxide passivation layer, and combinations thereof.

In an exemplary embodiment of the present solar cell the thickness of the intrinsic layer each individually is from 0.1 nm-50 nm, in particular 1-20 nm, such as 2-15 nm.

In an exemplary embodiment of the present solar cell the intrinsic layer each individually is textured, in particular with a same texturing as the substrate.

In an exemplary embodiment of the present solar cell the material of the transparent conductive oxide layer (12) is selected from Indium Tin Oxide (ITO), IOH, ZnO, or doped ZnO, such as Aluminium doped ZnO, doped Tin oxide, such as fluorine doped tin oxide, doped indium oxide, such as Indium Fluor Oxide (IFO:H), and Indium Tungsten Oxide (IWO), and/or wherein a thickness of the transparent conductive layer (12) is 10-200 nm, in particular 30-170 nm.

In an exemplary embodiment of the present solar cell the refractive index of the transparent conductive layer (12) is <2.2.

In an exemplary embodiment of the present solar cell in the at least one intrinsic layer (11) and transparent conductive oxide (TCO)-layer (12) providing electron transport, the TCO- layer is selected from Aluminium doped ZnO.

In an exemplary embodiment of the present solar cell in the at least one intrinsic layer (11) and transparent conductive oxide (TCO)-layer (12) providing hole transport, the TCO-layer is selected from IWO.

In an exemplary embodiment of the present solar cell the work function of the TCO layer (12) is from 2 eV to 8 eV, in particular 3.4 eV to 6.4 eV.

In an exemplary embodiment of the present solar cell the work function of the TCO layer (12) is 3.4 eV to 4.7 eV in case of the TCO-layer mainly transporting electrons. In an exemplary embodiment of the present solar cell the work function of the TCO layer (12) is 4.7 eV to 6.4 eV in case of the TCO-layer mainly collecting holes.

In an exemplary embodiment of the present solar cell in at least one first stack the TCO layer (12) has a work function for transporting electrons and in at least one second stack the TCO layer (12) has a work function for collecting holes.

In an exemplary embodiment of the present solar cell the TCO layer each individually is textured, in particular with a same texturing as the intrinsic layer.

In an exemplary embodiment of the present solar cell the VOC is >600 mV, such as > 700 mV, and/or wherein a J_sc is > 30 mA/cm², such as > 40 mA/cm², and/or a fill factor (FF) of >60%, in particular > 70%, such as > 80%, and/or having an efficiency of > 16%, in particular > 20%, such as > 23.2%. Measurements are carried out under the so-called Standard Test Conditions (temperature of solar cell of 25 C, irradiance equal to 1000 W/m² and AM 1.5 spectrum), considered as the industry standard for the characterization of solar cells.

The invention is further detailed by the accompanying figures and examples, which are exemplary and explanatory of nature and are not limiting the scope of the invention. To the person skilled in the art, it may be clear that many variants, being obvious or not, may be conceivable falling within the scope of protection, defined by the present claims.

SUMMARY OF FIGURES

Figurel shows a prior art solar cell.

Figures 2a-b, 3 and 4a-b show present layouts. Figs. 2a-2b are two terminal (2T) layouts, and fig. 3 and 4a-b a three terminal (3T) layout.

Figure 6 shows a prior art electrical representation. The left part represents a prior art PV- cell, and the left part a prior art DC-DC boost converter.

Figures 7-9 and 11-16 show present electrical representations. In fig. 7 the left part represents the present PV-cell with increased self-inductance, and the right part an optimized and simplified DC-DC boost converter.

Figure 10 shows a four terminal (4T) layout.

Figs. 17a,b show experimental results.

DETAILED DESCRIPTION OF FIGURES

I solar cell

10 substrate

I I p-doped poly silicon oxide

12 n-doped poly silicon oxide

13 p-doped crystalline silicon

14 n-doped crystalline silicon

15 thin dielectric layer

17 dielectric layer or stack of layers

18b back side metal contacts or back side metal layer 18f front side metal contacts or front side metal layer 19 transparent conductive oxide layer

20 textured surface

21 highly doped p-type Si or hole transport layer

22 highly doped n-type Si or electron transport layer

31 positive PV-generator terminal

32 negative PV-generator terminal

33 first passive component terminal

34 second passive component terminal

41 external terminal [not directly part of the invention]

42 external terminal [not directly part of the invention]

The figures are further detailed in the description of the experiments below.

Fig. 1 shows a cross-section of a prior art front- and back-contacted (FBC) solar, with metal contacts 18f (front) and 18b (back, a silicon substrate 10, optionally p-doped poly silicon oxide 11 an optionally n-doped poly silicon oxide 12, p-doped crystalline silicon 13, n-doped crystalline silicon 14, thin dielectric layer 15, and an optional dielectric layer or stack of layers 17. The layers and substrate are optionally textured, as shown.

Figure 2a, b. On the left, a typical charge carrier collection structure of an interdigitated back-contacted (IBC) solar cell is shown (rear side of the cell). On the right, a possible re-design is proposed to increase the self-inductance of the cell. Therein interdigitated transport layers 21,22 are shown, for hole transport and electron transport, respectively. In the eventual IBC cell, metal contacts could be placed on top of these doped layers.

Figure 3. Approach where the inductor is electrically connected to one on the PV cell contacts, but it is spatially separated from the solar cell by an insulating layer.

Figure 4a, b. In high-efficiency front/back-contacted (FBC) cells, point contacts are used on the backside to reduce the relatively defective metal-semiconductor interface, as shown on the left. On the right, a possible re-design of such a backside metallization pattern is shown. By creating a spiral-like metallization pattern, the self-inductance of the PV cell can be increased.

Figure 5. Two-diode equivalent solar cell model expanded with self-inductance (schematically represented by L_s). I_Ph is the photocurrent, lai and Id2 represent the diode current, and R_Sh and R_s are the shunt and series resistance, respectively. Finally, Cpv is the PV cell capacitance and L_s represents the enhanced inductance due to the addition of a planar coil.

Figure 6. A prior art configuration of a PV cell (left) and a DC-DC boost converter (right). The DC-DC boost is an example converter that can be used for maximum power point tracking e.g., for strings of PV cells.

Figure 7. Proposed method where the higher inductance of the solar cell (left) allows for maximum power point tracking with a simplified power converter (right). Also optional electromagnetic contacts to external terminal 41,42 are shown.

Figs. 8-14 show electric schemes representing embodiments of the present invention.

Fig 8: Example circuit of a DC-DC boost converter. Fig 9: Example circuit of a DC-DC buck-boost converter. The numbers represent the potential connection points to the three terminals in Figure 3. Also optional electromagnetic contacts to external terminal 41,42 are shown.

Fig 10: On the left, an approach is presented where the planar conductor is completely separated from the PV cell by an insulating layer. As such, a four-terminal (4T) device is created. On the right, an example circuit of a DC-DC buck converter is shown. The numbers represent the potential connection points to the four terminals in the left Figure.

Fig. 11 : In the DC-DC-boost configuration, the inductor may be directly connected to the output of the PV generator. As such, a two-terminal PV / inductor configuration is sufficient to deploy the PV-integrated inductor in this converter.

Fig. 12: In the DC-DC-boost configuration, the inductor is directly connected to the output of the PV generator. However, in this configuration, there may need to be an externally accessible terminal in between the PV generator and the inductor. As such, at least a three-terminal PV / inductor configuration is required to deploy the PV-integrated inductor in this converter. Also optional electromagnetic contacts to external terminal 41,42 are shown.

Fig. 13: In the DC-DC buck configuration, there is no direct electrical connection between the PV generator and the inductor. As such, at least a four-terminal PV / inductor configuration may be required to deploy the PV-integrated inductor in this converter. Also optional electromagnetic contacts to external terminal 41,42 are shown.

Fig. 14: For wireless power transfer, there is no direct electrical connection between the PV generator and the primary coil. As such, at least a four-terminal PV / inductor configuration is required to deploy the PV-integrated inductor as the primary coil for wireless power transfer.

Fig. 15: In certain power converter topologies, more than one inductor may be used. In the figure, one inductor is directly connected to the PV generator, whereas the other is not. Also optional electromagnetic contacts to external terminal 41,42 are shown.

Fig. 16: In certain power converter topologies, more than one inductor may be used. In the figure, both inductors are directly connected to the PV generator. In this case, there needs to be an externally accessible terminal in between the PV generator and the inductors.

Fig. 17a,b show simulation result for the inductance (pH) and resistance (mfi) in view of number of coils.

Experiments

The following experiments are carried out.

Planar coil designs are optimized, such as in number of turns, thickness, and crosssection of the coils. Optimization is partly done through simulations in computer programs, such as COMSOL

In addition, also the combination of PV cell design and coil material and coil design is studied, both experimentally and through simulations.

An also simulations of PV devices connected to power converters are performed.

Simulation results Inventors have performed some simulations in COMSOL for planar coil geometries with an area of 10 cm². The simulated coil is made of copper, and high frequency effects (e.g. skin effect and proximity effect) are not included. For an increasing number of turns (1-8 turns) it can be seen that the inductance increases, resulting in an inductance above 3.5 pH at eight turns. This demonstrates that the inductance of such planar coils is sufficiently high for application in power converters connected to a solar cell (string). However, for increasing number of turns the resistance of the coil also increases, leading to higher parasitic ohmic losses in the coil. As such, the challenge for cell-integrated inductors is to realize a planar coil design that simultaneously has sufficiently high inductance and low enough parasitic resistance.

The invention although described in detailed explanatory context may be best understood in conjunction with the accompanying figures.

It should be appreciated that for commercial application it may be preferable to use one or more variations of the present system, which would similar be to the ones disclosed in the pre- sent application and are within the spirit of the invention.

Claims

1. A silicon based solar cell (1) comprising at least one p-n junction, a positive PV-generator terminal (31) in electrical contact with the p-n junction, a negative PV-generator terminal (32) in electrical contact with the p-n junction, a substrate (10), wherein the substrate comprises Si and dopants, at least one electrical contact layer (21,22,18), wherein the electrical contact layer, or part thereof is configured to function as a PV-generator terminal (31,32), wherein the at least one electrical contact layer covers < 99% of a surface of the solar cell at a respective front-side and/or respective back-side, in particular < 70%, more in particular <50%, characterized in that at least one passive component is provided, in particular a thin film passive component, wherein the at least one passive component each individually is provided at the respective front-side and/or respective back-side of the solar cell, wherein the at least one passive component covers < 99% of a surface of the solar cell at a respective front-side and/or respective back-side, in particular < 70%, more in particular <50%, wherein the at least one passive component each individually has a first passive component terminal (33) and a second passive component terminal (34), wherein the passive component has an inductance of 0.1 pH-lH, wherein at least one of the two passive component terminals (33,34) is configured to be in direct or indirect electro-magnetic contact with the respective PV-generator terminal (31,32), and the other of the two passive component terminals (34,33) is configured to be in contact with an external terminal.

2. The silicon based solar cell(l) according to claim 1, wherein at least one of the two passive component terminals coincides with the respective positive PV-generator terminal or negative PV-generator terminal, and/or wherein the at least one passive component forms an at least one first electrical contact layer and wherein said first electrical contact layer is in electrical contact with the respective p-n junction of the solar cell, and/or wherein at least one of the two passive component terminals coincides with the respective positive PV-generator terminal or negative PV-generator terminal and wherein at least one other of the two passive component terminals does not coincide with the respective positive PV-generator terminal or negative PV-generator terminal, and/or wherein the at least one passive component forms at least one second electrical contact layer and wherein said electrical second contact layer is in electric contact with the respective first electrical contact layer, wherein said first electrical contact layer is in electrical contact with the respective p-n junction of the solar cell, and/or wherein none of the two passive component terminals coincides with the respective p-n junction of the solar cell, and/or wherein the at least one passive component forms at least one second electrical contact layer and wherein said electrical second contact layer is in direct or indirect electro-magnetic contact with the respective first electrical contact layer, and wherein in particular said at least one first electrical contact layer and said at least one second electrical contact layer are electrically separated from one and another by an electrical insulation material, such as a SiCh layer, wherein said first electrical contact layer is in electrical contact with the respective p-n junction of the solar cell.

3. The silicon based solar cell according to any of claims 1-2, wherein the silicon of the substrate is selected from crystalline silicon, polycrystalline silicon, nano-crystalline silicon, and combinations thereof, and/or wherein the substrate (10) is a single sided or double-sided flat substrate (10) surface, and/or wherein the substrate (10) is a single sided or double-sided textured substrate (10) surface (ISO 4287: 1997), in particular textured with a surface roughness Ra of 1-20 pm, such as 2-10 pm, and/or wherein the textured surface has an aspect ratio (height: depth of a textured structure) of 2-10, and/or wherein the substrate (10) comprises l*10¹²-0.5*10¹⁹ n- or p-type dopants/cm³, in particular 2*10¹⁴-10¹⁷ dopants/cm³, more in particular 5*10¹⁴-10¹⁶ dopants/cm³, such as 8*10¹⁴-3*10¹⁵ dopants/cm³, and/or wherein the substrate (10) has a resistivity of 0.1-1000 ohm*cm at 300K, more in particular 1- 100 ohm* cm, such as 5-10 ohm* cm, and/or wherein a doping concentration is spatially constant, or wherein a doping concentration varies spatially, and/or wherein n-type dopants are selected from P, As, Bi, Sb and Li, and/or wherein p-type dopants are selected from B, Ga, and In, and/or wherein a dopant concentration is 5*10¹⁴-0.5*10¹⁹ n- or p-type dopants/cm³, and/or wherein the solar cell is selected from a hetero-j unction solar cell, a back-contacted solar cell, such as an interdigitated back-contacted solar cell, and a back and front contacted solar cell.

4. The silicon based solar cell according to any of claims 1-3, wherein at least one of the at least two passive component terminals is in electrical contact with at least one further electrical component, such as a switch, a capacitor, a diode, and a resistor, and/or wherein the at least one passive component is part of a circuit selected from a DC-DC circuit, such as a DC-DC boost circuit, a DC-DC buck boost circuit, a DC-DC buck circuit, and from a DC-AC circuit.

5. The silicon based solar cell(l) according to any of claims 1-4, wherein the at least one electrical contact layer comprises a spiral shaped conducting material.

6. The silicon based solar cell(l) according to any of claims 1-5, wherein the at least one passive component each individually has an inductance of 0.1 pH-lH, in particular 1 pH-lH, more in particular 2 pH-50 pH, such as 5-20 pH, and/or wherein the at least one passive component each individually has an inductance of 0.1 nH/mm²- 0.1 H/mm², in particular 0.5 nH/mm²-2 pH/mm², more in particular 2.5 nH/mm²-1.3 pH/mm², such as 10 nH/mm²-200 nH/mm², and/or 17 wherein the at least one passive component each individually is adapted to provide a high-power low frequency output, in particular < 500 kHz, more in particular <100 kHz, such as < 10 kHz, and/or wherein the at least one passive component each individually has a resistance of < 30 Q, in particular a resistance of < 1 Q, more in particular a resistance of < 0.1 Q, even more in particular a resistance of < 5m Q, and/or wherein at least one passive component is provided with at least one magnetic material, in particular at least one layer of magnetic material, and/or wherein at least one passive component is provided with at least one void, in particular air, wherein the at least one electrical contact layer and/or at least one passive component has a thickness of 0.1-100 pm, in particular a thickness of 1-50 pm, more in particular a thickness of 2-20 pm, and/or wherein the at least one electrical contact layer and/or at least one passive component has a width of 20-10000 pm, in particular 100-1000 pm, such as 180-220 pm, and/or wherein the at least one electrical contact layer and/or at least one passive component comprises a material selected from metals, in particular from Cu, W, Al, and Ag, from semi-conducting materials, such as n-doped Si and p-doped Si, from transparent conductive oxides, such as ITO, and combinations thereof, and/or in particular wherein the metal of the metal contacts (13) independently comprises at least one of Cu, Al, W, Ti, Ni, Cr, and Ag, and/or wherein a thickness of said metal contacts (13) is 200 nm-50 pm, in particular 1-25 pm, and/or wherein the metal contact (13) is selected from a metal layer, a metal grid, a metal line, or a combination thereof, and/or wherein the metal contact (13f) at a front side covers <20% of a surface area of the front side, preferably <10% thereof, such as <5% thereof.

7. The silicon based solar cell(l) according to any of claims 1-6, comprising two or more passive components, in particular three or more passive components, such as 4-6 passive components.

8. The silicon based solar cell(l) according to any of claims 1-7, wherein the at least one electrical contact layer is a charge carrier connecting layer, and/or wherein the solar cell has a size of 1*1 cm² - 20*20 cm², and/or wherein the at least one passive component is provided on the backside and/or wherein the at least one passive component is provided on the front side.

9. The silicon based solar cell(l) according to any of claims 1-8, comprising directly on the substrate, at least one intrinsic layer (11), and/or directly on the intrinsic layer a transparent conductive oxide (TCO)-layer (12), wherein the at least one intrinsic layer (11) and transparent conductive oxide (TCO)-layer (12) provide electron transport or hole transport, respectively, and a metal contact (13) in electrical contact with the TCO-layer, in particular wherein the at least one intrinsic layer (11) is selected from intrinsic Si, such as (i)a- 18

Si:H and (i)nc-Si:H, from intrinsic Si-dielectrics, such as (i)a-SiO_x:H, (i)a-SiC_x:H, and (i)a- SiNx:H, or dielectric metal oxide passivation layer, and combinations thereof, and/or wherein the thickness of the intrinsic layer each individually is from 0.1 nm-50 nm, in particular 1-20 nm, such as 2-15 nm, and/or wherein the intrinsic layer each individually is textured, in particular with a same texturing as the substrate.

10. The silicon based solar cell(l) according to any of claims 6-9, wherein the material of the transparent conductive oxide layer (12) is selected from Indium Tin Oxide (ITO), IOH, ZnO, or doped ZnO, such as Aluminium doped ZnO, doped Tin oxide, such as fluorine doped tin oxide, doped indium oxide, such as Indium Fluor Oxide (IFO:H), and Indium Tungsten Oxide (IWO), and/or wherein a thickness of the transparent conductive layer (12) is 10-200 nm, in particular 30-170 nm, and/or wherein the refractive index of the transparent conductive layer (12) is <2.2, and/or wherein in the at least one intrinsic layer (11) and transparent conductive oxide (TCO)-layer (12) providing electron transport, the TCO-layer is selected from Aluminium doped ZnO, and/or wherein in the at least one intrinsic layer (11) and transparent conductive oxide (TCO)-layer (12) providing hole transport, the TCO-layer is selected from IWO, and/or wherein the work function of the TCO layer (12) is from 2 eV to 8 eV, in particular 3.4 eV to 6.4 eV, and/or wherein the work function of the TCO layer (12) is 3.4 eV to 4.7 eV in case of the TCO-layer mainly transporting electrons, and/or wherein the work function of the TCO layer (12) is 4.7 eV to 6.4 eV in case of the TCO-layer mainly collecting holes, and/or wherein in at least one first stack the TCO layer (12) has a work function for transporting electrons and in at least one second stack the TCO layer (12) has a work function for collecting holes, and/or wherein the TCO layer each individually is textured, in particular with a same texturing as the intrinsic layer.

11. The silicon based solar cell(l) according to any of claims 1-10, wherein the VOC is >600 mV, such as > 700 mV, and/or wherein a J_sc is > 30 mA/cm², such as > 40 mA/cm², and/or a fill factor (FF) of >60%, in particular > 70%, such as > 80%, and/or having an efficiency of > 16%, in particular > 20%, such as > 23.2%, when tested under AMI.5 conditions.

12. PV-module comprising at least one silicon based solar cell(l) according to any of claims 1- 11.

13. The PV-module according to claim 12, comprising output power controlling electronics, wherein the output power controlling electronics is in electrical connection with the respective at 19 least one PV-generator terminal and/or the at least one passive component terminal of the at least one silicon based solar cell(l).

14. The PV-module according to claim 13, wherein the output power controlling electronics comprises at least one converter, in particular 1 converter per 6 solar cells, more in particular 1 converter per 4 solar cells, even more in particular 1 converter per 1-2 solar cells, wherein the converter is a DC-DC converter, a DC-DC converter, a DC-DC buck converter, a DC-DC buck booster converter, or a DC-AC converter.

15. A power supply system comprising 2-2¹³ PV-modules according to any of claims 12-14, in particular 2⁵-2¹⁰ PV-modules, more in particular 2⁷-2⁹ PV-modules.

16. Method of producing a silicon based solar cell(l) according to any of claims 1-14, comprising providing a substrate, such as a crystalline Si-substrate, optionally texturing the substrate, such as double-side texturing the substrate, thereafter immersing the substrate into a strong oxidizing solution, thereafter etching the oxidized substrate by dipping the oxidized substrate into an acidic solution, directly thereafter loading the etched substrate into a layer deposition tool, and depositing an intrinsic Si layer on at least one side of the etched substrate, thereafter depositing a transparent conductive oxide(TCO) layer on the at least one intrinsic Si- layer, depositing a metal layer on the TCO-layer, depositing a metal layer on the back-side, and patterning the metal layer and/or TCO layer therewith forming at least one passive component.