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WO2023019824A1 - Substrat et sa structure d'emballage - Google Patents

Substrat et sa structure d'emballage Download PDF

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Publication number
WO2023019824A1
WO2023019824A1 PCT/CN2021/137816 CN2021137816W WO2023019824A1 WO 2023019824 A1 WO2023019824 A1 WO 2023019824A1 CN 2021137816 W CN2021137816 W CN 2021137816W WO 2023019824 A1 WO2023019824 A1 WO 2023019824A1
Authority
WO
WIPO (PCT)
Prior art keywords
solder balls
region
area
substrate
solder
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2021/137816
Other languages
English (en)
Chinese (zh)
Inventor
周新书
孟宪余
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Axera Technology Beijing Co Ltd
Original Assignee
Axera Technology Beijing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Axera Technology Beijing Co Ltd filed Critical Axera Technology Beijing Co Ltd
Publication of WO2023019824A1 publication Critical patent/WO2023019824A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13016—Shape in side view

Definitions

  • the present application relates to the technical field of chip packaging, in particular, to a substrate and a packaging structure thereof.
  • the array of solder balls on the back of the chip is arranged at equal intervals, which is convenient for soldering to the circuit board.
  • the array of solder balls arranged at equal intervals limits the number of solder balls on the chip, and the number of solder balls arranged is relatively limited.
  • the present application provides a substrate and its packaging structure, which solve the above problems by arranging solder balls in different regions at unequal intervals.
  • the substrate may include a first region and a second region, the second region is arranged around the first region, and multiple solder balls, wherein there is a first pitch between the solder balls in the first region, and a second pitch smaller than the first pitch between the solder balls in the second region;
  • the solder balls in one area are provided with through holes for signal transmission through the through holes; the solder balls in the second area are led out through wires for signal transmission through the wires.
  • the above designed substrate by designing the first region and the second region, and designing the second distance between the solder balls in the second region to be smaller than the first distance between the solder balls in the first region, makes the designed substrate relatively For the arrangement of the first pitch, more solder balls can be arranged, which solves the problem of increasing the package size caused by the increase of the substrate in the related art, which in turn increases the cost of the package, or in order to realize the corresponding function
  • the technical problem that the substrate cannot be placed in the package is that the substrate cannot be placed in the package; in addition, by using the technical solution that the solder balls in the second area are led out through the leads, and the solder balls in the first area are transmitted through the through holes, the circuit board is reduced.
  • the number of wiring layers can achieve the purpose of cost saving.
  • a plurality of through holes may be arranged in the first region, each of the through holes is arranged in the first pitch, and the solder balls in the first region
  • the leads are connected to other circuit layers of the circuit board through corresponding through holes, so as to realize signal transmission between signals in the first area and the other circuit layers.
  • a plurality of passive elements may be arranged in the first region, and the passive elements are arranged at intervals from the solder balls.
  • the substrate may further include a third region disposed around the second region, and a plurality of solder balls are disposed in the third region, wherein the solder balls in the third region
  • the spacing between the solder balls is greater than or equal to the second spacing; wherein, the third area also includes a plurality of lead gaps, which are formed by the spacing between the solder balls in the third area greater than the second spacing The leads of the solder balls in the second region are led out through the lead gaps, so as to realize signal transmission in the second region.
  • the designed substrate can be arranged more than the arrangement of the first pitch.
  • solder balls in addition, the leads of the solder balls in the second area are drawn out through the lead gaps formed in the third area, the solder balls in the third area are directly drawn out through the leads, and the solder balls in the first area realize signal transmission through through holes, thereby achieving
  • the purpose of reducing the number of wiring layers of the circuit board is to reduce the cost of the circuit board; moreover, since the leads of the solder balls in the second area are drawn out through the lead gap formed in the third area, the leads in the second area have enough lead-out space , to avoid wiring or installation problems caused by lead volume or insufficient space.
  • the solder balls with close distances in the third area can form a solder ball pair, and the solder balls in the solder ball pair are drawn out through wires, so as to realize the distance in the third area through wires. transmission of signals.
  • the distance between the solder balls in the solder ball pair in the third region may be equal to the second distance, so as to facilitate the molding of the substrate.
  • the pairs of solder balls in the third region may be arranged in a first direction, and the lead gaps are formed between a plurality of pairs of solder balls in a second direction. , where the first direction is perpendicular to the second direction.
  • the leads in the second region and the third region may extend away from the first region along the second direction.
  • the solder balls in the first region, the second region and the third region may be symmetrically arranged.
  • the solder balls in the first region may be arranged in a matrix.
  • the four solder balls in the first region may share one through hole, so that the leads of the four solder balls are connected to the circuit board through the same through hole. other circuit layers.
  • the two solder balls in the first region may share a through hole, so that the leads of the two solder balls are connected to the circuit board through the same through hole. other circuit layers.
  • a through hole is separately provided for each solder ball in the first region, so that the lead wire of each solder ball is connected to the circuit board through the corresponding through hole other circuit layers.
  • Some other embodiments of the present application provide a package structure, which includes: a package body, the substrate according to any one of the foregoing embodiments, and circuit elements on the substrate.
  • the package structure designed above because it includes the substrate designed in some embodiments of the present application, therefore, the package structure designed can arrange more solder balls compared to the first-pitch arrangement, solving the problem of In the related art, the increase of the size of the package will lead to the increase of the package cost or the technical problem that the substrate cannot be placed in the package.
  • the solder balls in the second area are led out through leads, and the solder balls in the first area are transmitted through through holes, thereby reducing the number of wiring layers of the circuit board and achieving the purpose of saving costs.
  • FIG. 1 is a schematic diagram of a first structure of a substrate provided in an embodiment of the present application
  • FIG. 2 is a schematic diagram of a first structure of a via layout provided by an embodiment of the present application
  • FIG. 3 is a second structural schematic diagram of a via layout provided by an embodiment of the present application.
  • FIG. 4 is a second structural schematic diagram of the substrate provided by the embodiment of the present application.
  • FIG. 5 is a schematic diagram of a third structure of a substrate provided in an embodiment of the present application.
  • FIG. 6 is a schematic diagram of a fourth structure of a substrate provided in an embodiment of the present application.
  • FIG. 7 is a schematic structural diagram of a packaging structure provided by an embodiment of the present application.
  • Icons 1-package structure; 10-substrate; 101-first area; 1011-passive component; 102-second area; 103-third area; 1031-lead gap; 1032-second lead; 20-solder ball; 201 - through hole; 202 - first lead; 203 - solder ball pair; 50 - package; 60 - circuit element; L1 - first spacing; L2 - second spacing; L3 - third spacing.
  • the substrate 10 includes a first region 101 and a second region 102, and the second region 102 surrounds the first region 101, a plurality of solder balls 20 are arranged in the first area 101 and the second area 102, the solder balls 20 in the first area 101 have a first distance L1, and the solder balls 20 in the second area 102 There is a second distance L2, and the second distance L2 is smaller than the first distance L1.
  • the first distance L1 between each solder ball 20 in the first region 101 is 0.65mm
  • the second distance L2 between each solder ball 20 in the second region 102 can be less than 0.65mm, as specifically 0.4mm.
  • through-holes 201 are provided corresponding to the solder balls 20 in the first area 101, and then signal transmission is realized through the through-holes; Lead wires realize signal transmission.
  • the substrate with the above structural design by designing the first region 101 and the second region 102, and designing the second distance between the solder balls 20 in the second region 102 to be smaller than the first distance between the solder balls 20 in the first region , so that the designed substrate can arrange more solder balls compared to the equal-spaced arrangement of the first pitch, and can give the first region 101 and the second region 102 different circuit functions according to different regions.
  • the solder balls 20 in the second area 102 are led out through leads, and the solder balls 20 in the first area 101 realize signal transmission through through holes, thereby reducing the number of wiring layers of the circuit board and achieving the purpose of cost saving.
  • each through hole 201 in the first region 101 is arranged in the first pitch L1, and the leads of each solder ball 20 are connected to other circuit layers of the circuit board through the corresponding through hole 201, thereby realizing the first Signals in a region 101 are transmitted between other circuit layers, thereby reducing the number of wiring layers of the circuit board and reducing the design cost of the circuit board.
  • the four solder balls in the first region 101 can share one through hole 201, so that the leads of the four solder balls can be connected to other layers through the same through hole 201.
  • two solder balls in the first region 101 can share a through hole 201, so that the leads of the two solder balls can be connected to the circuit through the same through hole 201 other layers of the board, thereby avoiding contact between leads.
  • a through hole 201 may be provided for each solder ball 20 , so that the leads of each solder ball 20 are connected to other layers of the circuit board through the corresponding through hole 201 .
  • the solder balls 20 in the first region 101 and the solder balls 20 in the second region 102 present a symmetrical arrangement, and the symmetrical arrangement is the first region
  • the arrangement structure of the solder balls in 101 and the solder balls 20 in the second area 102 is symmetrical left and right, up and down; as a possible implementation mode, the solder balls 20 in the first area 101 can be arranged in a matrix as shown in FIG. 1 cloth.
  • the solder balls arranged in the first region 101 may not be arranged in a complete matrix in addition to the matrix symmetric arrangement mentioned above, and the solder balls may be removed as required ;
  • this program can also set a plurality of passive elements 1011 in the first area 101, the passive elements 1011 and solder balls 20 are arranged at intervals, the passive elements 1011 can be capacitance or components such as resistors.
  • the gain function required by the PCB board can be realized through the passive element 1011 of the substrate, for example, the passive element 1011 provides the PCB board with power gain, etc., thereby making the designed substrate cost low and simultaneously function stronger.
  • FIG. 10 Another substrate 10, which is also used for chip packaging. As shown in FIG. The second area 102 is arranged around the first area 101 , and the third area 103 is arranged around the second area 102 .
  • first distance L1 between the solder balls 20 in the first region 101
  • second distance L2 between the solder balls 20 in the second region 102
  • third distance L3 between the solder balls 20 in the third region 103.
  • the first distance L1 between the solder balls 20 in the first region 101 is 0.65mm
  • the second distance L2 between the solder balls 20 in the second region 102 can be 0.4mm
  • the distance L2 between the solder balls 20 in the third region 103 The third distance L3 between the solder balls may be equal to the second distance L2, that is, 0.4 mm, or greater than the second distance L2, such as 0.8 mm;
  • the third distance L3 is equal to the second distance L2 ie 0.4 mm; the third distance L3 between another part of the solder balls 20 is greater than the second distance L2 , for example 0.8 mm.
  • the third region 103 also includes a plurality of lead gaps 1031, the plurality of lead gaps 1031 are formed by the distance between the solder balls in the third region greater than the second distance L2, for example, the aforementioned third distance L3 is 0.8mm
  • the spacing between the lead wires 1031 is formed; the first lead wires 202 of the solder balls 20 in the second region 102 are led out through the lead wire gaps 1031 to realize signal transmission in the second region 102 .
  • solder balls in the third area 103 are directly drawn out through the second lead 1032, thereby realizing the signal transmission in the third area 103; the solder balls 20 in the first area 101 are connected to other layers of the circuit board through the through holes 201, thereby realizing the second Signal transmission in a region 101 , wherein the layout of the through holes 201 may be consistent with the layouts in FIG. 2 and FIG. 3 in the first embodiment, and will not be repeated here.
  • the substrate designed above by designing the first region 101, the second region 102 and the third region 103, and designing the second distance L2 between the solder balls 20 in the second region 102 to be smaller than the solder balls 20 in the first region 101
  • the first pitch L1 between them, the third pitch L3 of some of the solder balls in the third area is greater than the second pitch L2, and the pitch of the other part of the solder balls is equal to the second pitch L2, so that the designed substrates are relatively equal to the first pitch
  • More solder balls can be arranged in an equidistant arrangement; in addition, the leads of the solder balls 20 in the second region 102 are drawn out through the lead gaps formed in the third region 103, and the solder balls 20 in the third region 103 are drawn out through the lead gaps formed in the third region 103.
  • the solder balls 20 in the first region 101 realize signal transmission through through holes, thereby achieving the purpose of reducing the number of wiring layers of the circuit board and reducing the cost of the circuit board; Lead wires are led out through the lead wire gap formed in the third region 103 , so that the lead wires in the second region 102 have enough lead-out space to avoid installation problems caused by lead wire volume.
  • solder balls 20 in the third region 103 with similar distances form solder ball pairs 203
  • the solder balls 20 in the solder ball pairs 203 pass through the second lead 1032 lead out to implement signal transmission in the third area 103 through the second wire 1032 .
  • the number of solder balls in the solder ball pair 203 may be other than the 2 shown in FIG. 5 , for example, three solder balls 20 form a solder ball pair 203 .
  • the distance between the solder balls 20 in the solder ball pairs 203 is equal to the second distance, and the distance between every two solder ball pairs 203 is greater than the second distance L2, for example, in the solder ball pairs 203
  • the distance between the solder balls 20 is 0.4 mm, and the distance between every two solder ball pairs 203 is 0.8 mm, so that a lead gap 1031 is formed between every two solder ball pairs 203 .
  • the solder ball pairs 203 in the third region 103 are arranged in the first direction, and the lead gaps 1031 are formed in the second direction on the plurality of solder ball pairs. 203, wherein the first direction is perpendicular to the second direction. It can be seen from the example in FIG. 5 that the solder ball pairs 203 are arranged in the horizontal direction, and the lead gap 1031 is formed between the two solder ball pairs 203 in the vertical direction.
  • the leads of the second region 102 and the third region 103 extend away from the first region 101 along the second direction, that is, the second region 102 and the third region
  • the lead wires of 103 are all directly led to the outside of the substrate 10 .
  • the solder balls 20 in the first region 101, the solder balls 20 in the second region 102 and the third region 103 present a symmetrical arrangement, and the symmetrical arrangement
  • the arrangement structure of the solder balls in the first area 101, the solder balls 20 in the second area 102 and the third area 103 is symmetrical left and right, up and down; as a possible implementation mode, the solder balls 20 in the first area 101 Arranged in a matrix as shown in Figure 5.
  • Some other embodiments of the present application provide a packaging structure 1, as shown in FIG.
  • the circuit element 60 on the substrate 10 is disposed in the package body 50 .
  • the packaging structure designed above because it includes the substrate 10 designed in the first embodiment or the second embodiment, therefore, the designed packaging structure 1 can arrange more solder joints compared to the arrangement of the first pitch. Balls 20; In addition, the solder balls 20 in the second area 102 are drawn out through leads, and the solder balls 20 in the first area 101 realize signal transmission through the through holes 201, thereby reducing the number of wiring layers of the circuit board and achieving the purpose of saving costs.
  • the disclosed devices and methods may be implemented in other ways.
  • the device embodiments described above are only illustrative.
  • the division of the units is only a logical function division.
  • multiple units or components can be combined or May be integrated into another system, or some features may be ignored, or not implemented.
  • the mutual coupling or direct coupling or communication connection shown or discussed may be through some communication interfaces, and the indirect coupling or communication connection of devices or units may be in electrical, mechanical or other forms.
  • a unit described as a separate component may or may not be physically separated, and a component displayed as a unit may or may not be a physical unit, that is, it may be located in one place, or may be distributed to multiple network units. Part or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.
  • each functional module in each embodiment of the present application may be integrated to form an independent part, each module may exist independently, or two or more modules may be integrated to form an independent part.
  • the present application provides a substrate and its packaging structure, the substrate includes a first region and a second region, the second region is arranged around the first region, and a plurality of solder balls are arranged in the first region and the second region, wherein, There is a first pitch between the solder balls in the first area, and a second pitch smaller than the first pitch between the solder balls in the second area; the solder balls in the first area are provided with through holes to pass through The holes implement signal transmission; the solder balls in the second area are led out through the wires, so as to realize signal transmission through the wires.
  • the substrate provided by the present application, more solder balls can be arranged relative to a substrate with a unique pitch of solder balls, so as to realize the miniaturization of the substrate.
  • the substrate and its packaging structure of the present application are reproducible and can be used in various industrial applications.
  • the substrate and its packaging structure of the present application can be used in the field of chip packaging technology.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Abstract

La présente invention concerne un substrat et une structure d'emballage associée. Le substrat comprend une première zone et une seconde zone, la seconde zone étant disposée autour de la première zone, et une pluralité de billes de soudure étant disposées dans chacune de la première zone et de la seconde zone, un premier espacement entre les billes de soudure dans la première zone, et un espacement entre les billes de soudure dans la seconde zone étant un second espacement, qui est plus petit que le premier espacement ; les billes de soudure dans la première zone comprennent un trou traversant, de façon à réaliser une transmission de signal au moyen du trou traversant ; et les billes de soudure dans la seconde zone sont sorties au moyen d'un conducteur, de manière à réaliser une transmission de signal au moyen du conducteur. Le substrat selon la présente invention peut avoir plus de billes de soudure disposées sur celui-ci par rapport à un substrat sur lequel des billes de soudure sont agencées à un espacement unique, ce qui permet de réaliser une miniaturisation du substrat.
PCT/CN2021/137816 2021-08-19 2021-12-14 Substrat et sa structure d'emballage Ceased WO2023019824A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202110956893.7A CN113571480B (zh) 2021-08-19 2021-08-19 一种基板及其封装结构
CN202110956893.7 2021-08-19

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Publication Number Publication Date
WO2023019824A1 true WO2023019824A1 (fr) 2023-02-23

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WO (1) WO2023019824A1 (fr)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113571480B (zh) * 2021-08-19 2024-05-31 北京爱芯科技有限公司 一种基板及其封装结构

Citations (5)

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US6373139B1 (en) * 1999-10-06 2002-04-16 Motorola, Inc. Layout for a ball grid array
US6689634B1 (en) * 1999-09-22 2004-02-10 Texas Instruments Incorporated Modeling technique for selectively depopulating electrical contacts from a foot print of a grid array (BGA or LGA) package to increase device reliability
CN107318216A (zh) * 2017-06-22 2017-11-03 上海兆芯集成电路有限公司 印刷电路板和半导体封装结构
CN109801895A (zh) * 2018-12-29 2019-05-24 晶晨半导体（深圳）有限公司 焊球阵列封装芯片及印制电路板
CN113571480A (zh) * 2021-08-19 2021-10-29 北京爱芯科技有限公司 一种基板及其封装结构

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TWI686112B (zh) * 2017-06-22 2020-02-21 上海兆芯集成電路有限公司 印刷電路板和半導體封裝結構
CN215988713U (zh) * 2021-08-19 2022-03-08 北京爱芯科技有限公司 一种基板及其封装结构

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6689634B1 (en) * 1999-09-22 2004-02-10 Texas Instruments Incorporated Modeling technique for selectively depopulating electrical contacts from a foot print of a grid array (BGA or LGA) package to increase device reliability
US6373139B1 (en) * 1999-10-06 2002-04-16 Motorola, Inc. Layout for a ball grid array
CN107318216A (zh) * 2017-06-22 2017-11-03 上海兆芯集成电路有限公司 印刷电路板和半导体封装结构
CN109801895A (zh) * 2018-12-29 2019-05-24 晶晨半导体（深圳）有限公司 焊球阵列封装芯片及印制电路板
CN113571480A (zh) * 2021-08-19 2021-10-29 北京爱芯科技有限公司 一种基板及其封装结构

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