WO2023018177A1 - Tri-electrode diagonal memtransistor system, and convolution network operation device and operation method which use same - Google Patents

Abstract

A diagonal memtransistor system of the present invention comprises: a plurality of source electrode lines formed in a first direction and arranged in a second direction, which differs from the first direction; a plurality of drain electrode lines, which are formed in the second direction, intersect the source electrode lines, have intersecting regions intersecting the source electrode lines and stacked on the source electrode lines, and are arranged in the first direction; a plurality of synapse elements including a semiconductor layer provided in the intersecting regions between the plurality of source electrode lines and the plurality of drain electrode lines, and an adjustment layer for adjusting the Fermi level and conductance of the source electrode lines and the drain electrode lines in the intersecting regions; and at least one gate electrode line, which is formed in the direction between the first direction and the second direction, intersects the source electrode lines and the drain electrode lines in the intersecting regions, and is stacked on the adjustment layer.

Description

3-electrode diagonal memtransistor system and convolutional network arithmetic device and arithmetic method using the same

The present invention relates to a three-electrode diagonal memtransistor system, and a convolutional network calculation device and method using the same.

The present invention is a conductive type of the Ministry of Science and ICT (Task number: 2022M3H4A1A01009656, title of the research project: Implementation of one-step convolution operation through the development of a novel diagonal-gate memtransistor array element, project management agency: National Research Foundation of Korea, research period: 2022.01.01 ~ 2025.12.31) was derived from a study conducted as part of the study.

The present invention is a mid-career follow-up study of the Ministry of Science and ICT (Task number: 2022R1A2B5B02001455, title of the research project: Development of probabilistically controlled synapse and neuron material/device array capable of ultra-low power learning and 3D integration, project management institution: National Research Foundation, research period : 2022.03.01 ~ 2025.02.28) from a study conducted as part of

The present invention is a new concept device basic technology development of the Ministry of Science and ICT (Task number: 2020M3F3A2A03082825, research task title: Development of an artificial synapse device based on single-molecule-2D heterojunction capable of ultra-low power and high-efficiency learning, project management institution: National Research Foundation , Study period: 2020.07.01 ~ 2023.02.28) It was derived from a study conducted as part of the study.

On the other hand, in all aspects of the present invention, there is no property interest of the Korean government, which is the subject of the project.

Image/video recognition technology occupies a large part of big data application fields such as face recognition, autonomous driving, and waveform analysis. Currently, the most advanced recognition system is highly reliable input data processing technology regardless of location through convolutional neural networks. It is being used.

The convolutional network system creates a new convolutional feature map by converting an input signal through several filter networks, and shows accurate and high learning performance through an operation process based on its average.

Memristors and memtransistors capable of analog switching are in the spotlight as base elements of such a convolutional network, and have high energy efficiency due to the advantage of being able to operate and store data without a signal transmission medium.

However, the current convolution technology requires extreme energy consumption as the range to be calculated increases as the size of the image or filter increases or the number of layers increases, and the information storage and re-computation process in the pooling process to extract the average value of each This entails difficulties in an efficient recognition process.

The present invention provides a diagonal memtransistor system and method of manufacturing the same, which can increase the efficiency of the entire system by reducing the time and energy consumed in the convolution operation and pooling process, and a convolution network operation device and operation method using the diagonal memtransistor system. intended to provide

A diagonal memtransistor system according to an embodiment of the present invention includes a plurality of source electrode lines formed in a first direction and arranged along a second direction different from the first direction; a plurality of drain electrode lines formed in the second direction, intersecting the source electrode line, and having an intersection area intersecting the source electrode line stacked on the source electrode line, and arranged along the first direction; A semiconductor layer provided at intersections between the plurality of source electrode lines and the plurality of drain electrode lines, and a control layer for adjusting the Fermi level and conductance of the source electrode line and the drain electrode line in the intersection area A plurality of synaptic elements including; and at least one gate electrode line formed in a direction between the first direction and the second direction, crossing the source electrode line and the drain electrode line in the crossing area, and stacked on the control layer. .

The gate electrode line may be configured to cross synaptic elements to be simultaneously trained with the same weight among the plurality of synaptic elements.

The gate electrode line may be formed in a diagonal direction between the first direction and the second direction.

It may be configured to apply a weight control signal to the gate electrode line in order to simultaneously learn the same weight to a plurality of synaptic elements arranged along the gate electrode line.

A control unit configured to determine an input signal to be applied to each drain electrode line or each source electrode line and the weight control signal to be applied to each gate electrode line, wherein the control unit: determining the weight control signal based on filter values of a convolution filter; It may be configured to generate the input signal based on input values of the input data.

The drain electrode line may include a graphene layer formed on the semiconductor layer in the crossing area.

The adjustment layer may be configured to adjust the Fermi level of the graphene layer according to the voltage applied through the gate electrode line and to adjust the conductance of the source electrode line and the drain electrode line in the crossing region.

The control layer is: configured to be stacked on the drain electrode line intersecting the semiconductor layer; A top surface of the drain electrode intersecting the semiconductor layer and a side surface of the semiconductor layer may be covered.

The semiconductor layer may be configured to include at least one of ZnO, NiO, SnO, IGZO, SiOx, TiOx, and WOx.

The control layer may include: an organic ferroelectric including at least one of PVDF-TrFE and PVDF; or an inorganic ferroelectric including at least one of HZO and PZT.

A convolution network operating device for convolution processing input data using a convolution filter according to an embodiment of the present invention, comprising the diagonal memtransistor system, wherein the diagonal memtransistor system: of the input data generate input signals based on the input values; determining weight control signals based on filter values of the convolution filter; applying the input signals to the plurality of drain electrode lines or the plurality of source electrode lines; applying the weight control signals to the plurality of gate electrode lines; A convolution operation result is calculated based on output signals output to the plurality of source electrode lines or the plurality of drain electrode lines.

The diagonal memtransistor system: Extracts feature signals related to convolution operation values according to the sliding of the convolution filter among the output signals based on the size of the input data and the size of the convolution filter, and the feature It may be configured to pool the signals to generate a convolutional feature map.

A convolution network operation method for performing convolution processing on input data using a convolution filter according to an embodiment of the present invention, comprising the step of performing the convolution processing by the diagonal memtransistor system, wherein the convolution The performing of the solution process may include: generating input signals based on input values of the input data; determining weight control signals based on filter values of the convolution filter; applying the input signals to the plurality of drain electrode lines or the plurality of source electrode lines; applying the weight control signals to the plurality of gate electrode lines; and calculating a convolution operation result based on output signals output to the plurality of source electrode lines or the plurality of drain electrode lines.

extracting, by the diagonal memtransistor system, feature signals related to convolution operation values according to the sliding of the convolution filter among the output signals based on the size of the input data and the size of the convolution filter; and generating, by the diagonal memtransistor system, a convolution feature map by pooling the feature signals extracted based on the size of the input data and the size of the convolution filter. .

According to an embodiment of the present invention, a diagonal memtransistor system and its A manufacturing method and a convolutional network calculation device and method using a diagonal memtransistor system are provided.

In addition, according to an embodiment of the present invention, by calculating n×n pooling at one time, the pooling operation process and energy consumption can be reduced to 1/(n×n) compared to conventional methods.

1 is a diagram showing a diagonal memtransistor system 10 according to an embodiment of the present invention.

FIG. 2 is an enlarged view of one diagonal memtransistor element 11 included in the diagonal memtransistor system 10 .

3 is a diagram sequentially illustrating a process of manufacturing a diagonal memtransistor system 10 by a method of manufacturing a diagonal memtransistor element system according to an embodiment of the present invention.

4 is a diagram schematically illustrating a driving method of an existing CNN array under the condition of 4x4 input data and a 3x3 kernel (convolution filter).

FIG. 5 is a diagram showing the process of FIG. 4 in more detail, sequentially showing a process in which a convolution operation is performed on input data according to the sliding of the convolution filter.

FIG. 6 is a diagram schematically illustrating an operation method of the diagonal memtransistor system 10 under the same condition as in FIG. 4 .

FIG. 7 is a diagram showing the process of FIG. 6 in more detail, wherein the diagonal memtransistor system 10 having a diagonal array (when the gate electrode line is formed in a diagonal direction) stores separate information using feature map data. It is a diagram showing how the convolution operation result is output at once through the pooling process without any process.

FIG. 8 is an exemplary diagram illustrating how input data is received through the source electrode 120 and output through the drain electrode 220 in the manner shown in FIGS. 6 and 7 .

9 is a view showing how two pulse sequences are input in order to learn a weight in any one of the memtransistor elements of the existing synapse array.

FIG. 10 is a diagram showing how weights are learned for a plurality of diagonal memtransistor elements 11 with one pulse sequence input in the diagonal memtransistor system 10 according to an embodiment of the present invention.

11 is a diagram showing a state in which polarization occurs in a ferroelectric layer.

12 is a diagram showing drain-source current change characteristics according to gate voltage of the diagonal memtransistor device 11 .

FIG. 13 is a diagram showing a change characteristic of postsynaptic currents (PSC) according to application of a pulse gate voltage to the diagonal memtransistor device 11 .

Hereinafter, specific embodiments of the present invention will be described in detail with reference to the drawings.

In addition, in describing the present invention, if it is determined that a detailed description of a related known configuration or function may obscure the gist of the present invention, the detailed description will be omitted.

The embodiments of the present invention are provided to more completely explain the present invention to those skilled in the art, and the following examples may be modified in many different forms, and the scope of the present invention is as follows It is not limited to the examples.

Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the spirit of the invention to those skilled in the art.

In addition, each component in the following drawings is exaggerated for convenience and clarity of explanation, and the same reference numerals refer to the same elements in the drawings. As used herein, the term “and/or” includes any one and all combinations of one or more of the listed items.

Terms used in this specification are used to describe specific embodiments and are not intended to limit the present invention.

As used herein, the singular form may include the plural form unless the context clearly indicates otherwise. Also, when used herein, "comprise" and/or "comprising" specifies the presence of the recited shapes, numbers, steps, operations, elements, elements, and/or groups thereof. will,

It does not exclude the presence or addition of one or more other shapes, numbers, operations, elements, elements and/or groups.

FIG. 1 is a diagram showing a diagonal memtransistor system 10 according to an embodiment of the present invention, and FIG. 2 is an enlarged view of one diagonal memtransistor element 11 included in the diagonal memtransistor system 10. .

1 and 2, the diagonal memtransistor system 10 includes a plurality of source electrode lines 110, a plurality of drain electrode lines 210, a plurality of synaptic elements 600, and a gate electrode line 510. can include A plurality of source electrode lines 110 , a plurality of drain electrode lines 210 , a plurality of synaptic elements 600 , and a gate electrode line 510 may be formed on the substrate 20 .

Each source electrode line 110 may be formed in a predetermined first direction. The plurality of source electrode lines 110 may be arranged parallel to each other along a second direction different from the first direction.

The source electrode line 110 may be configured to extend from one side of the source electrode 120 in the first direction. A preset voltage may be applied to the source electrode line 110 and the source electrode 120 . For example, a reference voltage (eg, ground voltage) or an input value corresponding to input data may be applied to the source electrode 120 and the source electrode line 110 . Each drain electrode line 210 may be formed to extend from the drain electrode 220 in the second direction. The plurality of drain electrode lines 210 may be formed to cross the plurality of source electrode lines 110 . The plurality of drain electrode lines 210 may be arranged parallel to each other along the first direction.

The drain electrode line 210 may be formed on the semiconductor layer 300 of the synaptic device 600 . A portion of the drain electrode line 210 crossing the source electrode line 110 (intersection area) may be stacked on a portion of the source electrode line 110 .

For example, when the second direction is perpendicular to the first direction, a portion of the drain electrode line 210 is perpendicular to a portion of the source electrode line 110 and is stacked on the source electrode line 110. It can be. Therefore, as shown in FIG. 1, a lattice shape (crossbar array structure) can be achieved.

A preset voltage may be applied to the drain electrode line 210 and the drain electrode 220 . For example, a reference voltage (eg, ground voltage) or an input value corresponding to input data may be applied to the drain electrode 220 and the drain electrode line 210 .

The source electrode line 110 and the drain electrode line 210 may be formed of a conductive material such as metal. In an embodiment, the drain electrode line 210 may include a graphene layer.

The synaptic device 600 may be provided at intersections between the plurality of source electrode lines 110 and the plurality of drain electrode lines 210, respectively. The synaptic device 600 includes a semiconductor layer 300 provided in the intersection area between the source electrode line 110 and the drain electrode line 210, and the source electrode line 110 and the drain electrode line 210 in the intersection area. It may include a control layer 400 for adjusting the Fermi level and conductance of .

The semiconductor layer 300 may be provided between the source electrode line 110 and the drain electrode line 210 . More specifically, the semiconductor layer 300 is stacked on the source electrode line 110 and the source electrode line 110 in the intersection area where the source electrode line 110 and the drain electrode line 210 overlap each other. It may be provided between the drain electrode lines 210 .

In an embodiment, the semiconductor layer is ZnO (zinc oxide), NiO (nickel oxide), SnO (tin oxide), IGZO (indium gallium zinc oxide), SiOx (silicon oxide), TiOx (titanium oxide), and WOx (tungsten oxide) However, the material constituting the semiconductor layer 300 is not limited thereto.

The control layer 400 may be configured to cover the upper surface of the semiconductor layer 300 .

More specifically, the control layer 400 may cover the semiconductor layer 300 and the drain electrode line 210 provided on the semiconductor layer 300 together.

In addition, the adjustment layer 400 is configured to be stacked on the drain electrode line 210 crossing the semiconductor layer 300, or the upper surface of the drain electrode 210 crossing the semiconductor layer 300 and the semiconductor layer 300 It may be configured to cover the side of the.

The control layer 400 adjusts the Fermi level of the graphene layer of the drain electrode line 210 by the gate voltage applied through the gate electrode line 510 to form a Schottky barrier between the semiconductor layer 300 and the graphene layer. ) can be formed of a material that can control.

In an embodiment, the control layer 400 may be composed of an organic ferroelectric or an inorganic ferroelectric. The organic ferroelectric may include at least one of polyvinylidene fluoride trifluoro ethylene (PVDF-TrFE) and polyvinylidene fluoride (PVDF). The ferroelectric may include at least one of HZO (Hf0.5Zr0.5O2) and PZT (lead zirconate titanate). However, materials constituting the control layer 400 are not limited thereto. Here, PVDF may be polyvinylidene fluoride, and PZT may be lead zirconate titanate.

The gate electrode line 510 may be formed to cross the source electrode line 110 and the drain electrode line 210 at an intersection area between the source electrode line 110 and the drain electrode line 210 . The gate electrode line 510 may be stacked on the control layer 400 at an intersection area between the source electrode line 110 and the drain electrode line 210 . The gate electrode line 510 may contact the upper surface of the control layer 400 and be formed in a third direction.

The third direction may be a direction between the first direction and the second direction. The length direction of the gate electrode line 510 may be formed in a direction between the length direction of the source electrode line 110 and the length direction of the drain electrode line 210 . Accordingly, as shown in FIG. 1 , looking at the shape of the diagonal memtransistor system 10 as a whole, the gate electrode line 510 may be formed in a diagonal direction.

According to another example, the gate electrode line 510 may be formed in a non-diagonal direction so as to intersect with synaptic elements to be simultaneously trained with the same weight among a plurality of synaptic elements. That is, the gate electrode line 510 may be formed in a direction between the first direction and the second direction while being bent or bent so that it can be stacked on synaptic elements to be simultaneously trained with the same weight rather than in a diagonal straight direction. there is.

The diagonal memtransistor system 10 may further include a source electrode 120 , a drain electrode 220 and a gate electrode 520 .

The gate electrode 520 may be configured to apply a weight control signal to the gate electrode line 510 in order to simultaneously learn the same weight for a plurality of synaptic devices 600 arranged along the specific gate electrode line 510. can

The source electrode 120 may be provided at an end of the source electrode line 110 . The drain electrode 220 may be provided at an end of the drain electrode line 210 . The gate electrode 520 may be provided at an end of the gate electrode line 510 .

The diagonal memtransistor system 10 according to an embodiment of the present invention may further include a controller (not shown). The controller may be configured to determine an input signal to be applied to each drain electrode line 210 or each source electrode line 110 and a weight control signal to be applied to each gate electrode line 510 . One of the drain electrode line 210 and the source electrode line 110 may be used as an input and the other as an output.

In an embodiment, the control unit determines a weight control signal based on filter values of a convolution filter for convolving input data, applies it to the gate electrode 520 and the gate electrode line 510, and applies the input value of the input data. An input signal may be generated based on and applied to the drain electrode 220 or the source electrode 120 .

The diagonal memtransistor system 10 may calculate a convolution operation result based on output signals output to the plurality of source electrode lines 110 or the plurality of drain electrode lines 210 . The diagonal memtransistor system 10 is based on the size of the input data and the size of the convolution filter, among the output signals of the plurality of source electrode lines 120, related to the convolution operation values according to the sliding of the convolution filter. A convolutional feature map may be generated by extracting feature signals and pooling the extracted feature signals.

FIG. 3 is a diagram sequentially illustrating a process of manufacturing the diagonal memtransistor system 10 by the manufacturing method S10 of the diagonal memtransistor element system according to an embodiment of the present invention.

Referring to FIG. 3 , the diagonal memtransistor device system manufacturing method ( S10 ) includes steps S100 to S500 .

In step S100 , a plurality of source electrodes 120 , a plurality of source electrode lines 110 having a first direction as a longitudinal direction, and a plurality of drain electrodes 220 may be formed on the substrate.

For example, in step S100, the SiO2 / Si substrate is ultrasonically cleaned in ethanol for 15 minutes and acetone for 15 minutes, followed by washing with flowing pure water (DI water), followed by nitrogen air blowing (S110), AZ5214 Photoresist After spin-coating, baking at 120 ° C for 1 minute (S120), corresponding to the source electrode 120, the source electrode line 110 and the drain electrode 220 using a photo mask After exposing the pattern part to be exposed, developing for 15 seconds in MIF300 developer (S130) and depositing aluminum (Al) to a thickness of 3 nm using a thermally evaporator, and then gold (Au) to a thickness of 22 nm After the deposition, a lift-off process using acetone is performed to remove photoresist (PR) (S140).

In step S200 , the semiconductor layer 300 may be formed in a partial area (an area where the drain electrode line and the gate electrode line intersect) on the source electrode line 110 .

For example, step S200 is a step of performing photolithography for the semiconductor layer 300 (S210) and IGZO using an RF-sputtering system to form the semiconductor layer 300 having a size of 80 um2. may include depositing to a thickness of 15 nm under deposition conditions of 50 W, 19 sccm of Ar, 2 sccm of O2, and 20 mTorr, and then performing lift-off with acetone (S220).

In step S300 , a plurality of drain electrode lines 210 connecting a partial region on the semiconductor layer 300 and a partial region on the drain electrode 220 may be formed in a second direction.

For example, in step S300, a large-area graphene layer is transferred on the semiconductor layer 300 corresponding to the intersection area between the source electrode line 110 and the drain electrode line 210, and immersed in acetone for 20 minutes. Removing the graphene protective layer PMMA by washing with DI water (S310), removing the photoresist except for the portion of the drain electrode line 210 having an area of 40 um2 on the graphene layer through photolithography and developing (S320) and etching the graphene layer except for the drain electrode line 210 through a reactive-ion etching (RIE) process under RIE conditions of 40 W, 10 sccm for Ar, 10 sccm for O2, and 0.2 Torr, and then lift-off the photoresist using acetone. Step S330 may be included.

In step S400 , an adjustment layer 400 configured to cover both the semiconductor layer 300 and the graphene layer of the drain electrode line 210 provided on the semiconductor layer 300 may be formed.

For example, in step S400, a solution in which polyvinylidene-trifluoroethylene (PVDF-TrFE) (70:30), an organic ferroelectric polymer, is dissolved in a DMF solvent at 8 wt% is spin-coated, and then , crystallization by annealing at 135 °C for 2 hours.

In step S500 , the gate electrode line 510 may be formed in a third direction (diagonal direction) between the first and second directions so as to contact a partial region of the upper surface of the control layer 400 .

For example, in step S500, after developing the gate electrode line 510 through photolithography to cover the channel area of each synaptic element including the semiconductor layer 300, depositing Al to a thickness of 25 nm by thermal evaporation. (S510) and lift-off of the gate pattern on PVDF-TrFE, an organic material, by exposing to PGMEA (Propylene glycol monomethyl ether acetate) solvent that can selectively remove only the photoresist for 10 minutes to perform lift-off (S520) can include

4 is a diagram schematically illustrating a driving method of an existing CNN array under the condition of 4x4 input data and a 3x3 kernel (convolution filter), and FIG. 5 is a diagram showing the process of FIG. 4 in more detail, showing the convolution filter It is a diagram sequentially showing the convolution operation process for input data according to sliding.

Referring to FIGS. 4 and 5, in the case of the conventional CNN array driving method, sliding using a kernel is performed 4 times, a feature map is extracted through this, and then max pooling is performed on the feature map. Apply and output.

FIG. 6 is a diagram schematically illustrating a convolution operation process by the diagonal memtransistor system 10 according to an embodiment of the present invention under the same conditions as in FIG. 4, and FIG. 7 is a diagram showing the process of FIG. 6 in more detail. , A pooling process is performed without a process of storing separate information using feature map data by the diagonal memtransistor system 10 having a diagonal array (when the gate electrode line is formed in a diagonal direction) 8 is a diagram showing how the convolution operation result is output at once through the method shown in FIGS. 6 and 7, input data is received through the source electrode 120, and data is received through the drain electrode 220 This is an example of the output.

Referring to FIGS. 6 and 7 , the diagonal memtransistor system 10 according to an embodiment of the present invention may derive a feature map through one input of input data, and the process of separately storing the derived feature map Without, the convolution operation result data can be directly output through a pooling process.

For example, as shown in FIGS. 6 and 7 , when input data includes input values corresponding to a total of 16 pixel values from 1 to 16, each input value corresponds to each source electrode 120 ) can be entered in column form at once. To this end, the number of source electrodes must be 16 equal to the number of input values constituting the input data (eg, the number of pixels in an image that is a unit of convolution processing) or more. For example, when input data has a size of NXN, the number of source electrode lines 110 and drain electrode lines 120 may be implemented as N2, respectively. Output data generated through the feature map derivation and pooling process is output through the drain electrode 220. In the case of the illustrated example, the A output is output through the first drain electrode 220, and the output data is output through the second drain electrode 220. A B output may be output, a C output may be output through the fifth drain electrode 220 , and a D output may be output through the sixth drain electrode 220 .

At this time, the outputs A to D may be simultaneously output through the plurality of drain electrodes 220 by the diagonal memtransistor system 10 . That is, in a 16x4 array element structure sharing a gate line, A, B, C, and D operation values are extracted at once through vector operation through Ohm's law and Kirchhoff's law. Accordingly, according to an embodiment of the present invention, a fast and efficient convolution operation is possible.

9 is a view showing inputting two pulse sequences in order to learn a weight in any one memtransistor element of an existing synaptic array, and FIG. 10 is a diagonal memtransistor system (10) according to an embodiment of the present invention. ), it is a diagram showing how weights are learned to a plurality of diagonal memtransistor elements 11 with one pulse sequence input.

Referring to FIG. 9 , in order to learn a weight for one memtransistor element corresponding to (a), a pulse sequence must be input to each of the source electrode line and the drain electrode line.

In contrast, referring to FIG. 10 , the diagonal memtransistor system 10 according to an embodiment of the present invention generates a plurality of memtransistor elements (a specific gate electrode line) by applying a pulse sequence once through a specific gate electrode line. A weight control signal used for learning may be simultaneously transmitted to a plurality of synaptic elements arranged according to the synaptic element).

Referring back to FIG. 2 , the diagonal memtransistor element 11 has a three-terminal structure, and the source electrode line 110 and the drain electrode line 210 are a semiconductor layer 300 (eg, an IGZO layer) as a channel layer. ) can intersect vertically. At this time, the control layer 400 may be provided to cover the upper surface of the drain electrode line 210 provided on the semiconductor layer 300, and in other cases, the drain electrode line 210 provided on the semiconductor layer 300. It may be provided to cover both the upper surface and the side surface of the semiconductor layer 300 . Also, the gate electrode line 510 may be provided in a direction between a direction in which the source electrode line 110 is provided and a direction in which the drain electrode line 210 is provided.

As described above, the diagonal memtransistor system 10 according to an embodiment of the present invention can be applied as a convolutional network calculation apparatus and method for performing convolutional network calculation. The convolution network operation device generates input signals based on input values of input data, applies them to a plurality of drain electrode lines (or a plurality of source electrode lines), and determines weight control signals based on filter values of a convolution filter. and applied to a plurality of gate electrode lines.

The convolution network calculator may calculate a convolution operation result based on output signals output to a plurality of source electrode lines (or a plurality of drain electrode lines). At this time, the convolution network calculation device extracts feature signals related to convolution calculation values according to the sliding of the convolution filter among the output signals based on the size of the input data and the size of the convolution filter, pools the feature signals, and Convolutional feature maps can be created.

In the case of the embodiment shown in FIG. 7 , output signals of the first, second, fifth, and sixth source electrode lines among the first to sixth source electrode lines are extracted as feature signals, and the feature signals are pooled to obtain convolutional features. will create a map. When sequential numbers are given in the order of rows and columns of the input data, the order of the feature signals extracted from the output signals is, for example, Nk+1, Nk+2, . . . , Nk+N-M+1 (k is 0, 1, ..., N-M) (N: size of input data, M: size of convolution filter). In this case, among the N2 output signals, (N-M+1) 2 feature signals may be extracted. In the case of FIG. 7, since N = 4 and M = 3, 4 (22) corresponding to the 1st and 2nd sequential numbers (in the case of k = 0) and the 5th and 6th sequential numbers (in the case of k = 1) Characteristic signals A, B, C, and D are output through source electrodes.

11 is a diagram showing polarization in a ferroelectric layer, FIG. 12 is a diagram showing drain-source current change characteristics according to gate voltage of the diagonal memtransistor device 11, and FIG. 13 is a diagram showing the diagonal memtransistor device 11 ) is a diagram showing the characteristics of PSC (postsynaptic currents) change according to the application of a pulse gate voltage. 12, the horizontal axis represents the gate voltage applied to the gate electrode of the diagonal memtransistor element 11, and the vertical axis represents the current flowing between drain and source. In the experiment of FIG. 12, the drain-source voltage was kept constant at 1V.

13 , the horizontal axis represents the pulse voltage applied to the gate electrode of the diagonal memtransistor device 11, and the vertical axis represents postsynaptic currents according to the pulse voltage. In the experiment of FIG. 13, a 30V pulse voltage corresponding to a potentiating pulse for increasing the weight of a synaptic element is repeatedly applied to the gate electrode of the diagonal memtransistor element 11 at a 500 ms cycle for 30 seconds, and then the synapse again. A -30V pulse voltage corresponding to a depressing pulse for reducing the weight of the device was repeatedly applied for 30 seconds at a cycle of 500 ms, and the drain-source voltage was kept constant at 1.5 V.

11 to 13, the electric field applied to the gate electrode 520 and the gate electrode line 510 causes polarization in the ferroelectric layer, and the Fermi level of graphene can be adjusted according to the direction of the polarization. be able to

This is directly connected to the adjustment of the height of the Schottky barrier between the graphene layer and the semiconductor layer, and accordingly, the conductance of the diagonal memtransistor element 11 can be adjusted.

Referring back to FIGS. 2 and 11 to 13 , a diagonal memtransistor element as a varistor structure device that adjusts the Schottky barrier using the graphene layer of the drain electrode line 210 and the ferroelectric of the control layer 400 When (11) is manufactured in a vertical structure, the footprint can be reduced compared to a horizontal artificial synapse device. In particular, according to an embodiment of the present invention, simultaneous learning can be secured by dividing a weight update region and a matrix multiplication operation driving region constituting a diagonal gate array.

As described above, according to the diagonal memtransistor system according to the embodiment of the present invention, the data sliding operation between the input data and the convolution filter is not required, so the circuit can be simplified, and convolution and pooling can be performed simultaneously. Therefore, the amount of calculation can be reduced to less than 1/4 compared to the prior art, and the calculation speed can be dramatically increased. In addition, it is possible to increase the efficiency of simultaneous learning of weights of synaptic elements, and it is not necessary to store feature maps for pooling processing and does not require a separate pooling layer, so data input/output and calculation amount can be further reduced.

Although the present invention has been described through examples above, the above examples are only for explaining the idea of the present invention and are not limited thereto. Those skilled in the art will understand that various modifications can be made to the above-described embodiments. The scope of the present invention is defined only through the interpretation of the appended claims.

Claims (14)

a plurality of source electrode lines formed in a first direction and arranged along a second direction different from the first direction; a plurality of drain electrode lines formed in the second direction, intersecting the source electrode line, and having an intersection area intersecting the source electrode line stacked on the source electrode line, and arranged along the first direction; A semiconductor layer provided at intersections between the plurality of source electrode lines and the plurality of drain electrode lines, and a control layer for adjusting the Fermi level and conductance of the source electrode line and the drain electrode line in the intersection area A plurality of synaptic elements including; and At least one gate electrode line formed in a direction between the first direction and the second direction, crossing the source electrode line and the drain electrode line in the crossing area, and stacked on the control layer, Diagonal memtransistor system. According to claim 1, The gate electrode line is: A diagonal memtransistor system configured to cross synaptic elements to be simultaneously trained with the same weight among the plurality of synaptic elements. According to claim 2, Wherein the gate electrode line is configured to be formed in a diagonal direction between the first direction and the second direction. According to claim 1, The diagonal memtransistor system further comprises a gate electrode configured to apply a weight control signal to the gate electrode line in order to simultaneously learn the same weight to a plurality of synaptic elements arranged along the gate electrode line. According to claim 4, Further comprising a control unit configured to determine an input signal to be applied to each drain electrode line or each source electrode line, and the weight control signal to be applied to each gate electrode line, The control unit: determining the weight control signal based on filter values of a convolution filter for performing convolution on input data; The diagonal memtransistor system configured to generate the input signal based on input values of the input data. According to claim 1, The diagonal memtransistor system of claim 1 , wherein the drain electrode line includes a graphene layer formed on the semiconductor layer in the crossing region. According to claim 6, The adjustment layer is configured to adjust the Fermi level of the graphene layer according to the voltage applied through the gate electrode line, and to adjust the conductance of the source electrode line and the drain electrode line in the crossing region, diagonal memtransistor system. According to claim 7, The control layer is: configured to be stacked on the drain electrode line intersecting the semiconductor layer; A diagonal memtransistor system configured to surround a top surface of the drain electrode crossing the semiconductor layer and a side surface of the semiconductor layer. According to claim 1, Wherein the semiconductor layer is configured to include at least one of ZnO, NiO, SnO, IGZO, SiOx, TiOx, and WOx. According to claim 1, The control layer is: an organic ferroelectric including at least one of PVDF-TrFE and PVDF; or A diagonal memtransistor system configured to include an inorganic ferroelectric including at least one of HZO and PZT. In the convolution network calculation device for convolution processing input data using a convolution filter, Including the diagonal memtransistor system according to claim 1, The diagonal memtransistor system: generating input signals based on input values of the input data; determining weight control signals based on filter values of the convolution filter; applying the input signals to the plurality of drain electrode lines or the plurality of source electrode lines; applying the weight control signals to the plurality of gate electrode lines; Convolution network calculation device configured to calculate a convolution operation result based on output signals output to the plurality of source electrode lines or the plurality of drain electrode lines. According to claim 11, The diagonal memtransistor system: Based on the size of the input data and the size of the convolution filter, feature signals related to convolution operation values according to the sliding of the convolution filter are extracted from among the output signals, and the feature signals are pooled to obtain a convolution feature. A convolutional network computing unit, configured to generate a map. In the convolution network operation method of convolution processing input data using a convolution filter, performing the convolution process by the diagonal memtransistor system according to claim 1; The step of performing the convolution process is: generating input signals based on input values of the input data; determining weight control signals based on filter values of the convolution filter; applying the input signals to the plurality of drain electrode lines or the plurality of source electrode lines; applying the weight control signals to the plurality of gate electrode lines; and And calculating a convolution operation result based on output signals output to the plurality of source electrode lines or the plurality of drain electrode lines. According to claim 13, extracting, by the diagonal memtransistor system, feature signals related to convolution operation values according to the sliding of the convolution filter among the output signals based on the size of the input data and the size of the convolution filter; and Further comprising generating a convolution feature map by pooling the feature signals extracted based on the size of the input data and the size of the convolution filter by the diagonal memtransistor system.

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