CN112836812B - Neural network based on floating gate transistor - Google Patents

Abstract

The invention provides a neural network based on a floating gate transistor, which comprises a multi-node input unit: the multi-node input unit comprises a multi-input floating gate transistor, wherein a plurality of grid input ends of the multi-input floating gate transistor are respectively connected with a plurality of external bionic sensor input signals, a source electrode is grounded, and a drain electrode is used as an output end of the neuron network. The invention provides a brand-new electronic afferent neuron realization architecture. The architecture is applied to a hardware nerve form neural network, realizes the conversion from an analog signal to a neuron signal, has the advantages of simple structure, multiple functions, low power consumption and the like, and is more suitable for the neuron network.

Description

Neural network based on floating-gate transistors

Technical Field

The present invention relates to the field of neural networks, and in particular to a neural network based on floating gate transistors.

Background technique

As the next generation of neuromorphic computing technology, neural networks are an ideal choice for building energy-efficient storage and computing integrated data processing centers. In order to realize a sensing, storage and computing integrated intelligent processing system, it is necessary to build an efficient perception information interface (biologically called afferent nerves) to establish a real-time connection between the data processing center and the sensor. However, the existing technology uses CMOS to build electronic afferent neurons, which have problems such as high power consumption, complex circuit structure and process, and are difficult to apply to new neuromorphic neural networks.

Summary of the invention

The technical problem to be solved by the present invention is to provide a neural network based on floating gate transistors, which solves the problems of high power consumption, complex circuit structure and process, and is suitable for a new type of neuromorphic neural network.

In order to solve the above problems, the present invention provides a neural network based on floating-gate transistors, including a multi-node input unit: the multi-node input unit includes a multi-input floating-gate transistor, and the multiple gate input terminals of the multi-input floating-gate transistor are respectively connected to multiple external bionic sensor input signals, the source is grounded, and the drain serves as the output terminal of the neural network.

The present invention provides a new electronic afferent neuron implementation architecture. This architecture is oriented to the application of hardware neuromorphic neural networks, realizes the conversion of analog signals to neuron signals, has the advantages of simple structure, multiple functions, low power consumption, etc., and is more suitable for neuron networks.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a schematic diagram showing the structure of a floating-gate transistor-based neural network according to a specific embodiment of the present invention.

FIG2 is a diagram showing an implementation architecture of an electronic afferent neuron according to a specific embodiment of the present invention.

3A and 3B are device structure diagrams of a floating gate transistor according to a specific embodiment of the present invention.

Detailed ways

The specific implementation of the floating gate transistor-based neural network provided by the present invention is described in detail below with reference to the accompanying drawings.

FIG1 is a schematic diagram of the structure of a floating-gate transistor-based neural network according to a specific embodiment of the present invention, including a multi-node input unit. The multi-node input unit includes a multi-input floating-gate transistor, wherein the multiple gate input terminals of the multi-input floating-gate transistor are respectively connected to multiple external bionic sensor input signals V ₀₁ , V ₀₂ , ... V _0N , the source is grounded, and the drain serves as the output terminal U _d(t) of the neural network.

The multi-node input unit integrates the external bionic sensor input signals V ₀₁ ~V _0N to obtain the floating gate voltage VF of the multi-input floating gate transistor. Combined with the structure shown in FIG. 1, the voltage is given by the following formula:

Among them, _V0 to _VN are the floating gate voltages of each column of floating gate transistors, which are the weighted average of the input voltages of each gate node, _C01 ~ _C0N are the parasitic capacitances between the floating gate and the gate oxide of the first column of floating gate transistors, and the corresponding _CN1 ~ _CNN are the parasitic capacitances between the floating gate and the gate oxide of the Nth column of floating gate transistors. The weighted average is the floating gate voltage _VF of the multi-input floating gate transistor, and _C1 ~ _CN are the parasitic capacitances between the gate oxide and the top silicon of each column of floating gate transistors.

When the floating gate voltage V _F of the multi-input floating gate transistor is less than the threshold voltage _VT , the multi-input floating gate transistor is not turned on; when the floating gate voltage V _F reaches the threshold voltage _VT of the multi-input floating gate transistor, the multi-input floating gate transistor begins to turn on. After the multi-input floating gate transistor is turned on, the drain voltage increases accordingly, thereby realizing the information integration function of the signal.

Based on the above principles, this specific embodiment provides a new electronic afferent neuron implementation architecture, and its architecture diagram is shown in Figure 2. This architecture is oriented to the application of hardware neuromorphic neural networks, realizes the conversion of analog signals to neuron signals, has the advantages of simple structure, multiple functions, low power consumption, etc., and is more suitable for neural networks.

In a specific embodiment, the multi-input floating gate transistor of the multi-node input unit is a multi-input floating gate transistor with a fully depleted SOI material of a 22nm process node as a substrate, and its device structure is shown in Figures 3A and 3B. The transistor includes a substrate, a buried oxide on the surface of the substrate, and a top layer of silicon on the surface of the buried oxide. The top layer of silicon forms a source, a drain, and a conductive channel formed of a thin film silicon (Thin Si-body) material between the source and the drain through doping. A gate is set on the surface of the conductive channel and a floating gate on the surface of the gate. Its advantage is that it can utilize the characteristics of the fully depleted SOI material, directly form a source, a drain, and a conductive channel on the top layer of silicon through doping, and directly form a series connection between transistors, without the need to make an additional conductive isolation well, so it is a low-cost and efficient selection method.

The above is only a preferred embodiment of the present invention. It should be pointed out that ordinary technicians in this technical field can make several improvements and modifications without departing from the principle of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims (2)

1. A floating gate transistor-based neural network comprising a multi-node input unit: the multi-node input unit comprises a multi-input floating gate transistor, wherein a plurality of grid input ends of the multi-input floating gate transistor are respectively connected with a plurality of external bionic sensor input signals, a source electrode is grounded, and a drain electrode is used as an output end of the neuron network;

The multi-input-end floating gate transistor of the multi-node input unit is a multi-input-end floating gate transistor taking fully-depleted SOI material as a substrate;

the transistor comprises a substrate, a buried oxide layer on the surface of the substrate and top silicon on the oxidized surface of the buried oxide layer, wherein the top silicon is doped to form a source, a drain and a conductive channel between the source and the drain, wherein the conductive channel is formed by adopting a thin film silicon material;

the surface of the conducting channel is provided with a grid electrode and a floating gate on the surface of the grid electrode, a source electrode, a drain electrode and the conducting channel are directly formed on the top silicon through doping, and series connection among transistors is directly formed.

2. The floating gate transistor based pulsed neural network of claim 1, wherein the fully depleted SOI material is employed as a substrate for a multi-input floating gate transistor using a 22nm node process.