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WO2022124404A1 - Dispositif à semi-conducteur - Google Patents

Dispositif à semi-conducteur Download PDF

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Publication number
WO2022124404A1
WO2022124404A1 PCT/JP2021/045616 JP2021045616W WO2022124404A1 WO 2022124404 A1 WO2022124404 A1 WO 2022124404A1 JP 2021045616 W JP2021045616 W JP 2021045616W WO 2022124404 A1 WO2022124404 A1 WO 2022124404A1
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WIPO (PCT)
Prior art keywords
layer
hole blocking
semiconductor device
insulating film
oxide
Prior art date
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Ceased
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PCT/JP2021/045616
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English (en)
Japanese (ja)
Inventor
安史 樋口
孝 四戸
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Flosfia Inc
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Flosfia Inc
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Filing date
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Application filed by Flosfia Inc filed Critical Flosfia Inc
Priority to JP2022568351A priority Critical patent/JPWO2022124404A1/ja
Priority to EP21903500.3A priority patent/EP4261892A4/fr
Priority to CN202180083250.4A priority patent/CN116583955A/zh
Publication of WO2022124404A1 publication Critical patent/WO2022124404A1/fr
Priority to US18/207,912 priority patent/US20230335581A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/411—Insulated-gate bipolar transistors [IGBT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/411—Insulated-gate bipolar transistors [IGBT]
    • H10D12/441—Vertical IGBTs
    • H10D12/461—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions
    • H10D12/481—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/63—Vertical IGFETs
    • H10D30/635—Vertical IGFETs having no inversion channels, e.g. vertical accumulation channel FETs [ACCUFET] or normally-on vertical IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H10D30/668—Vertical DMOS [VDMOS] FETs having trench gate electrodes, e.g. UMOS transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
    • H10D62/107—Buried supplementary regions, e.g. buried guard rings 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/393—Body regions of DMOS transistors or IGBTs 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/681—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having a compositional variation, e.g. multilayered
    • H10D64/685—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having a compositional variation, e.g. multilayered being perpendicular to the channel plane
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D8/00—Diodes
    • H10D8/60—Schottky-barrier diodes 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/691—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator comprising metallic compounds, e.g. metal oxides or metal silicates 

Definitions

  • the present invention relates to a semiconductor device.
  • the present invention also relates to a system having a semiconductor device.
  • Patent Document 1 proposes a semiconductor device having a Ga 2 O 3 system semiconductor layer and a gate insulating film arranged in contact with the semiconductor layer.
  • the semiconductor layer is a p-type semiconductor layer, holes are injected from the semiconductor layer into the gate insulating film arranged in contact with each other, and the film life of the gate insulating film is shortened. There was a problem that the characteristics fluctuated.
  • Examples of semiconductors include silicon carbide, gallium nitride, gallium nitride, gallium nitride, and gallium nitride nitride semiconductors including mixed crystals thereof.
  • semiconductors include silicon carbide, gallium nitride, gallium nitride, gallium nitride, and gallium nitride nitride semiconductors including mixed crystals thereof.
  • a semiconductor device using gallium oxide (Ga 2 O 3 ) having a larger bandgap than the above-mentioned semiconductor material has attracted attention.
  • Semiconductor devices containing crystalline oxide semiconductors with a large bandgap are expected to be applied to power semiconductor devices such as inverters as switching elements. Since it has a wide bandgap, gallium oxide is also expected to be applied as a light receiving / receiving device such as an LED or a sensor.
  • gallium oxide has five crystal structures of ⁇ , ⁇ , ⁇ , ⁇ , and ⁇ . Among them, gallium oxide having a corundum structure has a high bandgap and is attracting attention as a semiconductor material for next-generation power devices. However, since gallium oxide has a ⁇ -gallia structure as the most stable phase, it is difficult to form a crystal film containing gallium oxide having a corundum structure, which is a semi-stable phase, without using a special film forming method. There was also a problem that there was a problem and that the thermal behavior of the crystal film in the semiconductor device was unknown.
  • Patent Document 2 describes gallium oxide as an InAlGaO-based semiconductor, which can control the bandgap by mixing indium and aluminum with each other or in combination.
  • a semiconductor device using an oxide semiconductor such as gallium oxide or aluminum gallium oxide mixed crystal having a wide band gap it comes into contact with a p-type semiconductor layer (channel layer) or an n-type semiconductor layer (drift layer).
  • a semiconductor device including an oxide semiconductor such as an InAlGaO-based semiconductor a semiconductor device capable of preventing deterioration of the characteristics of the gate insulating film and having excellent reliability has been desired.
  • One of the objects of the present invention is to prevent deterioration of the characteristics of the gate insulating film and to provide a semiconductor device having excellent reliability.
  • the present inventor has at least a gate insulating film, a hole-blocking layer in which the semiconductor device is arranged in contact with the gate insulating film, and the positive.
  • Gate insulation includes at least an oxide semiconductor layer arranged in contact with the hole blocking layer, and the hole blocking layer is arranged between the gate insulating film and the oxide semiconductor layer. It was found that the deterioration of the characteristics of the film could be prevented and a semiconductor device having excellent reliability could be obtained, and it was found that the above-mentioned conventional problems could be solved at once.
  • the hole blocking includes a gate insulating film, a hole blocking layer arranged in contact with the gate insulating film, and an oxide semiconductor layer arranged in contact with the hole blocking layer.
  • the hole blocking layer has a first conductive type
  • the oxide semiconductor layer has a second conductive type different from the first conductive type.
  • Semiconductor equipment [3] The semiconductor device according to the above [1] or [2], wherein the band gap of the hole blocking layer and the band gap of the oxide semiconductor layer are different.
  • the oxide semiconductor layer 3 contains at least one metal selected from gallium, iridium, nickel, rhodium, and chromium.
  • the interface between the oxide semiconductor layer and the hole blocking layer serves as a barrier for blocking the injection of holes from the oxide semiconductor layer.
  • Semiconductor equipment [9] The semiconductor device according to any one of [5] to [8], wherein the barrier height against holes at the interface between the oxide semiconductor layer and the hole blocking layer is 1.0 eV or more.
  • the oxide semiconductor layer has an n-type conductive type.
  • the hole blocking layer has a p-type conductive type.
  • the oxide semiconductor layer 7 contains at least one metal selected from gallium, aluminum, and indium.
  • the interface between the gate insulating film and the hole blocking layer serves as a barrier for blocking the injection of holes from the oxide semiconductor layer.
  • Semiconductor device The semiconductor device according to any one of [10] to [13], wherein the barrier height against holes at the interface between the gate insulating film and the hole blocking layer is 1.0 eV or more.
  • a semiconductor device comprising the above, in which the p-type hole blocking layer and the p-type oxide layer are partially in contact with each other.
  • a system having at least a circuit and a semiconductor device electrically connected to the circuit, wherein the semiconductor device is the semiconductor device according to any one of [1] to [17].
  • deterioration of the characteristics of the gate insulating film can be prevented, and a semiconductor device having excellent reliability can be provided.
  • the first embodiment of the present invention is a schematic bird's-eye view showing a cross-sectional structure of a semiconductor device.
  • a schematic cross-sectional view taken along the line Ib-Ib of the semiconductor device shown in FIG. 1-a is shown.
  • a schematic cross-sectional view of a semiconductor device is shown.
  • FIG. 2B shows a schematic cross-sectional view taken along the line IIb-IIb of the semiconductor device shown in FIG. 2-b.
  • a schematic cross-sectional view of a semiconductor device is shown.
  • a schematic cross-sectional view of a semiconductor device is shown.
  • FIG. 4A is a schematic cross-sectional view taken along the line IVb-IVb of the semiconductor device shown in FIG. 4-a.
  • It is a block block diagram which shows an example of the control system including the semiconductor device which concerns on embodiment of this invention. It is a circuit diagram which shows an example of the control system including the semiconductor device which concerns on embodiment of this invention. It is a block block diagram which shows an example of the control system including the semiconductor device which concerns on embodiment of this invention. It is a circuit diagram which shows an example of the control system including the semiconductor device which concerns on embodiment of this invention. It is a block diagram of the mist CVD apparatus used in embodiment of this invention.
  • the semiconductor device comprises a gate insulating film, a hole blocking layer arranged in contact with the gate insulating film, and an oxide semiconductor layer arranged in contact with the hole blocking layer. It is characterized in that the hole blocking layer is provided between the gate insulating film and the oxide semiconductor layer. Further, as another aspect of the present invention, the gate insulating film, the n-type hole blocking layer arranged in contact with the gate insulating film, and the n-type hole blocking layer arranged in contact with the gate insulating film are arranged in contact with each other.
  • a semiconductor device including the oxide layer of the above, wherein the p-type hole blocking layer and the p-type oxide layer are partially in contact with each other.
  • the hole blocking layer is a layer (which may be a plurality of regions) that prevents holes from being injected into the gate insulating film from the oxide semiconductor layer (which may be multi-layered).
  • the oxide semiconductor layer has a trench as desired, and the hole blocking layer is arranged between the oxide semiconductor layer and the gate insulating film arranged so as to cover the bottom surface and the side surface of the trench.
  • the shape of the hole blocking layer differs depending on whether the hole blocking layer is arranged at a position close to the side surface of the trench or close to the bottom surface of the trench.
  • the conductive type of the hole blocking layer is preferably different from the conductive type of the oxide semiconductor layer having the trench.
  • the hole blocking layer is preferably an oxide layer.
  • the hole blocking layer preferably contains at least one metal selected from aluminum, indium and gallium, and is selected from aluminum, indium and gallium.
  • the hole blocking layer contains a metal oxide containing indium and gallium as a main component.
  • the hole blocking layer contains at least one metal selected from gallium, iridium, nickel, rhodium, and chromium, and gallium.
  • the metal oxide contains a metal oxide of at least one metal selected from iridium, nickel, rhodium, and chromium as a main component.
  • the "main component” means that the metal oxide has an atomic ratio of preferably 50% or more, more preferably 70% or more, still more preferably 90% or more with respect to all the components of the hole blocking layer. It means that it is included, and it means that it may be 100%.
  • the oxide semiconductor layer having the trench is an n-type oxide semiconductor layer (for example, an n-type gallium oxide semiconductor, an n-type aluminum gallium oxide semiconductor, an n-type indium gallium oxide semiconductor, and an n-type indium aluminum gallium oxide semiconductor.
  • the hole blocking layer is of at least one oxide selected from a p-type oxide semiconductor layer (eg, p-type iridium gallium oxide, Mg-doped gallium oxide). Layer) is preferred. Further, as one of the embodiments of the present invention, it is preferable that the hole blocking layer has a barrier of 1.0 eV or more as a barrier against holes in the oxide semiconductor layer.
  • the method for forming the hole blocking layer may be the same as the method for forming the oxide semiconductor layer described later.
  • the oxide semiconductor layer is not particularly limited as long as the object of the present invention is not impaired.
  • the oxide semiconductor layer is preferably a crystalline oxide semiconductor layer.
  • the constituent material of the oxide semiconductor layer for example, a metal oxide containing one or more metals selected from aluminum, gallium, indium, iron, chromium, vanadium, titanium, rhodium, nickel, cobalt and iridium. And so on.
  • the conductive type of the oxide semiconductor layer is not particularly limited, and may be an n-type or a p-type.
  • the oxide semiconductor layer preferably contains at least one metal selected from aluminum, indium and gallium, and is selected from aluminum, indium and gallium. It is more preferable to contain a metal oxide of at least one kind of metal as a main component, and even more preferably to contain a metal oxide containing at least gallium as a main component, which is ⁇ -Ga 2 O 3 or a mixed crystal thereof. Is the most preferable.
  • the oxide semiconductor layer contains at least one metal selected from gallium, iridium, nickel, rhodium, and chromium, and gallium.
  • a metal oxide of at least one metal selected from iridium, nickel, gallium, and chromium as a main component.
  • the "main component” means that the metal oxide has an atomic ratio of preferably 50% or more, more preferably 70% or more, still more preferably 90% or more with respect to all the components of the oxide semiconductor layer. It means that it is included, and it means that it may be 100%.
  • the crystal structure of the crystalline oxide semiconductor layer is also not particularly limited as long as the object of the present invention is not impaired.
  • the crystal structure of the crystalline oxide semiconductor layer includes, for example, a corundum structure, a ⁇ -galia structure, a hexagonal structure (for example, ⁇ -type structure, etc.), an orthorhombic structure (for example, a ⁇ -type structure, etc.), a cubic structure, and the like. Alternatively, a square crystal structure or the like can be mentioned.
  • the crystalline oxide semiconductor layer preferably has a corundum structure, a ⁇ -Galia structure or a hexagonal structure (for example, a ⁇ -type structure), and more preferably has a corundum structure. ..
  • the thickness of the oxide semiconductor layer is not particularly limited, and may be 1 ⁇ m or less, or may be 1 ⁇ m or more.
  • the surface area of the oxide semiconductor layer is not particularly limited, but may be 1 mm 2 or more or 1 mm 2 or less, preferably 10 mm 2 to 300 cm 2 , preferably 100 mm 2 to 100 cm 2 . It is more preferable to have it.
  • the crystalline oxide semiconductor layer may be usually a single crystal or a polycrystal. In the embodiment of the present invention, the crystalline oxide semiconductor layer is preferably a single crystal layer.
  • the oxide semiconductor layer preferably contains a dopant.
  • the dopant is not particularly limited and may be a known one.
  • n such as tin, germanium, silicon, titanium, zirconium, vanadium or niobium.
  • Examples include type dopants.
  • the conductive type of the oxide semiconductor layer is p-type, examples thereof include p-type dopants such as magnesium, calcium, and zinc.
  • the content of the dopant is preferably 0.00001 atomic% or more, more preferably 0.00001 atomic% to 20 atomic%, and 0.00001 atomic% to 10 atomic% in the composition of the semiconductor layer. Is most preferable. More specifically, the concentration of the dopant may usually be about 1 ⁇ 10 16 / cm 3 to 1 ⁇ 10 22 / cm 3 , and the concentration of the dopant may be, for example, about 1 ⁇ 10 17 / cm. The concentration may be as low as 3 or less. Further, according to the present invention, the dopant may be contained in a high concentration of about 1 ⁇ 10 20 / cm 3 or more. In the embodiment of the present invention, it is preferably contained at a carrier concentration of 1 ⁇ 10 17 / cm 3 or more.
  • the oxide semiconductor layer (hereinafter, also simply referred to as "semiconductor layer” or “semiconductor film”) may be formed by using a known means.
  • the means for forming the semiconductor layer include a CVD method, a MOCVD method, a MOVPE method, a mist CVD method, a mist epitaxy method, an MBE method, an HVPE method, a pulse growth method, and an ALD method.
  • the means for forming the semiconductor layer is preferably a MOCVD method, a mist CVD method, a mist epitaxy method or an HVPE method, and preferably a mist CVD method or a mist epitaxy method.
  • the raw material solution is atomized (atomization step) using the mist CVD apparatus shown in FIG. 9, droplets are suspended, and atomization obtained after atomization is performed.
  • a semiconductor film containing a crystalline oxide semiconductor as a main component on the substrate by transporting the droplets to the substrate with a carrier gas (transportation step) and then thermally reacting the atomized droplets in the vicinity of the substrate.
  • the semiconductor layer is formed by laminating (depositioning step).
  • the atomization step atomizes the raw material solution.
  • the means for atomizing the raw material solution is not particularly limited as long as the raw material solution can be atomized, and may be known means, but in the embodiment of the present invention, the atomizing means using ultrasonic waves is preferable. ..
  • Atomized droplets obtained using ultrasonic waves have a zero initial velocity and are preferable because they float in the air. For example, instead of spraying them like a spray, they float in space and are transported as a gas. Since it is a possible mist, it is not damaged by collision energy, so it is very suitable.
  • the droplet size is not particularly limited and may be a droplet of about several mm, but is preferably 50 ⁇ m or less, and more preferably 100 nm to 10 ⁇ m.
  • the raw material solution is not particularly limited as long as it can be atomized or atomized and contains a raw material capable of forming a semiconductor film, and may be an inorganic material or an organic material.
  • the raw material is preferably a metal or a metal compound, and is selected from aluminum, gallium, indium, iron, chromium, vanadium, titanium, rhodium, nickel, cobalt and iridium. It is more preferable to contain more than a kind of metal.
  • a solution in which the metal is dissolved or dispersed in an organic solvent or water in the form of a complex or a salt can be preferably used.
  • the form of the complex include an acetylacetonate complex, a carbonyl complex, an ammine complex, and a hydride complex.
  • the salt form include organic metal salts (for example, metal acetate, metal oxalate, metal citrate, etc.), metal sulfide salts, nitrified metal salts, phosphorylated metal salts, and halogenated metal salts (for example, metal chloride). Salts, metal bromide salts, metal iodide salts, etc.) and the like.
  • an additive such as a hydrohalic acid or an oxidizing agent with the raw material solution.
  • the hydrohalogen acid include hydrobromic acid, hydrochloric acid, hydroiodic acid, and the like. Among them, hydrobromic acid or hydrobromic acid because it can suppress the generation of abnormal grains more efficiently. Hydroiodic acid is preferred.
  • the oxidizing agent include hydrogen peroxide (H 2 O 2 ), sodium peroxide (Na 2 O 2 ), barium peroxide (BaO 2 ), benzoyl peroxide (C 6 H 5 CO) 2 O 2 and the like. Peroxides, hypochlorous acid (HClO), perchloric acid, nitric acid, ozone water, organic peroxides such as peracetic acid and nitrobenzene can be mentioned.
  • the raw material solution may contain a dopant.
  • the dopant By including the dopant in the raw material solution, doping can be performed satisfactorily.
  • the dopant is not particularly limited as long as it does not interfere with the object of the present invention.
  • the dopant include n-type dopants such as tin, germanium, silicon, titanium, zirconium, vanadium or niobium, or Mg, H, Li, Na, K, Rb, Cs, Fr, Be, Ca, Sr and Ba. , Ra, Mn, Fe, Co, Ni, Pd, Cu, Ag, Au, Zn, Cd, Hg, Ti, Pb, N, P-type dopants and the like.
  • the content of the dopant is appropriately set by using a calibration curve showing the relationship between the desired carrier density and the concentration of the dopant in the raw material.
  • the solvent of the raw material solution is not particularly limited, and may be an inorganic solvent such as water, an organic solvent such as alcohol, or a mixed solvent of an inorganic solvent and an organic solvent.
  • the solvent preferably contains water, and more preferably water or a mixed solvent of water and alcohol.
  • the atomized droplets are transported to the film forming chamber by the carrier gas.
  • the carrier gas is not particularly limited as long as the object of the present invention is not impaired, and for example, an inert gas such as oxygen, ozone, nitrogen or argon, or a reducing gas such as hydrogen gas or forming gas is a suitable example. Can be mentioned.
  • the type of carrier gas may be one type, but may be two or more types, and a diluted gas having a reduced flow rate (for example, a 10-fold diluted gas) or the like is further used as the second carrier gas. May be good.
  • the carrier gas may be supplied not only at one place but also at two or more places.
  • the flow rate of the carrier gas is not particularly limited, but is preferably 0.01 to 20 L / min, and more preferably 1 to 10 L / min.
  • the flow rate of the diluted gas is preferably 0.001 to 2 L / min, more preferably 0.1 to 1 L / min.
  • the semiconductor film is formed on the substrate by thermally reacting the atomized droplets in the vicinity of the substrate.
  • the thermal reaction may be any effect as long as the atomized droplets react with heat, and the reaction conditions and the like are not particularly limited as long as the object of the present invention is not impaired.
  • the thermal reaction is usually carried out at a temperature equal to or higher than the evaporation temperature of the solvent, but is preferably not too high (for example, 1000 ° C.) or lower, more preferably 650 ° C. or lower, and most preferably 300 ° C. to 650 ° C. preferable.
  • the thermal reaction is carried out under any of a vacuum, a non-oxygen atmosphere (for example, an inert gas atmosphere, etc.), a reducing gas atmosphere, and an oxygen atmosphere, as long as the object of the present invention is not impaired.
  • a vacuum for example, an inert gas atmosphere, etc.
  • a reducing gas atmosphere for example, a reducing gas atmosphere
  • an oxygen atmosphere for example, a nitrogen atmosphere
  • it is preferably carried out in an inert gas atmosphere or an oxygen atmosphere.
  • it may be carried out under any conditions of atmospheric pressure, pressurization and depressurization, but in the embodiment of the present invention, it is preferably carried out under atmospheric pressure.
  • the film thickness can be set by adjusting the film formation time.
  • the substrate is not particularly limited as long as it can support the semiconductor film.
  • the material of the substrate is not particularly limited as long as it does not impair the object of the present invention, and may be a known substrate, an organic compound, or an inorganic compound.
  • the shape of the substrate may be any shape and is effective for any shape, for example, plate-like, fibrous, rod-like, columnar, prismatic, such as a flat plate or a disk. Cylindrical, spiral, spherical, ring-shaped and the like can be mentioned, but in the embodiment of the present invention, a substrate is preferable.
  • the thickness of the substrate is not particularly limited in the embodiment of the present invention.
  • the substrate is not particularly limited as long as it has a plate shape and serves as a support for the semiconductor film. It may be an insulator substrate, a semiconductor substrate, a metal substrate or a conductive substrate, but the substrate is preferably an insulator substrate, and the surface is made of metal. A substrate having a film is also preferable.
  • the substrate includes, for example, a base substrate containing a substrate material having a corundum structure as a main component, a substrate substrate containing a substrate material having a ⁇ -galia structure as a main component, and a substrate material having a hexagonal structure as a main component. Examples include a base substrate.
  • the “main component” means that the substrate material having the specific crystal structure has an atomic ratio of preferably 50% or more, more preferably 70% or more, and further preferably 90% with respect to all the components of the substrate material. It means that it is contained in% or more, and may be 100%.
  • the substrate material is not particularly limited and may be known as long as it does not interfere with the object of the present invention.
  • Examples of the substrate material having the corundum structure are ⁇ -Al 2 O 3 (sapphire substrate) or ⁇ -Ga 2 O 3 , and a-plane sapphire substrate, m-plane sapphire substrate, and r-plane sapphire substrate are preferable.
  • C-plane sapphire substrate, ⁇ -type gallium oxide substrate (a-plane, m-plane or r-plane) and the like are more preferable examples.
  • the base substrate containing the substrate material having a ⁇ -Galia structure as a main component for example, ⁇ -Ga 2 O 3 substrate or Ga 2 O 3 and Al 2 O 3 are included, and Al 2 O 3 is more than 0 wt%.
  • Examples thereof include a mixed crystal substrate having a content of 60 wt% or less.
  • Examples of the base substrate containing a substrate material having a hexagonal structure as a main component include a SiC substrate, a ZnO substrate, and a GaN substrate.
  • an annealing treatment may be performed after the film forming step.
  • the annealing treatment temperature is not particularly limited as long as it does not impair the object of the present invention, and is usually 300 ° C. to 650 ° C., preferably 350 ° C. to 550 ° C.
  • the annealing treatment time is usually 1 minute to 48 hours, preferably 10 minutes to 24 hours, and more preferably 30 minutes to 12 hours.
  • the annealing treatment may be performed in any atmosphere as long as the object of the present invention is not impaired. It may be in a non-oxygen atmosphere or in an oxygen atmosphere. Examples of the non-oxygen atmosphere include an inert gas atmosphere (for example, a nitrogen atmosphere) and a reduced gas atmosphere. However, in the embodiment of the present invention, the inert gas atmosphere is preferable, and the nitrogen atmosphere is preferable. It is more preferably below.
  • the semiconductor film may be provided directly on the substrate, or another layer such as a stress relaxation layer (for example, a buffer layer, an ELO layer, etc.), a peeling sacrificial layer, or the like may be provided.
  • the semiconductor film may be provided therethrough.
  • the means for forming each layer is not particularly limited and may be known means, but in the embodiment of the present invention, the mist CVD method is preferable.
  • the semiconductor film may be used in a semiconductor device as the semiconductor layer after using a known means such as peeling from the substrate or the like, or may be used as it is in the semiconductor device as the semiconductor layer. You may use it.
  • the hole blocking layer has a first conductive type and the oxide semiconductor layer has a second conductive type different from the first conductive type. .. It is also preferable that the band gap of the hole blocking layer and the band gap of the oxide semiconductor layer are different.
  • the gate insulating film is not particularly limited as long as it does not impair the object of the present invention.
  • Examples of the gate insulating film include SiO 2 , Si 3 N 4 , Al 2 O 3 , GaO, AlGaO, InAlGaO, AlInZnGaO 4 , AlN, Hf 2 O 3 , SiN, SiON, MgO, GdO, and phosphorus.
  • a suitable example is an oxide film such as an oxide film containing at least the oxide film.
  • the gate insulating film may be formed by a known method, and examples of such known forming means include a dry method and a wet method. Examples of the dry method include known methods such as sputtering, vacuum deposition, CVD, and PLD. Examples of the wet method include a coating method such as screen printing and die coating.
  • FIG. 1-a is a schematic bird's-eye view showing a cross-sectional structure of a semiconductor device as the first embodiment of the present invention.
  • the electrode and a part of the insulating film are removed, and the structure in the depth direction shown in the figure is also shown.
  • FIG. 1-b shows a schematic cross-sectional view cut by Ib-Ib shown in FIG. 1-a.
  • the semiconductor device 100 comprises a gate insulating film 1, a hole blocking layer 2 arranged in contact with the gate insulating film 1, and an oxide semiconductor layer 3 arranged in contact with the hole blocking layer 2. Includes.
  • the hole blocking layer 2 is provided between the gate insulating film 1 and the oxide semiconductor layer 3.
  • the gate insulating film 1, the hole blocking layer 2, and the oxide semiconductor layer 3 have a portion where they are arranged side by side in the horizontal direction in a plan view.
  • the oxide semiconductor layer 3 contains at least one metal selected from gallium, iridium, nickel, rhodium, and chromium.
  • the hole blocking layer 2 has a first conductive type
  • the oxide semiconductor layer 3 has a second conductive type different from the first conductive type. Is preferable.
  • the first conductive type is, for example, an n-type conductive type
  • the second conductive type is a p-type conductive type. Further, as shown in FIG.
  • the hole blocking layer 2 is the gate insulating film 1 arranged along the trench 10 at least in the length direction and the depth direction of the side surface of the trench. It is preferable that the two layers are arranged so as to extend without interruption. With such a preferable configuration, it is possible to more preferably prevent the injection of holes from the oxide semiconductor layer 3 into the gate insulating film 1. The effect of preventing hole injection in this embodiment will be described in detail with reference to the band diagram shown in FIGS. 1-d.
  • the gate insulating film 1 is, for example, a SiO 2 film
  • the oxide semiconductor layer 3 is a p-type iridium gallium oxide layer.
  • a hole blocking layer can be arranged to form a barrier against holes.
  • the barrier height against holes at the interface between the oxide semiconductor layer 3 and the hole blocking layer 2 is 1.0 eV or more.
  • the hole blocking layer 2 having a barrier against holes of 1.0 eV or more with respect to the oxide semiconductor layer 3.
  • a barrier against holes is formed between the oxide semiconductor layer 3 and the hole blocking layer 2.
  • Another layer may be arranged between the oxide semiconductor layer 3 and the hole blocking layer 2 as long as the object of the present invention is not impaired.
  • the semiconductor device 100 has a first semiconductor region 12 arranged on the oxide semiconductor layer 3 and adjacent to the upper side surface of the gate insulating film arranged along the trench 10. Have. It is preferable that the upper end portion of the hole blocking layer 2 arranged between the oxide semiconductor layer 3 and the gate insulating film is in contact with and / or embedded in the first semiconductor region 12. Further, it is also preferable that the upper end portion of the hole blocking layer 2 is flush with the upper surface of the first semiconductor region 12 because the formation of the hole blocking layer 3 is facilitated. Further, the semiconductor device 100 has a second semiconductor region 13 arranged on the oxide semiconductor layer 3, and as shown in FIG. 1-a, the first semiconductor region 12 and the second semiconductor region 13 are included.
  • FIG. 1-c shows a schematic cross-sectional view of the semiconductor device 100.
  • the semiconductor device 100 covers the first electrode 11 (gate electrode in this embodiment) embedded in the trench 10, the upper surface of the gate electrode 11 and the upper surface of the gate insulating film 1, and further covers the upper surface of the first semiconductor region 12.
  • the insulating film 14 between the first electrode and the second electrode (the insulating film between the source and the gate in this embodiment), the insulating film 14 between the source and the gate, and the first semiconductor region 12 are arranged so as to cover at least a part thereof.
  • the oxide semiconductor layer 7 contains at least one metal selected from gallium, aluminum, and indium. Further, the oxide semiconductor layer 3 contains at least one metal selected from iridium, nickel, rhodium, and chromium.
  • the conductive type of the second oxide semiconductor layer 7 and the oxide layer 9 is different from the conductive type of the first oxide semiconductor layer 3.
  • the first oxide semiconductor layer 3 is a p-type iridium gallium oxide layer
  • the second oxide semiconductor layer 7 is an n-type gallium oxide semiconductor layer
  • the oxide layer 9 is used. Is an n + type gallium oxide semiconductor layer.
  • the semiconductor device 100 of the present embodiment is a MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor).
  • the first oxide semiconductor layer 3 is formed on the second oxide semiconductor layer 7, and further, the first semiconductor region 12 is formed on the first oxide semiconductor layer 3.
  • a mask for etching
  • the first oxide semiconductor layer 3 is formed from the upper surface of the first semiconductor region 12 by etching. It penetrates and forms a groove having a depth reaching the second oxide semiconductor layer 7.
  • the hole blocking layer 2 is formed.
  • a mask for film formation
  • the hole blocking layer 2 is formed only on the side surface of the trench as shown in FIG. 1-b by the above film forming method.
  • the oxide semiconductor layer 7, the hole blocking layer 2, and the first semiconductor region 12 for example, a film forming method such as a MOCVD method, a mist CVD method, a mist epitaxy method, or an HVPE method can be used. Can be mentioned.
  • the hole blocking layer 2 may be provided so as to cover the side surface and the bottom surface of the trench. In this case, it is not necessary to provide a mask (for film formation) on the bottom surface of the trench. Further, even in such an embodiment, the effect of preventing the injection of holes from the first oxide semiconductor layer 3 into the gate insulating film 1 can be obtained.
  • the gate insulating film 1 is formed by covering the hole blocking layer arranged in the trench.
  • the method for forming the gate insulating film include a CVD method, an atmospheric pressure CVD method, a plasma CVD method, and a mist CVD method.
  • the first electrode 11 (gate electrode) is embedded in the trench in which the gate insulating film 1 is arranged.
  • the insulating film 14 between the first electrode and the second electrode is formed, and the second electrode 15 is formed on the insulating film 14 between the first electrode and the second electrode.
  • the third electrode 16 located on the opposite side of the second electrode 15 may be formed, but the formation of the electrodes is an example, and the order is not particularly limited.
  • the method for forming the first electrode 11, the second electrode 15, and the third electrode 16 is not particularly limited and may be a known means. Specific examples of the means for forming the first electrode or the second electrode layer include sputtering, vacuum deposition, and CVD.
  • FIG. 2-a is a schematic bird's-eye view showing a cross-sectional structure of a semiconductor device as a second embodiment of the present invention.
  • the electrode and a part of the insulating film are removed, and the structure in the depth direction shown in the figure is also shown.
  • FIG. 2-b shows a schematic cross-sectional view cut by IIb-IIb shown in FIG. 2-a.
  • the semiconductor device 200 comprises a gate insulating film 1, a hole blocking layer 6 arranged in contact with the gate insulating film 1, and an oxide semiconductor layer 7 arranged in contact with the hole blocking layer 6. Includes.
  • the hole blocking layer 6 is provided between the gate insulating film 1 and the oxide semiconductor layer 7. Further, as shown in FIG.
  • the hole blocking layer 6 has a portion of the gate insulating film 1 arranged along the trench 10 at least at the bottom of the trench, which covers the gate insulating film 1. ..
  • the gate insulating film 1 may be covered and may not be arranged so as to extend without interruption, and if it is at least partially arranged, holes from the oxide semiconductor layer 7 to the gate insulating film 1 may be provided. Can be prevented from injecting. The effect of preventing hole injection in this embodiment will be described in detail with reference to the band diagram shown in FIG. 2-d.
  • the gate insulating film 1 is a SiO 2 film
  • the oxide semiconductor layer 7 is an n-type gallium oxide layer.
  • the oxide semiconductor layer 7 When the oxide semiconductor layer 7 is arranged in contact with the gate insulating film 1, there is no barrier against holes between the gate insulating film 1 and the oxide semiconductor layer 7, so that the oxide semiconductor is present. Holes are injected from the layer 7 into the gate insulating film 1, which leads to deterioration of the gate insulating film 1.
  • the hole blocking layer 2 of the p-type iridium oxide gallium layer between the oxide semiconductor layer 7 and the gate insulating film 1
  • the gate insulating film 1 and the hole insulating film 1 are positive.
  • a barrier against holes is formed between the hole blocking layer 2 and the hole blocking layer 2.
  • the hole blocking layer 2 was generated in the n-type gallium oxide layer 7 by at least partially connecting the hole blocking layer 2 to the p-type oxide semiconductor layer 3 arranged on the n-type gallium oxide layer 7. There is a way to release holes to the source electrode via the hole blocking layer 6 which is the p-type iridium gallium oxide layer. In this embodiment, by arranging the hole blocking layer 6, it is only necessary to provide a path for releasing holes. In the combination of the material of the hole blocking layer 6 and the material of the gate insulating film 1, a barrier against holes is formed between the hole blocking layer 6 and the gate insulating film 1. As long as it does not interfere with the object of the present invention, it is not particularly limited.
  • the hole blocking layer 6 is at least in the length direction of the side surface of the trench of the gate insulating film 1 arranged along the trench 10 like the hole blocking layer 2 of the semiconductor device 100 in the first embodiment. In the depth direction, it is not necessary to cover the gate insulating film 1 and arrange it so as to extend without interruption.
  • the hole blocking layers 6 can be arranged as a plurality of hole blocking regions 6 at intervals in the length direction of the side surface of the trench, as shown in FIG. 2-b.
  • the holes released into the p-type oxide semiconductor layer 3 are further released from the source electrode 15 via the second semiconductor region 13.
  • a mask (for etching) is placed on the upper surface of the second oxide semiconductor layer 7.
  • a plurality of recesses are formed on the upper surface side of the second oxide semiconductor layer 7 at regular intervals in the length direction of the trench 10 shown in FIG. 2-b.
  • the hole blocking layer 6 is embedded in the plurality of recesses.
  • the hole blocking layer 6 is preferably a plurality of hole blocking regions arranged at intervals along the bottom surface of the trench.
  • the oxide semiconductor layer 3 is formed on the second oxide semiconductor layer 7 in which a plurality of hole blocking regions are embedded, and the first semiconductor region 12 is formed on the oxide semiconductor layer 3. do. Then, a mask (for etching) is placed in an area other than forming the trench 10 on the first semiconductor region 12. By etching, a trench 10 having a depth that penetrates the first oxide semiconductor layer 3 from the upper surface of the first semiconductor region 12 and reaches the hole blocking layer 6 is formed.
  • a film forming method such as a MOCVD method, a mist CVD method, a mist epitaxy method, or an HVPE method can be used. Can be mentioned.
  • the gate insulating film 1 is formed in the trench.
  • the method for forming the gate insulating film include a CVD method, an atmospheric pressure CVD method, a plasma CVD method, and a mist CVD method.
  • the first electrode 11 (gate electrode) is embedded in the trench in which the gate insulating film 1 is arranged.
  • the insulating film 14 between the first electrode and the second electrode may be formed, and the second electrode 15 may be formed on the insulating film 14 between the first electrode and the second electrode.
  • the third electrode 16 located on the opposite side of the second electrode 15 may be formed, but the formation of the electrodes is an example, and the order is not particularly limited.
  • the method for forming the first electrode 11, the second electrode 15, and the third electrode 16 is not particularly limited and may be a known means. Specific examples of the means for forming the first electrode or the second electrode layer include sputtering, vacuum deposition, and CVD.
  • MOSFET Metal-Oxide-Semiconductor Field Effect Transistor
  • FIG. 3 is a schematic bird's-eye view showing a cross-sectional structure of a semiconductor device as a third embodiment of the present invention.
  • the semiconductor device 300 comprises a gate insulating film 1, a hole blocking layer 2 arranged in contact with the gate insulating film 1, and an oxide semiconductor layer 3 arranged in contact with the hole blocking layer 2. Includes.
  • the hole blocking layer 2 is provided between the gate insulating film 1 and the oxide semiconductor layer 3. Similar to the semiconductor device 100 shown in FIG. 1-b, the hole blocking layer 2 is gate-insulated at least in the length direction and the depth direction of the side surface of the trench of the gate insulating film 1 arranged along the trench 10.
  • the semiconductor device 300 By covering the film 1 and arranging it so as to extend without interruption, it is possible to prevent the injection of holes from the oxide semiconductor layer 3 into the gate insulating film 1.
  • the difference between the semiconductor device 300 and the semiconductor device 100 of the first embodiment is that instead of the oxide layer 9 (n + type gallium oxide semiconductor layer) of the semiconductor device 100, the semiconductor device 300 has an oxide layer. 19 (p + type oxide semiconductor layer) is arranged. That is, the semiconductor device 300 covers the first electrode 11 (gate electrode in this embodiment) embedded in the trench 10, the upper surface of the gate electrode 11 and the upper surface of the gate insulating film 1, and further covers the first semiconductor region 12.
  • the insulating film 14 between the first electrode and the second electrode (in this embodiment, the insulating film between the emitter and the gate) 14 arranged so as to cover at least a part of the upper surface of the above surface, the insulating film between the emitter and the gate 14, and the first. It has a semiconductor region 12 and a second electrode 15 (emitter electrode in this embodiment) arranged so as to cover the upper surface of the second semiconductor region 13. Further, when the oxide semiconductor layer 3 is the first oxide semiconductor layer, the semiconductor device 300 is arranged in contact with the first oxide semiconductor layer 3 and the bottom of the trench is embedded in the second.
  • the oxide semiconductor layer 7 of the above, the oxide layer 19 arranged in contact with the second oxide semiconductor layer 7, and the third electrode 16 arranged in contact with the oxide layer 19 has a collector electrode).
  • the semiconductor device 300 of this embodiment is an IGBT (Insulated Gate Bipolar Transistor).
  • FIG. 4-a shows a schematic cross-sectional view of a semiconductor device as a fourth embodiment of the present invention.
  • FIG. 4-b shows a schematic cross-sectional view taken along the line IVb-IVb of the semiconductor device shown in FIG. 4-a.
  • the semiconductor device 400 has a gate insulating film 1, an n-type hole blocking layer 2 arranged in contact with the gate insulating film 1, and a p. It has a type oxide semiconductor layer 3. Further, the semiconductor device 400 is further arranged in contact with the p-type hole blocking layer 6 arranged in contact with at least a part of the gate insulating film 1 and the p-type hole blocking layer 6. It also contains an n-type oxide semiconductor layer 6.
  • the p-type hole blocking layer 6 and the p-type oxide semiconductor layer 3 are partially in contact with each other.
  • hole injection into the gate insulating film 1 is suppressed not only in the side surface portion of the trench 10 in which the gate insulating film 1 is arranged but also in the bottom portion.
  • a structure that can be obtained is obtained. Therefore, deterioration of the characteristics of the gate insulating film can be prevented more satisfactorily, and a more reliable semiconductor device can be provided.
  • It is preferable that at least a part of the lower end of the n-type hole blocking layer 2 is embedded in the p-type hole blocking layer 6. As shown in FIG.
  • the n-type hole blocking layer 2 is a gate insulating film of the gate insulating film 1 arranged along the trench 10 at least in the length direction and the depth direction of the side surface of the trench. By covering 1 and arranging it so as to extend without interruption, it is possible to prevent holes from being injected from the oxide semiconductor layer 3 into the gate insulating film 1. Further, as shown in FIG. 4-b, the p-type hole blocking layer 6 has a portion of the gate insulating film 1 arranged along the trench 10 at least at the bottom of the trench, which covers the gate insulating film 1. is doing.
  • the p-type hole blocking layer 6 may cover the gate insulating film 1 and may not be arranged so as to extend without interruption, and if it is at least partially arranged, it is an oxide semiconductor. It is possible to prevent the injection of holes from the layer 7 into the gate insulating film 1. Further, as for the method of forming the hole blocking layer 2 and the hole blocking layer 6 in the present embodiment, the forming methods described in 1 and 2 for the embodiment can be referred to as an example.
  • the semiconductor device 400 of the present embodiment is a MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor), but instead of the oxide layer (n-type oxide semiconductor layer) 9, the oxide layer 19 (p-type oxide) is used. If the semiconductor layer) is arranged, the semiconductor device 400 of the present embodiment can also be used as an IGBT (Insulated Gate Bipolar Transistor).
  • MOSFET Metal-Oxide-Semiconductor Field Effect Transistor
  • the crystal structure of the oxide semiconductor layer is not particularly limited, but as one of the embodiments of the present invention, when the oxide semiconductor layer is a Ga 2 O 3 semiconductor layer, it has a corundum structure or a ⁇ -gallia structure. Is preferable.
  • the semiconductor device according to the embodiment of the present invention is particularly useful for power devices such as MOSFETs and IGBTs having a trench structure.
  • the above-mentioned semiconductor device of the present invention can be applied to a power conversion device such as an inverter or a converter in order to exert the above-mentioned functions. More specifically, it can be applied as a diode built in an inverter or a converter, a cyclist as a switching element, a power transistor, an IGBT (Insulated Gate Bipolar Transistor), a MOSFET (Metal-Oxide-Semiconductor Doctor), a Field Effect Transistor, or the like. can.
  • FIG. 5 is a block configuration diagram showing an example of a control system using a semiconductor device according to an embodiment of the present invention
  • FIG. 17 is a circuit diagram of the control system, which is particularly suitable for mounting on an electric vehicle. It is a control system.
  • the control system 500 includes a battery (power supply) 501, a boost converter 502, a step-down converter 503, an inverter 504, a motor (drive target) 505, and a drive control unit 506, which are mounted on an electric vehicle. It becomes.
  • the battery 501 is composed of a storage battery such as a nickel hydrogen battery or a lithium ion battery, and stores electric power by charging at a power supply station or regenerative energy during deceleration, and is required for the operation of the traveling system and the electrical system of an electric vehicle. It can output DC voltage.
  • the boost converter 502 is a voltage converter equipped with, for example, a chopper circuit, and boosts a DC voltage of, for example, 200 V supplied from the battery 501 to, for example, 650 V by the switching operation of the chopper circuit, and outputs the DC voltage to a traveling system such as a motor. be able to.
  • the step-down converter 503 is also a voltage converter equipped with a chopper circuit, but by stepping down the DC voltage of, for example, 200 V supplied from the battery 501 to, for example, about 12 V, a power window, power steering, or an in-vehicle electric device can be used. It can be output to the electrical system including.
  • the inverter 504 converts the DC voltage supplied from the boost converter 502 into a three-phase AC voltage by a switching operation and outputs it to the motor 505.
  • the motor 505 is a three-phase AC motor constituting the traveling system of the electric vehicle, and is rotationally driven by the three-phase AC voltage output from the inverter 504. Communicate to.
  • the drive control unit 506 has the function of a controller equipped with a calculation unit such as a CPU (Central Processing Unit) and a data storage unit such as a memory, and generates a control signal using the input measurement signal to the inverter 504. By outputting as a feedback signal, the switching operation by the switching element is controlled.
  • a calculation unit such as a CPU (Central Processing Unit)
  • a data storage unit such as a memory
  • the AC voltage applied to the motor 505 by the inverter 504 is instantaneously corrected, so that the operation control of the electric vehicle can be accurately executed, and the safe and comfortable operation of the electric vehicle is realized. It is also possible to control the output voltage to the inverter 504 by giving the feedback signal from the drive control unit 506 to the boost converter 502.
  • FIG. 6 is a circuit configuration excluding the buck converter 503 in FIG. 5, that is, a circuit configuration showing only a configuration for driving the motor 505.
  • the semiconductor device of the present invention is used for switching control by being adopted in the boost converter 502 and the inverter 504, for example, as a shot key barrier diode.
  • the boost converter 502 is incorporated in a chopper circuit to perform chopper control
  • the inverter 504 is incorporated in a switching circuit including an IGBT to perform switching control.
  • An inductor (coil, etc.) is interposed in the output of the battery 501 to stabilize the current, and a capacitor (electrolytic capacitor, etc.) is interposed between the battery 501, the boost converter 502, and the inverter 504. We are trying to stabilize the voltage.
  • a calculation unit 507 composed of a CPU (Central Processing Unit) and a storage unit 508 composed of a non-volatile memory are provided in the drive control unit 506.
  • the signal input to the drive control unit 506 is given to the calculation unit 507, and a feedback signal for each semiconductor device is generated by performing necessary calculations.
  • the storage unit 508 temporarily holds the calculation result by the calculation unit 507, stores physical constants and functions required for drive control in the form of a table, and appropriately outputs them to the calculation unit 507.
  • a known configuration can be adopted for the calculation unit 507 and the storage unit 508, and the processing capacity thereof and the like can be arbitrarily selected.
  • a diode, a switching element such as a thyristor, a power transistor, an IGBT, a MOSFET, or the like is used for the switching operation of the boost converter 502, the step-down converter 503, and the inverter 504. .
  • gallium oxide (Ga 2 O 3 ), particularly corundum type gallium oxide ( ⁇ -Ga 2 O 3 ), as the material for these semiconductor devices the switching characteristics are significantly improved. Further, by applying the semiconductor device or the like according to the present invention, extremely good switching characteristics can be expected, and further miniaturization and cost reduction of the control system 500 can be realized.
  • each of the boost converter 502, the buck converter 503, and the inverter 504 can be expected to have the effect of the present invention, and any one of them, any combination of two or more, or a drive control unit 506 is also included.
  • the effect of the present invention can be expected in any of the above.
  • the control system 500 described above can be applied not only to the control system of an electric vehicle by applying the semiconductor device of the present invention, but also to a control system for all purposes such as stepping up / down the power from a DC power source and converting power from DC to AC. It is possible to apply to. It is also possible to use a power source such as a solar cell as the battery.
  • FIG. 7 is a block configuration diagram showing another example of a control system using the semiconductor device according to the embodiment of the present invention
  • FIG. 8 is a circuit diagram of the control system, which is an infrastructure device operated by electric power from an AC power source. It is a control system suitable for mounting on household appliances.
  • the control system 600 inputs electric power supplied from an external, for example, a three-phase AC power supply (power supply) 601 and includes an AC / DC converter 602, an inverter 604, a motor (drive target) 605, and the like. It has a drive control unit 606, which can be mounted on various devices (described later).
  • the three-phase AC power supply 601 is, for example, a power generation facility of an electric power company (thermal power plant, hydropower plant, geothermal power plant, nuclear power plant, etc.), and its output is supplied as an AC voltage while being stepped down via a substation. To. Further, it is installed in a building or a nearby facility in the form of a private power generator or the like and is supplied by a power cable.
  • the AC / DC converter 602 is a voltage conversion device that converts an AC voltage into a DC voltage, and converts an AC voltage of 100V or 200V supplied from the three-phase AC power supply 601 into a predetermined DC voltage. Specifically, it is converted into a commonly used desired DC voltage such as 3.3V, 5V, or 12V by voltage conversion. When the drive target is a motor, conversion to 12V is performed. It is also possible to adopt a single-phase AC power supply instead of the three-phase AC power supply, and in that case, if the AC / DC converter has a single-phase input, the same system configuration can be obtained.
  • the inverter 604 converts the DC voltage supplied from the AC / DC converter 602 into a three-phase AC voltage by a switching operation and outputs it to the motor 605.
  • the form of the motor 604 differs depending on the control target, but when the control target is a train, it drives wheels, when it is factory equipment, it drives a pump or various power sources, and when it is a home appliance, it drives a compressor or the like. It is a three-phase AC motor, which is rotationally driven by a three-phase AC voltage output from the inverter 604, and transmits the rotational driving force to a drive target (not shown).
  • the inverter 604 is no longer required for the control system 600, and as shown in FIG. 7, a DC voltage is supplied from the AC / DC converter 602 to the drive target.
  • a DC voltage of 3.3 V is supplied to a personal computer or the like, and a DC voltage of 5 V is supplied to an LED lighting device or the like.
  • the drive control unit 606 uses various sensors (not shown), measured values such as the rotation speed and torque of the drive target, the temperature and flow rate of the surrounding environment of the drive target, etc. to measure these measurement signals, and these measurement signals are input to the drive control unit 606. At the same time, the output voltage value of the inverter 604 is also input to the drive control unit 606. Based on these measurement signals, the drive control unit 606 gives a feedback signal to the inverter 604 and controls the switching operation by the switching element. As a result, the AC voltage applied to the motor 605 by the inverter 604 is instantaneously corrected, so that the operation control of the drive target can be accurately executed, and the stable operation of the drive target is realized. Further, as described above, when the drive target can be driven by a DC voltage, it is also possible to perform feedback control of the AC / DC converter 602 instead of the feedback to the inverter.
  • FIG. 8 shows the circuit configuration of FIG. 7.
  • the semiconductor device of the present invention is used for switching control by being adopted in an AC / DC converter 602 and an inverter 604, for example, as a Schottky barrier diode.
  • an AC / DC converter 602 for example, a Schottky barrier diode having a circuit configuration in a bridge shape is used, and DC conversion is performed by converting and rectifying the negative voltage component of the input voltage to a positive voltage.
  • the inverter 604 is incorporated in the switching circuit of the IGBT to perform switching control.
  • An inductor (coil, etc.) is interposed between the three-phase AC power supply 601 and the AC / DC converter 602 to stabilize the current, and a capacitor (electrolytic capacitor) is placed between the AC / DC converter 602 and the inverter 604. Etc.) are intervened to stabilize the voltage.
  • a calculation unit 607 composed of a CPU and a storage unit 608 composed of a non-volatile memory are provided in the drive control unit 606.
  • the signal input to the drive control unit 606 is given to the calculation unit 607, and a feedback signal for each semiconductor device is generated by performing necessary calculations.
  • the storage unit 608 temporarily holds the calculation result by the calculation unit 607, stores physical constants and functions required for drive control in the form of a table, and appropriately outputs them to the calculation unit 607.
  • a known configuration can be adopted for the calculation unit 607 and the storage unit 608, and the processing capacity thereof and the like can be arbitrarily selected.
  • the rectifying operation and switching operation of the AC / DC converter 602 and the inverter 604 are performed by a diode, a thyristor which is a switching element, and a power transistor.
  • IGBT, MOSFET and the like are used.
  • gallium oxide (Ga 2 O 3 ), particularly corundum type gallium oxide ( ⁇ -Ga 2 O 3 ), as the material for these semiconductor devices the switching characteristics are improved. Further, by applying the semiconductor film or the semiconductor device according to the present invention, extremely good switching characteristics can be expected, and further miniaturization and cost reduction of the control system 600 can be realized.
  • each of the AC / DC converter 602 and the inverter 604 can be expected to have the effect of the present invention, and the effect of the present invention can be expected in any one or combination of these, or in any form including the drive control unit 606. Can be expected.
  • the motor 605 is illustrated as a drive target in FIGS. 7 and 8, the drive target is not necessarily limited to those that operate mechanically, and many devices that require an AC voltage can be targeted.
  • the control system 600 it can be applied as long as the drive target is driven by inputting power from an AC power source, and infrastructure equipment (for example, power equipment such as buildings and factories, communication equipment, traffic control equipment, water and sewage treatment). It can be installed for drive control of equipment such as equipment, system equipment, labor-saving equipment, trains, and home appliances (for example, refrigerators, washing machines, personal computers, LED lighting equipment, video equipment, audio equipment, etc.). can.
  • the semiconductor device of the present invention is useful for a power semiconductor device including a trench structure. Further, in the embodiment of the present invention, it has a structure capable of effectively suppressing the injection of holes into the gate insulating film, and is useful for a power semiconductor device or a system or equipment having a power semiconductor device.

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  • Thin Film Transistor (AREA)

Abstract

Un objet de la présente invention est de proposer une structure pour empêcher l'injection de trous dans un film d'isolation de grille. Ce dispositif à semi-conducteur comprend un film d'isolation de grille, une couche de blocage de trous disposée en contact avec le film d'isolation de grille, et une couche d'oxyde semi-conducteur disposée en contact avec la couche de blocage de trous, la couche de blocage de trous étant disposée entre le film isolant de grille et la couche d'oxyde semi-conducteur.
PCT/JP2021/045616 2020-12-11 2021-12-10 Dispositif à semi-conducteur Ceased WO2022124404A1 (fr)

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JP2022568351A JPWO2022124404A1 (fr) 2020-12-11 2021-12-10
EP21903500.3A EP4261892A4 (fr) 2020-12-11 2021-12-10 Dispositif à semi-conducteur
CN202180083250.4A CN116583955A (zh) 2020-12-11 2021-12-10 半导体装置
US18/207,912 US20230335581A1 (en) 2020-12-11 2023-06-09 Semiconductor device

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WO2013035843A1 (fr) 2011-09-08 2013-03-14 株式会社タムラ製作所 ÉLÉMENT SEMI-CONDUCTEUR DE Ga2O3
WO2014050793A1 (fr) 2012-09-28 2014-04-03 Ｒｏｃａ株式会社 Dispositif à semi-conducteur ou cristal semi-conducteur, et procédé de production d'un dispositif à semi-conducteur ou d'un cristal semi-conducteur
JP2019021753A (ja) * 2017-07-14 2019-02-07 トヨタ自動車株式会社 ゲートスイッチング素子とその製造方法
WO2019098296A1 (fr) * 2017-11-15 2019-05-23 株式会社Flosfia Dispositif à semi-conducteur
JP2020035928A (ja) * 2018-08-30 2020-03-05 富士電機株式会社 窒化ガリウム系半導体装置および窒化ガリウム系半導体装置の製造方法

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JP2020035928A (ja) * 2018-08-30 2020-03-05 富士電機株式会社 窒化ガリウム系半導体装置および窒化ガリウム系半導体装置の製造方法

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See also references of EP4261892A4

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EP4261892A4 (fr) 2024-12-04
TW202230810A (zh) 2022-08-01
EP4261892A1 (fr) 2023-10-18
JPWO2022124404A1 (fr) 2022-06-16
US20230335581A1 (en) 2023-10-19
CN116583955A (zh) 2023-08-11

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