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WO2019111095A1 - Matériau semi-conducteur et dispositif à semi-conducteur - Google Patents

Matériau semi-conducteur et dispositif à semi-conducteur Download PDF

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Publication number
WO2019111095A1
WO2019111095A1 PCT/IB2018/059319 IB2018059319W WO2019111095A1 WO 2019111095 A1 WO2019111095 A1 WO 2019111095A1 IB 2018059319 W IB2018059319 W IB 2018059319W WO 2019111095 A1 WO2019111095 A1 WO 2019111095A1
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Prior art keywords
oxide
insulator
conductor
transistor
film
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English (en)
Japanese (ja)
Inventor
山崎舜平
馬場晴之
本田龍之介
奥野直樹
三本菅正太
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Semiconductor Energy Laboratory Co Ltd
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Semiconductor Energy Laboratory Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/70—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the floating gate being an electrode shared by two or more components
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/68—Floating-gate IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/69—IGFETs having charge trapping gate insulators, e.g. MNOS transistors

Definitions

  • One embodiment of the present invention relates to a semiconductor material and a semiconductor device.
  • a semiconductor device refers to any device that can function by utilizing semiconductor characteristics.
  • a semiconductor circuit such as a transistor, a semiconductor circuit, an arithmetic device, and a memory device are one embodiment of a semiconductor device.
  • Display devices liquid crystal display devices, light emitting display devices, etc.
  • projection devices lighting devices
  • electro-optical devices power storage devices
  • storage devices semiconductor circuits
  • imaging devices electronic devices, and the like may have semiconductor devices in some cases. .
  • one embodiment of the present invention is not limited to the above technical field.
  • One aspect of the invention disclosed in the present specification and the like relates to a product, a method, or a manufacturing method.
  • one aspect of the present invention relates to a process, a machine, a manufacture, or a composition (composition of matter).
  • Oxide semiconductor materials are widely known as semiconductor thin films applicable to transistors, but oxide semiconductors are attracting attention as other materials.
  • oxide semiconductor for example, not only single-component metal oxides such as indium oxide and zinc oxide but also multi-component metal oxides are known.
  • oxides of multi-element metals in particular, research on In-Ga-Zn oxide (hereinafter also referred to as IGZO) has been actively conducted.
  • Non-Patent Documents 1 to 3 a c-axis aligned crystalline (CAAC) structure and an nc (nanocrystalline) structure which are neither single crystal nor amorphous are found in an oxide semiconductor (see Non-Patent Documents 1 to 3) ).
  • Non-Patent Document 1 and Non-Patent Document 2 also disclose a technique for manufacturing a transistor using an oxide semiconductor having a CAAC structure.
  • non-patent documents 4 and 5 show that even oxide semiconductors that are less crystalline than the CAAC structure and the nc structure have minute crystals.
  • Non-Patent Document 6 a transistor using IGZO as an active layer has extremely low off-state current (see Non-Patent Document 6), and LSIs and displays utilizing its characteristics have been reported (see Non-Patent Document 7 and Non-Patent Document 8) ).
  • An object of one embodiment of the present invention is to provide a semiconductor device capable of holding data for a long time.
  • An object of one embodiment of the present invention is to provide a semiconductor device including a transistor including an oxide semiconductor, in which electrical characteristics and reliability of the transistor are stable.
  • An object of one embodiment of the present invention is to provide a semiconductor device having favorable electrical characteristics.
  • An object of one embodiment of the present invention is to provide a highly reliable semiconductor device.
  • An object of one embodiment of the present invention is to provide a semiconductor device which can be miniaturized or highly integrated.
  • An object of one embodiment of the present invention is to provide a semiconductor device with high productivity.
  • An object of one embodiment of the present invention is to provide a semiconductor device with high information writing speed.
  • An object of one embodiment of the present invention is to provide a semiconductor device with high design freedom.
  • An object of one embodiment of the present invention is to provide a semiconductor device capable of suppressing power consumption.
  • An object of one embodiment of the present invention is to provide a novel semiconductor device.
  • One embodiment of the present invention relates to a first oxide having a first region, a second region, a third region, a fourth region, and a fifth region, and a first oxide over the first region.
  • a conductor and a second conductor on the second region, a first conductor, and a third conductor on the third region, a second conductor and a fourth region on the fourth region An opening exposing the fourth conductor, the fifth region, the third conductor on the third region, and the fourth conductor on the fourth region, and a first oxide,
  • a first insulator provided to cover the first conductor, the second conductor, the third conductor, and the fourth conductor, a second oxide provided in the opening, and an opening
  • the fifth region comprises the second region and the third region.
  • the second region is disposed between the first region and the fifth region
  • the third region is disposed between the fourth region and
  • the first oxide in the fifth region, the carrier density of 1.0 ⁇ 10 16 [cm -3] or less, Hall mobility is at 12.0 [cm 2 / Vs] or less, When the carrier density is 1.0 ⁇ 10 19 cm ⁇ 3 or more and 3.0 ⁇ 10 19 cm ⁇ 3 or less, the Hall mobility is 20.0 cm 2 / Vs or more.
  • the fifth region of the first oxide is a channel formation region of the transistor, and the operating frequency of the transistor is 100 MHz or more.
  • the second oxide includes In, an element M (M is Al, Ga, Y, or Sn), and Zn.
  • the second oxide includes an element M (M is Al, Ga, Y, or Sn) and Zn.
  • the first oxide includes In, an element M (M is Al, Ga, Y, or Sn), and Zn.
  • a semiconductor device with high information writing speed can be provided.
  • the semiconductor device in a semiconductor device including a transistor including an oxide semiconductor, the semiconductor device can have stable electrical characteristics and reliability of the transistor.
  • a semiconductor device which can be miniaturized or highly integrated can be provided. According to one embodiment of the present invention, a semiconductor device with high design freedom can be provided. According to one embodiment of the present invention, a semiconductor device with high productivity can be provided.
  • a semiconductor device capable of holding data for a long time can be provided.
  • a semiconductor device capable of suppressing power consumption can be provided.
  • a highly reliable semiconductor device can be provided.
  • a semiconductor device having favorable electrical characteristics can be provided.
  • a novel semiconductor device can be provided.
  • FIG. 7A and 7B are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention.
  • FIG. 10 is an enlarged view of a channel formation region of a semiconductor device according to one embodiment of the present invention.
  • FIG. 7 shows electrical characteristics of a transistor of one embodiment of the present invention, and a correlation between data retention time and an operating frequency of a semiconductor device.
  • FIG. 6 shows a correlation between data holding time and an operating frequency of a semiconductor device according to one embodiment of the present invention.
  • 7A to 7D are top views and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • 7A to 7D are top views and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • 7A to 7D are top views and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • 7A to 7D are top views and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • 7A to 7D are top views and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • 7A to 7D are top views and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • 7A to 7D are top views and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • 7A to 7D are top views and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • 7A to 7D are top views and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.
  • 5A and 5B are a schematic view and a block diagram illustrating a configuration example of a memory device according to one embodiment of the present invention.
  • FIG. 18 is a circuit diagram illustrating a configuration example of a memory device according to one embodiment of the present invention.
  • FIG. 7A and 7B are a schematic view and a block diagram of a semiconductor device according to one embodiment of the present invention.
  • FIG. 10 is a schematic view of a memory device according to one embodiment of the present invention.
  • FIG. 7 illustrates an electronic device according to one embodiment of the present invention.
  • 7A and 7B illustrate a carrier concentration and Hall mobility of an oxide semiconductor and a sample structure in one embodiment of the present invention.
  • 13A to 13C illustrate the relationship between carrier concentration and Hall mobility of an oxide semiconductor according to one embodiment of the present invention.
  • a transistor is an element having at least three terminals of a gate, a drain (drain terminal, drain region or drain electrode), and a source (source terminal, source region or source electrode). is there. Then, a region where a channel is formed between the drain and the source (hereinafter, also referred to as a channel formation region) is provided, and current can flow between the drain and the source through the channel formation region. It is a thing. Note that in this specification and the like, a region where a channel is formed refers to a region through which current mainly flows.
  • the functions of the source and the drain may be switched when adopting transistors of different polarities or when the direction of current changes in circuit operation. Therefore, in this specification and the like, the terms “source” and “drain” can be used interchangeably.
  • the term “electrically connected” includes the case where they are connected via "something having an electrical function".
  • the “thing having an electrical function” is not particularly limited as long as it can transmit and receive electrical signals between connection targets.
  • “those having some electrical action” include electrodes, wirings, switching elements such as transistors, resistance elements, inductors, capacitors, elements having various other functions, and the like.
  • the nitrided oxide refers to a compound having a higher content of nitrogen than oxygen.
  • oxynitride refers to a compound having a higher content of oxygen than nitrogen.
  • the content of each element can be measured, for example, using Rutherford Backscattering Spectroscopy (RBS) or the like.
  • the "parallel” means the state by which two straight lines are arrange
  • substantially parallel means the state by which two straight lines are arrange
  • vertical means that two straight lines are arranged at an angle of 80 ° or more and 100 ° or less. Therefore, the case of 85 degrees or more and 95 degrees or less is also included.
  • “substantially perpendicular” refers to a state in which two straight lines are arranged at an angle of 60 ° or more and 120 ° or less.
  • a barrier film is a film having a function of suppressing permeation of impurities such as hydrogen or oxygen, and in the case where the barrier film has conductivity, it is called a conductive barrier film.
  • the normally on characteristic of the transistor means that it is in the on state when there is no application of a potential by the power supply (0 V).
  • the normally-on characteristic of a transistor may be an electrical characteristic in which current (Id) flows between the drain and the source when the voltage (Vg) applied to the gate of the transistor is 0 V.
  • an oxide semiconductor is a type of metal oxide.
  • the metal oxide refers to an oxide having a metal element.
  • the metal oxide may exhibit insulation, semiconductivity, and conductivity depending on the composition and formation method.
  • a metal oxide which exhibits semiconductivity is referred to as a metal oxide semiconductor or an oxide semiconductor (also referred to as an oxide semiconductor or simply an OS).
  • a metal oxide exhibiting an insulating property is referred to as a metal oxide insulator or an oxide insulator.
  • a metal oxide which exhibits conductivity is called a metal oxide conductor or an oxide conductor. That is, a metal oxide used for a channel formation region or the like of a transistor can be called an oxide semiconductor.
  • Embodiment 1 In this embodiment, one embodiment of a semiconductor device is described with reference to FIGS.
  • FIG. 1A, 1B, and 1C are a top view and a cross-sectional view of a transistor 200 and a periphery of the transistor 200 according to one embodiment of the present invention.
  • FIG. 1A is a top view
  • FIG. 1B is a cross-sectional view corresponding to an alternate long and short dash line A1-A2 shown in FIG. 1A
  • FIG. . Note that in the top view of FIG. 1A, some elements are omitted for clarity of the drawing.
  • the semiconductor device of one embodiment of the present invention includes the transistor 200, an insulator 214 functioning as an interlayer film, an insulator 216, an insulator 280, an insulator 282, and an insulator 284.
  • a conductor 246 (a conductor 246a and a conductor 246b) electrically connected to the transistor 200 and functioning as a plug is included.
  • an insulator 247 having a barrier property may be provided between the conductor 246 and the insulator 280.
  • the transistor 200 includes a conductor 260 (conductor 260a and a conductor 260b) functioning as a first gate electrode, a conductor 205 functioning as a second gate electrode, and an insulator functioning as a first gate insulating film.
  • a conductor 240a which functions as one of a source or a drain, a conductor 242a, a conductor 240b which functions as the other of the source or the drain, a conductor 242b, an insulator 274, and an insulator 275 are included.
  • the oxide 230 a metal oxide which functions as an oxide semiconductor (hereinafter, also referred to as an oxide semiconductor) is preferably used.
  • a transistor including an oxide semiconductor has extremely low leak current in a non-conduction state; thus, a semiconductor device with low power consumption can be provided.
  • an oxide semiconductor can be formed by a sputtering method or the like and thus can be used for a transistor included in a highly integrated semiconductor device.
  • an oxide semiconductor used for the oxide 230 b has low mobility in a range of carrier density which is an off region of the transistor (e.g., 1.0 ⁇ 10 16 [cm ⁇ 3 ] or less);
  • the carrier density is increased by the accumulation effect of carriers by the gate electric field in a range of carrier density which is an on region of the transistor (for example, 1.0 ⁇ 10 19 [cm ⁇ 3 ] or more); It is preferable that the mobility also be high.
  • the conductor 242a (conductor 242b) is provided in contact with the top surface and the side surface of the conductor 240a (conductor 240b) and the top surface of the oxide 230b. Note that the film thickness of the conductor 240 is preferably thicker than at least the conductor 242.
  • the side surface of the conductor 242 opposite to the conductor 260 has a substantially vertical shape.
  • the angle formed by the side surface and the bottom surface of the conductor 242 may be 10 ° to 80 °, preferably 30 ° to 60 °.
  • the opposing side surfaces of the conductor 242a and the conductor 242b are not limited to the same planar shape, and may be stepped.
  • FIG. 2 An enlarged view of a channel formation region of the transistor 200 shown in FIG. 1 is shown in FIG.
  • FIG. 2 As shown in FIG. 2, at the bottom of the opening formed in the insulator 280, the insulator 274, and the insulator 275, not only the oxide 230 b but also a part of the top surfaces of the conductor 242 a and the conductor 242 b are exposed. Structure. Further, an oxide 230 c, an insulator 250, and a conductor 260 are embedded in the opening.
  • a distance between the conductor 242 a and the conductor 242 b which is a substantial channel length of the transistor 200 is a channel length L 1.
  • the distance of the opening in the channel length direction is an opening diameter L2.
  • the distance in the channel length direction of the conductor 242a or the conductor 242b extending into the opening is set to the length L3 of the exposed conductor 242.
  • the distance in the channel length direction of the region where the exposed conductor 242a or 242b and the conductor 260 overlap with each other is a length L4 where the conductor 242 and the conductor 260 overlap. Note that in the transistor 200 illustrated in FIG. 2, the distance L4 at which the conductor 242 and the conductor 260 overlap is equal to the total film thickness of the oxide 230 c and the insulator 250 from the length L3 of the exposed conductor 242. Equal to the length.
  • the substantial channel length L1 is shorter than the opening diameter L2.
  • the length L 3 of the exposed conductor 242 is longer than the total film thickness of the oxide 230 c and the insulator 250. It has a length L4 in which the conductor 242 and the conductor 260 overlap.
  • the contribution of the electric field of the conductor 260 also increases in the regions in the vicinity of the conductor 242 a and the conductor 242 b of the oxide 230. That is, the characteristics (also referred to as frequency characteristics) of the on current and the operating frequency of the transistor 200 can be improved. Therefore, improvement in controllability of the transistor due to the gate electric field applied to the conductor 260 can be expected.
  • the semiconductor device in this section is a DRAM using a memory cell of a 1OS transistor / one capacitance element type.
  • a DRAM using a memory cell of a 1OS transistor single capacitive element type is also referred to as a DOSRAM (Dynamic Oxide Semiconductor Random Access Memory). Further, the details of the DOSRAM will be described in a later embodiment.
  • the data holding time of the DOSRAM means the time required for the charge stored in the holding capacity of the DOSRAM to decrease from "the size after data writing" to "a certain size".
  • the above-mentioned “certain size” is taken as the time required for the potential applied to the capacitive element (retention capacity 3.5 fF) included in DOSRAM to drop 0.2 V from the state after data writing.
  • the term “1 hour for holding DOSRAM data” means that the time taken for the potential applied to the capacitor element of the DOSRAM to decrease by 0.2 V from the state after data writing is one hour.
  • the data retention time of the DOSRAM depends on the magnitude of the off leak current of the transistor included in the DOSRAM.
  • Id that is, Icut
  • the data retention time of DOSRAM is inversely proportional to the size of Icut of the transistor included in DOSRAM.
  • Icut can be estimated by extrapolating using the following equation (1) based on the shift value (Vsh) and the subthreshold swing value (S-value).
  • Expression (1) is an expression that holds true assuming that the off-state current of the transistor monotonously decreases in accordance with Svalue obtained by Vg-Id measurement until Vg reaches 0 V.
  • the data retention time of the DOSRAM can be estimated by calculating Vsh and Svalue obtained from the Id-Vg characteristic.
  • the DOSRAM operating frequency is defined as the reciprocal of the data write cycle time of DOSRAM.
  • the data write cycle time of the DOSRAM is a parameter set by the charging time of the capacitive element of the DOSRAM.
  • the time equivalent to 40% of the data write cycle time (the reciprocal of the DOSRAM operating frequency) of the DOSRAM is set as the charging time of the capacitive element of the DOSRAM.
  • the DOSRAM operating frequency depends on the charging time of the capacitive element of the DOSRAM. Therefore, when estimating the DOSRAM operating frequency, it is first necessary to know in advance the charging interval of the capacitive element of the DOSRAM.
  • a state in which a potential of 0.55 V or more is applied to a capacitive element (retention capacity 3.5 fF) of the DOSRAM is defined as a “charged state” of the capacitive element. Therefore, in the present embodiment, the time from when the data write operation of DOSRAM is started to the time the potential applied to the capacitor reaches 0.55 V corresponds to the charging time of the capacitor of the DOSRAM.
  • the charge time t of the capacitive element of the DOSRAM can be expressed by the following equation (3) by modifying the equation (2).
  • the state in which the potential applied to the capacitive element with the storage capacity of 3.5 fF is 0.55 V or more is defined as the “state in which the capacitive element is charged”. Therefore, by substituting the measured value or the calculated value of the transistor according to one embodiment of the present invention described above to the Cs of the formula (3), 3.5 fF for Cs, +0.55 V for Vcs, the capacitive element included in DOSRAM Charging time t can be calculated.
  • the charging time of the capacitive element of the DOSRAM depends on the size of the Id of the transistor of the DOSRAM at the time of writing the DOSRAM data. That is, the DOSRAM operating frequency can be estimated by acquiring the Id-Vs characteristic.
  • the DOSRAM data write operation is reproduced by actually applying, to the transistor according to one embodiment of the present invention, a potential assumed to be applied to the transistor included in the DOSRAM at the time of writing the DOSRAM data.
  • the Id of the transistor was measured. Specifically, the gate potential Vg of the transistor is fixed to +2.25 V, the drain potential Vd is fixed to +1.08 V, the back gate potential Vbg is arbitrary, and the source potential Vs is swept from 0 V to +0.55 V.
  • the Id measurement of the transistor was performed. The measurement temperature was 27 ° C.
  • samples (Sample 1D to Sample 3D) having different sizes are prepared.
  • the values of the parameters assumed in the calculation using the device simulator the values of the parameters different among the samples 1D to 3D are shown in Table 1.
  • the insulator 250 is assumed to be silicon oxide (SiOx).
  • the oxide 230c is assumed to be a metal oxide (semiconductor).
  • the oxide 230c is assumed to be a metal oxide (insulator).
  • the gate potential can be reduced at the time of operation of the transistor while maintaining the physical thickness.
  • Id-Vg characteristics at a drain voltage Vd of 1.2 V, a back gate voltage Vbg of 0 V, and a temperature of 27 ° C. of Sample 1D are shown in FIG.
  • the horizontal axis is the gate voltage Vg [V]
  • the vertical axis is the drain current Id [A].
  • Icut is calculated from the Id-Vg characteristic shown in FIG. Moreover, Id-Vg characteristic is computed also on sample 2D and sample 3D on the same conditions, and Icut is computed.
  • FIG. 3 (B), 4 (A), and 4 (B) show estimates of data retention time and operating frequency at a power supply voltage of 2.5 V and a temperature of 27 ° C for a DOSRAM having any one of Samples 1D to 3D. Shown in).
  • FIG. 3 (B) is an estimate for DOSRAM with sample 1D
  • FIG. 4 (A) is an estimate for DOSRAM with sample 2D
  • FIG. 4 (B) is an estimate for DOSRAM with sample 3D .
  • the horizontal axis is the data holding time [sec]
  • the vertical axis is the operating frequency [MHz].
  • the data retention time at which the operating frequency is 100 MHz or more may be 10 years or more in the DOSRAM having the sample 3D.
  • the characteristics are favorable.
  • the insulator 214 and the insulator 216 function as interlayer films.
  • An insulator such as TiO 3 (BST) can be used in a single layer or a stack.
  • aluminum oxide, bismuth oxide, germanium oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to these insulators.
  • these insulators may be nitrided.
  • silicon oxide, silicon oxynitride, or silicon nitride may be stacked over the above insulator.
  • the insulator 214 preferably functions as a barrier film which prevents impurities such as water or hydrogen from entering the transistor 200 from the substrate side. Therefore, the insulator 214 preferably uses an insulating material having a function of suppressing diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms (the above-described impurities are less likely to be transmitted). Alternatively, it is preferable to use an insulating material having a function of suppressing the diffusion of oxygen (eg, at least one of oxygen atoms, oxygen molecules, and the like) (the above oxygen is difficult to permeate). Further, for example, aluminum oxide, silicon nitride, or the like may be used as the insulator 214. With this structure, diffusion of impurities such as hydrogen and water from the substrate side to the transistor 200 side with respect to the insulator 214 can be suppressed.
  • an insulating material having a function of suppressing diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper
  • the insulator 216 preferably has a lower dielectric constant than the insulator 214.
  • parasitic capacitance generated between wirings can be reduced.
  • the conductor 260 may function as a first gate (also referred to as a front gate) electrode.
  • the conductor 205 may function as a second gate (also referred to as a back gate) electrode.
  • the threshold voltage of the transistor 200 can be controlled by changing the potential applied to the conductor 205 independently and not in conjunction with the potential applied to the conductor 260.
  • the threshold voltage of the transistor 200 can be greater than 0 V and off current can be reduced. Therefore, when a negative potential is applied to the conductor 205, the drain current when the potential applied to the conductor 260 is 0 V can be smaller than when no potential is applied.
  • the channel formation region can be electrically surrounded by the electric field of the conductor 260 having a function as the first gate electrode and the electric field of the conductor 205 having a function as the second gate electrode.
  • a structure of a transistor which electrically surrounds a channel formation region by an electric field of the first gate electrode and the second gate electrode is referred to as a surrounded channel (S-channel) structure.
  • the conductor 205 is formed to be embedded in the insulator 216.
  • the height of the top surface of the conductor 205 and the height of the top surface of the insulator 216 can be approximately the same.
  • the conductor 205 is illustrated as a single layer, the present invention is not limited to this.
  • the conductor 205 may have a multilayer film structure of two or more layers.
  • an ordinal number may be provided and distinguished in order of formation.
  • the conductor 205 is a single layer; however, the present invention is not limited to this.
  • the conductor 205 may be provided as a stacked structure of two or more layers.
  • the conductor 205 preferably contains a conductive material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms (the above-mentioned impurities are less likely to permeate).
  • a conductive material having a function of suppressing the diffusion of oxygen for example, at least one of oxygen atom, oxygen molecule, and the like
  • the function of suppressing the diffusion of impurities or oxygen is a function of suppressing the diffusion of any one or all of the impurities or the oxygen.
  • the conductor 205 is preferably formed using a highly conductive conductive material containing tungsten, copper, or aluminum as a main component. Further, it is preferable to improve the flatness of the top surface of the conductor 205.
  • the average surface roughness (Ra) of the top surface of the conductor 205 may be 1 nm or less, preferably 0.5 nm or less, more preferably 0.3 nm or less. Accordingly, the planarity of the insulator 224 formed over the conductor 205 can be improved and the crystallinity of the oxide 230 can be improved.
  • the insulator 222 and the insulator 224 function as a second gate insulator.
  • the electrical characteristics of the transistor which is easily changed due to impurities and oxygen vacancies in the oxide semiconductor may be deteriorated in reliability.
  • hydrogen contained in the oxide semiconductor reacts with oxygen bonded to a metal atom to be water, which may form an oxygen vacancy.
  • oxygen vacancies in the oxide semiconductor are preferably reduced as much as possible.
  • the insulator 222 preferably has a barrier property.
  • the insulator 222 functions as a layer which suppresses entry of an impurity such as hydrogen from the peripheral portion of the transistor 200 into the transistor 200.
  • the diffusion of oxygen may be suppressed in an atmosphere at 350 ° C., preferably 400 ° C., as an example of a film having a barrier property.
  • TDS thermal desolation spectroscopy
  • the second film is considered to have a barrier to oxygen.
  • the film may be one in which the release of molecular oxygen (O 2 ) is detected at 2.0 ⁇ 10 14 molecules / cm 2 or less at 600 ° C. or less.
  • the film having the barrier property also suppresses the diffusion of hydrogen.
  • diffusion of hydrogen may be suppressed in an atmosphere at 350 ° C., preferably 400 ° C.
  • the release of hydrogen molecules (H 2 ) is 3.0 at 400 ° C. or less
  • the second film is considered to have a barrier property to hydrogen when it is detected at 10 15 molecules / cm 2 or less.
  • the film may be one in which release of hydrogen molecules (H 2 ) is detected at 1.0 ⁇ 10 15 molecules / cm 2 or less at 400 ° C. or less.
  • the film having the barrier property also suppresses the diffusion of water.
  • the diffusion of water may be suppressed in an atmosphere at 350 ° C., preferably 400 ° C.
  • the release of water molecules (H 2 O) is less than 400 ° C.
  • the second film is considered to have a barrier property to water.
  • the film is one in which the release of water molecules (H 2 O) is detected at 5.0 ⁇ 10 15 molecules / cm 2 or less at 400 ° C. or less.
  • the insulator 222 is, for example, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO 3 ) or It is preferable to use an insulator containing a so-called high-k material such as Ba, Sr) TiO 3 (BST) in a single layer or a laminate. As the miniaturization and higher integration of transistors progress, problems such as leakage current may occur due to thinning of the gate insulator. By using a high-k material for the insulator functioning as a gate insulator, it is possible to reduce the gate potential at the time of transistor operation while maintaining the physical thickness.
  • a so-called high-k material such as Ba, Sr) TiO 3 (BST)
  • an oxide containing oxygen at a higher proportion than oxygen in the stoichiometric composition may be provided in the vicinity of the oxide semiconductor.
  • a region where oxygen is present in excess of the stoichiometric composition (hereinafter, also referred to as an excess oxygen region) is preferably formed.
  • the insulator 224 is preferably an oxide containing oxygen at a higher proportion than the stoichiometric composition. That is, the insulator 224 preferably has a region where oxygen is present in excess of the stoichiometric composition (hereinafter also referred to as an excess oxygen region).
  • an excess oxygen region By providing the insulator having an excess oxygen region in contact with the region where the channel of the oxide 230 is formed, oxygen vacancies in the oxide 230 included in the transistor 200 can be reduced and reliability can be improved.
  • an oxide material from which part of oxygen is released by heating is preferably used as the insulator having an excess oxygen region.
  • the oxide from which oxygen is released by heating means that the amount of released oxygen in terms of molecular oxygen is 1.0 ⁇ 10 18 atoms / cm 3 or more, preferably 3.0 ⁇ 10 20 in TDS analysis. It is an oxide film which is atoms / cm 3 or more.
  • the surface temperature of the film at the time of TDS analysis is preferably in the range of 100 ° C. to 700 ° C., or 100 ° C. to 500 ° C.
  • the insulator 224 is preferably thermally stable.
  • silicon oxide and silicon oxynitride are thermally stable, in the case where a high-k material is used for the insulator 222, a stack which is thermally stable and has a high relative dielectric constant by being combined with the insulator 222 It can be structured.
  • FIG. 1 illustrates a two-layer stack structure as the second gate insulator
  • a single layer or a stack structure of three or more layers may be used.
  • the invention is not limited to the laminated structure made of the same material, but may be a laminated structure made of different materials.
  • the oxide 230 which has a region functioning as a channel formation region includes an oxide 230a, an oxide 230b over the oxide 230a, and an oxide 230c over the oxide 230b.
  • the oxide 230a under the oxide 230b diffusion of impurities from the structure formed below the oxide 230a to the oxide 230b can be suppressed.
  • the oxide 230c over the oxide 230b diffusion of impurities from the structure formed above the oxide 230c to the oxide 230b can be suppressed.
  • the In may diffuse into the insulator 250.
  • the metal In in the insulator 250 traps negative charge and has a high probability of affecting the transistor characteristics and variations thereof, such as a positive shift of the threshold voltage of the transistor and an increase in the S value.
  • the transistor needs a higher driving voltage and low voltage driving becomes difficult. In this case, power consumption of the transistor and an electronic device including the transistor increase. Therefore, an oxide which does not contain In may be used as the oxide 230c in contact with the insulator 250.
  • the energy at the lower end of the conduction band of the oxide 230a and the oxide 230c be higher than the energy at the lower end of the conduction band of the oxide 230b.
  • the electron affinity of the oxide 230a and the oxide 230c is preferably smaller than the electron affinity of the oxide 230b.
  • one embodiment of the present invention is not limited thereto, and the electron affinity of the oxide 230a and the oxide 230c may be approximately the same as the electron affinity of the oxide 230b. That is, the oxide 230a, the oxide 230b, and the oxide 230c may be formed using oxides of the same composition.
  • the energy level at the lower end of the conduction band changes smoothly at the junction of the oxide 230a, the oxide 230b, and the oxide 230c.
  • the energy level at the bottom of the conduction band at the junction of the oxide 230a, the oxide 230b, and the oxide 230c can be said to be continuously changed or connected continuously.
  • the density of defect states in the mixed layer formed at the interface between the oxide 230 a and the oxide 230 b and at the interface between the oxide 230 b and the oxide 230 c may be lowered.
  • oxide 230 a and the oxide 230 b, and the oxide 230 b and the oxide 230 c contain at least one element in common with oxygen, a mixed layer with low density of defect states can be formed.
  • the structures and materials of the oxide 230a, the oxide 230b, and the oxide 230c will be described below.
  • an In-Ga-Zn oxide, a Ga-Zn oxide, or gallium oxide can be used.
  • the number of layers of the oxide 230a may be two or more. Note that in the case where the oxide 230a has a stacked-layer structure, the band gap of the first oxide layer is preferably larger than that of the second oxide layer.
  • the oxide 230a may have a stacked-layer structure of a first oxide layer (referred to as the oxide 230a1) and a second oxide layer (oxide 230a2) over the oxide 230a1.
  • the oxide 230a1 an oxide which does not contain In is preferably used.
  • oxide 230b an In—Ga—Zn oxide can be used.
  • an In-Ga-Zn oxide, a Ga-Zn oxide, or gallium oxide can be used.
  • the number of layers of the oxide 230c may be two or more.
  • the band gap of the second oxide layer is preferably larger than that of the first oxide layer.
  • the oxide 230c may have a stacked-layer structure of a first oxide layer (referred to as oxide 230c1) and a second oxide layer (referred to as oxide 230c2) over the oxide 230c1.
  • oxide 230c1 a first oxide layer
  • oxide 230c2 a second oxide layer
  • a metal oxide of a number ratio], or 3: 1: 2 [atomic number ratio] can be used.
  • the oxide 230a and the oxide 230c preferably have the above-described stacked structure, and in other words, the oxide in contact with the insulator (the insulator 224 or the insulator 250) is In. It can be said that the oxide is not contained.
  • the insulator 224 and the insulator 250 function as gate insulators, and thus when In is diffused, characteristics of the transistor become poor. Therefore, by using an oxide which does not contain In as an oxide in contact with the insulator (the insulator 224 or the insulator 250), a highly reliable semiconductor device can be provided.
  • a main route of carriers is the oxide 230 b.
  • the oxide 230 a and the oxide 230 c into the above-described stacked structure, the density of defect states in the interface between the oxide 230 a and the oxide 230 b and the interface between the oxide 230 b and the oxide 230 c can be reduced. The excellent effect of being able to Therefore, the influence of interface scattering on carrier conduction is reduced, and the transistor 200 can obtain high on current and high frequency characteristics.
  • the present invention is not limited to this. Only one of the oxide 230a and the oxide 230c may have a stacked structure.
  • the oxide 230 c is preferably provided in the opening provided in the insulator 280 via the insulator 274 and the insulator 275.
  • the insulator 274 or the insulator 275 has a barrier property, diffusion of impurities from the insulator 280 into the oxide 230 can be suppressed.
  • the conductor 240 (the conductor 240a and the conductor 240b) and the conductor 242 (the conductor 242a and the conductor 242b) function as a source electrode and a drain electrode.
  • the conductor 240a and the conductor 242a function as a source electrode
  • the conductor 240b and the conductor 242b function as a drain electrode.
  • the conductor 240 and the conductor 242 aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, It is preferable to use a metal element selected from ruthenium, iridium, strontium, lanthanum, or an alloy containing the above-described metal element as a component, or an alloy in which the above-described metal element is combined.
  • tantalum nitride, titanium nitride, tungsten, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, oxide containing lanthanum and nickel, etc. are used. Is preferred.
  • tantalum nitride, titanium nitride, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, oxide containing lanthanum and nickel are difficult to oxidize.
  • metal nitride films such as tantalum nitride are preferable because they have a barrier property to hydrogen or oxygen and have high oxidation resistance.
  • the oxygen concentration of the oxide 230 may be reduced in the vicinity of the conductor 242 of the oxide 230. Further, in a region in the vicinity of the conductor 242 of the oxide 230, a metal compound layer including a metal contained in the conductor 242 and a component of the oxide 230 may be formed. In that case, the carrier density is increased in the region near the conductor 242 of the oxide 230, and the region becomes a low resistance region.
  • conductor 240 and the conductor 242 are illustrated to have a single-layer structure in FIG. 1, a stacked structure of two or more layers may be employed.
  • a barrier layer may be provided over the conductor 242.
  • the barrier layer preferably uses a substance having a barrier property to oxygen or hydrogen.
  • a metal oxide for example, a metal oxide can be used.
  • an insulating film having a barrier property to oxygen or hydrogen such as aluminum oxide, hafnium oxide, or gallium oxide, is preferably used.
  • silicon nitride formed by a CVD method may be used.
  • the range of material selection of the conductor 240 and the conductor 242 can be broadened.
  • a material with low oxidation resistance such as tungsten or aluminum, but high conductivity can be used.
  • a conductor which can be easily formed or processed can be used.
  • the insulator 250 functions as a first gate insulator.
  • the insulator 250 is preferably provided in the opening provided in the insulator 280 through the oxide 230 c, the insulator 274, and the insulator 275.
  • the insulator 250 preferably has a reduced In concentration as much as possible.
  • the insulator 250 may have a stacked structure similarly to the second gate insulator.
  • the insulator that functions as a gate insulator into a stacked structure of a high-k material and a thermally stable material, it is possible to reduce the gate potential during transistor operation while maintaining the physical thickness. It becomes.
  • the equivalent oxide thickness (EOT) of the insulator that functions as a gate insulator it is possible to reduce the equivalent oxide thickness (EOT) of the insulator that functions as a gate insulator.
  • EOT equivalent oxide thickness
  • metal oxide containing one or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, or magnesium as the insulator 250 A thing can be used.
  • a conductor 260 functioning as a first gate electrode includes a conductor 260a and a conductor 260b over the conductor 260a.
  • the conductive material 260 a is preferably a conductive material having a function of suppressing diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms.
  • impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms.
  • the conductor 260a has a function of suppressing the diffusion of oxygen
  • the material selectivity of the conductor 260b can be improved. That is, by including the conductor 260a, oxidation of the conductor 260b can be suppressed, and a decrease in conductivity can be prevented.
  • a conductive material having a function of suppressing the diffusion of oxygen for example, tantalum, tantalum nitride, ruthenium, ruthenium oxide or the like is preferably used.
  • an oxide semiconductor that can be used as the oxide 230 can be used as the conductor 260a.
  • the electric resistance value of the conductor 260a can be reduced to be a conductor. This can be called an OC (Oxide Conductor) electrode.
  • the conductor 260b is preferably formed using a conductive material containing tungsten, copper, or aluminum as a main component.
  • a conductor with high conductivity For example, a conductive material containing tungsten, copper, or aluminum as a main component can be used.
  • the conductor 260b may have a stacked structure, for example, a stack of titanium and titanium nitride and the above conductive material.
  • the insulator 274 and the insulator 275 function as an interlayer film having a barrier property.
  • the insulator 274 preferably functions as a barrier insulating film which suppresses entry of an impurity such as water or hydrogen from the insulator 280 side to the transistor 200 similarly to the insulator 214 and the like.
  • the insulator 274 preferably has lower hydrogen permeability than the insulator 224.
  • the insulator 274 includes the side surface of the oxide 230 c, the top and side surfaces of the conductor 242, the side surface of the conductor 240, the side surfaces of the oxide 230 a and the oxide 230 b, and the top surface of the insulator 224. It is preferable to touch. With this structure, hydrogen contained in the insulator 280 is prevented from entering the oxide 230 from the top surface direction or the side surface direction of the conductor 240, the conductor 242, the oxide 230, and the insulator 224. be able to.
  • the insulator 274 preferably has a function of suppressing the diffusion of oxygen (eg, at least one of oxygen atom, oxygen molecule, and the like) (the above-described oxygen is difficult to transmit).
  • the insulator 274 preferably has lower oxygen permeability than the insulator 280 or the insulator 224.
  • an insulator containing an oxide of one or both of aluminum and hafnium may be deposited.
  • aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like is preferably used as the insulator containing one or both of the oxides of aluminum and hafnium.
  • the insulator 275 preferably functions as a barrier insulating film which suppresses entry of an impurity such as water or hydrogen into the transistor 200 from the insulator 280 side, similarly to the insulator 222 or the like.
  • the insulator 275 preferably has lower hydrogen permeability than the insulator 224.
  • the insulator 275 is preferably disposed in contact with the insulator 274. In the case where the insulator having a barrier property has a stacked structure, hydrogen contained in the insulator 280 can be prevented from entering the oxide 230 from the side direction of the conductor 260, the oxide 230, and the insulator 250. it can.
  • the insulator 280 can be formed by the insulator 274 or the insulator 275. It is separated from the insulator 224, the oxide 230, and the insulator 250. With this structure, entry of an impurity such as hydrogen from the outside of the transistor 200 can be suppressed; thus, the transistor 200 can have favorable electrical characteristics and reliability.
  • the insulator 275 preferably has a function of suppressing the diffusion of oxygen (eg, at least one of oxygen atom, oxygen molecule, and the like) (the above-described oxygen is difficult to transmit).
  • the insulator 275 preferably has lower oxygen permeability than the insulator 224.
  • the insulator 275 has a function of suppressing the diffusion of oxygen, whereby the conductor 260 can be inhibited from reacting with oxygen included in the insulator 280.
  • an insulator containing aluminum nitride may be used.
  • a nitride insulator preferably satisfying the composition formula AlNx (x is a real number greater than 0 and 2 or less, preferably x is a real number greater than 0.5 and 1.5 or less) is preferably used.
  • the nitride insulator can be a film which is excellent in insulation and excellent in thermal conductivity; therefore, the heat dissipation of heat generated when the transistor 200 is driven can be improved.
  • titanium aluminum nitride, titanium nitride, or the like may be used.
  • the film can be formed without using a strong oxidizing gas such as oxygen or ozone as a film forming gas.
  • silicon nitride, silicon nitride oxide, or the like can be used as the insulator 275.
  • an insulator containing an oxide of one or both of aluminum and hafnium may be deposited.
  • aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like is preferably used as the insulator containing one or both of the oxides of aluminum and hafnium.
  • the insulator 275 is preferably deposited using an ALD method. Since the ALD method is a film formation method with good coverage, formation of steps or the like due to the unevenness of the insulator 275 can be prevented.
  • the insulator 280, the insulator 282, and the insulator 284 function as interlayer films.
  • the insulator 280 is provided over the insulator 224, the oxide 230, and the conductor 242 through the insulator 275 and the insulator 274.
  • the insulator 280 may function as a planarization film covering the uneven shape below it. With this structure, the film formability of the insulator 282 is improved. Thus, the insulator 282 can seal the transistor 200 and the insulator 280 without disconnection.
  • the insulator 282 preferably functions as a barrier insulating film which suppresses entry of an impurity such as water or hydrogen into the transistor 200 from the outside, similarly to the insulator 214.
  • the insulator 280 and the insulator 284 preferably have a dielectric constant lower than that of the insulator 282.
  • parasitic capacitance generated between wirings can be reduced.
  • the transistor 200 may be electrically connected to another structure through a plug or a wiring such as the conductor 280 embedded in the insulator 280, the insulator 282, and the insulator 284.
  • a conductive material such as a metal material, an alloy material, a metal nitride material, or a metal oxide material can be used as a single layer or a laminate, similarly to the conductor 205.
  • a high melting point material such as tungsten or molybdenum which achieves both heat resistance and conductivity.
  • it is preferably formed of a low resistance conductive material such as aluminum or copper. Wiring resistance can be lowered by using a low resistance conductive material.
  • the conductivity as a wiring can be increased. While being held, diffusion of impurities from the outside can be suppressed.
  • an insulator 247 having a barrier property may be provided between the conductor 246 and the insulator 280. With the insulator 247, oxygen in the insulator 280 can be reacted with the conductor 246 to suppress oxidation of the conductor 246.
  • the range of material selection of the conductor used for the plug and the wiring can be expanded.
  • materials having low oxidation resistance, such as tungsten and aluminum, but having high conductivity can be used.
  • a conductor which can be easily formed or processed can be used.
  • a semiconductor device having a transistor with high switching characteristics can be provided.
  • a semiconductor device including a transistor including an oxide semiconductor with high mobility when turned on can be provided.
  • a semiconductor device including a transistor including an oxide semiconductor with large on-state current can be provided.
  • a semiconductor device including a transistor including an oxide semiconductor with low off current can be provided.
  • metal oxides As the oxide 230, a metal oxide which functions as an oxide semiconductor (hereinafter, also referred to as an oxide semiconductor) is preferably used. Hereinafter, metal oxides applicable to the oxide 230 according to the present invention will be described.
  • the metal oxide preferably contains at least indium or zinc. In particular, it is preferable to contain indium and zinc. In addition to them, aluminum, gallium, yttrium or tin is preferably contained. In addition, one or more selected from boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium may be included.
  • the metal oxide is an In-M-Zn oxide having indium, an element M and zinc.
  • the element M is aluminum, gallium, yttrium, tin or the like.
  • Other elements applicable to the element M include boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium and the like.
  • the element M a plurality of the aforementioned elements may be combined in some cases.
  • metal oxides having nitrogen may also be collectively referred to as metal oxides.
  • a metal oxide having nitrogen may be referred to as metal oxynitride.
  • Oxide semiconductors can be divided into single crystal oxide semiconductors and other non-single crystal oxide semiconductors.
  • non-single crystal oxide semiconductor for example, c-axis aligned crystalline oxide semiconductor (CAAC-OS), polycrystalline oxide semiconductor, nanocrystalline oxide semiconductor (nc-OS), pseudo amorphous oxide semiconductor (a-like) OS: amorphous-like oxide semiconductor) and amorphous oxide semiconductor.
  • the CAAC-OS has c-axis orientation, and a plurality of nanocrystals are connected in the a-b plane direction to form a strained crystal structure.
  • distortion refers to a portion where the orientation of the lattice arrangement changes between the region in which the lattice arrangement is aligned and the region in which another lattice arrangement is aligned in the region where the plurality of nanocrystals are connected.
  • the nanocrystals are based on hexagons, but may not be regular hexagons and may be non-hexagonal. Moreover, distortion may have a lattice arrangement such as pentagon and heptagon. Note that in the CAAC-OS, it is difficult to confirm clear crystal grain boundaries (also referred to as grain boundaries) even in the vicinity of strain. That is, it is understood that the formation of crystal grain boundaries is suppressed by the distortion of the lattice arrangement. This is because the CAAC-OS can tolerate distortion due to the fact that the arrangement of oxygen atoms is not dense in the a-b plane direction, or that the bonding distance between atoms is changed due to metal element substitution. It is for.
  • a CAAC-OS is a layered crystal in which a layer containing indium and oxygen (hereinafter referred to as In layer) and a layer containing element M, zinc and oxygen (hereinafter referred to as (M, Zn) layer) are stacked. It tends to have a structure (also referred to as a layered structure).
  • In layer a layer containing indium and oxygen
  • M, Zn zinc and oxygen
  • indium and the element M can be substituted with each other, and when the element M in the (M, Zn) layer is replaced with indium, it can also be expressed as a (In, M, Zn) layer.
  • indium in the In layer is substituted with the element M, it can also be represented as an (In, M) layer.
  • CAAC-OS is a highly crystalline metal oxide. On the other hand, it is difficult to confirm clear crystal grain boundaries in CAAC-OS, so it can be said that the decrease in electron mobility due to crystal grain boundaries does not easily occur. In addition, since the crystallinity of metal oxides may be lowered due to the incorporation of impurities or the formation of defects, CAAC-OS is a metal oxide with few impurities or defects (also referred to as oxygen vacancy (V 2 O )). It can be said that it is a thing. Therefore, the metal oxide having a CAAC-OS has stable physical properties. Therefore, a metal oxide having a CAAC-OS is resistant to heat and has high reliability.
  • the nc-OS has periodicity in atomic arrangement in a minute region (eg, a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm).
  • nc-OS has no regularity in crystal orientation among different nanocrystals. Therefore, no orientation can be seen in the entire film. Therefore, the nc-OS may not be distinguished from the a-like OS or the amorphous oxide semiconductor depending on the analysis method.
  • IGZO indium-gallium-zinc oxide
  • IGZO indium-gallium-zinc oxide
  • IGZO may have a stable structure by using the above-mentioned nanocrystals.
  • IGZO tends to be difficult to grow crystals in the atmosphere, so smaller crystals (for example, the above-mentioned nanocrystals) than large crystals (here, crystals of a few mm or crystals of a few cm) But may be structurally stable.
  • the a-like OS is a metal oxide having a structure between nc-OS and an amorphous oxide semiconductor.
  • the a-like OS has a wrinkle or low density region. That is, a-like OS has lower crystallinity than nc-OS and CAAC-OS.
  • Oxide semiconductors have various structures, and each has different characteristics.
  • the oxide semiconductor of one embodiment of the present invention may have two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, an nc-OS, and a CAAC-OS.
  • a thin film with high crystallinity is preferably used as the oxide semiconductor used for the semiconductor of the transistor.
  • the stability or the reliability of the transistor can be improved.
  • the thin film include a thin film of a single crystal oxide semiconductor or a thin film of a polycrystalline oxide semiconductor.
  • a high temperature or laser heating step is required in order to form a thin film of a single crystal oxide semiconductor or a thin film of a polycrystalline oxide semiconductor on a substrate. Thus, the cost of manufacturing increases and the throughput also decreases.
  • CAAC-IGZO In-Ga-Zn oxide
  • nc-IGZO In-Ga-Zn oxide having an nc structure was discovered (see Non-Patent Document 3).
  • nc-IGZO has periodicity in atomic arrangement in a minute area (for example, an area of 1 nm or more and 3 nm or less) and regularity in crystal orientation is not observed between different areas. There is.
  • Non-Patent Document 4 and Non-Patent Document 5 show the transition of the average crystal size by the irradiation of an electron beam to the thin films of the above-described CAAC-IGZO, nc-IGZO, and IGZO with low crystallinity.
  • a low crystalline IGZO thin film crystalline IGZO of about 1 nm has been observed even before electron beam irradiation. Therefore, it is reported here that in IGZO, the presence of a completely amorphous structure could not be confirmed.
  • the thin film of CAAC-IGZO and the thin film of nc-IGZO have high stability to electron beam irradiation as compared with the thin film of IGZO having low crystallinity. Therefore, it is preferable to use a thin film of CAAC-IGZO or a thin film of nc-IGZO as a semiconductor of the transistor.
  • a transistor using an oxide semiconductor has extremely low leak current in a non-conductive state, specifically, an off-state current per ⁇ m channel width of the transistor is on the order of yA / ⁇ m (10 -24 A / ⁇ m).
  • Non-Patent Document 6 For example, a low power consumption CPU or the like to which a characteristic that a leak current of a transistor including an oxide semiconductor is low is applied is disclosed (see Non-Patent Document 7).
  • Non-Patent Document 8 application of a transistor including an oxide semiconductor to a display device utilizing a characteristic that leakage current of the transistor is low has been reported (see Non-Patent Document 8).
  • the displayed image is switched several tens of times per second.
  • the number of times of switching images per second is called a refresh rate.
  • the refresh rate may be referred to as a drive frequency.
  • Such fast screen switching which is difficult for human eyes to perceive, is considered as the cause of eye fatigue. Therefore, it has been proposed to reduce the number of image rewrites by reducing the refresh rate of the display device.
  • power consumption of the display device can be reduced by driving with a lower refresh rate.
  • Such a driving method is called idling stop (IDS) driving.
  • IDS idling stop
  • the discovery of the CAAC structure and the nc structure contributes to the improvement of the electrical characteristics and reliability of a transistor using an oxide semiconductor having a CAAC structure or an nc structure, as well as a reduction in manufacturing cost and an increase in throughput.
  • researches on application of the transistor to a display device and an LSI using the characteristic that the leakage current of the transistor is low have been advanced.
  • FIG. 5 to FIG. 12 shows a top view.
  • (B) in each drawing is a cross-sectional view corresponding to a portion indicated by an alternate long and short dash line A1-A2 illustrated in (A), and is also a cross-sectional view in the channel length direction of the transistor 200.
  • (C) in each drawing is a cross-sectional view corresponding to a portion indicated by dashed dotted line A3-A4 in (A), and is also a cross-sectional view in the channel width direction of the transistor 200.
  • one part element is abbreviate
  • a substrate (not shown) is prepared, and an insulator 214 is formed over the substrate.
  • the film formation of the insulator 214 can be performed by sputtering, chemical vapor deposition (CVD), molecular beam epitaxy (MBE), pulsed laser deposition (PLD), or ALD. This can be performed using an atomic layer deposition (Atomic Layer Deposition) method or the like.
  • the CVD method can be classified into a plasma enhanced CVD (PECVD) method using plasma, a thermal CVD (TCVD: thermal CVD) method using heat, a photo CVD method using light, etc. . Furthermore, it can be divided into metal CVD (MCVD: Metal CVD) and metal organic CVD (MOCVD: Metal Organic CVD) depending on the source gas used.
  • PECVD plasma enhanced CVD
  • TCVD thermal CVD
  • MCVD Metal CVD
  • MOCVD Metal Organic CVD
  • the plasma CVD method provides high quality films at relatively low temperatures.
  • the thermal CVD method is a film formation method capable of reducing plasma damage to an object to be processed because plasma is not used.
  • a wiring, an electrode, an element (such as a transistor or a capacitor), or the like included in a semiconductor device may be charged up by receiving charge from plasma. At this time, wirings, electrodes, elements, and the like included in the semiconductor device may be broken by the stored charge.
  • a thermal CVD method which does not use plasma, such plasma damage does not occur, so that the yield of the semiconductor device can be increased.
  • the thermal CVD method since plasma damage does not occur during film formation, a film with few defects can be obtained.
  • the ALD method is also a film formation method capable of reducing plasma damage to an object to be processed. Further, in the ALD method, since plasma damage does not occur during film formation, a film with few defects can be obtained. Some precursors used in the ALD method include impurities such as carbon. For this reason, the film provided by the ALD method may contain a large amount of impurities such as carbon, as compared with a film provided by another film formation method. In addition, quantification of impurities can be performed using X-ray photoelectron spectroscopy (XPS).
  • XPS X-ray photoelectron spectroscopy
  • the CVD method and the ALD method are film forming methods in which a film is formed by a reaction on the surface of an object to be processed unlike a film forming method in which particles released from a target or the like are deposited. Therefore, the film forming method is less susceptible to the shape of the object to be processed, and has good step coverage.
  • the ALD method since the ALD method has excellent step coverage and uniformity of thickness, it is suitable for coating the surface of an opening with a high aspect ratio.
  • the ALD method may be preferably used in combination with another deposition method such as a CVD method having a high deposition rate.
  • the CVD method and the ALD method can control the composition of the obtained film by the flow rate ratio of the source gas.
  • a film having any composition can be formed depending on the flow rate ratio of the source gas.
  • a film whose composition is continuously changed can be formed by changing the flow ratio of the source gas while forming the film.
  • a film having a barrier property such as aluminum oxide may be formed by a sputtering method.
  • the insulator 214 may have a multilayer structure.
  • an aluminum oxide film may be formed by a sputtering method, and an aluminum oxide film may be formed by an ALD method over the aluminum oxide.
  • an aluminum oxide film may be formed by an ALD method, and an aluminum oxide film may be formed by a sputtering method over the aluminum oxide.
  • a conductive film to be the conductor 205 is formed over the insulator 214.
  • tungsten may be formed as a conductive film to be the conductor 205.
  • the conductive film to be the conductor 205 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the conductive film to be the conductor 205 can be a multilayer film.
  • a conductive film to be the conductor 205 is processed using a lithography method to form the conductor 205.
  • the resist is exposed through a mask.
  • the exposed area is removed or left using a developer to form a resist mask.
  • the conductor, the semiconductor, the insulator, or the like can be processed into a desired shape by etching through the resist mask.
  • the resist mask may be formed by exposing the resist using KrF excimer laser light, ArF excimer laser light, EUV (Extreme Ultraviolet) light, or the like.
  • a liquid immersion technique may be used in which a liquid (for example, water) is filled and exposed between the substrate and the projection lens.
  • an electron beam or an ion beam may be used instead of the light described above.
  • the mask is unnecessary. Note that for the removal of the resist mask, dry etching such as ashing can be performed, wet etching can be performed, wet etching can be performed after the dry etching, or dry etching can be performed after the wet etching.
  • a hard mask made of an insulator or a conductor may be used instead of the resist mask.
  • an insulating film or a conductive film serving as a hard mask material is formed over the conductive film to be the conductor 205, a resist mask is formed over the conductive film, and the hard mask material is etched.
  • a hard mask can be formed. The etching of the conductive film to be the conductor 205 may be performed after the resist mask is removed, or may be performed with the resist mask left. In the latter case, the resist mask may disappear during etching. The hard mask may be removed by etching after the conductive film to be the conductor 205 is etched. On the other hand, when the material of the hard mask does not affect the post-process or can be used in the post-process, it is not necessary to remove the hard mask.
  • a capacitively coupled plasma (CCP) etching apparatus having a parallel plate electrode can be used as a dry etching apparatus.
  • the capacitive coupling type plasma etching apparatus having a parallel plate type electrode may be configured to apply a high frequency power to one of the parallel plate type electrodes.
  • a plurality of different high frequency power supplies may be applied to one of the parallel plate electrodes.
  • a high frequency power supply of the same frequency may be applied to each of the parallel plate electrodes.
  • high-frequency power supplies having different frequencies may be applied to the parallel plate electrodes.
  • a dry etching apparatus having a high density plasma source can be used.
  • an inductively coupled plasma (ICP) etching apparatus can be used as a dry etching apparatus having a high density plasma source.
  • an insulating film to be the insulator 216 is formed over the conductor 214 and the conductor 205.
  • silicon oxide may be deposited by a CVD method.
  • the insulator to be the insulator 216 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the thickness of the insulating film to be the insulator 216 is equal to or larger than that of the conductor 205. For example, when the thickness of the conductor 205 is 1, the thickness of the insulating film to be the insulator 216 is 1 or more and 3 or less.
  • a CMP (Chemical Mechanical Polishing) process is performed on the insulating film to be the insulator 216, so that part of the insulating film to be the insulator 216 is removed and the surface of the conductor 205 is exposed. Accordingly, the conductor 205 and the insulator 216 whose top surface is flat can be formed (see FIG. 5).
  • the conductor 205 may be embedded in the insulator 216 to form a wiring layer including the conductor 205.
  • an opening reaching the insulator 214 is formed in the insulator 216.
  • the openings include, for example, grooves and slits.
  • the region in which the opening is formed may be referred to as an opening.
  • the formation of the opening may use wet etching, it is preferable to use dry etching for fine processing.
  • the insulator 214 it is preferable to select an insulator that functions as an etching stopper film when etching the insulator 216 to form a groove.
  • a silicon oxide film is used as the insulator 216 which forms a groove
  • a silicon nitride film, an aluminum oxide film, or a hafnium oxide film may be used as the insulator 214.
  • a conductive film to be the conductor 205 is formed. It is desirable that the conductive film contains a non-oxidizable material. For example, tantalum nitride, tungsten nitride, titanium nitride, or the like can be used. Alternatively, a stacked film of tantalum, tungsten, titanium, molybdenum, aluminum, copper, and a molybdenum-tungsten alloy can be used.
  • the conductive film to be the conductor 205 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the conductive film to be the conductor 205 may have a multilayer structure.
  • tantalum nitride is formed by sputtering and titanium nitride is stacked over the tantalum nitride.
  • a conductive film with low resistance such as copper is formed by a plating method, a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. With such a stacked body, even when a metal such as copper is used as a part of the conductor 205, diffusion of the metal from the conductor 205 can be prevented.
  • CMP treatment is performed to remove part of the upper layer of the conductive film to be the conductor 205 and the lower layer of the conductive film to be the conductor 205, thereby exposing the insulator 216.
  • the conductive film to be the conductor 205 remains only in the opening.
  • the conductor 205 can be formed with a flat top surface.
  • part of the insulator 216 may be removed by the CMP treatment. From the above, a wiring layer including the conductor 205 can be formed.
  • the conductive film to be the conductor 205 preferably contains a conductive material having a function of suppressing permeation of oxygen.
  • tantalum nitride may be formed by a sputtering method
  • titanium nitride may be formed by a CVD method
  • tungsten may be formed over the titanium nitride by a CVD method.
  • the insulator 222 and the insulator 224 are formed over the insulator 216 and the conductor 205.
  • the insulator 222 and the insulator 224 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the insulator 222 and the insulator 224 may function as a gate insulator, a stacked structure of a material with high heat resistance such as silicon oxide and a material with a high dielectric constant may be used.
  • silicon oxide may be used.
  • the insulator 222 an insulator containing an oxide of one or both of aluminum and hafnium may be formed. Note that aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like is preferably used as the insulator containing one or both of the oxides of aluminum and hafnium.
  • an insulator including an oxide of one or both of aluminum and hafnium has a barrier property to oxygen, hydrogen, and water.
  • the insulator 222 has a barrier property to hydrogen and water, diffusion of hydrogen and water contained in a structure provided in the periphery of the transistor 200 to the inside of the transistor 200 through the insulator 222 is suppressed. , And the formation of oxygen vacancies in the oxide 230 can be suppressed.
  • heat treatment is preferably performed.
  • the heat treatment may be performed at 250 ° C. to 650 ° C., preferably 300 ° C. to 500 ° C., more preferably 320 ° C. to 450 ° C.
  • the heat treatment is performed in a nitrogen or inert gas atmosphere or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. Further, the heat treatment may be performed under reduced pressure.
  • the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas in order to compensate for desorbed oxygen. Good.
  • the heat treatment after forming the insulator 224, treatment is performed at a temperature of 400 ° C. for one hour in a nitrogen atmosphere.
  • impurities such as water and hydrogen contained in the insulator 224 can be removed, and the like.
  • heat treatment can also be performed at each timing after film formation of the insulator 222.
  • the heat treatment uses the heat treatment conditions described above.
  • plasma treatment including oxygen may be performed on the insulator 224 in a reduced pressure state.
  • a device having a power supply for generating high density plasma using microwaves is preferably used.
  • the substrate side may have a power supply for applying an RF (Radio Frequency).
  • plasma treatment including oxygen may be performed. Note that impurities such as water and hydrogen contained in the insulator 224 can be removed by appropriately selecting the conditions of the plasma treatment. In that case, the heat treatment may not be performed.
  • a conductive film to be the oxide film 230A, the oxide film 230B, and the conductive film 240A is sequentially formed over the insulator 224.
  • the conductive film to be the oxide film 230A, the oxide film 230B, and the conductor 240 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the oxide film 230B can be formed, for example, by sputtering.
  • an oxygen gas, a mixed gas of oxygen and a rare gas, a mixed gas of oxygen and nitrogen, or a mixed gas of oxygen and nitrogen and a noble gas may be used as a sputtering gas.
  • the flow rate of oxygen gas in the sputtering gas is 1, the flow rate of nitrogen gas may be 0.1 or more and 3 or less.
  • the characteristics of the oxide film 230B can be controlled by adjusting the ratio of nitrogen gas to oxygen gas.
  • the above In-M-Zn oxide target can be used.
  • an oxide semiconductor may be selected as appropriate for the oxide film 230A in accordance with the desired characteristics.
  • the same material and a film formation method as the oxide film 230B can be used.
  • the oxide film 230A preferably contains at least one of the metal elements of the oxide film 230B.
  • the oxide film 230A is formed by a sputtering method
  • oxygen or a mixed gas of oxygen and a rare gas may be used as a sputtering gas.
  • oxygen vacancies in the oxide film to be formed can be reduced.
  • the oxide film 230A is formed by sputtering
  • the above In-M-Zn oxide target can be used.
  • Each oxide film may be formed in accordance with characteristics to be obtained for the oxide 230 by appropriately selecting deposition conditions and an atomic ratio.
  • the oxide film is preferably formed continuously without being exposed to the air environment.
  • adhesion of impurities or moisture from the air environment to the oxide film 230A and the oxide film 230B can be prevented. Therefore, generation of defects in the vicinity of the interface between the oxide film 230A and the oxide film 230B can be suppressed and can be kept normal.
  • the conductive film 240A is formed and the oxide film 230B is exposed.
  • the conductive film 240A has a shape having an opening in FIG. 5, the present embodiment is not limited to this.
  • a portion corresponding to a region between the conductor 240a and the conductor 240b may be removed from the conductive film to be the conductive film 240A.
  • the conductive film to be the conductive film 240A may be divided into an island-shaped conductor corresponding to the conductor 240a and an island-shaped conductor corresponding to the conductor 240b.
  • the conductive film to be the conductive film 240A may be processed by a lithography method.
  • dry etching or wet etching can be used for the processing. Machining by dry etching is suitable for micromachining.
  • the conductive film 242A is formed over the oxide film 230B and the conductive film 240A (see FIG. 5).
  • the oxide film 230A, the oxide film 230B, the conductive film 240A, and the conductive film 242A are processed into an island shape, and the oxide 230a, the oxide 230b, the conductor 240 (the conductor 240a and the conductor 240b), and The conductor 242B is formed. Note that in this process, the thickness of a region which does not overlap with the oxide 230a of the insulator 224 may be thin (see FIG. 6).
  • the oxide 230 a, the oxide 230 b, the conductor 240, and the conductor 242 B are formed so that at least part thereof overlaps with the conductor 205.
  • the angle between the side surface of the oxide 230 a and the side surface of the oxide 230 b and the top surface of the insulator 222 may be low.
  • the angle between the side surface of the oxide 230a and the side surface of the oxide 230b and the top surface of the insulator 222 is preferably 60 ° to less than 70 °.
  • the side surfaces of the oxide 230 a, the oxide 230 b, the conductor 240, and the conductor 242 B may be approximately perpendicular to the top surface of the insulator 222.
  • the oxide 230 a, the oxide 230 b, the conductor 240, and the side surface of the conductor 242 B are approximately perpendicular to the top surface of the insulator 222, whereby the area is reduced and the density is increased.
  • a curved surface is provided at a portion where the side surface of the conductor 242B and the upper surface of the conductor 242B are continuous. That is, the end of the side surface and the end of the top surface are preferably curved (also referred to as round shape).
  • the curved surface has, for example, a radius of curvature of 3 nm or more and 10 nm or less, preferably 5 nm or more and 6 nm or less at an end portion of the conductor 242B.
  • oxide film 230A, the oxide film 230B, the conductive film 240A, and the conductive film 242A may be processed by a lithography method.
  • dry etching or wet etching can be used for the processing. Machining by dry etching is suitable for micromachining.
  • an impurity due to an etching gas or the like may be attached or diffused to the surface or the inside of the oxide 230a, the oxide 230b, or the like.
  • the impurities include, for example, fluorine or chlorine.
  • Washing may be performed to remove the above-described impurities and the like.
  • the cleaning method may be wet cleaning using a cleaning solution or the like, plasma treatment using plasma, or cleaning by heat treatment, and the above cleaning may be combined as appropriate.
  • cleaning treatment may be performed using an aqueous solution prepared by diluting oxalic acid, phosphoric acid, hydrofluoric acid, or the like with carbonated water or pure water.
  • ultrasonic cleaning may be performed using pure water or carbonated water. In this embodiment, ultrasonic cleaning using pure water or carbonated water is performed.
  • heat treatment may be performed.
  • the heat treatment conditions the above-described heat treatment conditions can be used.
  • a dummy gate film to be the dummy gate 262A is formed over the insulator 224, the oxide 230a, the oxide 230b, the conductor 240, and the conductor 242B.
  • the dummy gate is a temporary gate electrode. That is, by processing the dummy gate film to be the dummy gate 262A, a temporary gate electrode is formed, the dummy gate is removed in a later step, and a gate electrode made of a conductive film or the like is formed instead. Therefore, it is preferable to use a film that is easy to be finely processed and easily removed from the dummy gate film to be the dummy gate 262A.
  • the dummy gate film to be the dummy gate 262A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • a sputtering method a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • an insulator, a semiconductor, or a conductor can be used.
  • polysilicon, silicon such as microcrystalline silicon or amorphous silicon, or a metal film such as aluminum, titanium, or tungsten may be used.
  • the resin film may be formed using a coating method.
  • the dummy gate film to be the dummy gate 262A can be a multilayer film using different film types.
  • the dummy gate film to be the dummy gate 262A can be a conductive film and a two-layer film in which a resin film is formed over the conductive film.
  • the conductive film may function as a stopper film for CMP treatment in a later CMP step.
  • the end point detection of the CMP process may be possible, and the process variation may be reduced.
  • the dummy gate film to be the dummy gate 262A is etched by the lithography method to form the dummy gate 262A.
  • the dummy gate 262A is formed to at least partially overlap with the conductor 205 and the oxide 230a and the oxide 230b.
  • an insulating film 274A and an insulating film 275A are formed to cover the oxide 230a, the oxide 230b, the conductor 240, the conductive film 242A, and the dummy gate 262A (see FIG. 7).
  • the insulating film 274A and the insulating film 275A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the insulating film 275A aluminum oxide may be formed while the substrate is heated at high temperature.
  • the substrate heating temperature at the time of forming the insulating film 275A may be 200 ° C. or higher, preferably 250 ° C. or higher, more preferably 350 ° C. or higher.
  • the dummy gate 262A it is possible to prevent the dummy gate 262A from being deformed when the insulating film 275A is formed at the above temperature.
  • the insulating film 275A is preferably formed by sputtering.
  • the insulator 224 and the insulating film 275A overlap with each other through the insulating film 274A by forming the insulating film 275A by a sputtering method in an atmosphere containing oxygen.
  • Oxygen can be added near the region.
  • the thickness of the insulating film 274A may be 0.5 nm or more and 2.0 nm or less.
  • part of oxygen contained in the sputtering gas may be supplied to a deposition target. That is, at the time of film formation by sputtering, ions and sputtered particles are present between the target and the substrate.
  • the target is connected to a power supply and given a potential E0.
  • the substrate is given a potential E1 such as a ground potential.
  • the substrate may be electrically floating.
  • Ions in the plasma are accelerated by the potential difference E2-E0 and collide with the target to repel particles sputtered from the target.
  • the sputtered particles adhere to and deposit on the film formation surface to form a film.
  • some ions may be recoiled by the target, and may be taken into the insulator 224 below the formed film through the film formed as recoil ions.
  • ions in the plasma are accelerated by the potential difference E2-E1 and strike the film formation surface. At this time, some ions of the ions reach the inside of the insulator 224.
  • a region into which the ions are taken is formed in the insulator 224. That is, when the ions are ions including oxygen, an excess oxygen region is formed in the insulator 224.
  • an excess oxygen region can be formed. Excess oxygen in the insulator 224 can be supplied to the oxide 230 to compensate for oxygen vacancies in the oxide 230.
  • a region having excess oxygen can be formed in the insulator 224 at the same time as the insulating film 275A is formed. Note that as the amount of oxygen contained in the sputtering gas increases, the amount of oxygen supplied to the insulator 224 also increases. Further, part of oxygen supplied to the insulator 224 reacts with hydrogen remaining in the insulator 224 to be water, and is released from the insulator 224 by heat treatment to be performed later. Therefore, the hydrogen concentration in the insulator 224 can be reduced.
  • oxygen can be supplied to the oxide 230 from the excess oxygen region provided in the insulator 224.
  • the insulator 274 has a function of suppressing the diffusion of oxygen upward, whereby oxygen can be prevented from diffusing from the oxide 230 to the insulator 280.
  • the insulator 222 has a function of suppressing diffusion of oxygen downward, whereby oxygen can be prevented from diffusing from the oxide 230 to the substrate side.
  • oxygen is supplied to the channel formation region of the oxide 230.
  • oxygen vacancies in the oxide 230 can be reduced and normally on conversion of the transistor can be suppressed.
  • addition of fluorine may be performed after formation of one or both of the insulating film 275A and the insulating film 274A.
  • the addition of fluorine to one or both of the insulating films 275A and 274A is performed by plasma treatment in an atmosphere containing a fluorine-based gas (eg, CF 4 or the like), or by doping a gas containing fluorine ,It can be carried out.
  • a fluorine-based gas eg, CF 4 or the like
  • doping a gas containing fluorine ,It can be carried out.
  • an insulating film to be the insulator 280 is formed over the insulating film 275A.
  • the insulating film to be the insulator 280 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • portions of the insulating film to be the insulator 280, the dummy gate 262A, the insulating film 274A, and the insulating film 275A are removed until a portion of the dummy gate 262A is exposed, and the insulator 280, the dummy gate 262B, and the insulating Form body 274 and insulator 275 (see FIG. 8).
  • CMP is preferably used to form the insulator 280, the dummy gate 262B, the insulator 274, and the insulator 275.
  • the conductive film may function as a stopper film for CMP processing in the CMP step. is there.
  • the conductive film may be able to detect the end point of the CMP process, and may reduce the variation in height of the dummy gate 262A.
  • the top surface of the dummy gate 262B substantially coincides with the top surfaces of the insulator 274, the insulator 275 and the insulator 280.
  • the dummy gate 262B is removed to form an opening 262 (see FIG. 9).
  • the removal of the dummy gate 262B can be performed using wet etching, dry etching, ashing, or the like. Alternatively, a plurality of the above processes may be combined as appropriate. For example, a wet etching process may be performed after the ashing process.
  • a dummy film 263A is formed over the insulator 280, the insulator 275, the insulator 274, and the conductor 242B (see FIG. 9).
  • the dummy film 263A needs to be formed on the side wall of the opening 262, and the thickness of the dummy film determines the distance between the conductor 242a and the conductor 242b, that is, the substantial channel length L1. For this reason, it is preferable to form the dummy film 263A using the ALD method, which has high coverage and can easily make fine adjustment of the film thickness.
  • the thickness of the dummy film 263A may be set as appropriate in accordance with the electrical characteristics required of the transistor 200. For example, the channel length can be substantially reduced by 10 nm by setting the film thickness to 5 nm. Note that since the dummy film 263A is finally removed, it is preferable to use a film that is easy to microprocess and easy to remove.
  • the dummy film 263A is anisotropically etched to leave only a portion in contact with the sidewall of the opening 262 of the dummy film 263A, thereby forming the dummy film 263B.
  • the conductor 242B is etched to form a conductor 242a and a conductor 242b (see FIG. 10). The etching of the dummy film 263B and the etching of the conductor 242B may be performed continuously.
  • part of the top surface of the oxide 230 b exposed from between the conductor 242 a and the conductor 242 b may be removed.
  • the conductor 242 a and the conductor 242 b are formed using the remaining dummy film 263 B as a mask.
  • the openings 262 formed in the insulator 280, the insulator 275, and the insulator 274 overlap with the region between the conductor 242a and the conductor 242b.
  • the conductor 260 can be disposed between the conductor 242a and the conductor 242b in a self-aligned manner in a later step.
  • the remaining dummy film 263B is selectively removed using isotropic etching to form an opening 263 where the oxide 230b is exposed (see FIG. 11).
  • isotropic etching for example, wet etching or etching using a reactive gas may be used.
  • the distance between the conductor 242a and the conductor 242b can be shorter than the length of the opening 262 in the channel length direction.
  • an oxide film 230C is formed (see FIG. 12).
  • the oxide film 230C can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the oxide film to be the oxide film 230C may be formed using the same film formation method as the oxide film 230A or the oxide film 230B in accordance with the characteristics required for the oxide film 230C.
  • the insulating film 250A is formed (see FIG. 12).
  • the insulating film 250A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • a silicon oxynitride film is preferably formed by a CVD method.
  • the film formation temperature at the time of forming the insulating film 250A is preferably 350 ° C. or more and less than 450 ° C., particularly about 400 ° C. By forming the insulating film 250A at 400 ° C., an insulator with few impurities can be formed.
  • heat treatment or plasma treatment may be performed.
  • the above-described heat treatment conditions can be used.
  • the water concentration and the hydrogen concentration of the insulating film 250A can be reduced.
  • the conductive film 260A and the conductive film 260B are formed (see FIG. 12).
  • the conductive film 260A and the conductive film 260B can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • the conductive film 260A is formed by an ALD method
  • the conductive film 260B is formed by a CVD method.
  • the oxide film 230C, the insulator 250, and the conductor 260 are polished by polishing the oxide film 230C, the insulating film 250A, the conductive film 260A, and the conductive film 260B until the insulator 280 is exposed. And the conductor 260b) (see FIG. 13).
  • the conductor 260 is formed to be embedded in the opening 263 and the region between the conductor 242a and the conductor 242b.
  • the arrangement of the conductor 260, the conductor 242a, and the conductor 242b is selected in a self-aligned manner with respect to the opening of the insulator 280. That is, in the transistor 200, the gate electrode can be arranged between the source electrode and the drain electrode in a self-aligned manner.
  • the conductor 260 can be formed without providing a positioning margin, so that the area occupied by the transistor 200 can be reduced.
  • the semiconductor device can be miniaturized and highly integrated.
  • the insulator 282 and the insulator 284 are formed over the insulator 280 (see FIG. 13).
  • the insulator 282 and the insulator 284 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • an aluminum oxide film is preferably formed by, for example, a sputtering method.
  • a sputtering method By depositing an aluminum oxide film by sputtering, diffusion of hydrogen contained in a structure formed over the insulator 282, for example, the insulator 284 may be suppressed in some cases.
  • an opening which reaches the conductor 242 a and the conductor 242 b is formed in the insulator 274, the insulator 275, the insulator 280, the insulator 282, and the insulator 284.
  • the formation of the opening may be performed using a lithography method.
  • the conductor 240 (the conductor 240a and the conductor 240b) is preferably provided so as to overlap with the conductor 246 (the conductor 246a and the conductor 246b).
  • the insulator 274, the insulator 275, the insulator 280, the insulator 282, and the insulator 284 are etched to form an opening reaching the conductor 242 (in the opening, the conductor 246, and In the insulator 247, the conductor 240 is provided so as to overlap with the bottom of the opening. Therefore, even when the conductor 242 penetrates, the conductor 240 on the oxide 230 b is exposed, which can prevent the oxide 230 b from being over-etched.
  • an insulating film to be the insulator 247 is formed, and the insulating film is anisotropically etched to form the insulator 247.
  • the conductive film can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • an insulating film having a function of suppressing permeation of oxygen is preferably used as the insulating film to be the insulator 247.
  • an aluminum oxide film is preferably formed by an ALD method.
  • anisotropic etching may be performed by, for example, dry etching.
  • a conductive film to be the conductor 246 (the conductor 246a and the conductor 246b) is formed.
  • the conductive film to be the conductor 246 preferably has a stacked structure including a conductor having a function of suppressing permeation of impurities such as water and hydrogen.
  • a stack of tantalum nitride, titanium nitride, or the like, tungsten, molybdenum, copper, or the like can be used.
  • the conductive film to be the conductor 246 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
  • CMP treatment is performed to remove part of the conductive film to be the conductor 246 and expose the insulator 284. As a result, the conductive film can be left only in the opening to form a conductor 246 having a flat top surface (see FIG. 1).
  • the conductor 246 may be formed after the insulator having a barrier property is formed on the side wall portion of the opening.
  • the conductor 246 may be formed after the insulator having a barrier property is formed on the side wall portion of the opening.
  • aluminum oxide By forming aluminum oxide on the side wall portion of the opening, permeation of oxygen from the outside can be suppressed and oxidation of the conductor 246 can be prevented. Further, impurities such as water and hydrogen can be prevented from diffusing from the conductor 246 to the outside.
  • the aluminum oxide can be formed by depositing aluminum oxide in an opening using an ALD method or the like and performing anisotropic etching.
  • a semiconductor device including the transistor 200 illustrated in FIG. 1 can be manufactured.
  • the transistor 200 can be manufactured by using the method for manufacturing a semiconductor device described in this embodiment.
  • a transistor using an oxide as a semiconductor (hereinafter, may be referred to as an OS transistor) and a capacitor according to one embodiment of the present invention are applied with reference to FIGS. 14 and 15.
  • a storage device (hereinafter sometimes referred to as an OS memory device) will be described.
  • the OS memory device is a storage device including at least a capacitor and an OS transistor which controls charge and discharge of the capacitor. Since the off-state current of the OS transistor is extremely small, the OS memory device has excellent retention characteristics and can function as a non-volatile memory.
  • FIG. 14A shows an example of the configuration of the OS memory device.
  • the memory device 1400 includes a peripheral circuit 1411 and a memory cell array 1470.
  • the peripheral circuit 1411 includes a row circuit 1420, a column circuit 1430, an output circuit 1440, and a control logic circuit 1460.
  • the column circuit 1430 includes, for example, a column decoder, a precharge circuit, a sense amplifier, and a write circuit.
  • the precharge circuit has a function of precharging the wiring.
  • the sense amplifier has a function of amplifying a data signal read from the memory cell.
  • the wiring is a wiring connected to a memory cell included in the memory cell array 1470, which will be described in detail later.
  • the amplified data signal is output as the data signal RDATA to the outside of the storage device 1400 through the output circuit 1440.
  • the row circuit 1420 includes, for example, a row decoder, a word line driver circuit, and the like, and can select a row to be accessed.
  • the storage device 1400 is externally supplied with a low power supply voltage (VSS), a high power supply voltage (VDD) for the peripheral circuit 1411, and a high power supply voltage (VIL) for the memory cell array 1470 as a power supply voltage. Further, control signals (CE, WE, RE), an address signal ADDR, and a data signal WDATA are input to the storage device 1400 from the outside.
  • the address signal ADDR is input to the row decoder and the column decoder, and WDATA is input to the write circuit.
  • the control logic circuit 1460 processes external input signals (CE, WE, RE) to generate control signals for row decoders and column decoders.
  • CE is a chip enable signal
  • WE is a write enable signal
  • RE is a read enable signal.
  • the signal processed by the control logic circuit 1460 is not limited to this, and another control signal may be input as necessary.
  • Memory cell array 1470 has a plurality of memory cells MC arranged in a matrix and a plurality of wirings.
  • the number of wirings connecting the memory cell array 1470 and the row circuit 1420 is determined by the configuration of the memory cells MC, the number of memory cells MC provided in one column, and the like.
  • the number of wirings connecting the memory cell array 1470 and the column circuit 1430 is determined by the configuration of the memory cells MC, the number of memory cells MC in one row, and the like.
  • FIG. 14A shows an example in which the peripheral circuit 1411 and the memory cell array 1470 are formed on the same plane
  • the present embodiment is not limited to this.
  • the memory cell array 1470 may be provided so as to overlap with part of the peripheral circuit 1411.
  • a sense amplifier may be provided so as to overlap below the memory cell array 1470.
  • [DOSRAM] 15A to 15C show an example of the circuit configuration of a memory cell of a DRAM.
  • a DRAM using a memory cell of a 1OS transistor single capacitive element type may be referred to as a DOSRAM.
  • the memory cell 1471 illustrated in FIG. 15A includes a transistor M1 and a capacitor CA.
  • the transistor M1 has a gate (sometimes referred to as a front gate) and a back gate.
  • the first terminal of the transistor M1 is connected to the first terminal of the capacitive element CA, the second terminal of the transistor M1 is connected to the wiring BIL, the gate of the transistor M1 is connected to the wiring WOL, and the back gate of the transistor M1 Is connected to the wiring BGL.
  • the second terminal of the capacitive element CA is connected to the wiring CAL.
  • the wiring BIL functions as a bit line
  • the wiring WOL functions as a word line.
  • the wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitive element CA. It is preferable to apply a low level potential to the wiring CAL at the time of data writing and reading.
  • the wiring BGL functions as a wiring for applying a potential to the back gate of the transistor M1. By applying an arbitrary potential to the wiring BGL, the threshold voltage of the transistor M1 can be increased or decreased.
  • the memory cell MC is not limited to the memory cell 1471 and can change the circuit configuration.
  • the memory cell MC may have a configuration in which the back gate of the transistor M1 is connected to the wiring WOL instead of the wiring BGL.
  • the memory cell MC may be a memory cell including a single gate transistor, that is, a transistor M1 having no back gate.
  • the transistor 200 can be used as the transistor M1.
  • the leak current of the transistor M1 can be made very low. That is, since the written data can be held for a long time by the transistor M1, the frequency of refresh of the memory cell can be reduced. In addition, the refresh operation of the memory cell can be made unnecessary.
  • the leakage current is very low, multilevel data or analog data can be held in the memory cell 1471, the memory cell 1472, and the memory cell 1473.
  • the bit line when the sense amplifier is provided so as to overlap below the memory cell array 1470, the bit line can be shortened.
  • the bit line capacitance can be reduced, and the storage capacitance of the memory cell can be reduced.
  • [NOSRAM] 15D to 15G show examples of the circuit configuration of a gain cell type memory cell of a two-transistor one-capacitance element.
  • the memory cell 1474 illustrated in FIG. 15D includes a transistor M2, a transistor M3, and a capacitor CB.
  • the transistor M2 has a front gate (sometimes simply referred to as a gate) and a back gate.
  • NOSRAM Nonvolatile Oxide Semiconductor RAM
  • the first terminal of the transistor M2 is connected to the first terminal of the capacitive element CB, the second terminal of the transistor M2 is connected to the wiring WBL, the gate of the transistor M2 is connected to the wiring WOL, and the back gate of the transistor M2 Is connected to the wiring BGL.
  • the second terminal of the capacitive element CB is connected to the wiring CAL.
  • the first terminal of the transistor M3 is connected to the wiring RBL, the second terminal of the transistor M3 is connected to the wiring SL, and the gate of the transistor M3 is connected to the first terminal of the capacitive element CB.
  • the wiring WBL functions as a write bit line
  • the wiring RBL functions as a read bit line
  • the wiring WOL functions as a word line.
  • the wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitive element CB. When writing data, holding data, and reading data, it is preferable to apply a low level potential to the wiring CAL.
  • the wiring BGL functions as a wiring for applying a potential to the back gate of the transistor M2. By applying an arbitrary potential to the wiring BGL, the threshold voltage of the transistor M2 can be increased or decreased.
  • the memory cell MC is not limited to the memory cell 1474, and the configuration of the circuit can be changed as appropriate.
  • the memory cell MC may have a configuration in which the back gate of the transistor M2 is connected to the wiring WOL instead of the wiring BGL.
  • the memory cell MC may be a memory cell including a single gate transistor, that is, a transistor M2 having no back gate.
  • the memory cell MC may have a configuration in which the wiring WBL and the wiring RBL are combined into one wiring BIL.
  • the transistor 200 can be used as the transistor M2.
  • the leakage current of the transistor M2 can be made very low.
  • the frequency of refresh of the memory cell can be reduced.
  • the refresh operation of the memory cell can be made unnecessary.
  • the memory cell 1474 can hold multilevel data or analog data.
  • the transistor M3 may be a transistor having silicon in a channel formation region (hereinafter, may be referred to as a Si transistor).
  • the conductivity type of the Si transistor may be n-channel or p-channel.
  • the Si transistor may have higher field effect mobility than the OS transistor. Therefore, a Si transistor may be used as the transistor M3 functioning as a read out transistor. Further, by using a Si transistor for the transistor M3, the transistor M2 can be provided by being stacked on the transistor M3, so that the area occupied by the memory cell can be reduced and high integration of the memory device can be achieved.
  • the transistor M3 may be an OS transistor.
  • OS transistors are used for the transistors M2 and M3, the memory cell array 1470 can be configured using only n-type transistors.
  • FIG. 15H shows an example of a gain cell type memory cell of three transistors and one capacitance element.
  • the memory cell 1478 illustrated in FIG. 15H includes transistors M4 to M6 and a capacitor CC.
  • the capacitive element CC is appropriately provided.
  • the memory cell 1478 is electrically connected to the wirings BIL, RWL, WWL, BGL, and GNDL.
  • the wiring GNDL is a wiring for applying a low level potential. Note that the memory cell 1478 may be electrically connected to the wirings RBL and WBL instead of the wiring BIL.
  • the transistor M4 is an OS transistor having a back gate, and the back gate is electrically connected to the wiring BGL. Note that the back gate and the gate of the transistor M4 may be electrically connected to each other. Alternatively, the transistor M4 may not have a back gate.
  • the transistors M5 and M6 may be n-channel Si transistors or p-channel Si transistors, respectively.
  • the transistors M4 to M6 may be OS transistors.
  • the memory cell array 1470 can be configured using only n-type transistors.
  • the transistor 200 can be used as the transistor M4.
  • the leak current of the transistor M4 can be made very low.
  • peripheral circuit 1411 and the memory cell array 1470 and the like described in this embodiment are not limited to the above. Arrangements or functions of these circuits and wirings, circuit elements, and the like connected to the circuits may be changed, deleted, or added as needed.
  • FIG. 1200 An example of a chip 1200 on which the semiconductor device of the present invention is mounted is shown using FIG.
  • a plurality of circuits (systems) are mounted on the chip 1200.
  • SoC system on chip
  • the chip 1200 includes a central processing unit (CPU) 1211, a graphics processing unit (GPU) 1212, one or more analog operation units 1213, one or more memory controllers 1214, one or more Interface 1215, one or more network circuits 1216, and the like.
  • CPU central processing unit
  • GPU graphics processing unit
  • analog operation units 1213 one or more analog operation units 1213
  • memory controllers 1214 one or more memory controllers 1214
  • Interface 1215 one or more network circuits 1216, and the like.
  • the chip 1200 is provided with a bump (not shown), and is connected to a first surface of a printed circuit board (PCB) 1201 as shown in FIG. 16B. Further, a plurality of bumps 1202 are provided on the back surface of the first surface of the PCB 1201 and are connected to the motherboard 1203.
  • PCB printed circuit board
  • the motherboard 1203 may be provided with a storage device such as a DRAM 1221 and a flash memory 1222.
  • a storage device such as a DRAM 1221 and a flash memory 1222.
  • the DOS RAM described in the above embodiment can be used for the DRAM 1221.
  • the NOSRAM described in the above embodiment can be used for the flash memory 1222.
  • the CPU 1211 preferably has a plurality of CPU cores.
  • the GPU 1212 preferably has a plurality of GPU cores.
  • the CPU 1211 and the GPU 1212 may each have a memory for temporarily storing data.
  • a memory common to the CPU 1211 and the GPU 1212 may be provided in the chip 1200.
  • the memory the aforementioned NOSRAM or DOSRAM can be used.
  • the GPU 1212 is suitable for parallel calculation of a large number of data, and can be used for image processing and product-sum operation. By providing the image processing circuit and the product-sum operation circuit using the oxide semiconductor of the present invention in the GPU 1212, image processing and product-sum operation can be performed with low power consumption.
  • the wiring between the CPU 1211 and the GPU 1212 can be shortened, and data transfer from the CPU 1211 to the GPU 1212, data transfer between memories of the CPU 1211 and the GPU 1212, And, after the calculation by the GPU 1212, transfer of the calculation result from the GPU 1212 to the CPU 1211 can be performed at high speed.
  • the analog operation unit 1213 includes one or both of an A / D (analog / digital) conversion circuit and a D / A (digital / analog) conversion circuit. Further, the product-sum operation circuit may be provided in the analog operation unit 1213.
  • the memory controller 1214 has a circuit functioning as a controller of the DRAM 1221 and a circuit functioning as an interface of the flash memory 1222.
  • the interface 1215 includes an interface circuit with an external connection device such as a display device, a speaker, a microphone, a camera, and a controller.
  • the controller includes a mouse, a keyboard, a game controller, and the like.
  • USB Universal Serial Bus
  • HDMI registered trademark
  • High-Definition Multimedia Interface or the like can be used.
  • the network circuit 1216 includes a network circuit such as a LAN (Local Area Network). It may also have circuitry for network security.
  • LAN Local Area Network
  • the circuits can be formed in the same manufacturing process. Therefore, even if the number of circuits required for the chip 1200 increases, there is no need to increase the number of manufacturing processes, and the chip 1200 can be manufactured at low cost.
  • the PCB 1201 provided with the chip 1200 having the GPU 1212, the DRAM 1221, and the motherboard 1203 provided with the flash memory 1222 can be referred to as a GPU module 1204.
  • the GPU module 1204 has a chip 1200 using SoC technology, so its size can be reduced. Moreover, since it is excellent in image processing, it is suitable to use for portable electronic devices, such as a smart phone, a tablet terminal, a laptop PC, and a portable (portable) game machine.
  • a deep neural network DNN
  • CNN convolutional neural network
  • RNN recursive neural network
  • DBM deep layer Boltzmann machine
  • the chip 1200 can be used as an AI chip, or the GPU module 1204 can be used as an AI system module because operations such as DBN can be performed.
  • Embodiment 4 application examples of a memory device using the semiconductor device described in the above embodiment will be described.
  • the semiconductor device described in the above embodiment is, for example, a storage device of various electronic devices (for example, an information terminal, a computer, a smartphone, an electronic book terminal, a digital camera (including a video camera), a recording and reproducing device, a navigation system, etc.) Applicable to Here, the computer includes a tablet computer, a notebook computer, a desktop computer, and a large computer such as a server system.
  • the semiconductor device described in the above embodiment is applied to various removable storage devices such as a memory card (for example, an SD card), a USB memory, and an SSD (solid state drive).
  • FIG. 17 schematically shows some configuration examples of the removable storage device.
  • the semiconductor device described in the above embodiment is processed into a packaged memory chip and used for various storage devices and removable memories.
  • FIG. 17A is a schematic view of a USB memory.
  • the USB memory 1100 includes a housing 1101, a cap 1102, a USB connector 1103, and a substrate 1104.
  • the substrate 1104 is housed in a housing 1101.
  • the memory chip 1105 and the controller chip 1106 are attached to the substrate 1104.
  • the semiconductor device described in the above embodiment can be incorporated in the memory chip 1105 or the like of the substrate 1104.
  • FIG. 17 (B) is a schematic view of the appearance of the SD card
  • FIG. 17 (C) is a schematic view of the internal structure of the SD card.
  • the SD card 1110 has a housing 1111, a connector 1112 and a substrate 1113.
  • the substrate 1113 is housed in a housing 1111.
  • the memory chip 1114 and the controller chip 1115 are attached to the substrate 1113.
  • the capacity of the SD card 1110 can be increased.
  • a wireless chip provided with a wireless communication function may be provided over the substrate 1113.
  • data can be read and written from the memory chip 1114 by wireless communication between the host device and the SD card 1110.
  • the semiconductor device described in the above embodiment can be incorporated in the memory chip 1114 or the like of the substrate 1113.
  • FIG. 17D is a schematic view of the appearance of the SSD
  • FIG. 17E is a schematic view of the internal structure of the SSD.
  • the SSD 1150 includes a housing 1151, a connector 1152, and a substrate 1153.
  • the substrate 1153 is housed in a housing 1151.
  • the memory chip 1154, the memory chip 1155, and the controller chip 1156 are attached to the substrate 1153.
  • the memory chip 1155 is a work memory of the controller chip 1156, and for example, a DOSRAM chip may be used.
  • the capacity of the SSD 1150 can be increased.
  • the semiconductor device described in the above embodiment can be incorporated in the memory chip 1154 or the like of the substrate 1153.
  • This embodiment can be implemented in appropriate combination with the structures described in the other embodiments and the like.
  • FIG. 18 illustrates a specific example of an electronic device using the semiconductor device according to one embodiment of the present invention.
  • the monitor 830 is shown in FIG.
  • the monitor 830 includes a display portion 831, a housing 832, a speaker 833, and the like. Furthermore, an LED lamp, an operation key (including a power switch or an operation switch), a connection terminal, various sensors, a microphone, and the like can be included.
  • the monitor 830 can be operated by the remote controller 834.
  • the monitor 830 can also function as a television device by receiving broadcast waves.
  • Examples of broadcast radio waves that can be received by the monitor 830 include ground waves, radio waves transmitted from satellites, and the like. Further, as the airwaves, there are analog broadcasting, digital broadcasting and the like, and also there are broadcasting of video and audio or audio only. For example, broadcast radio waves transmitted in a specific frequency band in the UHF band (300 MHz to 3 GHz) or the VHF band (30 MHz to 300 MHz) can be received. Further, for example, by using a plurality of data received in a plurality of frequency bands, the transfer rate can be increased, and more information can be obtained. Thus, an image having a resolution exceeding full high vision can be displayed on the display portion 831. For example, images having resolutions of 4K-2K, 8K-4K, 16K-8K, or higher can be displayed.
  • a computer network such as the Internet, LAN (Local Area Network), Wi-Fi (registered trademark) or the like It may be At this time, the monitor 830 may not have a tuner.
  • the monitor 830 can be connected to a computer and used as a computer monitor. Further, the monitor 830 connected to the computer can be viewed by a plurality of people simultaneously, and can be used for a conference system. Further, the monitor 830 can be used for a video conference system by displaying information of a computer via a network or connecting the monitor 830 to the network.
  • the monitor 830 can also be used as digital signage.
  • the semiconductor device of one embodiment of the present invention can be used for a driver circuit of a display portion or an image processing portion.
  • the semiconductor device of one embodiment of the present invention for a driver circuit of a display portion or an image processing portion, high-speed operation and signal processing can be realized with low power consumption.
  • image processing such as noise removal processing, gradation conversion processing, color tone correction processing, luminance correction processing, and the like is performed by using an AI system using the semiconductor device of one embodiment of the present invention for the image processing unit of the monitor 830.
  • inter-pixel interpolation processing accompanying resolution up-conversion
  • inter-frame interpolation processing accompanying frame frequency up-conversion.
  • gradation conversion process not only conversion of the number of gradations of an image, but also interpolation of gradation values in the case of increasing the number of gradations can be performed.
  • high dynamic range (HDR) processing which extends the dynamic range, is also included in the tone conversion processing.
  • a video camera 2940 illustrated in FIG. 18B includes a housing 2941, a housing 2942, a display portion 2943, an operation switch 2944, a lens 2945, a connection portion 2946, and the like.
  • the operation switch 2944 and the lens 2945 are provided in the housing 2941
  • the display portion 2943 is provided in the housing 2942.
  • the video camera 2940 includes an antenna, a battery, and the like inside a housing 2941.
  • the housing 2941 and the housing 2942 are connected by the connection portion 2946, and the angle between the housing 2941 and the housing 2942 can be changed by the connection portion 2946.
  • the direction of the image displayed on the display portion 2943 can be changed and the display / non-display of the image can be switched.
  • the semiconductor device of one embodiment of the present invention can be used for a driver circuit of a display portion or an image processing portion.
  • the semiconductor device of one embodiment of the present invention for a driver circuit of a display portion or an image processing portion, high-speed operation and signal processing can be realized with low power consumption.
  • imaging in accordance with the environment around the video camera 2940 can be realized. Specifically, shooting can be performed with the optimal exposure according to the ambient brightness. In addition, high dynamic range (HDR) shooting can be performed in the case of simultaneously shooting a situation with different brightness, such as shooting in back light, indoors and outdoors.
  • HDR high dynamic range
  • the AI system can learn the habit of the photographer and assist the imaging. Specifically, by learning the blurring of the camera shake of the photographer and correcting the camera shake during shooting, it is possible to minimize the disturbance of the image due to the camera shake in the photographed image. In addition, when using the zoom function during shooting, it is possible to control the orientation of the lens so that the subject is always shot at the center of the image.
  • An information terminal 2910 illustrated in FIG. 18C includes a housing 2911, a display portion 2912, a microphone 2917, a speaker portion 2914, a camera 2913, an external connection portion 2916, an operation switch 2915, and the like.
  • the display portion 2912 includes a display panel and a touch screen in which a flexible substrate is used.
  • the information terminal 2910 includes an antenna, a battery, and the like inside the housing 2911.
  • the information terminal 2910 can be used as, for example, a smartphone, a mobile phone, a tablet information terminal, a tablet personal computer, an electronic book reader, or the like.
  • a memory device using the semiconductor device of one embodiment of the present invention can hold control information of the data terminal 2910, a control program, and the like for a long time.
  • image processing such as noise removal processing, tone conversion processing, color tone correction processing, and luminance correction processing is performed. be able to. Further, it is possible to execute inter-pixel interpolation processing accompanying resolution up-conversion and inter-frame interpolation processing accompanying frame frequency up-conversion. Further, in the gradation conversion process, not only conversion of the number of gradations of an image, but also interpolation of gradation values in the case of increasing the number of gradations can be performed. Also, high dynamic range (HDR) processing, which extends the dynamic range, is also included in the tone conversion processing.
  • HDR high dynamic range
  • the AI system can learn the habit of the user and assist the operation of the information terminal 2910.
  • An information terminal 2910 equipped with an AI system can predict touch input from movement of a user's finger, eyes, or the like.
  • a laptop personal computer 2920 illustrated in FIG. 18D includes a housing 2921, a display portion 2922, a keyboard 2923, a pointing device 2924, and the like.
  • the laptop personal computer 2920 includes an antenna, a battery, and the like inside a housing 2921.
  • a memory device using the semiconductor device of one embodiment of the present invention can hold control information of a laptop personal computer 2920, a control program, and the like for a long time.
  • an image such as a noise removal process, a gradation conversion process, a color tone correction process, and a luminance correction process. Processing can be performed. Further, it is possible to execute inter-pixel interpolation processing accompanying resolution up-conversion and inter-frame interpolation processing accompanying frame frequency up-conversion. Further, in the gradation conversion process, not only conversion of the number of gradations of an image, but also interpolation of gradation values in the case of increasing the number of gradations can be performed. Also, high dynamic range (HDR) processing, which extends the dynamic range, is also included in the tone conversion processing.
  • HDR high dynamic range
  • the AI system can learn the habit of the user and assist the operation of the laptop personal computer 2920.
  • a laptop personal computer 2920 equipped with an AI system can predict touch input to the display portion 2922 from movement of a user's finger, eyes, or the like.
  • input prediction is performed from past text input information, and figures such as texts and photographs before and after, and conversion is assisted. This makes it possible to reduce input errors and conversion errors as much as possible.
  • FIG. 18E is an external view showing an example of a car
  • FIG. 18F shows a navigation device 860.
  • the automobile 2980 has a car body 2981, wheels 2982, a dashboard 2983, lights 2984 and the like.
  • the automobile 2980 includes an antenna, a battery, and the like.
  • the navigation device 860 includes a display unit 861, operation buttons 862, and an external input terminal 863.
  • the car 2980 and the navigation device 860 may be independent of each other, but it is preferable that the navigation device 860 be incorporated in the car 2980 and be configured to function in conjunction.
  • a memory device using the semiconductor device of one embodiment of the present invention can hold control information of a vehicle 2980 or a navigation device 860, a control program, and the like for a long time.
  • the AI system learns the driving technology and habit of the driver, and assists safe driving, gasoline, and battery Assist the operation of using fuel efficiently.
  • it comprehensively learns the behavior of the car such as the speed and movement method of the car 2980, road information stored in the navigation device 860, etc.
  • the navigation device 860 can transmit the road information to the car 2980 to control the speed of the car 2980 or assist steering operation.
  • This embodiment can be implemented in appropriate combination with the structures described in the other embodiments and the like.
  • the relationship between the carrier concentration of the oxide semiconductor and the Hall mobility was evaluated. Specifically, Hall effect measurement was performed on a sample on which an oxide semiconductor was deposited, and carrier concentration and Hall mobility were calculated using the results.
  • the Hall effect measurement by applying a magnetic field perpendicular to the current direction to the current flowing, the Hall effect in which an electromotive force appears in a direction perpendicular to both the current and the magnetic field is used. It is a method of measuring electrical properties such as carrier density, mobility and resistivity.
  • the Hall effect measurement was performed using the Van der Pauw method.
  • ResiTest manufactured by Toyo Corporation was used for the measurement of the Hall effect.
  • FIG. 19A shows structures of the samples A1 to A17 and the samples B1 to B17.
  • the samples A1 to A17 and the samples B1 to B17 each include the substrate 900, the oxide semiconductor 902 over the substrate 900, and the oxide semiconductor 904 over the oxide semiconductor 902.
  • a quartz substrate was used as the substrate 900 in the samples A1 to A17 and the samples B1 to B17.
  • an oxide semiconductor 902 was formed to a thickness of 5 nm over the substrate 900 by a sputtering method.
  • the oxide semiconductor 904 was formed to a thickness of 15 nm over the oxide semiconductor 902 by a sputtering method.
  • the pressure was 0.7 Pa
  • the distance between the substrate and the target was 60 nm
  • the DC power supply was 0.5 kW
  • the substrate temperature was 200 ° C.
  • the oxide semiconductor 904 was formed to a thickness of 15 nm over the oxide semiconductor 902 by a sputtering method.
  • heat treatment in a hydrogen atmosphere does not involve heat treatment of sample A1 and sample B1 (RT), sample A2 and sample B2 at 100 ° C., sample A3 and sample B3 at 125 ° C., sample A4, And sample B4 at 150 ° C., sample A5 and sample B5 at 160 ° C., sample A6 and sample B6 at 170 ° C., sample A7 and sample B7 at 180 ° C., sample A8 and sample B8 at 190 ° C., sample A9, And sample B9 at 200 ° C., sample A10 and sample B10 at 225 ° C., sample A11 and sample B11 at 250 ° C., sample A12 and sample B12 at 275 ° C., sample A13 and sample B13 at 300 ° C., sample A14, And sample B14 at 325 ° C, sample A15, and sample B15 at 350 ° C, sample A16, and sample B16 at 375 ° C, sample A1.
  • RT heat treatment of sample A1
  • Samples A1 to A17 and Samples B1 to B17 were manufactured.
  • FIG. 20A shows the transition of the carrier concentration of the oxide semiconductor 904 with respect to the temperature at the time of heat treatment in a hydrogen atmosphere.
  • the horizontal axis represents temperature [° C.] at the time of heat treatment in a hydrogen atmosphere, and the vertical axis represents carrier concentration [cm ⁇ 3 ] of the oxide semiconductor 904.
  • the sample A group was plotted by a black circle, and the sample B group was plotted by a white circle.
  • the carrier concentration of the oxide semiconductor 904 is higher as the temperature at the heat treatment in a hydrogen atmosphere is higher.
  • the carrier concentration of each of the sample group A and the sample group B sharply increased when the temperature of the heat treatment in a hydrogen atmosphere was around 150 ° C. to 200 ° C.
  • the transition of the Hall mobility of the oxide semiconductor 904 with respect to the temperature at the time of heat treatment in a hydrogen atmosphere is shown in FIG.
  • the horizontal axis represents temperature [° C.] at the time of heat treatment in a hydrogen atmosphere
  • the vertical axis represents Hall mobility [cm 2 / Vs] of the oxide semiconductor 904.
  • the sample A group was plotted by a black circle
  • the sample B group was plotted by a white circle.
  • the Hall mobility of the oxide semiconductor 904 is rapidly increased when the temperature in heat treatment in a hydrogen atmosphere is higher than 200 ° C.
  • FIG. 19B illustrates the relationship between the carrier concentration of the oxide semiconductor 904 and the Hall mobility in the sample A group and the sample B group.
  • the sample A group was plotted by a black circle
  • the sample B group was plotted by a white circle.
  • the Hall mobility when the carrier concentration of the oxide semiconductor 904 is high, the Hall mobility also tends to be high.
  • the Hall mobility when the carrier density was 1.0 ⁇ 10 16 [cm ⁇ 3 ] or less, the Hall mobility was 12.0 [cm 2 / Vs] or less.
  • the Hall mobility when the carrier density is 1.0 ⁇ 10 19 cm ⁇ 3 or more and 3.0 ⁇ 10 19 cm 3 or less, the Hall mobility is 20.0 cm 2 / Vs or more. .
  • the donor concentration of the region where the channel is formed is preferably 1.0 ⁇ 10 16 [cm ⁇ 3 ] or less. Further, in the state where the Hall mobility is low, in the operation of turning on the transistor, the carrier concentration of the channel portion becomes high due to the carrier accumulation effect by the electric field generated from the gate electrode. That is, according to the relationship between the carrier concentration and the Hall mobility shown in FIG. 19B, it can be inferred that the mobility of the transistor is improved.
  • the oxide semiconductor of one embodiment of the present invention in the range of the density of carriers in the off region of the transistor (e.g., 1.0 ⁇ 10 16 [cm -3] or less), the mobility is low.
  • an oxide semiconductor of one embodiment of the present invention in the range of the density of carriers in the ON area of the transistor (e.g., 1.0 ⁇ 10 19 [cm -3 ] or more 3.0 ⁇ 10 19 [cm -3] or less
  • the carrier density increases and the mobility also increases due to the carrier accumulation effect by the gate electric field.

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  • Thin Film Transistor (AREA)

Abstract

L'invention concerne un dispositif à semi-conducteur présentant d'excellentes propriétés électriques. Plus particulièrement, l'invention porte sur un transistor utilisant un oxyde semi-conducteur dans la région de formation de canal, la fréquence de fonctionnement du transistor étant supérieure ou égale à 100 [MHz]. Quand la densité de porteurs de charge de l'oxyde semi-conducteur utilisé dans la région de formation de canal est inférieure ou égale à 1.0×1016 [cm-3], la mobilité de Hall est inférieure ou égale à 12.0 [cm2/Vs], et quand la densité de porteurs de charge est comprise entre 1.0×1019 [cm-3] et 3.0×1019 [cm-3], la mobilité de Hall est supérieure ou égale à 20.0 [cm2/Vs].
PCT/IB2018/059319 2017-12-08 2018-11-27 Matériau semi-conducteur et dispositif à semi-conducteur Ceased WO2019111095A1 (fr)

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