WO2019191242A1

WO2019191242A1 - Direct inkjet printing of quadrilateral cross section plated and/or filled vias

Info

Publication number: WO2019191242A1
Application number: PCT/US2019/024297
Authority: WO
Inventors: Avi SHABTAI
Original assignee: Nano Dimension Technologies Ltd; IP Law Offices of Guy Levi LLC
Current assignee: Nano Dimension Technologies Ltd; IP Law Offices of Guy Levi LLC
Priority date: 2018-03-27
Filing date: 2019-03-27
Publication date: 2019-10-03
Anticipated expiration: 2020-09-27

Abstract

The disclosure relates to methods for direct printing of plated and/or filled vias with quadrilateral cross section in multilayered printed circuit boards, flexible printed circuits, or high- density interconnect circuits. Specifically, the disclosure is directed to the direct inkjet printing of multilayered PCBs, FPCs, or HDI circuit boards with filled and/or plated vias having quadrilateral (e.g., square, rectangle, parallelograms) cross section allowing for higher density of vias in a given surface area, and/or reduction in the area needed for printed circuits.

Description

DIRECT INKJET PRINTING OF QUADRILATERAL CROSS SECTION PLATED AND/OR

FILLED VIAS

BACKGROUND

[0001] The disclosure is directed to methods for direct ink jet printing of vias with quadrilateral cross section in the X-Y direction, in multilayered printed circuit boards (PCBs). Specifically, the disclosure is directed to the direct inkjet printing of multilayered PCBs, as well as as high-density interconnect circuit boards and flexible printed circuit boards, with plated and/or filled vias of various types having quadrilateral (e.g., square, rectangle, parallelogram) cross section allowing for higher density of vias in a given surface area or reduction in the area necessary to accommodate the vias.

[0002] To improve circuits’ integration, multi-layered printed circuit boards may be required. Current fabrication of multi-layered printed circuit boards require complicated processes including drilling (mechanical and/or laser assisted) to form; through, blind or buried via holes in order to enable conduction between components on the layer stack. This in turn requires laminating the boards and soldering to adhere elements to the printed circuit board. When soldering is performed in order to adhere elements to the printed circuit board, a region, where a solder is melted and spread, is further required and the elements are thus located in an area wider than the size of elements, themselves, thus limiting miniaturization.

[0003] Likewise, High Density Interconnect (HDI) circuit board designs, which typically require a higher wiring and pad density than conventional PCBs - along with smaller trace widths and spaces, make extensive use of blind vias, buried vias, and via-in-pads. These in turn can significantly increase the number of connections without increasing the board size (and conversely, enable even further miniaturization of conventional PCBs). Manufacturing these types of vias in a multilayer PCB requires either a process of sequential lamination of prepared components, or precise drilling of a completed multilayer PCB, both which can limit design and fabrication.

[0004] Moreover, current limitations on board thickness, stemming from recommendations on Via Aspect Ratio, (in other words, the ratio of the circuit board thickness to the smallest unplated drilled hole diameter), again reduce flexibility in PCB, FPC, and HDI circuits design.

[0005] The following disclosure addresses these shortcomings. SUMMARY

[0006] Disclosed, in various embodiments, are methods for direct printing of at least one of plated and filled vias with quadrilateral cross section in the X-Y (horizontal) direction in multilayered printed circuit boards.

[0007] In an embodiment provided herein is an inkjet printing method for forming a plated and/or filled via defining a longitudinal axis having a quadrilateral cross-section perpendicular to the longitudinal axis, the filled and/or filled vias integrated in a multi-layered printed circuit board (PCB), flexible printed circuit or high-density interconnect circuit, comprising: providing a substrate; providing an ink jet printing system comprising: a first print head having: at least one aperture, a dielectric ink reservoir, and a first dispenser (e.g., pump, piezo-electric pulse, print head and the like) configured to supply the dielectric ink through the aperture; a second print head having: at least one aperture, a conductive ink reservoir, and a second dispenser configured to supply the conductive ink through the aperture; a conveyor, operably coupled to the first print head and to the second print head, configured to convey the substrate to the first and second print head; providing a dielectric ink composition and a conductive ink composition; using the first print head, forming an insulating layer on the substrate, the insulating layer defining a non-printed quadrilateral space; curing the insulating layer using the conductive ink, forming at least one of a trace corresponding to periphery of the non- printed quadrilateral space and a pattern corresponding to the non-printed quadrilateral space; sintering the at least one of the trace corresponding to periphery of the non-printed quadrilateral space and the pattern corresponding to the non-printed quadrilateral space; and repeating the steps of forming (d) to the step of sintering (g) corresponding to the desired number of layers removing the substrate thereby forming at least one of a plated via and a filled via having a quadrilateral cross- section in a multi-layered printed circuit board (PCB).

[0008] These and other features of the methods for direct printing of plated and/or filled vias with quadrilateral cross section in multilayered printed circuit boards, will become apparent from the following detailed description when read in conjunction with the figures and examples, which are exemplary, not limiting.

BRIEF DESCRIPTION OF THE FIGURES

[0009] For a better understanding of the methods for direct printing of plated and/or filled vias with quadrilateral cross section in multilayered printed circuit boards (PCBs) flexible printed circuits (FPCs) and high density interconnect circuits (HDI circuits), with regard to the embodiments thereof, reference is made to the accompanying examples and figures, in which:

[00010] FIG. 1 illustrates a comparison between the current state of affairs (left half) and the proposed technology (right half);

[00011] FIG. 2, illustrates an embodiment of the resulting X-Y top plan view of circuit pattern of a multi-layered PCB; and

[00012] FIG. 3, illustrates X-Z cross section of a typical multilayer PCB comprising the quadrilateral cross section plated and/or filled vias.

DETAILED DESCRIPTION

[00013] Provided herein are embodiments of methods for direct inkjet printing of plated and/or filled vias with quadrilateral cross section in multilayered printed circuit boards.

[00014] The methods described herein can be used to form the printed circuit board (PCB) in a continuous process using the inkjet printing device or using several passes. Using the methods described herein, the dielectric material used to form the board, which is typically formed separately and provided as a substrate for further printing of the conductive and insulating layers on top of it, is eliminated and, using the methods described herein, it is possible to achieve higher component density, as well as increase flexibility in design.

[00015] Accordingly and in an embodiment, provided herein is an inkjet printing method for forming at least one of a plated and/or filled via defining a longitudinal axis having a quadrilateral cross-section perpendicular to the longitudinal axis, the filled and/or filled vias integrated in a multi layered printed circuit board (PCB), flexible printed circuit (FPC), or high density interconnect circuit (HDI circuit) comprising: providing a substrate; providing an ink jet printing system comprising: a first print head having: at least one aperture, a dielectric ink reservoir, and a first dispenser configured to supply the dielectric ink through the aperture; a second print head having: at least one aperture, a conductive ink reservoir, and a second dispenser configured to supply the conductive ink through the aperture; a conveyor, operably coupled to the first print head and to the second print head, configured to convey the substrate to the first and second print head; providing a dielectric ink composition and a conductive ink composition; using the first print head, forming an insulating layer on the substrate, the insulating layer defining a non-printed quadrilateral space; curing the insulating layer using the conductive ink, forming at least one of a trace corresponding to periphery of the non-printed quadrilateral space, and a pattern corresponding to the non-printed quadrilateral space; sintering the at least one of the trace corresponding to the periphery of the non-printed quadrilateral space and the pattern corresponding to the non-printed quadrilateral space; and repeating the steps of forming (d) to the step of sintering (g) corresponding to the desired number of layers removing the substrate thereby forming at least one of a plated via and a filled via having a quadrilateral cross-section in a multi-layered PCB, FPC, or HDI circuit.

[00016] The term“quadrilateral” or“generally quadrilateral”, or“substantially quadrilateral” as used herein in reference to the cross section of the plated and/or filled via normal to the Z direction (in other words, normal to the vias’ longitudinal axis. The term refers in an embodiment to a cross- sectional profile that has four sides, at least two of which are generally parallel to each other and define the X dimension (left to right) of the plated and/or filled via. The two other sides or faces (which therefore define the Y aspect/dimension of the plated and/or filled via) may or may not be parallel to each other. The determination on which quadrilateral cross section is used, may be determined based on the component density in any direction that will assure the necessary conductivity of the electronically coupled components across the layer stack. Accordingly, the quadrilateral cross section can define at least one of a square, a rectangle and a parallelogram.

[00017] In an embodiment, he term“dispenser” is used to designate the device from which the drops are dispensed. The dispenser can be, for example an apparatus for dispensing small quantities of liquid including micro-valves, piezoelectric dispensers, continuous-jet print-heads, boiling (bubble- jet) dispensers, and others affecting the temperature and properties of the fluid flowing through the dispenser.

[00018] As illustrated in FIG. 1, showing the current state of affairs and illustrating that using a circular cross section with radius n, r₂, which can be the same or different, the net effect is the elimination of a square enclosing the circle with D x D dimensions. To the extent the area of the plated and/or filled via is proportional to the necessary conductivity, (See right hand side, FIG. 1), it is possible to obtain the same area using square cross section in 88.6% of the surface. Moreover, and as seen in FIG. 1, the footprint of the plated and/or filled vias (or pads for that matter) on the layer’s surface is substantially decreased ( h x h) vs. (h x U), assuming the same minimal proximity between the vias that will guarantee no“bleeding” or crosstalk.

[00019] The plated and/or filled vias having a quadrilateral cross-section can each be at least one of a microvia, a through-hole via, a blind via, a buried via and a via-in-pad. “Microvia” refers in an embodiment to the aspect ratio of a hole, in other words, the ratio of the length or depth of a hole to its diameter. Accordingly, in the PCBs formed integrally as in here (in other words, with no necessary additional step for forming vias, like lasering or drilling) by the methods disclosed and claimed herein, microvia refers to through holes, blind holes and buried holes having an aspect ratio between pad diameter (or circuit trace width at the hole) that is equal to or greater than 1.5. For example, using the first printhead, the second printhead or both, the quadrilateral cross section hole can have a blind hole diagonal of between about 25 and 75 pm, or 50 pm, with a pad diagonal (see e.g., element 250 FIG. 2) of between about 30pm and about 150 pm, for example, 100 pm. The plated and/or filled via holes can be, for example a through via hole (spanning the whole thickness of the multi-layered PCB in the Z direction (up-and-down), a buried via hole (not exposed to any outer layer), a blind via hole (exposed to one outer layer only) or a combination of the foregoing. The thickness of each layer can be between about 3 pm and about 1 cm per layer. For example, total number of layers comprising the quadrilateral cross section plated and/or filled vias formed using the methods provided, can be about 100 pm thick, while the layer(s) can be about 25 pm thick.

[00020] Here, unlike the current state of affairs whereby due to the via aspect ratio it is not recommended for a microvia, which is usually reserved for blind or buried vias, to penetrate more than one or two layers, using the methods provided herein, it is possible to design and obtain microvias for more than 3 layers.

[00021] Furthermore, using the methods provided herein, it is possible to print quadrilateral pads, which form better substrate for quadrilateral printed circuits, thus allowing for higher density of components and, using corresponding via-in-pad having quadrilateral cross section, the efficiency in space utilization is substantially increased (see e.g., FIG. 1, right-hand-side).

[00022] In an embodiment, the via defines a longitudinal axis ¾ wherein the longitudinal axis is not perpendicular to at least one of the apical outer layer and the basal outer layer of the printed circuit board (see e.g., 360, FIG. 3), nor is the longitudinal axis of via 360, is a straight line, thus allowing vias to connect components that are not directly beneath or above them.

[00023] The method of forming the PCB’s can comprise a step of providing a substrate (e.g., a peelable substrate such as a film). The print head (and derivatives thereof; are to be understood to refer to any device or technique that deposits, transfers or creates material on a surface in a controlled manner) depositing the dielectric ink, can be configured to provide the ink droplet(s) upon demand, in other words, as a function of various process parameters such as conveyor speed, desired PCB sub- layer thickness, whether the via is filled or plated, vias density and directional density gradient (of vias and components), or their combination.

[00024] The substrate, which can be, for example removable or peelable, can also be a relatively rigid material, for example, glass or crystal (e.g., sapphire), Alternatively, the substrate may be a flexible (e.g., Tollable) substrate (or film) to allow for an easy peeling of the substrate from the PCB, for example, poly(ethylenenaphthalate) (PEN), polyimide (e.g. KAPTONE^® by DuPont), silicon polymers, poly(ethyleneterphtalate) (PET), poly(tetrafluoroethylene) (PTFE) films etc.

[00025] Other similar functional steps (and therefore means for affecting these steps) may be taken before or after the first or second print heads (e.g., for sintering the conductive layer). These steps may include (but not limited to): a heating step (affected by a heating element such as a chuck, or hot air); photobleaching (using e.g., a UV light source and a photo mask); drying (e.g., using vacuum region, or heating element); (reactive) plasma deposition (e.g., using pressurized plasma gun and a plasma beam controller); cross linking (e.g., by selectively initiated through the addition of a photoacid such as {4- [(2- hydroxytetradecyl)-oxyl] -phenyl } -phenyliodonium hexafluoro antimonate to a polymer solutions prior to coating or used as dispersant with the metal precursor or nanoparticles); annealing, or facilitating redox reactions.

[00026] Formulating the conductive and/or dielectric ink composition(s), may take into account the requirements, if any, imposed by the deposition tool and the surface characteristics (e.g., at least one of hydrophilic or hydrophobic, and the surface energy) of the (optionally removable) substrate. Using ink-jet printing with a piezo head, the viscosity of either the conductive ink and/or dielectric ink (measured at 20°C) can be, for example, not lower than about 5 cP, e.g., not lower than about 8 cP, or not lower than about 10 cP, and not higher than about 30 cP, e.g., not higher than about 20 cP, or not higher than about 15 cP. The conductive ink, and/or dielectric ink can each be configured (e.g., formulated) to have a dynamic surface tension (referring to a surface tension when an ink-jet ink droplet is formed at the print-head aperture) of between about 25 mN/m and about 35 mN/m, for example between about 29 mN/m and about 31 mN/m measured by maximum bubble pressure tensiometry at a surface age of 50 ms and at 25°C. The dynamic surface tension can be formulated to provide a contact angle with the peelable substrate or the insulating layer(s) of between about 100 ⁰ and about 165°.

[00027] In an embodiment, the ink-jet ink compositions and methods allowing for a continuous or semi-continuous ink-jet printing of a PCB (and/or FPC and/or HDI circuits) including the filled and/or plated vias having a quadrilateral cross section, can be patterned by expelling droplets of the liquid ink-jet ink provided herein from an orifice one-at-a-time, as the print-head (or the substrate) is maneuvered, for example in two (X-Y) (it should be understood that the print head can also move in the Z axis) dimensions at a predetermined distance above the substrate or any subsequent layer. The ink-jet print heads provided used in the methods described herein can provide a minimum layer film thickness equal to or less than about 3 pm- 10,000 pm

[00028] In an embodiment, the volume of each droplet of the conductive ink, and/or the dielectric ink, can range from 0.5 to 300 picoLiter (pL), for example 1-4 pL and depended on the strength of the driving pulse and the properties of the ink. The waveform to expel a single droplet can be a 10V to about 70 V pulse, or about 16V to about 20V, and can be expelled at frequencies between about 5 kHz and about 500 kHz.

[00029] The dielectric ink compositions described herein can have in addition, a continuous phase comprising: a cross-linking agent, a co-monomer, a co-oligomer, co-polymer or a composition comprising one or more of the foregoing. Likewise, the oligomer and/or polymer backbone can be induced to form cross links by contacting the polymer with an agent that will form free radicals on the backbone, thereby allowing for cross-linking sites. In an embodiment, the cross-linking agent, co monomer, co-oligomer, co-polymer or a composition comprising one or more of the foregoing can be a part, or configured to form a solution, emulsion, gel or suspension within the continuous phase.

[00030] In an embodiment, the continuous phase used in the PCBs fabricated using the disclosed methods including the vias having a quadrilateral cross section can comprise: multifunctional acrylate monomer, oligomer, polymer or their combination; a cross-linking agent; and a radical photoinitiator, and can be partially or entirely soluble in the continuous phase.

[00031] Initiating the dielectric resin backbone can be done using an initiator, for example benzoyl peroxide (BP) and other peroxide-containing compounds. The term "initiator" as used herein generally refers to a substance that initiates a chemical reaction, specifically any compound which initiates polymerization, or produces a reactive species which initiates polymerization, including, for example and without limitation, co-initiators and/or photoinitiator(s).

[00032] In another embodiment, the continuous phase comprises active components of a polymer capable of undergoing photoinitiation using a photoinitiator. Such live monomer, live oligomer, live polymer or their combination capable of undergoing photoinitiation can be for example, multifunctional acrylates, for example a multifunctional acrylate that can be multifunctional acrylate is selected from the group consisting of l,2-ethanediol diacrylate, 1,3 -propanediol diacrylate, 1,4- butanediol diacrylate, l,6-hexanediol diacrylate, dipropylene glycol diacrylate, neopentyl glycol diacrylate, ethoxylated neopentyl glycol diacrylate, propoxylated neopentyl glycol diacrylate, tripropylene glycol diacrylate, bisphenol-A-diglycidyl ether diacrylate, hydroxypivalic acid neopentanediol diacrylate, ethoxylated bisphenol-A-diglycidyl ether diacrylate, polyethylene glycol diacrylate, trimethylolpropane triacrylate, ethoxylated trimethylolpropane triacrylate, propoxylated trimethylolpropane triacrylate, propoxylated glycerol triacrylate, tris(2-acryloyloxyethyl)isocyanurate, pentaerythritol triacrylate, ethoxylated pentaerythritol triacrylate, pentaerythritol tetraacrylate, ethoxylated pentaerythritol tetraacrylate, ditrimethylolpropane tetraacrylate, dipentaerythritol pentaacrylate and dipentaerythritol hexaacrylate.

[00033] Photoinitiators that can be used with the multifunctional acrylates described herein can be, for example radical photoinitiator. These radical photoinitiators can be, for example Irgacure® 500 from CIBA SPECIALTY CHEMICAL and Darocur® 1173, Irgacure® 819, Irgacure® 184, TPO- L (ethyl(2,4,6, trimethyl benzoil) phenyl phosphinate) benzophenone and acetophenone compounds and the like. For example, the radical photoinitiator can be cationic photo-initiator, such as mixed triarylsulfonium hexafluoroantimonate salts. Another example of the radical photoinitiator used in the active continuous phase described herein, can be 2-ispropylthioxanthone.

[00034] The terms“live monomer”,“live oligomer”,“polymer” or their counterparts (co monomer e.g., ) combination refers in an embodiment to a monomer, a short group of monomers or a polymer having at least one functional group capable of forming a radical reaction (in other words, the reaction can be continued and is not otherwise terminated by an end-group).

[00035] The cross-linking agent used in the compositions, kits and methods described herein, for forming the PCB including the vias having a quadrilateral cross section can be, for example, a primary or secondary polyamine and adducts thereof, or in another example, an anhydride, a polyamide, a C4-C30 polyoxyalkylene in which the alkylene groups each independently comprise 2 to 6 carbon atoms, or a composition comprising one or more of the foregoing.

[00036] The suspension may require the presence of a surfactant and optionally a

co surfactants. The surfactants and/or cosurfactants may be cationic surfactants, anionic surfactants, non-ionic surfactant and amphiphilic copolymers, such as block copolymers.

[00037] Moreover, the dielectric layer portion can have a substantially uniform thickness throughout, thereby creating a substantially planar (e.g., flat) surface for receiving an additional conductive circuit pattern. The insulating layer may be an UV curable adhesive or other polymer material. In an embodiment, the dielectric ink comprises a UV curable polymer. Other dielectric polymers such as, for example, polyester (PES), polyethylene (PE), polyvinyl alcohol (PVOH) and poly-methyl methacrylate (PMMA), Poly(vinylpirrolidone) (PVP, water soluble and may be beneficial not to clog the print head orifice). Other dielectric materials can be photoresistive polymers, for example, SU-8 based polymers, polymer-derived ceramics or their combination and copolymers can also be used.

[00038] Fabricating a multi-layered PCB, FPC, or HDI circuit, can be done, for example, by forming a second dielectric layer on the continuous surface formed by the first pattern and with the quadrilateral spaces formed in the areas not occupied by the dielectric ink, curing the dielectric layer, using the conductive ink, forming at least one of a conductive trace on the internal periphery of the quadrilateral spaces formed in the areas not occupied by the dielectric ink, and a pattern corresponding to the non-printed quadrilateral space; and sintering the conductive trace and/or pattern (printed throughout the void created by the dielectric ink) thus forming consecutive layer of plated and/or filled vias with quadrilateral cross section.

[00039] The ink-jet systems used to implement the methods provided herein, can further comprises a computer aided manufacturing (“CAM”) module, the module comprising a data processor, a non-volatile memory, and a set of executable instructions stored on the non-volatile memory, which when executed cause the processor to: receive a 3D visualization file representing the printed circuit board including the vias having a quadrilateral cross section; generate a file that represents at least one, substantially 2D layer for printing the printed circuit board including the filled and/or plated vias having quadrilateral cross section, creating a substantially 2D representation image of the substantially 2D layer including the filled and/or plated vias having quadrilateral cross section; receive a selection of parameters related to the printed circuit board including the filled and/or plated vias having quadrilateral cross section; and alter the file representing the at least one, substantially 2D layer based on at least one of the selection of parameters, wherein the CAM module is configured to control each of the first and second print heads.

[00040] Accordingly, the step of using the first print head is preceded by a step of: using the CAM module, obtaining a generated file representing a first, substantially 2D layer of the printed circuit board including the filled and/or plated vias having quadrilateral cross section for printing, the 2D layer comprising a pattern representative of the dielectric ink, and the conductive ink, wherein the parameters used in the selection of parameters related to the printed circuit board including the filled and/or plated vias having quadrilateral cross section, are at least one of the dielectric ink pattern in the layer, the conductive ink pattern in the layer, curing requirements for the dielectric ink, sintering for the conductive ink pattern in the layer, at least one of a location and a type of each via, minimum distance between vias, via aspect ratio, a sub-layer destination, the thickness ratio between the dielectric layer and the conductive layer, whether the vias are plated of filled, whether the vias are through hole, blind, or buried vias, and whether the via terminates on an external surface with a quadrilateral contact pad.

[00041] A more complete understanding of the components, methods, and devices disclosed herein can be obtained by reference to the accompanying drawings. These figures (also referred to herein as“FIG.”) are merely schematic representations based on convenience and the ease of demonstrating the present disclosure, and are, therefore, not intended to indicate relative size and dimensions of the devices or components thereof, their relative size relationship and/or to define or limit the scope of the exemplary embodiments. Although specific terms are used in the following description for the sake of clarity, these terms are intended to refer only to the particular structure of the embodiments selected for illustration in the drawings, and are not intended to define or limit the scope of the disclosure. In the drawings and the following description below, it is to be understood that like numeric designations refer to components of like function. Likewise, cross sections are referred to on normal orthogonal coordinate apparatus having XYZ axis, such that Y axis refers to front-to-back, X axis refers to side-to-side, and Z axis refers to up-and-down.

[00042] Turning now to FIG.s 2 and 3, illustrating plane view and cross section thereof fabricated using the methods described herein for forming a multilayer PCB including the filled and/or plated vias having quadrilateral cross section, wherein: before removing the substrate 100 (See FIG. 3), forming dielectric layer 302 and curing the dielectric layer (e.g., using UV radiation), then, using the conductive ink 301, forming a conductive pattern on the internal periphery of the dielectric pattern defining the quadrilateral space; and sintering the conductive pattern (e.g., using VISNIR actininc radiation). In the above described multilayer printed circuit board, via hole 350 (which can be plated or filled), for connecting conductor circuits sandwiched within dielectric layer 301 can be formed, where via hole 350 can be a plated (or filled) through hole (PTH) via 351 and/or blind via hole 352, or buried via hole 353 (see e.g., FIG. 3). Using the methods described herein, via holes 350, whether penetrating through holes 351, non-through holes, or blind via hole 352 and or buried via holes 353, can be formed using the inkjet printing methods by directly forming the quadrilateral voids (if plated), or columns (if filled vias) through the layers. Following the removal of substrate layer 100, the formed PCBs FPCs and/or HDI circuits can then, if needed or desired, be further stamped, routed, drilled, milled, etched equipped with various electrical elements, e.g. by robotic arm, can be soldered to it, or otherwise processed to create passages in conformance with a predetermined circuit board layout. The resulting variety of these passages can become wiring passages.

[00043] The term "comprising" and its derivatives, as used herein, are intended to be open ended terms that specify the presence of the stated features, elements, components, groups, integers, and/or steps, but do not exclude the presence of other unstated features, elements, components, groups, integers and/or steps. The foregoing also applies to words having similar meanings such as the terms, "including", "having" and their derivatives.

[00044] All ranges disclosed herein are inclusive of the endpoints, and the endpoints are independently combinable with each other.“Combination” is inclusive of blends, mixtures, alloys, reaction products, and the like. The terms“a”,“an” and“the” herein do not denote a limitation of quantity, and are to be construed to cover both the singular and the plural, unless otherwise indicated herein or clearly contradicted by context. The suffix“(s)” as used herein is intended to include both the singular and the plural of the term that it modifies, thereby including one or more of that term (e.g., the film(s) includes one or more films). Reference throughout the specification to“one embodiment”, “another embodiment”,“an embodiment”, and so forth, when present, means that a particular element (e.g., feature, structure, and/or characteristic) described in connection with the embodiment is included in at least one embodiment described herein, and may or may not be present in other embodiments. In addition, it is to be understood that the described elements may be combined in any suitable manner in the various embodiments.

[00045] All ranges disclosed herein are inclusive of the endpoints, and the endpoints are independently combinable with each other. Furthermore, the terms“first,”“second,” and the like, herein do not denote any order, quantity, or importance, but rather are used to denote one element from another.

[00046] Likewise, the term "about" means that amounts, sizes, formulations, parameters, and other quantities and characteristics are not and need not be exact, but may be approximate and/or larger or smaller, as desired, reflecting tolerances, conversion factors, rounding off, measurement error and the like, and other factors known to those of skill in the art. In general, an amount, size, formulation, parameter or other quantity or characteristic is "about" or "approximate" whether or not expressly stated to be such.

[00047] Accordingly, provided herein is an inkjet printing method for forming at least one of a plated via and a filled via having a quadrilateral cross-section in a multi-layered printed circuit board (PCB) comprising: providing a substrate; providing an inkjet printing system comprising: a first print head having: at least one aperture, a dielectric ink reservoir, and a first dispenser configured to supply the dielectric ink through the aperture; a second print head having: at least one aperture, a conductive ink reservoir, and a second dispenser configured to supply the conductive ink through the aperture; a conveyor, operably coupled to the first print head and to the second print head, configured to convey the substrate to the first and second print head; providing a dielectric ink composition and a conductive ink composition; using the first print head, forming an insulating layer on the substrate, the insulating layer defining a non-printed quadrilateral space; curing the insulating layer using the conductive ink, forming at least a trace corresponding to periphery of the non-printed quadrilateral space, and a pattern corresponding to the non-printed quadrilateral space; sintering at least one of the trace corresponding to periphery of the non-printed quadrilateral space, and the pattern corresponding to the non-printed quadrilateral space; and repeating the steps of forming (d) to the step of sintering (g) corresponding to the desired number of layers removing the substrate thereby forming at least one of a plated via and a filled via having a quadrilateral cross-section in a multi-layered printed circuit board (PCB), wherein (i) the at least one of filled via and plated via is at least one of a through-hole via, a blind via, a buried via and a via- in-pad, (ii) the at least one of filled via and plated via defines a longitudinal axis and wherein the longitudinal axis is not perpendicular to at least one of the apical outer layer and the basal outer layer of the printed circuit board, (iii) the longitudinal axis is not a straight line, wherein (iv) the quadrilateral cross section is at least one of a square, a rectangle, and a parallelogram, wherein (v) wherein the step of curing comprises at least one of heating, photobleaching, drying, depositing plasma, cross linking, annealing, and facilitating redox reaction, wherein (vi) sintering comprises at least one of heating and drying, wherein (vii) the ink-jet system further comprises a computer aided manufacturing (“CAM”) module, the module comprising a data processor, a non-volatile memory, and a set of executable instructions stored on the non-volatile memory, which when executed cause the processor to: receive a 3D visualization file representing the printed circuit board including the at least one of the filled via and the plated via having quadrilateral cross section; generate a file that represents at least one, substantially 2D layer for printing the printed circuit board including the filled and/or plated vias having quadrilateral cross section, creating a substantially 2D representation image of the substantially 2D layer including the filled and/or plated vias having quadrilateral cross section; receive a selection of parameters related to the printed circuit board including the filled and/or plated vias having quadrilateral cross section; and alter the file representing the at least one, substantially 2D layer based on at least one of the selection of parameters, wherein the CAM module is configured to control each of the first and second print heads, (viii) the step of using the first print head is preceded by a step of: using the CAM module, obtaining a generated file representing a first, substantially 2D layer of the printed circuit board including the filled and/or plated vias having quadrilateral cross section for printing, the 2D layer comprising a pattern representative of the dielectric ink, and the conductive ink, wherein (ix) the parameters used in the selection of parameters related to the printed circuit board including the filled and/or plated vias having quadrilateral cross section are at least one of the dielectric ink pattern in the layer, the conductive ink pattern in the layer, curing requirements for the dielectric ink, sintering for the conductive ink pattern in the layer, at least one of a location and a type of each via, minimum distance between vias, via aspect ratio, a sub-layer destination, whether the via is filled or plated via, and the type of via, and (x) at least one of a printed circuit board (PCB), a flexible printed circuit (FPC), a high-density interconnect circuit (HDIC), and their combination fabricated using the methods provided herein.

[00048] The above examples and description have of course been provided only for the purpose of illustration, and are not intended to limit the disclosed technology in any way. As will be appreciated by the skilled person, the disclosed technology can be carried out in a great variety of ways, employing more than one technique from those described above, all without exceeding the scope of the invention.

Claims

What is claimed:

1. An inkjet printing method for forming at least one of a plated via and a filled via having a quadrilateral cross-section in a multi-layered printed circuit board (PCB) comprising: a. providing a substrate;

b. providing an ink jet printing system comprising:

i. a first print head having: at least one aperture, a dielectric ink reservoir, and a first dispenser configured to supply the dielectric ink through the aperture;

ii. a second print head having: at least one aperture, a conductive ink reservoir, and a second dispenser configured to supply the conductive ink through the aperture;

iii. a conveyor, operably coupled to the first print head and to the second print head, configured to convey the substrate to the first and second print head;

c. providing a dielectric ink composition and a conductive ink composition;

d. using the first print head, forming an insulating layer on the substrate, the insulating layer defining a non-printed quadrilateral space;

e. curing the insulating layer.

f. using the conductive ink, forming at least a trace corresponding to periphery of the non-printed quadrilateral space, and a pattern corresponding to the non-printed quadrilateral space; g. sintering at least one of the trace corresponding to periphery of the non-printed quadrilateral space, and the pattern corresponding to the non-printed quadrilateral space; and

h. repeating the steps of forming (d) to the step of sintering (g) corresponding to the desired number of layers

i. removing the substrate thereby forming at least one of a plated via and a filled via having a quadrilateral cross-section in a multi-layered printed circuit board (PCB).

2. The method of claim 1, wherein the at least one of filled via and plated via is at least one of a through-hole via, a blind via, a buried via and a via-in-pad.

3. The method of claim 1, wherein the quadrilateral cross section is at least one of a square, a rectangle, and a parallelogram.

4. The method of claim 1, wherein the at least one of filled via and plated via defines a longitudinal axis and wherein the longitudinal axis is not perpendicular to at least one of the apical outer layer and the basal outer layer of the printed circuit board.

5. The method of claim 4, wherein the longitudinal axis is not a straight line.

6. The method of claim 1, wherein the step of curing comprises at least one of heating, photobleaching, drying, depositing plasma, cross linking, annealing, and facilitating redox reaction.

7. The method of claim 1, wherein sintering comprises at least one of heating and drying.

8. The method of claim 1, wherein the ink-jet system further comprises a computer aided manufacturing (“CAM”) module, the module comprising a data processor, a non-volatile memory, and a set of executable instructions stored on the non-volatile memory, which when executed cause the processor to:

a. receive a 3D visualization file representing the printed circuit board including the at least one of the filled via and the plated via having quadrilateral cross section;

b. generate a file that represents at least one, substantially 2D layer for printing the printed circuit board including the filled and/or plated vias having quadrilateral cross section, creating a substantially 2D representation image of the substantially 2D layer including the filled and/or plated vias having quadrilateral cross section;

c. receive a selection of parameters related to the printed circuit board including the filled and/or plated vias having quadrilateral cross section; and

d. alter the file representing the at least one, substantially 2D layer based on at least one of the selection of parameters, wherein the CAM module is configured to control each of the first and second print heads.

9. The method of claim 8, wherein the step of using the first print head is preceded by a step of: using the CAM module, obtaining a generated file representing a first, substantially 2D layer of the printed circuit board including the filled and/or plated vias having quadrilateral cross section for printing, the 2D layer comprising a pattern representative of the dielectric ink, and the conductive ink.

10. The method of claim 9, wherein the parameters used in the selection of parameters related to the printed circuit board including the filled and/or plated vias having quadrilateral cross section are at least one of the dielectric ink pattern in the layer, the conductive ink pattern in the layer, curing requirements for the dielectric ink, sintering for the conductive ink pattern in the layer, at least one of a location and a type of each via, minimum distance between vias, via aspect ratio, a sub-layer destination, and whether the via is filled or plated via.

11. At least one of a printed circuit board, a flexible printed circuit, a high-density interconnect circuit and their combination fabricated using the method of any one of claims 1-10.