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WO2019181110A1 - Élément d'imagerie à semi-conducteurs, dispositif d'imagerie et procédé de commande pour élément d'imagerie à semi-conducteurs - Google Patents

Élément d'imagerie à semi-conducteurs, dispositif d'imagerie et procédé de commande pour élément d'imagerie à semi-conducteurs Download PDF

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Publication number
WO2019181110A1
WO2019181110A1 PCT/JP2018/046093 JP2018046093W WO2019181110A1 WO 2019181110 A1 WO2019181110 A1 WO 2019181110A1 JP 2018046093 W JP2018046093 W JP 2018046093W WO 2019181110 A1 WO2019181110 A1 WO 2019181110A1
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Prior art keywords
signal
pixel
ramp
solid
state imaging
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English (en)
Japanese (ja)
Inventor
隆 細江
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Sony Semiconductor Solutions Corp
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Sony Semiconductor Solutions Corp
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
    • H04N25/616—Noise processing, e.g. detecting, correcting, reducing or removing noise involving a correlated sampling function, e.g. correlated double sampling [CDS] or triple sampling
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
    • H04N25/618—Noise processing, e.g. detecting, correcting, reducing or removing noise for random or high-frequency noise
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/78—Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters

Definitions

  • the present technology relates to a solid-state imaging device, an imaging apparatus, and a control method for the solid-state imaging device.
  • the present invention relates to a solid-state imaging device, an imaging apparatus, and a control method for the solid-state imaging device that convert an analog signal into a digital signal for each column.
  • an ADC Analog-to-Digital Converter
  • a solid-state imaging device has been proposed in which an ADC performs AD (Analog-to-Digital) conversion of the reset level and signal level of an analog pixel signal a plurality of times for each pixel, and a subsequent circuit adds and averages them (for example, see Patent Document 1.)
  • AD Analog-to-Digital
  • Patent Document 1 a single slope type ADC provided with a comparator and a counter is used.
  • the comparator compares the ramp signal having the slope with the pixel signal, and the counter counts the count value over a period until the comparison result is inverted. Since sampling and AD conversion are executed every cycle of the ramp signal, the frequency of the ramp signal matches the sampling frequency.
  • the reading speed can be maintained, but in particular, it is necessary to make the slope of the ramp signal steep in order to perform AD conversion on a high-intensity signal, and the resolution of AD conversion decreases, The image quality may be degraded.
  • the above-described conventional technique has a problem that it is difficult to improve the image quality while maintaining the reading speed.
  • the present technology has been developed in view of such a situation, and an object of the present technology is to improve image quality while maintaining a reading speed in a solid-state imaging device provided with an analog-digital converter.
  • the present technology has been made to solve the above-described problems, and a first aspect thereof includes a ramp signal supply unit that supplies a ramp signal having a frequency corresponding to a signal level of a pixel signal, and the ramp signal.
  • a solid-state imaging device including a comparator that compares the pixel signal with the pixel signal and outputs a comparison result, and a counter that counts a count value over a period until the comparison result is inverted, and a control method thereof is there. As a result, the ramp signal having a frequency corresponding to the signal level of the pixel signal is compared with the pixel signal.
  • the ramp signal supply unit may supply the ramp signal having a lower frequency as the signal level is lower.
  • the lower the signal level of the pixel signal, the lower the frequency of the ramp signal and the pixel signal are compared.
  • the ramp signal supply unit detects whether or not the signal level is higher than a predetermined threshold and outputs a detection result, and the frequency differs based on the detection result.
  • a selector that selects any one of a plurality of ramp signals and supplies the selected ramp signal to the comparator may be provided. This brings about the effect that one of the plurality of ramp signals is selected based on whether the signal level of the pixel signal is higher than a predetermined threshold value.
  • the predetermined threshold value is one
  • the selector selects one of two ramp signals having different frequencies
  • the detector includes one of the two ramp signals.
  • a latch circuit that holds the comparison result as a hold value when a specific timing corresponding to the predetermined threshold value has passed within a lower frequency cycle, and generates the detection result based on the hold value and And a logic gate that outputs to the selector.
  • the detection result is generated by the latch circuit and the logic gate.
  • the predetermined threshold includes two different thresholds, the selector selects one of three ramp signals having different frequencies, and the detector includes the plurality of ramp signals.
  • a first latch circuit that holds the comparison result when a first timing corresponding to one of the two threshold values has elapsed within a cycle of the ramp signal having the lowest frequency as a first hold value;
  • a second latch circuit that holds the comparison result when the second timing corresponding to the other of the two threshold values has elapsed within a cycle as a second hold value; and the first and second hold values
  • a logic gate that generates the detection result based on the output and outputs the detection result to the selector.
  • the detection result is generated by the first and second latch circuits and the logic gate.
  • the detector can detect whether the signal level is higher than the predetermined threshold based on the count value. This brings about the effect
  • the detector may compare the bias voltage indicating the predetermined threshold with the pixel signal and output the comparison result as the detection result. As a result, the detection result is generated by comparison with the bias voltage.
  • a division circuit that divides the count value by a larger divisor as the frequency of the selected ramp signal is higher may be further provided. This brings about the effect
  • the first aspect further includes a setting unit that sets a maximum value of the number of samplings for each pixel based on a statistic of the level of the light-shielded pixel signal from each of the plurality of light-shielded pixels that are shielded from light.
  • the pixel signal may include an effective pixel signal from each of a plurality of effective pixels that are not shielded from light and the light-shielded pixel signal. This brings about the effect that the maximum value of the number of times of sampling for each pixel is set based on the level statistics of the light-shielded pixel signal.
  • a ramp signal supply unit that supplies a ramp signal having a frequency corresponding to a signal level of a pixel signal, and a comparison that compares the ramp signal with the pixel signal and outputs a comparison result.
  • An imaging apparatus comprising: a counter; a counter that counts a count value over a period until the comparison result is inverted; and a recording unit that records image data generated from the count value.
  • FIG. 6 is a timing chart illustrating an example of the operation of the solid-state imaging device when the signal level is high in the first embodiment of the present technology.
  • 7 is a timing chart illustrating an example of the operation of the solid-state imaging device when the signal level is low in the first embodiment of the present technology.
  • 6 is a timing chart illustrating an example of the operation of the solid-state imaging device when the signal level is high and the number of sampling times is a maximum of 4 times according to the first embodiment of the present technology.
  • 6 is a timing chart illustrating an example of the operation of the solid-state imaging device when the signal level is low and the number of sampling times is a maximum of 4 times in the first embodiment of the present technology.
  • 6 is a flowchart illustrating an example of the operation of the solid-state imaging element according to the first embodiment of the present technology. It is a block diagram showing an example of 1 composition of a solid-state image sensing device in a 2nd embodiment of this art. It is a block diagram which shows one structural example of the sampling frequency setting part in the 2nd Embodiment of this technique. It is a figure showing an example of setting of the number of times of sampling in a 2nd embodiment of this art.
  • 12 is a timing chart illustrating an example of the operation of the solid-state imaging device when the signal level is the highest in the third embodiment of the present technology.
  • 14 is a timing chart illustrating an example of an operation of a solid-state imaging device when a signal level is an intermediate value according to the third embodiment of the present technology.
  • 14 is a timing chart illustrating an example of the operation of the solid-state imaging device when the signal level is the lowest in the third embodiment of the present technology.
  • First Embodiment Example of supplying a ramp signal having a frequency corresponding to a signal level
  • Second Embodiment Example in which the maximum number of samplings is set based on the statistic of the light-shielded pixel signal and a ramp signal having a frequency corresponding to the level is supplied
  • Third Embodiment Example of supplying one of three ramp signals having different frequencies according to the signal level
  • Fourth Embodiment Example in which a count value is monitored and a ramp signal having a frequency according to the signal level is supplied
  • Fifth Embodiment Example of supplying a ramp signal having a frequency corresponding to a signal level based on a comparison result with a bias voltage
  • FIG. 1 is a block diagram illustrating a configuration example of the imaging apparatus 100 according to the first embodiment of the present technology.
  • the imaging apparatus 100 captures image data and includes an imaging lens 110, a solid-state imaging device 200, a recording unit 120, and an imaging control unit 130.
  • an imaging device 100 for example, a smartphone, a digital camera, a personal computer, an in-vehicle camera, and an IoT (Internet of Things) camera are assumed.
  • the imaging lens 110 collects incident light and guides it to the solid-state imaging device 200.
  • the solid-state imaging device 200 captures image data according to the control of the imaging control unit 130.
  • the solid-state imaging device 200 supplies captured image data to the recording unit 120 via a signal line 209.
  • the recording unit 120 records image data.
  • the imaging control unit 130 controls the solid-state imaging device 200 to capture image data.
  • the imaging control unit 130 supplies a control signal including the vertical synchronization signal VSYNC to the solid-state imaging device 200 via the signal line 139.
  • the vertical synchronization signal VSYNC is a periodic signal having a constant frequency (30 Hz or the like) indicating the imaging timing of image data.
  • the imaging apparatus 100 may further include an interface, and may transmit image data to the outside through the interface, or may further include a display unit and display the image data on the display unit.
  • FIG. 2 is a block diagram illustrating a configuration example of the solid-state imaging device 200 according to the first embodiment of the present technology.
  • the solid-state imaging device 200 includes a vertical scanning circuit 210, a pixel array unit 220, and a DAC (Digital to Analog Converter) 230.
  • the solid-state imaging device 200 includes a read current control unit 240, a timing control circuit 250, a column signal processing unit 300, and a horizontal scanning circuit 260.
  • a plurality of pixels 221 are arranged in a two-dimensional grid.
  • a set of pixels 221 arranged in the horizontal direction is referred to as “row”, and a set of pixels 221 arranged in the direction perpendicular to the row is referred to as “column”.
  • the vertical scanning circuit 210 drives the rows in order under the control of the timing control circuit 250 and outputs an analog pixel signal to each of the pixels 221 in the row.
  • the DAC 230 generates a plurality of ramp signals having different frequencies by performing DA (Digital-to-Analog) conversion on the digital signal from the timing control circuit 250.
  • the ramp signal is a sawtooth waveform periodic signal, and sampling of the pixel signal and AD conversion are executed each time the period of the ramp signal elapses.
  • the read current control unit 240 supplies the pixel 221 with an operation current for reading a pixel signal.
  • the timing control circuit 250 controls the operation timing of the vertical scanning circuit 210, the DAC 230, the column signal processing unit 300, and the horizontal scanning circuit 260 in synchronization with the vertical synchronization signal VSYNC.
  • the column signal processing unit 300 performs various signal processing including AD conversion processing on the pixel signal for each column.
  • the column signal processing unit 300 outputs the image data after the signal processing to the recording unit 120.
  • the horizontal scanning circuit 260 sequentially outputs pixel signals for each column after AD conversion.
  • FIG. 3 is a block diagram illustrating a configuration example of the column signal processing unit 300 according to the first embodiment of the present technology.
  • the column signal processing unit 300 includes an AD converter 310 and a memory 350 for each column. When the number of columns is M (M is an integer), M AD converters 310 and M memories 350 are provided.
  • the column signal processing unit 300 includes a sense amplifier 360, a digital operation unit 370, and an interface unit 380.
  • the AD converter 310 converts an analog signal into a digital signal.
  • An analog pixel signal Vin from the corresponding column is input to the AD converter 310, and the AD converter 310 converts the pixel signal Vin into digital pixel data Dout. Then, the AD converter 310 holds the pixel data Dout in the corresponding memory 350.
  • Memory 350 holds pixel data Dout.
  • the memory 350 outputs the held pixel data Dout to the sense amplifier 360 according to the control of the horizontal scanning circuit 260.
  • the sense amplifier 360 amplifies the pixel data Dout and supplies it to the digital operation unit 370.
  • the digital operation unit 370 performs predetermined signal processing on the pixel data Dout.
  • the digital operation unit 370 supplies the processed pixel data to the interface unit 380.
  • the digital calculation unit 370 performs HDR (High Dynamic Range) composition processing and image plane phase difference detection processing as necessary.
  • the former HDR synthesizing process is a process for synthesizing a plurality of pixel data having different exposure times to expand the dynamic range.
  • the latter image plane phase difference detection processing is processing for obtaining a phase difference by obtaining a phase difference between two images based on pixel data from a plurality of phase difference pixels.
  • a phase difference pixel for detecting the phase difference and other normal pixels are arranged in the pixel array unit 220. Then, the ramp signal is switched according to the luminance for each of the phase difference pixel and the normal pixel.
  • the interface unit 380 supplies image data including pixel data to the recording unit 120.
  • FIG. 4 is a block diagram illustrating a configuration example of the timing control circuit 250 and the AD converter 310 according to the first embodiment of the present technology.
  • the timing control circuit 250 includes a timing generator 251 and a clock generator 252.
  • the AD converter 310 includes a selector 311, a comparator 312, a counter 313, a division circuit 314, and a detector 320.
  • the timing generator 251 generates the trigger signal TRG for each AD conversion within the period of the vertical synchronization signal VSYNC and supplies it to the detector 320. For example, when the number of rows is M and AD conversion of the reset level and the signal level is performed for each row, the trigger signal TRG is generated M ⁇ 2 times for each period of the vertical synchronization signal VSYNC.
  • the clock generator 252 generates a predetermined clock signal CLK having a frequency higher than that of the vertical synchronization signal VSYNC and supplies it to the counter 313 over the AD conversion period.
  • the clock signal CLK is generated by multiplying the vertical synchronization signal VSYNC.
  • Ramp signals RMPH and RMPL from the DAC 230 are input to the selector 311.
  • the ramp signal RMPH is a signal having a higher frequency than the ramp signal RMPL.
  • the selector 311 selects one of the ramp signals RMPH and RMPL based on the detection result DET from the detector 320 and supplies the selected signal to the comparator 312 as the ramp signal RMPS.
  • the comparator 312 compares the ramp signal RMPS with the pixel signal Vin.
  • the comparator 312 supplies the comparison result CMP_OUT to the counter 313 and the detector 320.
  • the counter 313 counts the count value in synchronization with the clock signal CLK over a period until the comparison result CMP_OUT is inverted.
  • the counter 313 supplies the count value CNT to the division circuit 314.
  • the division circuit 314 divides the count value CNT according to the enable signal CAL_EN from the detector 320.
  • the enable signal CAL_EN is a signal for instructing whether or not to perform division. For example, “1” is set when division is performed, and “0” is set when division is not performed.
  • the division circuit 314 divides the signal level count value CNT by a larger divisor as the frequency of the selected ramp signal is higher, performs CDS processing, and supplies the pixel data Dout to the memory 350. .
  • the division circuit 314 performs CDS processing without dividing the signal level count value CNT and supplies the pixel data Dout to the memory 350.
  • the detector 320 detects whether or not the level of the pixel signal Vin is higher than a predetermined threshold value.
  • a predetermined threshold value when the pixel 221 generally converts light into electrons by photoelectric conversion, the level of the pixel signal Vin decreases as the luminance increases. For this reason, when the level of the pixel signal Vin is equal to or lower than the threshold, the luminance of the light received by the pixel 221 corresponding to the pixel signal is equal to or higher than the predetermined luminance corresponding to the threshold. On the other hand, when the level of the pixel signal Vin is higher than the threshold value, the luminance of the light received by the pixel 221 corresponding to the pixel signal is lower than the predetermined luminance.
  • the detector 320 generates a detection result DET indicating whether the signal level of the pixel signal Vin is higher than a predetermined threshold (in other words, whether the luminance is lower than the predetermined luminance) and supplies the detection result DET to the selector 311.
  • the detector 320 also supplies the same signal as the detection result DET to the division circuit 314 as the enable signal CAL_EN.
  • the selector 311 selects the ramp signal RMPL having a low frequency when the detection result DET indicates that the luminance is equal to or higher than the predetermined luminance, and selects the ramp signal RMPH when the detection result DET indicates that the luminance is lower than the predetermined luminance. To do.
  • the operation of the detector 320 and the selector 311 supplies a ramp signal having a frequency corresponding to the signal level of the pixel signal Vin.
  • the circuit including the detector 320 and the selector 311 is an example of a ramp signal supply unit described in the claims.
  • the frequency of the ramp signal RMPS is the same as the sampling frequency.
  • the higher the frequency of the ramp signal (sampling frequency) the greater the number of samplings per pixel, so that random noise can be reduced by averaging each sampled signal.
  • the lower the luminance the worse the SNR (Signal-Noise (Ratio) (because noise appears to be large), so the high-frequency ramp signal RMPH is suitable for AD conversion for the pixel signal Vin of a pixel with low luminance.
  • the lower the frequency of the ramp signal (sampling frequency), the smaller the number of samplings per pixel, so the effect of reducing random noise becomes smaller.
  • the amplitude increases as the sampling frequency is lowered, the AD conversion can be performed without overflow of the counter 313 even if the luminance is high.
  • the low-frequency ramp signal RMPL is suitable for AD conversion for the pixel signal Vin of a pixel with high luminance.
  • the selector 311 selects the low-frequency lamp signal RMPL suitable for high luminance when the luminance of the pixel is equal to or higher than the predetermined luminance, and selects the high-frequency lamp suitable for low luminance when the luminance is lower than the predetermined luminance.
  • the signal RMPH is selected.
  • the division circuit 314 is arrange
  • the division circuit 314 can also be arranged in a circuit subsequent to the AD converter 310 (such as a digital arithmetic unit 370).
  • the image quality can be improved by increasing the number of times of sampling for each pixel without changing the sampling frequency. However, this is not preferable because the reading speed decreases instead of improving the image quality.
  • the slope of the ramp signal is made steeper in the case of high luminance than in the case of low luminance, the amplitude can be increased without changing the reading speed, and AD conversion can be performed without overflowing the high luminance signal level. .
  • this is not preferable because the resolution of AD conversion is lowered.
  • FIG. 5 is a circuit diagram illustrating a configuration example of the detector 320 according to the first embodiment of the present technology.
  • the detector 320 includes a latch circuit 321 and an inverter 322.
  • the latch circuit 321 holds the comparison result CMP_OUT at the timing indicated by the trigger signal TRG from the timing generator 251.
  • the latch circuit 321 supplies the hold value to the inverter 322.
  • the latch circuit 32 for example, a gated D latch is used.
  • the comparison result CMP_OUT is input to the data input terminal D of the latch circuit 321, and the trigger signal TRG is input to the enable terminal E.
  • the output terminal Q is connected to the inverter 322.
  • the inverter 322 inverts the hold value of the latch circuit 321 and supplies it to the selector 311 as the detection result DET. Further, the inverter 322 supplies the inverted value to the division circuit 314 as the enable signal CAL_EN.
  • the inverter 322 is an example of a logic gate described in the claims.
  • FIG. 6 is a diagram illustrating an example of the operation of the latch circuit 321 according to the first embodiment of the present technology.
  • the enable terminal E is at a low level, the previous held value Qprev is output.
  • the hold value When the data input terminal D is at a low level and the enable terminal E is at a high level, the hold value is reset and a logical value of “0” is output. When the data input terminal D and the enable terminal E are at the high level, the hold value is set and the logic value “1” is output.
  • FIG. 7 is a diagram illustrating an example of the operation of the selector 311 according to the first embodiment of the present technology.
  • the selector 311 selects the low-frequency ramp signal RMPL corresponding to high luminance.
  • the selector 311 selects the high-frequency ramp signal RMPH corresponding to low luminance.
  • FIG. 8 is a diagram illustrating an example of the operation of the divider circuit 314 according to the first embodiment of the present technology.
  • the division circuit 314 performs CDS processing without dividing the count value CNT of the signal level and outputs the pixel data Dout when the enable signal CAL_EN is at a low level, that is, when the pixel has high luminance.
  • the enable signal CAL_EN is at a high level, that is, when the pixel has a low luminance
  • the division circuit 314 divides the count value CNT of the signal level by the number of samplings for each pixel, performs CDS processing, and outputs the pixel data Dout. Output.
  • FIG. 9 is a timing chart showing an example of the operation of the solid-state imaging device 200 when the signal level is high according to the first embodiment of the present technology.
  • the vertical scanning circuit 210 exposes the first row at timings T2 to T4, and drives the rows at timings T4 to T5. At the timings T4 to T5, the pixel signals in the first row are read out.
  • the vertical scanning circuit 210 exposes the second row at timings T3 to T5, and drives the rows at timings T5 to T6. At the timings T5 to T6, the pixel signals in the second row are read out.
  • the third and subsequent rows are sequentially exposed and read out. In this way, the data is sequentially read out line by line by a so-called rolling shutter system.
  • the selector 311 selects, for example, the high-frequency ramp signal RMPH for low luminance and outputs it as the ramp signal RMPS.
  • the ramp signal RMPS (RMPH) decreases at a constant speed during the period from the timing T11 to T13, returns to the original level, and decreases again during the period from the timing T14 to T16. Further, the ramp signal RMPS decreases at a constant speed within the period of timing T17 to T20, returns to the original level, and decreases again during the period of timing T21 to T23.
  • the frequency of the high-frequency ramp signal RMPH is (Mult_num ⁇ 2) / (t ⁇ ) where t is the readout time of one row, N is the number of rows, and Max_num is the maximum number of sampling times of the reset level and signal level. N) Hertz.
  • the low-frequency ramp signal RMPL has the same reset level sampling frequency as the ramp signal RMPH, and the signal level sampling frequency is less than the ramp signal RMPH.
  • the vertical scanning circuit 210 initializes the pixels 221 in the row immediately before the end of the exposure of the row. At the end of exposure, the vertical scanning circuit 210 transfers charges within the pixel.
  • the pixel signal Vin at the time of initialization corresponds to the aforementioned reset level
  • the pixel signal Vin at the time of charge transfer corresponds to the signal level.
  • the alternate long and short dash line in the figure indicates the fluctuation of the pixel signal Vin.
  • the reset level is output, and the signal level is output immediately after the timing T16. When the luminance of the pixel is low, a relatively high signal level is output.
  • the comparator 312 compares the reset level with the high-frequency ramp signal RMPS and outputs a comparison result CMP_OUT. This comparison result CMP_OUT is inverted at each of timings T12, 15, 19 and 22, for example.
  • the timing control circuit 250 internally generates an enable signal CMP_EN in order to generate the trigger signal TRG.
  • the enable signal CMP_EN is at a high level over a period from timing T17 to T20, which is a first sampling period of the signal level, for example.
  • the timing control circuit 250 generates and outputs a trigger signal TRG at the timing T20 when the enable signal CMP_EN falls. This timing corresponds to a specific timing within the cycle of the low-frequency ramp signal RMPL.
  • the detector 320 latches the comparison result CMP_OUT when the trigger signal TRG is output.
  • the comparison result CMP_OUT is inverted at that time. For this reason, the low level is latched at timing T20, and a high level detection result DET obtained by inverting it is output.
  • the ramp signal is switched to a high frequency at timing T20.
  • the counter 313 counts the count value CNT in synchronization with the clock signal CLK at timings T11 to T12 until the comparison result CMP_OUT is inverted. Thereby, the first AD conversion with respect to the reset level is performed. Next, the count value CNT is similarly counted at timings T14 to T15 until the comparison result CMP_OUT is inverted. Thereby, the second AD conversion for the reset level is performed. Similarly, at timings T17 to T19 and timings T21 to T22, the first and second AD conversions for the signal level are performed.
  • the division circuit 314 divides each count value CNT of the reset level and the signal level by “2”.
  • the division circuit 314 performs CDS processing for obtaining a difference between the reset level after division and the signal level, and outputs the processed data as pixel data Dout.
  • the signal level is higher than the threshold corresponding to the timing of the trigger signal TRG (that is, the luminance is low)
  • a high-frequency ramp signal is selected.
  • the number of AD conversions for each pixel is increased, and random noise can be reduced by averaging each count value CNT.
  • the SN ratio can be improved by reducing the random noise, and the image quality can be improved.
  • FIG. 10 is a timing chart showing an example of the operation of the solid-state imaging device 200 when the signal level is low according to the first embodiment of the present technology.
  • the selector 311 first selects the high-frequency ramp signal RMPH for low luminance and outputs it as the ramp signal RMPS.
  • the timing control circuit 250 outputs the trigger signal TRG at a specific timing T18 within the cycle of the low-frequency ramp signal RMPL.
  • the detector 320 latches the comparison result CMP_OUT when the trigger signal TRG is output.
  • the comparison result CMP_OUT is not inverted at the time of the trigger signal TRG and is at the high level. Therefore, the high level is latched at timing T18, and the low level detection result DET obtained by inverting the high level is output.
  • the ramp signal Since the detection result DET is at the low level, the ramp signal remains the low-frequency ramp signal RMPL at the timing T19.
  • the waveform of the selected ramp signal RMPS in the figure is the same as that of the low frequency ramp signal RMPL. As illustrated in the figure, the ramp signal RMPL is maintained constant at timings T18 to T19 at which frequency switching is determined. This is because it takes some time to complete the frequency switching by the selector 311.
  • the counter 313 counts the count value CNT at timings T11 to T12 and T14 to T15 until the comparison result CMP_OUT is inverted. Thereby, AD conversion for the reset level is performed twice. Similarly, the count value CNT is counted at timings T17 to T20. Thereby, AD conversion with respect to a signal level is performed only once.
  • the division circuit 314 performs CDS processing without dividing the signal level count value CNT, and outputs the result as pixel data Dout. On the other hand, the reset level count value CNT is divided by “2”.
  • the low-frequency ramp signal is selected.
  • the amplitude of the ramp signal can be increased and AD conversion can be performed without overflow in the case of high luminance. Therefore, the image quality can be improved.
  • the number of times of sampling for each pixel is reduced, in the case of high luminance, since the random noise is relatively small, the SN ratio is not deteriorated.
  • the division circuit 314 does not divide when a low-frequency ramp signal is selected, but division can also be performed at this time. For example, consider a case where AD conversion is performed twice for each pixel when the luminance is high, and AD conversion is performed four times for each pixel when the luminance is low. In this case, the division circuit 314 may divide by “2” when the luminance is high and divide by “4” when the luminance is low. Thus, the number of AD conversions for each pixel corresponding to the frequency of the ramp signal is set as the divisor.
  • the AD converter 310 adaptively switches the ramp signal according to the luminance of the pixel, so that the image quality of the image data can be improved while maintaining the reading speed. .
  • FIG. 11 is a timing chart showing an example of the operation of the solid-state imaging device when the signal level is high and the number of sampling times is a maximum of 4 times in the first embodiment of the present technology.
  • FIG. 12 is a timing chart showing an example of the operation of the solid-state imaging device when the signal level in the first embodiment of the present technology is low and the number of samplings is a maximum of four times.
  • the maximum number of times of sampling for each pixel is two, but the number of times of sampling is not limited to two.
  • the number of samplings per pixel can be set to a maximum of four times.
  • FIG. 13 is a flowchart illustrating an example of the operation of the solid-state imaging device 200 according to the first embodiment of the present technology. This operation is started, for example, when a predetermined application for capturing image data is executed.
  • the vertical scanning circuit 210 selects and drives a row (step S901).
  • the detector 320 in the AD converter 310 monitors the comparison result CMP_OUT and determines whether or not the luminance of the pixel is higher than a predetermined luminance (step S902).
  • step S902 Yes
  • the selector 311 selects a low-frequency ramp signal for high luminance, and the AD converter 310 performs AD conversion for the signal level once for each pixel (step S903).
  • the selector 311 selects a high-frequency ramp signal for low luminance, and the AD converter 310 performs AD conversion on the signal level for each pixel. This is performed twice (step S904). Then, the AD converter 310 divides the count value of the signal level (step S905).
  • step S906 determines whether all rows have been selected (step S906). When all the rows have not been selected (Step S906: No), the vertical scanning circuit 210 repeatedly executes Step S901 and the subsequent steps. On the other hand, when all the rows have been selected (step S906: Yes), the operation for capturing image data is terminated. When a plurality of pieces of image data are continuously captured, the processes in steps S901 to S906 are repeatedly executed in synchronization with the vertical synchronization signal VSYNC.
  • the selector 311 selects and supplies a ramp signal having a frequency corresponding to the signal level of the pixel signal.
  • the AD conversion can be performed a number of times according to the luminance of the pixel. For example, as the luminance of the pixel is lower, the number of AD conversions can be increased to reduce random noise. Thereby, it is possible to improve the image quality while maintaining the reading speed.
  • the maximum value of the number of sampling (ie, AD conversion) for each pixel is fixed to 2 or the like.
  • the solid-state imaging device 200 according to the second embodiment is different from the first embodiment in that the maximum value of the number of times of sampling is changed based on a pixel signal of an OPB (OPtical Black) pixel.
  • OPB optical Black
  • FIG. 14 is a block diagram illustrating a configuration example of the solid-state imaging device 200 according to the second embodiment of the present technology.
  • the solid-state imaging device 200 of the second embodiment is different from the first embodiment in that it further includes a sampling number setting unit 270.
  • the pixel array unit 220 is different from the first embodiment in that a plurality of OPB pixels 222 and a plurality of normal pixels 223 are arranged in a two-dimensional lattice pattern.
  • the OPB pixel 222 is a pixel that is shielded from light, and the normal pixel 223 is a pixel that is not shielded from light.
  • the pixel signal from the OPB pixel 222 is referred to as a “light-shielded pixel signal”, and the pixel signal from the normal pixel 223 is referred to as a “normal pixel signal”.
  • the OPB pixel 222 is an example of a light-shielding pixel described in the claims.
  • the sampling number setting unit 270 sets the maximum number of sampling times for each pixel based on the light-shielded pixel signal from the OPB pixel 222.
  • the sampling number setting unit 270 supplies the set value to the timing control circuit 250.
  • the timing control circuit 250 supplies the DAC 230 with a ramp signal RMPH having a frequency corresponding to the set value of the number of samplings.
  • the sampling number setting unit 270 is an example of a setting unit described in the claims.
  • FIG. 15 is a block diagram illustrating a configuration example of the sampling number setting unit 270 according to the second embodiment of the present technology.
  • the sampling number setting unit 270 includes an OPB variance calculation unit 271, an OPB average calculation unit 272, a weighting factor acquisition unit 273, a sampling number determination unit 274, a threshold calculation unit 275, an upper limit number acquisition unit 276, and a register 277.
  • the OPB average calculator 272 calculates an average Pix_ave of the light-shielded pixel signal PIX_OPB of each of the plurality of OPB pixels 222. This average Pix_ave is calculated by the following equation, for example.
  • the OPB average calculation unit 272 supplies the calculation result to the OPB variance calculation unit 271 and the weight coefficient acquisition unit 273. In the above equation, N is the number of OPB pixels 222.
  • the OPB variance calculation unit 271 calculates the variance Pix_dev of each light-shielded pixel signal PIX_OPB of the plurality of OPB pixels 222. This variance Pix_dev is calculated by the following equation, for example.
  • the OPB variance calculation unit 271 supplies the weighting coefficient acquisition unit 273.
  • the register 277 holds various set values required for the calculation of the number of samplings.
  • the register 277 holds an average maximum threshold Th_ave_max, an average minimum threshold Th_ave_min, a variance maximum threshold Th_dev_max, and a variance minimum threshold Th_dev_min.
  • the average maximum threshold Th_ave_max is a maximum value of the threshold compared with the average Pix_ave.
  • the average minimum threshold Th_ave_min is a minimum value of the threshold compared with the average Pix_ave.
  • the variance maximum threshold Th_dev_max is the maximum value of the threshold compared with the variance Pix_dev.
  • the minimum variance threshold Th_dev_min is a minimum threshold value to be compared with the variance Pix_dev.
  • a value proportional to the gain Pix_gain for the pixel signal is set as the threshold value to be compared with the average or variance. For this reason, the maximum threshold is set when the gain is maximum, and the minimum threshold is set when the gain is minimum.
  • the register 277 holds a sampling number upper limit value Multi_max_num for AD conversion of the pixel signal for each quantization bit number.
  • a sampling number upper limit value Multi_max_num for AD conversion of the pixel signal for each quantization bit number.
  • the sampling number upper limit Mult_max_12 when the number of quantization bits is 12 bits and the sampling number upper limit Mult_max_10 when the number of quantization bits is 10 bits are held.
  • a larger upper limit value is set as the number of quantization bits is larger.
  • the upper limit number acquisition unit 276 reads the sampling number upper limit value Multi_max_num corresponding to the quantization bit number Multi_bit_num specified by the imaging control unit 130 from the register 277.
  • the upper limit number acquisition unit 276 supplies the read sampling number upper limit value Multi_max_num to the sampling number determination unit 274.
  • the threshold value calculation unit 275 calculates a threshold value corresponding to the gain Pix_gain specified by the imaging control unit 130. For example, the threshold value calculation unit 275 reads the average maximum threshold value Th_ave_max and the average minimum threshold value Th_ave_min from the register 277, and calculates the average threshold value Th_ave corresponding to the gain Pix_gain by linear interpolation. Further, the threshold calculation unit 275 reads the maximum variance threshold Th_dev_max and the minimum variance threshold Th_dev_min from the register 277, and calculates the variance threshold Th_dev corresponding to the gain Pix_gain by linear interpolation. Then, the threshold calculation unit 275 supplies the calculated average threshold Th_ave and variance threshold Th_dev to the weight coefficient acquisition unit 273.
  • the weighting coefficient acquisition unit 273 obtains the weighting coefficient Mult_wegiht based on the average Pix_ave and the variance Pix_dev, and the average threshold Th_ave and the variance threshold Th_dev.
  • the weight coefficient acquisition unit 273 determines whether or not the following expression is established. Pix_ave> Th_ave Equation 1 Pix_dev> Th_dev Equation 2
  • the weighting factor acquisition unit 273 sets “1” to the weighting factor Multi_weigh.
  • the weighting factor acquisition unit 273 sets “2” to the weighting factor Multi_weight. Then, the weight coefficient acquisition unit 273 supplies the obtained weight coefficient Multi_weight to the sampling number determination unit 274.
  • the sampling number determination unit 274 determines the sampling number Mult_num based on the sampling number upper limit value Multi_max_num and the weighting coefficient Mult_weight. For example, the sampling number determination unit 274 determines whether or not the following expression holds. (Mult_weight) 2 > Mult_max_num Expression 3
  • the sampling count determination unit 274 sets the sampling count upper limit value Multi_max_num as the sampling count Multit_num. On the other hand, when Expression 3 is not satisfied, the sampling number determination unit 274 sets the square of the weighting coefficient Multi_weight as the sampling number Multi_num. The sampling number determination unit 274 supplies the obtained sampling number Mult_num to the timing control circuit 250 as the maximum value of the sampling number.
  • the timing control circuit 250 causes the DAC 230 to generate a ramp signal having a frequency corresponding to the sampling count Mult_num as a ramp signal RMPH having a higher frequency.
  • FIG. 16 is a diagram illustrating a setting example of the number of times of sampling in the second embodiment of the present technology. For example, when the sampling count upper limit value Multi_max_num is “4” and the weighting factor Multi_weight is “0”, “1” is set as the sampling count Mult_num. In addition, when the sampling number upper limit value Multi_max_num is “4” and the weighting factor Multi_weight is “1”, “2” is set as the sampling number Multi_num.
  • the solid-state imaging device 200 changes the maximum value of the number of times of sampling based on the statistic of the light-shielded pixel signal, so that the noise level estimated from the OPB pixel is used. Sampling can be performed by the number of times.
  • the selector 311 switches the frequency of the ramp signal in two steps depending on whether the signal level of the pixel signal is higher than the threshold value.
  • the switched frequency may be too high or too low, and the image quality may not be sufficiently improved by the two-stage switching.
  • the solid-state imaging device 200 of the third embodiment is different from the first embodiment in that the selector 311 switches the frequency of the ramp signal in three stages.
  • FIG. 17 is a block diagram illustrating a configuration example of the detector 320 according to the third embodiment of the present technology.
  • the detector 320 of the third embodiment differs from that of the first embodiment in that it further includes an AND (logical product) gate 323, a latch circuit 324, and an inverter 325.
  • the timing generator 251 according to the third embodiment generates trigger signals TRG1 and TRG2 that specify different timings. Then, the timing generator 251 supplies the trigger signal TRG1 to the latch circuit 321 and supplies the trigger signal TRG2 to the AND gate 323.
  • the AND gate 323 generates a logical product signal of the trigger signal TRG2 and the comparison result CMP_OUT and supplies it to the enable terminal E of the latch circuit 324.
  • the latch circuit 324 holds the comparison result CMP_OUT at the timing indicated by the signal from the AND gate 323.
  • the latch circuit 324 supplies the hold value to the inverter 325.
  • a gated D latch is used as the latch circuit 324. In the case of the gated D latch, the comparison result CMP_OUT is input to the data input terminal of the latch circuit 324, and the output terminal Q is connected to the inverter 325.
  • the inverter 325 inverts the value held in the latch circuit 324 and supplies the result to the selector 311 as the detection result DET2. Further, the inverter 322 of the third embodiment outputs the detection result DET1 to the selector 311. These inverted values are also supplied to the dividing circuit 314 as enable signals CAL_EN1 and CAL_EN2. Note that the inverters 322 and 325 are examples of logic gates recited in the claims.
  • FIG. 18 is a diagram illustrating an example of the operation of the selector 311 according to the third embodiment of the present technology.
  • the selector 311 further receives a ramp signal RMPM having a frequency intermediate between the ramp signals RMPH and RMPL.
  • the selector 311 selects the low-frequency ramp signal RMPL when the detection result DET2 is output.
  • the selector 311 selects the high-frequency ramp signal RMPH.
  • the selector 311 selects the ramp signal RMPM whose frequency is an intermediate frequency between the ramp signals RMPH and RMPL when the detection result DET1 is output.
  • the selector 311 switches the frequency of the ramp signal in three steps according to the luminance of the pixel.
  • FIG. 19 is a diagram illustrating an example of the operation of the divider circuit 314 according to the first embodiment of the present technology.
  • the division circuit 314 performs the CDS process without dividing the count value CNT of the signal level and outputs the pixel data Dout when both of the enable signals CAL_EN1 and CAL_EN2 are at the low level, that is, when the pixel has high luminance.
  • the division circuit 314 divides the count value CNT of the signal level by the number of samplings (for example, 4 times) for each pixel, CDS processing is performed to output pixel data Dout.
  • the division circuit 314 divides the signal level count value CNT by a predetermined number of samplings (such as twice) less than in the case of high luminance, performs CDS processing, and outputs pixel data Dout.
  • FIG. 20 is a timing chart showing an example of the operation of the solid-state imaging device 200 when the signal level is the highest in the third embodiment of the present technology.
  • the timing control circuit 250 internally generates enable signals CMP_EN1 and CMP_EN2 in order to generate trigger signals TRG1 and TRG2. Then, the timing control circuit 250 generates the trigger signal TRG1 at the timing T15 when the enable signal CMP_EN1 falls. Further, the timing control circuit 250 generates the trigger signal TRG2 at the timing T16 when the enable signal CMP_EN2 falls.
  • These trigger signals TRG1 and TRG2 are timings within the cycle of the ramp signal RMPL having the lowest frequency, and these signals exhibit different threshold values. That is, two different thresholds are used for the signal level. Hereinafter, the higher one of the two thresholds related to the signal level is ThH, and the lower one is ThL.
  • the detector 320 latches the comparison result CMP_OUT when the trigger signals TRG1 and TRG2 are output.
  • the comparison result CMP_OUT is inverted at both time points of the trigger signals TRG1 and TRG2, and is at the low level. For this reason, the low level is latched at timing T15, and a high level detection result DET1 obtained by inverting the low level is output. Also at the timing T16, the low level is latched, and the high level detection result DET2 obtained by inverting the low level is output.
  • the ramp signal is switched to a low frequency at timings T15 and T16.
  • the waveform of the selected ramp signal RMPS in the figure is the same as that of the low frequency ramp signal RMPL. Based on this ramp signal, four AD conversions are performed on the signal level for each pixel, for example, for each pixel.
  • FIG. 21 is a timing chart illustrating an example of the operation of the solid-state imaging device 200 having the intermediate signal level according to the third embodiment of the present technology.
  • the signal level is an intermediate value higher than the threshold value ThL and lower than or equal to the threshold value ThH.
  • the low level detection result DET1 is output at timing T15
  • the high level detection result DET2 is output at timing T16. Since the detection result DET1 is at a low level, the ramp signal RMPM having an intermediate frequency is selected at timing T15. At timing T16, since the detection result DET2 is at the high level, the selection of the ramp signal RMPM is maintained. Based on this ramp signal, AD conversion is performed twice for each pixel, for example, for each pixel with respect to the signal level.
  • FIG. 22 is a timing chart showing an example of the operation of the solid-state imaging device 200 when the signal level is the lowest in the third embodiment of the present technology.
  • a low level detection result DET2 is output at timing T15 and timing T16. Since the detection result DET1 is at a low level, the ramp signal RMPM having an intermediate frequency is selected at timing T15. At timing T16, since the detection result DET2 is at a low level, the ramp signal RMPL having the lowest frequency is selected. Based on this ramp signal, one AD conversion is performed on the signal level for each pixel, for example, for each pixel.
  • the selector 311 switches the frequency of the ramp signal in three steps based on the comparison result with two threshold values, but switches the frequency in four steps or more based on the comparison result with three or more threshold values. You can also. In this case, similarly, the lower the signal level of the pixel signal (that is, the higher the luminance), the lower the frequency of the ramp signal is selected.
  • the maximum value of the number of samplings can be set based on the statistic of the light-shielded pixel signal.
  • the selector 311 switches the frequency of the ramp signal in three steps based on the comparison result between the pixel signal and the two threshold values, so that the selector 311 switches the frequency of the ramp signal in two steps.
  • the frequency can be finely controlled. Thereby, the image quality of image data can be further improved.
  • the comparison result CMP_OUT is monitored by the detector 320 to detect whether or not the level of the pixel signal is higher than the threshold value, but the count value CNT is used instead of the comparison result CMP_OUT. It can also be monitored.
  • the detector of the fourth embodiment is different from that of the first embodiment in that it detects whether the signal level of the pixel signal is higher than a threshold value based on the count value CNT.
  • FIG. 23 is a block diagram illustrating a configuration example of the AD converter 310 according to the fourth embodiment of the present technology.
  • the AD converter 310 of the fourth embodiment is different from that of the first embodiment in that a detector 330 is provided instead of the detector 320.
  • the counter 313 of the fourth embodiment adds the count value CNT to the division circuit 314 and further outputs it to the detector 330.
  • the detector 330 compares the digital value when the analog threshold value is AD-converted with the count value CNT. Then, the detector 330 generates a detection result DET and an enable signal CAL_EN based on the comparison result.
  • the number of samplings can be set based on the statistic of the light-shielded pixel signal as in the second embodiment. Further, the frequency can be switched in three stages as in the third embodiment.
  • the detector 330 uses the comparison result CMP_OUT to detect whether the signal level of the pixel signal is higher than the threshold value based on the count value CNT.
  • the detection result DET can be generated without the need.
  • the detector 320 generates the detection result DET from the comparison result CMP_OUT using the latch circuit 321 and the inverter 322.
  • the detection result DET is generated without using the latch circuit 321 or the like. You can also The detector of the fifth embodiment is different from the first embodiment in that the detection result DET is generated by a comparator instead of the latch circuit 321.
  • FIG. 24 is a block diagram illustrating a configuration example of the AD converter 310 according to the fourth embodiment of the present technology.
  • the AD converter 310 according to the fourth embodiment differs from the first embodiment in that a detector 340 is provided instead of the detector 320.
  • a detector 340 is provided with a comparator 341.
  • the comparator 341 compares the bias voltage Vbias indicating the threshold value with the pixel signal Vin.
  • the comparator 341 outputs the comparison result as a detection result DET and an enable signal CAL_EN.
  • the maximum number of samplings can be set based on the statistic of the light-shielded pixel signal as in the second embodiment. Further, the frequency can be switched in three stages as in the third embodiment.
  • the detector 340 compares the bias voltage indicating the threshold with the pixel signal to generate the detection result DET.
  • the detection result DET can be generated without using it.
  • the technology according to the present disclosure can be applied to various products.
  • the technology according to the present disclosure is realized as a device that is mounted on any type of mobile body such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, personal mobility, an airplane, a drone, a ship, and a robot. May be.
  • FIG. 25 is a block diagram illustrating a schematic configuration example of a vehicle control system that is an example of a mobile control system to which the technology according to the present disclosure can be applied.
  • the vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001.
  • the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside information detection unit 12030, an in-vehicle information detection unit 12040, and an integrated control unit 12050.
  • a microcomputer 12051, a sound image output unit 12052, and an in-vehicle network I / F (interface) 12053 are illustrated as a functional configuration of the integrated control unit 12050.
  • the drive system control unit 12010 controls the operation of the device related to the drive system of the vehicle according to various programs.
  • the drive system control unit 12010 includes a driving force generator for generating a driving force of a vehicle such as an internal combustion engine or a driving motor, a driving force transmission mechanism for transmitting the driving force to wheels, and a steering angle of the vehicle. It functions as a control device such as a steering mechanism that adjusts and a braking device that generates a braking force of the vehicle.
  • the body system control unit 12020 controls the operation of various devices mounted on the vehicle body according to various programs.
  • the body system control unit 12020 functions as a keyless entry system, a smart key system, a power window device, or a control device for various lamps such as a headlamp, a back lamp, a brake lamp, a blinker, or a fog lamp.
  • the body control unit 12020 can be input with radio waves transmitted from a portable device that substitutes for a key or signals from various switches.
  • the body system control unit 12020 receives input of these radio waves or signals, and controls a door lock device, a power window device, a lamp, and the like of the vehicle.
  • the vehicle outside information detection unit 12030 detects information outside the vehicle on which the vehicle control system 12000 is mounted.
  • the imaging unit 12031 is connected to the vehicle exterior information detection unit 12030.
  • the vehicle exterior information detection unit 12030 causes the imaging unit 12031 to capture an image outside the vehicle and receives the captured image.
  • the vehicle outside information detection unit 12030 may perform an object detection process or a distance detection process such as a person, a car, an obstacle, a sign, or a character on a road surface based on the received image.
  • the imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of received light.
  • the imaging unit 12031 can output an electrical signal as an image, or can output it as distance measurement information. Further, the light received by the imaging unit 12031 may be visible light or invisible light such as infrared rays.
  • the vehicle interior information detection unit 12040 detects vehicle interior information.
  • a driver state detection unit 12041 that detects a driver's state is connected to the in-vehicle information detection unit 12040.
  • the driver state detection unit 12041 includes, for example, a camera that images the driver, and the vehicle interior information detection unit 12040 determines the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041. It may be calculated or it may be determined whether the driver is asleep.
  • the microcomputer 12051 calculates a control target value of the driving force generator, the steering mechanism, or the braking device based on the information inside / outside the vehicle acquired by the vehicle outside information detection unit 12030 or the vehicle interior information detection unit 12040, and the drive system control unit A control command can be output to 12010.
  • the microcomputer 12051 realizes ADAS (Advanced Driver Assistance System) functions including vehicle collision avoidance or impact mitigation, tracking based on inter-vehicle distance, vehicle speed maintenance traveling, vehicle collision warning, or vehicle lane departure warning. It is possible to perform cooperative control for the purpose.
  • ADAS Advanced Driver Assistance System
  • the microcomputer 12051 controls the driving force generator, the steering mechanism, the braking device, and the like based on the information around the vehicle acquired by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040. It is possible to perform cooperative control for the purpose of automatic driving that autonomously travels without depending on the operation.
  • the microcomputer 12051 can output a control command to the body system control unit 12020 based on information outside the vehicle acquired by the vehicle outside information detection unit 12030.
  • the microcomputer 12051 controls the headlamp according to the position of the preceding vehicle or the oncoming vehicle detected by the outside information detection unit 12030, and performs cooperative control for the purpose of anti-glare, such as switching from a high beam to a low beam. It can be carried out.
  • the sound image output unit 12052 transmits an output signal of at least one of sound and image to an output device capable of visually or audibly notifying information to a vehicle occupant or the outside of the vehicle.
  • an audio speaker 12061, a display unit 12062, and an instrument panel 12063 are illustrated as output devices.
  • the display unit 12062 may include at least one of an on-board display and a head-up display, for example.
  • FIG. 26 is a diagram illustrating an example of an installation position of the imaging unit 12031.
  • the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.
  • the imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, at positions such as a front nose, a side mirror, a rear bumper, a back door, and an upper part of a windshield in the vehicle interior of the vehicle 12100.
  • the imaging unit 12101 provided in the front nose and the imaging unit 12105 provided in the upper part of the windshield in the vehicle interior mainly acquire an image in front of the vehicle 12100.
  • the imaging units 12102 and 12103 provided in the side mirror mainly acquire an image of the side of the vehicle 12100.
  • the imaging unit 12104 provided in the rear bumper or the back door mainly acquires an image behind the vehicle 12100.
  • the imaging unit 12105 provided on the upper part of the windshield in the passenger compartment is mainly used for detecting a preceding vehicle or a pedestrian, an obstacle, a traffic light, a traffic sign, a lane, or the like.
  • FIG. 27 shows an example of the shooting range of the imaging units 12101 to 12104.
  • the imaging range 12111 indicates the imaging range of the imaging unit 12101 provided in the front nose
  • the imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided in the side mirrors, respectively
  • the imaging range 12114 The imaging range of the imaging part 12104 provided in the rear bumper or the back door is shown. For example, by superimposing the image data captured by the imaging units 12101 to 12104, an overhead image when the vehicle 12100 is viewed from above is obtained.
  • At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information.
  • at least one of the imaging units 12101 to 12104 may be a stereo camera including a plurality of imaging elements, or may be an imaging element having pixels for phase difference detection.
  • the microcomputer 12051 based on the distance information obtained from the imaging units 12101 to 12104, the distance to each three-dimensional object in the imaging range 12111 to 12114 and the temporal change in this distance (relative speed with respect to the vehicle 12100).
  • a predetermined speed for example, 0 km / h or more
  • the microcomputer 12051 can set an inter-vehicle distance to be secured in advance before the preceding vehicle, and can perform automatic brake control (including follow-up stop control), automatic acceleration control (including follow-up start control), and the like.
  • automatic brake control including follow-up stop control
  • automatic acceleration control including follow-up start control
  • cooperative control for the purpose of autonomous driving or the like autonomously traveling without depending on the operation of the driver can be performed.
  • the microcomputer 12051 converts the three-dimensional object data related to the three-dimensional object to other three-dimensional objects such as a two-wheeled vehicle, a normal vehicle, a large vehicle, a pedestrian, and a utility pole based on the distance information obtained from the imaging units 12101 to 12104. It can be classified and extracted and used for automatic avoidance of obstacles.
  • the microcomputer 12051 identifies obstacles around the vehicle 12100 as obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see.
  • the microcomputer 12051 determines the collision risk indicating the risk of collision with each obstacle, and when the collision risk is equal to or higher than the set value and there is a possibility of collision, the microcomputer 12051 is connected via the audio speaker 12061 or the display unit 12062. By outputting an alarm to the driver and performing forced deceleration or avoidance steering via the drive system control unit 12010, driving assistance for collision avoidance can be performed.
  • At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared rays.
  • the microcomputer 12051 can recognize a pedestrian by determining whether a pedestrian is present in the captured images of the imaging units 12101 to 12104. Such pedestrian recognition is, for example, whether or not the user is a pedestrian by performing a pattern matching process on a sequence of feature points indicating the outline of an object and a procedure for extracting feature points in the captured images of the imaging units 12101 to 12104 as infrared cameras. It is carried out by the procedure for determining.
  • the audio image output unit 12052 When the microcomputer 12051 determines that there is a pedestrian in the captured images of the imaging units 12101 to 12104 and recognizes the pedestrian, the audio image output unit 12052 has a rectangular contour line for emphasizing the recognized pedestrian.
  • the display unit 12062 is controlled so as to be superimposed and displayed.
  • voice image output part 12052 may control the display part 12062 so that the icon etc. which show a pedestrian may be displayed on a desired position.
  • the technology according to the present disclosure can be applied to the imaging unit 12031 among the configurations described above.
  • the imaging device 100 in FIG. 1 can be applied to the imaging unit 12031.
  • the processing procedure described in the above embodiment may be regarded as a method having a series of these procedures, and a program for causing a computer to execute these series of procedures or a recording medium storing the program. You may catch it.
  • a recording medium for example, a CD (Compact Disc), an MD (MiniDisc), a DVD (Digital Versatile Disc), a memory card, a Blu-ray disc (Blu-ray (registered trademark) Disc), or the like can be used.
  • this technique can also take the following structures.
  • a ramp signal supply unit that supplies a ramp signal having a frequency corresponding to the signal level of the pixel signal;
  • a comparator that compares the ramp signal with the pixel signal and outputs a comparison result;
  • a solid-state imaging device comprising: a counter that counts a count value over a period until the comparison result is inverted.
  • the ramp signal supply unit includes: A detector that detects whether the signal level is higher than a predetermined threshold and outputs a detection result;
  • the predetermined threshold value is one, The selector selects one of two ramp signals having different frequencies,
  • the detector is A latch circuit that holds the comparison result as a hold value when a specific timing corresponding to the predetermined threshold has elapsed within a cycle of the lower frequency of the two ramp signals;
  • the solid-state imaging device further comprising: a logic gate that generates the detection result based on the held value and outputs the detection result to the selector.
  • the predetermined threshold includes two different thresholds; The selector selects one of three ramp signals having different frequencies, The detector is A first holding value is stored as the first holding value when the first timing corresponding to one of the two threshold values has passed within the cycle of the ramp signal having the lowest frequency among the plurality of ramp signals.
  • the solid-state imaging device according to (3) further comprising: a logic gate that generates the detection result based on the first and second holding values and outputs the detection result to the selector.
  • a logic gate that generates the detection result based on the first and second holding values and outputs the detection result to the selector.
  • the solid-state imaging device according to any one of (1) to (7), further including a division circuit that divides the count value by a larger divisor as the frequency of the selected ramp signal is higher. (9) further includes a setting unit that sets a maximum value of the number of sampling times for each pixel based on a statistic of the level of the light-shielded pixel signal from each of the plurality of light-shielded pixels that are shielded; The solid-state imaging device according to any one of (1) to (8), wherein the pixel signal includes an effective pixel signal from each of a plurality of effective pixels that are not shielded from light and the light-shielded pixel signal.
  • a ramp signal supply unit that supplies a ramp signal having a frequency according to the signal level of the pixel signal; A comparator that compares the ramp signal with the pixel signal and outputs a comparison result; A counter that counts a count value over a period until the comparison result is inverted;
  • An imaging apparatus comprising: a recording unit that records image data generated from the count value.
  • (11) a ramp signal supply procedure for supplying a ramp signal having a frequency corresponding to the signal level of the pixel signal; A comparison procedure for comparing the ramp signal and the pixel signal and outputting a comparison result; And a counting procedure for counting a count value over a period until the comparison result is inverted.
  • Imaging device 110 Imaging lens 120 Recording part 130 Imaging control part 200 Solid-state image sensor 210 Vertical scanning circuit 220 Pixel array part 221 Pixel 222 OPB pixel 223 Normal pixel 230 DAC 240 read current control unit 250 timing control circuit 251 timing generator 252 clock generator 260 horizontal scanning circuit 270 sampling number setting unit 271 OPB dispersion calculation unit 272 OPB average calculation unit 273 weight coefficient acquisition unit 274 sampling number determination unit 275 threshold calculation unit 276 upper limit Count acquisition unit 277 Register 300
  • Column signal processing unit 310 AD converter 311 selector 312, 341 comparator 313 counter 314 division circuit 320, 330, 340 detector 321, 324 latch circuit 322, 325 inverter 323 AND (logical product) gate 350 Memory 360 Sense amplifier 370 Digital operation unit 380 Interface unit 12031 Imaging unit

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  • Transforming Light Signals Into Electric Signals (AREA)

Abstract

La présente invention améliore la qualité d'image tout en maintenant une vitesse de lecture dans un élément d'imagerie à semi-conducteurs comportant un convertisseur analogique/numérique. Cet élément d'imagerie à semi-conducteurs est pourvu d'une unité d'alimentation de signal de lampe, d'un comparateur et d'un compteur. Dans cet élément d'imagerie à semi-conducteurs, l'unité d'alimentation de signal de lampe fournit un signal de lampe d'une fréquence correspondant au niveau de signal d'un signal de pixel. Le comparateur compare le signal de lampe et le signal de pixel, et fournit un résultat de comparaison. Le compteur compte une valeur de comptage sur une période jusqu'à ce que le résultat de la comparaison soit inversé.
PCT/JP2018/046093 2018-03-19 2018-12-14 Élément d'imagerie à semi-conducteurs, dispositif d'imagerie et procédé de commande pour élément d'imagerie à semi-conducteurs Ceased WO2019181110A1 (fr)

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CN115209076A (zh) * 2021-04-14 2022-10-18 三星电子株式会社 成像装置及其操作方法

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TWI885140B (zh) 2020-06-08 2025-06-01 日商索尼半導體解決方案公司 固態攝像元件
JP7680860B2 (ja) 2021-03-16 2025-05-21 キヤノン株式会社 光電変換装置及び撮像システム
JP7757098B2 (ja) 2021-09-15 2025-10-21 キヤノン株式会社 光電変換装置及びその駆動方法

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