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WO2019163648A1 - Procédé de production de cellule solaire - Google Patents

Procédé de production de cellule solaire Download PDF

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Publication number
WO2019163648A1
WO2019163648A1 PCT/JP2019/005408 JP2019005408W WO2019163648A1 WO 2019163648 A1 WO2019163648 A1 WO 2019163648A1 JP 2019005408 W JP2019005408 W JP 2019005408W WO 2019163648 A1 WO2019163648 A1 WO 2019163648A1
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WIPO (PCT)
Prior art keywords
semiconductor layer
layer
lift
type semiconductor
solar cell
Prior art date
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PCT/JP2019/005408
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English (en)
Japanese (ja)
Inventor
良太 三島
足立　大輔
邦裕 中野
小西　克典
崇 口山
山本　憲治
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Kaneka Corp
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Kaneka Corp
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Priority to JP2020501718A priority Critical patent/JP7281444B2/ja
Publication of WO2019163648A1 publication Critical patent/WO2019163648A1/fr
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F10/00—Individual photovoltaic cells, e.g. solar cells
    • H10F10/10—Individual photovoltaic cells, e.g. solar cells having potential barriers
    • H10F10/16—Photovoltaic cells having only PN heterojunction potential barriers
    • H10F10/164—Photovoltaic cells having only PN heterojunction potential barriers comprising heterojunctions with Group IV materials, e.g. ITO/Si or GaAs/SiGe photovoltaic cells
    • H10F10/165—Photovoltaic cells having only PN heterojunction potential barriers comprising heterojunctions with Group IV materials, e.g. ITO/Si or GaAs/SiGe photovoltaic cells the heterojunctions being Group IV-IV heterojunctions, e.g. Si/Ge, SiGe/Si or Si/SiC photovoltaic cells
    • H10F10/166—Photovoltaic cells having only PN heterojunction potential barriers comprising heterojunctions with Group IV materials, e.g. ITO/Si or GaAs/SiGe photovoltaic cells the heterojunctions being Group IV-IV heterojunctions, e.g. Si/Ge, SiGe/Si or Si/SiC photovoltaic cells the Group IV-IV heterojunctions being heterojunctions of crystalline and amorphous materials, e.g. silicon heterojunction [SHJ] photovoltaic cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F71/00—Manufacture or treatment of devices covered by this subclass
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the present invention relates to a method for manufacturing a solar cell.
  • a solar cell is generally a double-sided electrode type in which electrodes are arranged on both surfaces (light-receiving surface and back surface) of a semiconductor substrate.
  • a back contact (back electrode) type solar cell in which an electrode is disposed only on the back surface as shown in Patent Document 1 has been developed.
  • the back contact type solar cell must be formed by electrically separating the p-type semiconductor layer and the n-type semiconductor layer in the back surface narrower than the area of the double-sided electrode type.
  • the p-type semiconductor layer and the n-type semiconductor layer are electrically separated using laser light. For this reason, a back contact type solar cell has the problem that manufacture becomes very complicated compared with the solar cell of a double-sided electrode type, for example.
  • the present invention has been made to solve the above-described conventional problems, and an object thereof is to easily manufacture a high-performance back contact solar cell.
  • one embodiment of the present invention includes a step of forming a first semiconductor layer of a first conductivity type on one main surface of two main surfaces facing each other in a semiconductor substrate; Forming a lift-off layer including a silicon-based thin film material on one semiconductor layer; selectively removing the lift-off layer and the first semiconductor layer; and one main surface including the lift-off layer and the first semiconductor layer A step of forming a second semiconductor layer of the second conductivity type, and a step of removing the second semiconductor layer covering the lift-off layer by removing the lift-off layer using an etching solution.
  • the step of selectively removing the lift-off layer and the first semiconductor layer includes a step of removing the first semiconductor layer by plasma etching using a gas containing hydrogen as a main component after removing the lift-off layer.
  • a high-performance back contact solar cell is easily manufactured.
  • FIG. 1 is a schematic cross-sectional view partially showing a solar cell according to an embodiment.
  • FIG. 2 is a plan view showing the back main surface of the crystal substrate constituting the solar cell according to the embodiment.
  • FIG. 3 is a partial schematic cross-sectional view showing one step of a method for manufacturing a solar cell according to an embodiment.
  • FIG. 4 is a partial schematic cross-sectional view showing one step of a method for manufacturing a solar cell according to an embodiment.
  • FIG. 5 is a partial schematic cross-sectional view showing one step of a method for manufacturing a solar cell according to an embodiment.
  • FIG. 6 is a partial schematic cross-sectional view showing a modification of the method for manufacturing a solar cell according to an embodiment and showing a step in place of FIG. FIG.
  • FIG. 7 is a partial schematic cross-sectional view showing one step of a method for manufacturing a solar cell according to an embodiment.
  • FIG. 8 is a partial schematic cross-sectional view showing one step of a method for manufacturing a solar cell according to one embodiment.
  • FIG. 9 is a partial schematic cross-sectional view showing one step of a method for manufacturing a solar cell according to one embodiment.
  • FIG. 10 is a partial schematic cross-sectional view showing one step of a method for manufacturing a solar cell according to an embodiment.
  • FIG. 1 is a partial cross-sectional view of a solar cell (cell) according to this embodiment.
  • the solar cell 10 uses a crystal substrate 11 made of silicon (Si).
  • the crystal substrate 11 has two main surfaces 11S (11SU, 11SB) facing each other.
  • the main surface on which light is incident is referred to as the front main surface 11SU
  • the opposite main surface is referred to as the back main surface 11SB.
  • the front main surface 11SU has a light receiving side that is more positively received than the back main surface 11SB and a non-light receiving side that is not actively receiving light.
  • the solar cell 10 is a so-called heterojunction crystal silicon solar cell, and is a back contact type (back electrode type) solar cell in which an electrode layer is disposed on the back main surface 11SB.
  • the solar cell 10 includes a crystal substrate 11, an intrinsic semiconductor layer 12, a conductive semiconductor layer 13 (p-type semiconductor layer 13p, n-type semiconductor layer 13n), a low reflection layer 14, and an electrode layer 15 (transparent electrode layer 17, metal electrode). Layer 18).
  • first conductivity type first conductivity type
  • second conductivity type second conductivity type
  • the crystal substrate 11 may be a semiconductor substrate formed of single crystal silicon or a semiconductor substrate formed of polycrystalline silicon.
  • a single crystal silicon substrate will be described as an example.
  • the conductivity type of the crystal substrate 11 is an n-type single crystal silicon substrate into which an impurity (for example, phosphorus (P) atom) that introduces electrons into silicon atoms is introduced, holes are introduced into the silicon atoms. It may be a p-type single crystal silicon substrate into which impurities to be introduced (for example, boron (B) atoms) are introduced.
  • impurities to be introduced for example, boron (B) atoms
  • the crystal substrate 11 has a texture structure TX (first texture structure) composed of peaks (convex) and valleys (concave) on the surfaces of the two main surfaces 11S from the viewpoint of confining received light. You may have.
  • TX first texture structure
  • the texture structure TX is obtained by, for example, anisotropic etching applying the difference between the etching rate of the crystal substrate 11 with the (100) plane orientation and the etching rate of the (111) plane orientation. Can be formed.
  • the size of the texture structure TX can be defined by the number of vertices (mountains), for example.
  • it is preferably in the range of 50000 / mm 2 or more and 100000 / mm 2 or less, particularly 70000 / mm 2 or more and 85000 / mm 2 or less. A range is preferable.
  • the thickness of the crystal substrate 11 may be 250 ⁇ m or less.
  • the measurement direction when measuring the thickness is a direction perpendicular to the average plane of the crystal substrate 11 (the average plane means a plane of the entire substrate independent of the texture structure TX). Therefore, hereinafter, the vertical direction, that is, the direction in which the thickness is measured is defined as the thickness direction.
  • the thickness of the crystal substrate 11 is 250 ⁇ m or less, the amount of silicon used can be reduced, so that it becomes easy to secure the silicon substrate and the cost can be reduced.
  • the back contact structure that collects holes and electrons generated by photoexcitation in the silicon substrate only on the back side is preferable from the viewpoint of the free path of each exciton.
  • the thickness of the crystal substrate 11 is preferably 50 ⁇ m or more, and more preferably 70 ⁇ m or more.
  • the thickness of the crystal substrate 11 is represented by the distance between straight lines connecting the convex vertices in the light-receiving side and the back surface side. Is done.
  • an intrinsic (i-type) semiconductor layer 12 can be disposed between the crystal substrate 11 and the conductive semiconductor layer 13.
  • the intrinsic semiconductor layer 12 (12U, 12p, 12n) covers both the main surfaces 11S (11SU, 11SB) of the crystal substrate 11, thereby performing surface passivation while suppressing diffusion of impurities into the crystal substrate 11.
  • intrinsic (i-type) is not limited to complete intrinsicity including no conductive impurities, but is “weak” including a small amount of n-type impurities or p-type impurities within a range in which a silicon-based layer can function as an intrinsic layer. Also included are layers that are substantially intrinsic of “n-type” or “weak p-type”.
  • the intrinsic semiconductor layer 12 (12U, 12p, 12n) is not essential, and may be appropriately formed as necessary.
  • the material of the intrinsic semiconductor layer 12 is not particularly limited, but may be an amorphous silicon-based material, which is a hydrogenated amorphous silicon-based thin film (a-Si: H thin film) containing silicon and hydrogen as a thin film. There may be.
  • amorphous as used herein refers to a structure having a long period and no order, that is, not only a complete disorder but also an order having a short period.
  • the thickness of the intrinsic semiconductor layer 12 is not particularly limited, but may be 2 nm or more and 20 nm or less. This is because when the thickness is 2 nm or more, the effect as a passivation layer for the crystal substrate 11 is enhanced, and when the thickness is 20 nm or less, a decrease in conversion characteristics caused by an increase in resistance can be suppressed.
  • the method for forming the intrinsic semiconductor layer 12 is not particularly limited, but a plasma CVD (plasma enhanced chemical vapor deposition) method is used. According to this method, passivation of the substrate surface can be effectively performed while suppressing the diffusion of impurities into the single crystal silicon. Further, in the case of the plasma CVD method, by changing the hydrogen concentration in the intrinsic semiconductor layer 12 in the thickness direction, it is possible to form an energy gap profile effective in recovering carriers.
  • a plasma CVD plasma enhanced chemical vapor deposition
  • the conditions for forming a thin film by plasma CVD include, for example, a substrate temperature of 100 ° C. to 300 ° C., a pressure of 20 Pa to 2600 Pa, and a high frequency power density of 0.003 W / cm 2 to 0.5 W / It may be cm 2 or less.
  • a silicon-containing gas such as monosilane (SiH 4 ) and disilane (Si 2 H 6 ), or those gases and hydrogen (H 2 ). May be a mixed gas.
  • a gas containing a different element such as methane (CH 4 ), ammonia (NH 3 ), or monogermane (GeH 4 ) is added to the above gas, and silicon carbide (SiC), silicon nitride (SiN x). ) Or a silicon compound such as silicon germanium (SIGe), the energy gap of the thin film may be changed as appropriate.
  • a gas containing a different element such as methane (CH 4 ), ammonia (NH 3 ), or monogermane (GeH 4 ) is added to the above gas, and silicon carbide (SiC), silicon nitride (SiN x).
  • SiN x silicon nitride
  • SiGe silicon germanium
  • Examples of the conductive semiconductor layer 13 include a p-type semiconductor layer 13p and an n-type semiconductor layer 13n. As shown in FIG. 1, the p-type semiconductor layer 13p is formed on a part of the back main surface 11SB of the crystal substrate 11 via the intrinsic semiconductor layer 12p. N-type semiconductor layer 13n is formed on the other part of the back main surface of crystal substrate 11 with intrinsic semiconductor layer 12n interposed. That is, the intrinsic semiconductor layer 12 is interposed between the p-type semiconductor layer 13p and the crystal substrate 11 and between the n-type semiconductor layer 13n and the crystal substrate 11 as an intermediate layer that plays a role of passivation.
  • the thicknesses of the p-type semiconductor layer 13p and the n-type semiconductor layer 13n are not particularly limited, but may be 2 nm or more and 20 nm or less. This is because when the thickness is 2 nm or more, the effect as a passivation layer for the crystal substrate 11 is enhanced, and when the thickness is 20 nm or less, a decrease in conversion characteristics caused by an increase in resistance can be suppressed.
  • the p-type semiconductor layer 13p and the n-type semiconductor layer 13n are arranged on the back side of the crystal substrate 11 so that the p-type semiconductor layer 13p and the n-type semiconductor layer 13n are electrically separated.
  • the width of the conductive semiconductor layer 13 may be 50 ⁇ m or more and 3000 ⁇ m or less, and more preferably 80 ⁇ m or more and 500 ⁇ m or less.
  • the gap between the p-type semiconductor layer 13p and the n-type semiconductor layer 13n may be 3000 ⁇ m or less, more preferably 1000 ⁇ m or less (note that the width of the semiconductor layer and the width of the electrode layer described later are Unless otherwise specified, the length of a portion of each patterned layer is intended to be the length in a direction perpendicular to the extending direction of the linear portion, for example, by patterning).
  • the p-type semiconductor layer 13p may be narrower than the n-type semiconductor layer 13n.
  • the width of the p-type semiconductor layer 13p may be not less than 0.5 times and not more than 0.9 times the width of the n-type semiconductor layer 13n, and is not less than 0.6 times and not more than 0.8 times. More preferred.
  • the low reflection layer 14 is a layer that suppresses reflection of light received by the solar cell 10.
  • the material of the low reflection layer 14 is not particularly limited as long as it is a light-transmitting material that transmits light.
  • distributed the nanoparticle of oxides such as a zinc oxide or a titanium oxide, for example.
  • the electrode layer 15 is formed so as to cover the p-type semiconductor layer 13p or the n-type semiconductor layer 13n, and is electrically connected to each conductive semiconductor layer 13. Thereby, the electrode layer 15 functions as a transport layer for guiding carriers generated in the p-type semiconductor layer 13p or the n-type semiconductor layer 13n.
  • the electrode layers 15p and 15n corresponding to the semiconductor layers 13p and 13n are spaced apart to prevent a short circuit between the p-type semiconductor layer 13p and the n-type semiconductor layer 13n.
  • the electrode layer 15 may be formed of only a metal having high conductivity. Further, from the viewpoint of electrical connection between the p-type semiconductor layer 13p and the n-type semiconductor layer 13n, or from the viewpoint of suppressing the diffusion of atoms into both the semiconductor layers 13p and 13n of the metal that is the electrode material, The electrode layer 15 made of a conductive oxide may be provided between the metal electrode layer and the p-type semiconductor layer 13p and between the metal electrode layer and the n-type semiconductor layer 13n.
  • the electrode layer 15 formed of a transparent conductive oxide is referred to as a transparent electrode layer 17, and the metal electrode layer 15 is referred to as a metal electrode layer 18.
  • an electrode layer formed on the comb back portion May be referred to as a bus bar portion, and an electrode layer formed on the comb tooth portion may be referred to as a finger portion.
  • the material of the transparent electrode layer 17 is not particularly limited.
  • TiO x titanium oxide
  • TiO x tin oxide
  • a transparent conductive oxide to which SnO x ), tungsten oxide (WO x ), molybdenum oxide (MoO x ), or the like is added at a concentration of 1 wt% or more and 10 wt% or less can be given.
  • the thickness of the transparent electrode layer 17 may be 20 nm or more and 200 nm or less.
  • a method for forming a transparent electrode layer suitable for this thickness for example, a physical organic vapor deposition (PVD: physical vapor deposition) method such as a sputtering method, or a metal organic using a reaction between an organic metal compound and oxygen or water.
  • PVD physical organic vapor deposition
  • MOCVD Metal-Organic-Chemical-Vapor-Deposition
  • the material of the metal electrode layer 18 is not particularly limited, and examples thereof include silver (Ag), copper (Cu), aluminum (Al), and nickel (Ni).
  • the thickness of the metal electrode layer 18 may be 1 ⁇ m or more and 80 ⁇ m or less.
  • Examples of a method for forming the metal electrode layer 18 suitable for this thickness include a printing method in which a material paste is printed by inkjet or screen printing, or a plating method.
  • the present invention is not limited to this, and when a vacuum process is employed, vapor deposition or sputtering may be employed.
  • the width of the comb tooth portions in the p-type semiconductor layer 13p and the n-type semiconductor layer 13n may be approximately the same as the width of the metal electrode layer 18 formed on the comb tooth portions.
  • the width of the metal electrode layer 18 may be narrower than the width of the comb tooth portion.
  • the width of the metal electrode layer 18 may be wider than the width of the comb tooth portion as long as the leakage current between the metal electrode layers 18 is prevented.
  • the intrinsic semiconductor layer 12, the conductive semiconductor layer 13, the low reflection layer 14, and the electrode layer 15 are stacked on the back side main surface 11SB of the crystal substrate 11, and the passivation and conductive properties of each bonding surface are stacked.
  • a predetermined annealing treatment is performed for the purpose of suppressing the generation of defect levels at the type semiconductor layer 13 and its interface and crystallizing the transparent conductive oxide in the transparent electrode layer 17.
  • Examples of the annealing process according to the present embodiment include an annealing process in which the crystal substrate 11 on which each of the above layers is formed is placed in an oven heated to 150 ° C. or more and 200 ° C. or less.
  • the atmosphere in the oven may be air, and more effective annealing treatment can be performed by using hydrogen or nitrogen as the atmosphere.
  • this annealing treatment may be an RTA (Rapid Thermal Annealing) process in which the crystal substrate 11 on which each layer is formed is irradiated with infrared rays by an infrared heater.
  • RTA Rapid Thermal Annealing
  • a crystal substrate 11 having a texture structure TX on each of a front main surface 11SU and a back main surface 11SB is prepared.
  • an intrinsic semiconductor layer 12 ⁇ / b> U is formed on the front main surface 11 ⁇ / b> SU of the crystal substrate 11.
  • the antireflection layer 14 is formed on the formed intrinsic semiconductor layer 12U.
  • silicon nitride (SiN x ) or silicon oxide (SiO x ) having a suitable light absorption coefficient and refractive index is used from the viewpoint of a light confinement effect for confining incident light.
  • the p-type semiconductor layer 13 p is formed on the back main surface 11 SB of the crystal substrate 11.
  • the intrinsic semiconductor layer 12p using, for example, i-type amorphous silicon is formed between the crystal substrate 11 and the p-type semiconductor layer 13p. Therefore, in the present embodiment, the step of forming the p-type semiconductor layer (first semiconductor layer) 13p is performed on one main surface of the crystal substrate (semiconductor substrate) 11 before the p-type semiconductor layer 13p is formed. (Back side main surface) The process includes forming an intrinsic semiconductor layer (first intrinsic semiconductor layer) 12p on 11S.
  • the p-type semiconductor layer 13p is a silicon layer to which a p-type dopant (boron (B) or the like) is added, and is preferably formed of amorphous silicon from the viewpoint of suppressing impurity diffusion or suppressing series resistance.
  • a p-type dopant boron (B) or the like
  • it is a silicon layer to which an n-type dopant (phosphorus (P) or the like) is added, and is similar to the p-type semiconductor layer 13p. It is preferably formed of crystalline silicon.
  • a silicon-containing gas such as monosilane (SiH 4 ) or disilane (Si 2 H 6 ), or a mixed gas of a silicon-based gas and hydrogen (H 2 ) may be used.
  • the dopant gas diborane (B 2 H 6 ) or the like can be used for forming the p-type semiconductor layer 13p, and phosphine (PH 3 ) or the like can be used for forming the n-type semiconductor layer.
  • impurities such as boron (B) or phosphorus (P) may be small, a mixed gas obtained by diluting a dopant gas with a raw material gas may be used.
  • the p-type semiconductor layer 13p or the n-type semiconductor layer 13n may be compounded by adding a gas containing any element.
  • lift-off layers LF (LF1, LF2) are formed on the formed p-type semiconductor layer 13p.
  • the lift-off layer LF is removed by patterning in the step shown in FIG. 7 described later, and further removed at the same time as the n-type semiconductor layer 13n in the step shown in FIG.
  • the lift-off layer LF is formed on the back main surface 11SB of the crystal substrate 11 in the order of the first lift-off layer LF1 and the second lift-off layer LF2.
  • the first lift-off layer LF1 may be mainly composed of silicon oxide (SiO x ) or silicon nitride (SiN x ).
  • the refractive index may be 1.45 or more and 1.90 or less. Further, in this case, if the refractive index of the first lift-off layer LF1 is 1.50 or more and 1.80 or less, particularly 1.55 or more and 1.72 or less, the suppression of undercut in the step shown in FIG. From the viewpoint of balance with lift-off in the step shown in FIG. This is because the difference in refractive index depends on the silicon content in the layer and is a factor affecting the etching rate of the lift-off layer LF.
  • the refractive index may be 1.60 or more and 2.10 or less.
  • the refractive index of the first lift-off layer LF1 in this case is preferably 1.70 or more and 2.00 or less, particularly 1.80 or more and 1.95 or less.
  • the above refractive index is preferably fitted from a dielectric function in spectroscopic ellipsometry measurement and a numerical value in light having a wavelength of 632 nm is extracted.
  • the structure of the first lift-off layer LF1 is not particularly limited, and examples thereof include a structure containing physical or chemical voids (defects) inside the layer.
  • the first lift-off layer LF1 is formed by a CVD (Chemical Vapor Deposition) method
  • the growing particles grow so as to be stacked substantially perpendicular to the film formation surface.
  • a large number of particle bodies formed of the grown particles are generated, and voids may be generated between these particle bodies.
  • the etching solution may easily enter the layer, and thus the etching rate may be increased. For this reason, the time of the below-mentioned lift-off process can be shortened.
  • the second lift-off layer LF2 may be hydrogenated amorphous silicon.
  • the second lift-off layer LF2 plays a role of a resist, so that a photoresist composed of an organic substance is not necessary, which is preferable.
  • the thickness of the lift-off layer LF may be 20 nm or more and 600 nm or less as a whole in a region that is not shielded by the mask 20 described later. In particular, the thickness of the lift-off layer LF is preferably 50 nm or more and 450 nm or less.
  • the second lift-off layer LF2 is preferably about 10 nm to 20 nm in a region not shielded by the mask 20, and is 5 nm or less, particularly preferably 3 nm or less, in a region shielded by the mask 20.
  • the lift-off layer LF has a laminated structure of three or more layers, it is preferable to use hydrogenated amorphous silicon for the upper lift-off layer.
  • the intrinsic semiconductor layer 12p, the p-type semiconductor layer 13p, and the lift-off layer LF (LF1, LF2) are formed in the process shown in FIG.
  • a mask 20 for selectively forming a film on the etching region may be disposed above the main surface 11SB. That is, as shown in FIG. 6, the region to be removed by patterning may be a structure shielded by the mask 20.
  • the reaction gas wraps around the region shielded by the mask 20, the thicknesses of the intrinsic semiconductor layer 12p, the p-type semiconductor layer 13p, and the lift-off layer LF on the crystal substrate 11 are as follows. Is smaller than the unshielded area.
  • the step of selectively removing the p-type semiconductor layer (first semiconductor layer) 13p shown in FIG. 7 (hereinafter referred to as a patterning step), the intrinsic semiconductor layer 12p, the p-type semiconductor layer 13p, and the lift-off Removal of the layer LF is facilitated.
  • the mask 20 is held so as to be spaced from the back side main surface 11SB of the crystal substrate 11 and not to contact the back side main surface 11SB.
  • the distance between the back surface of the mask 20 and the back main surface 11SB of the crystal substrate 11 is not particularly limited, but can be set to about 0.5 mm or more and 1.2 mm or less as an example.
  • the p-type semiconductor layer 13p and the lift-off layer LF formed in the step shown in FIG. 5 are removed by patterning.
  • a known method can be used, and patterning using an etching solution is preferable.
  • the back main surface 11SB of the crystal substrate 11 also has the texture structure TX from the viewpoint of giving priority to light capturing efficiency. In this case, the patterning process using a laser beam becomes somewhat difficult from the viewpoint of productivity.
  • the first lift-off layer LF1 and the second lift-off layer LF2 formed in the step shown in FIG. 5 are etched with hydrofluoric acid and a basic aqueous solution that generates hydroxide ions, respectively.
  • the thickness of the second lift-off layer LF2 made of hydrogenated amorphous silicon located at the upper portion is extremely small. For this reason, since there are many pinholes in this shielding region, the first lift-off layer LF1 and the second lift-off layer LF2 can be patterned only with hydrofluoric acid.
  • plasma etching in which a gas containing hydrogen as a main component is introduced may be used for etching the intrinsic semiconductor layer 12p and the p-type semiconductor layer 13p.
  • a gas containing hydrogen (H 2 ) as a main component is introduced into the crystal substrate 11 placed in a vacuum chamber, plasma is generated using a high frequency power source, and etching is performed using the generated plasma.
  • the main component here indicates that hydrogen is 90% by volume or more with respect to the total amount of gas introduced into the vacuum chamber.
  • the volume ratio of hydrogen is more preferably 95% or more.
  • the introduced gas species other than hydrogen include SiH 4 and CH 4 .
  • the intrinsic semiconductor layer 12p can be etched to expose the crystal substrate 11 in the patterning region. If it does in this way, the fall of the lifetime of the carrier generate
  • an n-type semiconductor layer 13n is formed.
  • the n-type semiconductor layer 13n can be formed on the entire surface on the back main surface 11SB of the crystal substrate 11. That is, the n-type semiconductor layer 13n is also formed on the lift-off layer LF.
  • an intrinsic semiconductor layer 12n is formed between the crystal substrate 11 and the n-type semiconductor layer 13n.
  • the n-type semiconductor layer 13n covers not only the upper surface of the lift-off layer LF but also the side surfaces (end surfaces) of the lift-off layer LF, the p-type semiconductor layer 13p, and the intrinsic semiconductor layer 12p via the intrinsic semiconductor layer 12n. It is formed.
  • the step of forming the n-type semiconductor layer (second semiconductor layer) 13n includes the lift-off layer LF of the crystal substrate (semiconductor substrate) 11 before the n-type semiconductor layer 13n is formed. a step of forming an intrinsic semiconductor layer (second intrinsic semiconductor layer) 12n on one main surface (back side main surface) 11S including the p-type semiconductor layer.
  • a step of cleaning the surface of the crystal substrate 11 exposed in the patterning step of FIG. 7 may be provided before forming the intrinsic semiconductor layer 12n. Absent.
  • the cleaning process may be performed with, for example, hydrofluoric acid for the purpose of removing defects and impurities generated on the surface of the crystal substrate 11 in the patterning process.
  • the lift-off layer LF and the lift-off layer LF are formed.
  • the intrinsic semiconductor layer 12n and the n-type semiconductor layer 13n thus formed are simultaneously removed. While the photolithography method is used in the patterning process shown in FIG. 7, a resist coating process such as photolithography and a developing process are not required in this process. For this reason, pattern formation with respect to the n-type semiconductor layer 13n can be easily performed.
  • hydrofluoric acid is used as an etching solution in this step.
  • the transparent electrode layer 17 (17p, 17n) is formed so as to generate the separation groove 25.
  • the transparent electrode layer 17 (17p, 17n) may be formed as follows instead of the sputtering method. For example, a transparent conductive oxide film is formed on the entire surface of the back main surface 11SB without using a mask, and then the transparent conductive film is formed on the p-type semiconductor layer 13p and the n-type semiconductor layer 13n by photolithography.
  • etching may be performed to leave the conductive oxide film.
  • etching may be performed to leave the conductive oxide film.
  • a linear metal electrode layer 18 (18p, 18n) is formed on the transparent electrode layer 17 by using, for example, a mesh screen (not shown) having an opening.
  • the back junction solar cell 10 is formed.
  • the lift-off layer LF is a multi-layer type, but is not limited thereto.
  • a single lift-off layer LF may be used. Note that such a single layer is preferably formed of the first lift-off layer LF1.
  • Crystal substrate a single crystal silicon substrate having a thickness of 200 ⁇ m was employed as the crystal substrate. Anisotropic etching was performed on both main surfaces of the single crystal silicon substrate. As a result, a pyramidal texture structure was formed on the crystal substrate.
  • the crystal substrate was introduced into a CVD apparatus, and an intrinsic semiconductor layer (thickness 8 nm) made of silicon was formed on both main surfaces of the introduced crystal substrate.
  • the film formation conditions were a substrate temperature of 150 ° C., a pressure of 120 Pa, a flow rate ratio of SiH 4 / H 2 of 3/10, and a power density of 0.011 W / cm 2 .
  • the film formation conditions were a substrate temperature of 150 ° C., a pressure of 60 Pa, a flow rate ratio of SiH 4 / B 2 H 6 of 1/3, and a power density of 0.01 W / cm 2 .
  • the flow rate of the B 2 H 6 gas in this example is a flow rate of the diluted gas obtained by diluting B 2 H 6 to 5000 ppm with H 2 .
  • lift-off layer Next, two lift-off layers were formed on the p-type semiconductor layer.
  • the lift-off layer was formed with the following two types of compositions.
  • silicon oxide (SiO x ) was formed to a thickness of 200 nm (a region without mask shielding) using a plasma CVD apparatus.
  • the substrate temperature was 150 ° C.
  • the pressure was 0.9 kPa
  • the flow rate ratio of SiH 4 / CO 2 / H 2 was 1/10/750
  • the power density was 0.15 W / cm 2 .
  • hydrogenated amorphous silicon was formed as a second lift-off layer on the first lift-off layer with a film thickness of 15 nm (region without mask shielding) using a plasma CVD apparatus.
  • the substrate temperature was 150 ° C.
  • the pressure was 120 Pa
  • the flow rate ratio of SiH 4 / H 2 was 3/10
  • the power density was 0.011 W / cm 2 .
  • silicon nitride (SiN x ) was formed to a thickness of 200 nm (region without mask shielding) using a plasma CVD apparatus.
  • the substrate temperature was 150 ° C.
  • the pressure was 0.2 kPa
  • the flow ratio of SiH 4 / HN 3 / H 2 was 1/4/50
  • the power density was 0.15 W / cm 2 .
  • hydrogenated amorphous silicon was formed as a second lift-off layer on the first lift-off layer with a film thickness of 15 nm (region without mask shielding) using a plasma CVD apparatus.
  • the substrate temperature was 150 ° C.
  • the pressure was 120 Pa
  • the flow rate ratio of SiH 4 / H 2 was 3/10
  • the power density was 0.011 W / cm 2 .
  • the film formation conditions were a substrate temperature of 150 ° C., a pressure of 60 Pa, a flow rate ratio of SiH 4 / PH 3 of 1/2, and a power density of 0.01 W / cm 2 .
  • the flow rate of the PH 3 gas in this example is the flow rate of the diluted gas in which PH 3 is diluted to 5000 ppm with H 2 .
  • an oxide film (film thickness: 100 nm) serving as a base of the transparent electrode layer was formed on the conductive semiconductor layer of the crystal substrate.
  • the transparent conductive oxide indium oxide (ITO) containing tin oxide at a concentration of 10% by weight was used as a target.
  • a mixed gas of argon (Ar) and oxygen (O 2 ) was introduced into the chamber of the sputtering apparatus, and the pressure in the chamber was set to 0.6 Pa. The mixing ratio of argon and oxygen was set such that the resistivity was the lowest (so-called bottom).
  • film formation was performed at a power density of 0.4 W / cm 2 using a DC power source.
  • etching was performed by photolithography so as to leave only the transparent conductive oxide film on the p-type semiconductor layer and the n-type semiconductor layer, thereby forming a transparent electrode layer.
  • the transparent electrode layer formed by this etching prevented conduction between the transparent conductive oxide film on the p-type semiconductor layer and the transparent conductive oxide film on the n-type semiconductor layer.
  • a silver paste (manufactured by Fujikura Kasei Co., Ltd .: Dotite FA-333) was screen-printed on the transparent electrode layer without dilution, and a heat treatment was performed in an oven at a temperature of 150 ° C. for 60 minutes. Thereby, the metal electrode layer was formed.
  • the thickness of the lift-off layer and the etching state were measured by using a SEM (Field Emission Scanning Electron Microscope S4800: manufactured by Hitachi High-Technologies Corporation) at a magnification of 100,000 times. After the p-type semiconductor layer patterning step, “ ⁇ ” was given when the etching was performed according to the designed patterning removal region, and “X” was given when the lift-off layer was excessively etched.
  • Examples 1 to 4 and Comparative Example 2 hydrogen plasma etching is used for etching the p-type semiconductor layer and the intrinsic semiconductor layer. However, in Comparative Example 2, although the mask is arranged, the thickness of each layer in the shielding region is increased. In Comparative Examples 1 and 3, hydrogen plasma etching is not performed.
  • Comparative Example 1 since hydrogen plasma etching was not performed, the p-type semiconductor layer was not sufficiently patterned in the p-type semiconductor layer patterning step. In Comparative Example 2, since the lift-off layer was removed in the p-type semiconductor layer patterning step and evaluation in the subsequent lift-off step was impossible, “ ⁇ ” was given.
  • the refractive index of the thin film formed on the glass substrate under the same conditions was determined by measuring using a spectroscopic ellipsometry (trade name M2000: manufactured by JA Woollam). From the fitting result, the refractive index of light having a wavelength of 632 nm was extracted.
  • Examples 1 and 2 silicon oxide was used for the first lift-off layer. In Examples 3 and 4, silicon nitride was used for the first lift-off layer.
  • Comparative Example 3 ozone / hydrofluoric acid in which 20 ppm of ozone was mixed with 5.5% by weight of hydrofluoric acid in patterning removal of the intrinsic semiconductor layer and the p-conductivity type semiconductor layer in the p-type semiconductor layer patterning step It was immersed in a liquid. That is, wet etching was performed.
  • the intrinsic semiconductor layer, the p-type semiconductor layer and the lift-off layer are shielded (masked) on the region to be removed by patterning.
  • the film thickness on these regions becomes small. Thereby, it turned out that favorable patterning can be easily performed by performing the subsequent plasma etching process.
  • Comparative Example 3 although the thickness of the patterning removal portion was reduced by film formation using a mask, the intrinsic semiconductor layer and the p-type semiconductor layer were removed with ozone / hydrofluoric acid, and the lift-off layer was also removed at the same time. It was nonconforming.

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  • Photovoltaic Devices (AREA)

Abstract

L'invention concerne un procédé comprenant : une étape de formation d'une première couche semi-conductrice (13p) d'un premier type conducteur sur une surface principale d'un substrat cristallin (11) ; une étape de formation d'une couche de décollement (LF) qui contient un matériau de film mince de silicium sur la première couche semi-conductrice ; une étape consistant à retirer sélectivement la couche de décollement et la première couche semi-conductrice ; une étape consistant à former une seconde couche semi-conductrice (13n) d'un second type de conductivité sur ladite surface principale contenant la couche de décollement et la première couche semi-conductrice ; et une étape consistant à retirer la seconde couche semi-conductrice qui recouvre la couche de décollement en retirant la couche de décollement à l'aide d'une solution de gravure. L'étape de retrait sélectif de la couche de décollement et de la première couche semi-conductrice comprend une étape de retrait de la première couche semi-conductrice, par gravure au plasma par introduction d'un gaz ayant de l'hydrogène en tant que composant principal de celui-ci, après retrait de la couche de décollement.
PCT/JP2019/005408 2018-02-23 2019-02-14 Procédé de production de cellule solaire Ceased WO2019163648A1 (fr)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11211519B2 (en) * 2018-02-23 2021-12-28 Kaneka Corporation Method for manufacturing solar cell
CN117712212A (zh) * 2024-02-05 2024-03-15 天合光能股份有限公司 太阳能电池和太阳能电池的制造方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03171725A (ja) * 1989-11-14 1991-07-25 Advanced Micro Devices Inc ｎ型、ｐ型および真性シリコンを同じウェーハ上で実質的に同じ速度でエッチングするための方法
US5286340A (en) * 1991-09-13 1994-02-15 University Of Pittsburgh Of The Commonwealth System Of Higher Education Process for controlling silicon etching by atomic hydrogen
WO2015060432A1 (fr) * 2013-10-25 2015-04-30 シャープ株式会社 Dispositif de conversion photoélectrique
WO2017217219A1 (fr) * 2016-06-15 2017-12-21 株式会社カネカ Cellule solaire et procédé de production de ladite cellule, et module de cellule solaire

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03171725A (ja) * 1989-11-14 1991-07-25 Advanced Micro Devices Inc ｎ型、ｐ型および真性シリコンを同じウェーハ上で実質的に同じ速度でエッチングするための方法
US5286340A (en) * 1991-09-13 1994-02-15 University Of Pittsburgh Of The Commonwealth System Of Higher Education Process for controlling silicon etching by atomic hydrogen
WO2015060432A1 (fr) * 2013-10-25 2015-04-30 シャープ株式会社 Dispositif de conversion photoélectrique
WO2017217219A1 (fr) * 2016-06-15 2017-12-21 株式会社カネカ Cellule solaire et procédé de production de ladite cellule, et module de cellule solaire

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11211519B2 (en) * 2018-02-23 2021-12-28 Kaneka Corporation Method for manufacturing solar cell
CN117712212A (zh) * 2024-02-05 2024-03-15 天合光能股份有限公司 太阳能电池和太阳能电池的制造方法
CN117712212B (zh) * 2024-02-05 2024-04-23 天合光能股份有限公司 太阳能电池和太阳能电池的制造方法

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