WO2019161710A1 - Startup circuit - Google Patents

Abstract

Provided by the present invention is a startup circuit; a voltage limiting circuit consisting of a p-channel metal-oxide semiconductor (P-MOS) transistor circuit, a voltage stabilizing circuit or a voltage clamping circuit controls the output voltage range so as to ensure that the output voltage meets the latter-stage ultra-wide input voltage range and the operating voltage range of a latter-stage boost circuit of a power source module startup circuit. The input voltage is sampled by means of an adjustable driving circuit to ensure that the startup circuit does not affect latter-stage power supply due to a pressure difference thereof during low voltage operation. During high voltage operation, the output voltage may be controlled within a voltage range to ensure that the output voltage of the startup circuit within the operating voltage range meets the operating voltage range of the latter-stage boost circuit. Meanwhile, the loss of circuit operation state is extremely low.

Description

Start circuit Technical field

The invention relates to a switching power supply starting circuit, in particular to a starting circuit for supplying power to a control circuit or a control IC of a power stage circuit or for supplying a power supply circuit of a startup stage.

Background technique

The startup circuit is widely used in the field of switching power supplies. In switching power supply products, whether it is a primary power supply (AC-DC converter) or a secondary power supply (DC-DC converter), it is necessary to obtain energy from the input terminal and provide a stable supply voltage for the subsequent stage control circuit or control IC. Power is supplied to drive the switch on and off by controlling the operation of the circuit to control the inductive device to periodically transfer energy.

In the general switching power supply, in order to solve the problem that the input voltage is lower than the minimum starting voltage of the control circuit or the control IC, the control circuit or the control IC enters an undervoltage state due to the inability to obtain a sufficiently high supply voltage, causing the corresponding switching power supply to fail to be turned on. A two-stage power supply circuit (such as the branch circuit structure of Figure 11) can be used. The first stage circuit clamps the wide input voltage limit to a lower voltage value, and the second stage circuit passes the boost circuit (generally the BOOST circuit). The voltage of the stage is raised to the normal working voltage of the control circuit or the control IC, so that the switching power supply system starts working; or the single-stage power supply circuit (such as the branch circuit structure of FIG. 12) is used to clamp the wide input voltage limit to a lower level. The voltage value reduces the voltage difference between the output voltages Vo and Vin at a low voltage, and expands the normal operating voltage range in which the Vo meets the control circuit or the control IC at a low voltage, so that the switching power supply system starts working. However, since the voltage difference between the voltage clamping circuit Vin and Vo is too large, the starting voltage of the second stage boosting circuit is limited. The traditional voltage clamp circuit scheme is shown in Figure 2 (the load is the post-stage boost circuit). The circuit works as follows: when the product is energized, the transistor Q1 is turned on, and the emitter current of the transistor Q1 is quickly charged to the capacitor C2. When the capacitor C2 The voltage (that is, the voltage at the positive terminal of the startup circuit supplied to the power supply terminal Vcc of the control IC) climbs to the regulated value of the Zener diode D1 minus the base and emitter conduction voltage drop of the transistor Q1, and the Vcc voltage will The stability no longer increases. When the Vcc voltage reaches the operating voltage of the booster circuit, the booster circuit starts to work, and the power supply voltage of the latter control circuit or the control IC is established. However, when the circuit is operating at low voltage, the transistor Q1 is in the amplification region, Q1 and The voltage drop across resistor R2 is large, limiting the voltage value of Vcc at low voltage, limiting the startup voltage of the boost circuit, which makes the switching power supply system difficult to start when Vin is low. With other types of voltage regulator circuits or voltage clamp circuits, there is also the problem of excessive pressure drop at low pressure.

In summary, the current limited voltage switching power supply startup circuit in the industry is limited to: using a two-stage power supply circuit scheme or a single-stage power supply circuit scheme, the first-stage voltage clamp circuit will have a low-voltage input and output voltage difference. The problem that the boost circuit or the latter control circuit cannot be started cannot meet the starting voltage range from extremely low voltage to high voltage.

Summary of the invention

In view of this, the present invention provides a startup circuit capable of real-time detection of an input voltage. When the input voltage is low, the P-MOS transistor is turned on, so that the voltage difference between the output voltage of the startup circuit and the input voltage is extremely low. The starting voltage of the booster circuit of the latter stage is basically followed by the input voltage, or the operating voltage of the latter stage control circuit or the control IC basically follows the input voltage; when the input voltage is detected to be high, the voltage formed by the voltage stabilizing circuit or the voltage clamping circuit Limit the circuit operation, limit the startup circuit output voltage to the working input voltage range of the post-stage boost circuit, or limit it within the operating voltage range of the latter stage control circuit or control IC.

The invention itself has extremely low loss. When the input voltage is low voltage, the adjustable driving circuit itself has low loss, and at the same time, because of the P-MOS tube, the P-MOS tube is saturated and turned on during low voltage operation, and the on-resistance of the starting circuit is started. The on-resistance is extremely low; when operating at high voltage, the voltage limiting circuit can adopt a voltage clamping circuit that satisfies the low loss, which not only ensures the normal operation of the starting circuit under high input voltage, but also reduces the loss of the starting circuit operation.

A starting circuit according to the present invention comprises a P-MOS tube, an adjustable driving circuit and a voltage limiting circuit; the input end of the adjustable driving circuit is connected to the input voltage Vin, and the input voltage Vin is subjected to voltage sampling to generate a driving. a voltage Vg, the driving voltage Vg is output to a gate of the P-MOS transistor, a source of the P-MOS transistor is connected to an input voltage Vin, and a drain of the P-MOS transistor is connected as an output end of a startup circuit Go to the latter stage circuit to supply power to the subsequent stage circuit; the input end and the output end of the voltage limiting circuit are respectively connected to the source and the drain of the P-MOS tube;

The voltage limiting circuit is a voltage stabilizing circuit that outputs a fixed voltage value, or a voltage limiting circuit that outputs a fixed voltage range; when the clock is stable, the output voltage of the voltage limiting circuit is a fixed voltage or a fixed voltage that meets the normal operation of the latter circuit. range;

The adjustable driving circuit is provided with a determining voltage interval. When the input voltage Vin is smaller than the minimum value of the adjustable driving circuit, the driving voltage Vg outputted by the adjustable driving circuit and the input voltage The Vin voltage difference is greater than the saturation turn-on voltage of the P-MOS transistor, the P-MOS transistor enters the saturation region to conduct, shorts the voltage limiting circuit, and the drain of the P-MOS transistor supplies power to the subsequent circuit;

When the input voltage Vin is within the adjustable voltage interval of the adjustable driving circuit, the voltage difference between the driving voltage Vg outputted by the adjustable driving circuit and the input voltage Vin is gradually decreased, and the P-MOS transistor enters Amplifying the region, and at the same time, the voltage limiting circuit is gradually turned on, and the drain of the P-MOS and the output of the voltage limiting circuit jointly supply power to the subsequent circuit;

When the input voltage Vin is greater than the maximum value of the adjustable voltage interval of the adjustable driving circuit, the driving voltage Vg outputted by the adjustable driving circuit has no voltage difference with the input voltage Vin, and the P-MOS transistor enters As the area is turned off, the output of the voltage limiting circuit supplies power to the subsequent stage circuit.

Preferably, when the input voltage Vin voltage is excessively large, the input voltage of the P-MOS transistor, that is, the driving voltage Vg, and the input voltage Vin of the starting circuit are gradually reduced; and P-MOS is also allowed. The voltage difference between the input voltage of the tube and the input voltage Vin of the starting circuit is changed from a saturation conduction voltage greater than the P-MOS tube to no pressure difference;

When the output voltage Vg of the control circuit is excessive from a low potential to a high potential, the P-MOS transistor is allowed to enter the amplification region from the saturation conduction region and then gradually enter the cut-off region; the P-MOS transistor is also allowed to be turned on from saturation. The state jumps directly to the off state;

When the operating state of the P-MOS transistor changes, the interval in which the voltage limiting circuit and the P-MOS transistor are simultaneously turned on is allowed, and only the P-MOS transistor or the voltage limiting circuit is independently turned on.

Preferably, the voltage limiting circuit includes a first chip, the first chip has a function of converting an input voltage Vin into a stable voltage range output; an input end of the first chip is connected to an input voltage Vin, The ground of the first chip is grounded, and the output of the first chip is connected to the drain of the P-MOS transistor.

Preferably, the voltage limiting circuit includes a second chip, the second chip has a function of converting an input voltage Vin into a fixed output voltage; an input end of the second chip is connected to an input voltage Vin, the second The ground of the chip is grounded, and the output of the second chip is connected to the drain of the P-MOS transistor.

Preferably, the voltage limiting circuit includes a seventh resistor, an eighth resistor, a second NPN transistor, a first capacitor and a first diode; and one end of the seventh resistor is connected to a collector of the second NPN transistor, The other end of the seventh resistor is connected to the input voltage Vin; one end of the eighth resistor is connected to the input voltage Vin, and the other end of the eighth resistor is connected to the base of the second NPN transistor; one end of the first capacitor is connected to the base of the second NPN transistor, The other end of the first capacitor is connected to the ground; the cathode of the first diode is connected to the base of the second NPN transistor, the anode of the first diode is connected to the input ground; and the emitter of the second NPN transistor is connected to the drain of the P-MOS transistor pole.

Preferably, the first diode is a Zener diode.

Preferably, the ground of the starting circuit is shared with an external power supply device and a subsequent circuit.

Preferably, the adjustable driving circuit comprises a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a first NPN transistor and a first PNP transistor; The resistor is connected between the input voltage Vin and the collector of the first NPN transistor; the fifth resistor is connected between the input voltage Vin and the sixth resistor; the other end of the sixth resistor is grounded; the emitter of the first NPN transistor is connected to the fourth resistor One end of the first NPN transistor is connected to the connection point of the fifth resistor and the sixth resistor; the other end of the fourth resistor is grounded; one end of the second resistor is connected to the collector of the first NPN transistor, and the other end of the second resistor is a base of the first PNP transistor is connected; an emitter of the first PNP transistor is connected to the input voltage Vin, and a collector of the first PNP transistor is connected to one end of the first resistor and outputs a driving voltage Vg as an output of the adjustable driving circuit; The other end of the resistor is grounded.

Compared with the prior art, the present invention has the following remarkable effects:

1. The invention adopts a P-MOS tube circuit to control the output voltage of the starting circuit at low voltage, thereby ensuring that the output voltage of the starting circuit is substantially consistent with the input voltage at low voltage, and satisfies the power supply requirement of the low voltage stepping circuit of the latter stage.

2. The circuit structure of the invention adopts a voltage limiting circuit composed of a voltage regulator circuit or a clamp circuit with a wide input voltage range, thereby ensuring that the output voltage of the starting circuit is not too high when the high voltage input is high, and satisfies the high voltage of the boosting circuit of the latter stage. The input voltage range.

3. The invention itself has extremely low loss, and adopts a voltage limiting circuit composed of a low-loss constant current limiting chip. The voltage sampling loss of the adjustable driving circuit is also small, and the circuit loss is not increased due to the circuit characteristics of the overcurrent device itself.

DRAWINGS

Figure 1 is a block diagram of the application of a conventional wide input range startup circuit that satisfies the low voltage input;

Figure 2 is a schematic diagram of a conventional voltage clamping circuit;

Figure 3 is a schematic block diagram of the present invention;

4 is a schematic diagram of an application of a first embodiment of the present invention;

Figure 5 is a schematic circuit diagram of a first embodiment of the present invention;

Figure 6 is a circuit diagram of a third embodiment of the present invention.

Detailed ways

Figure 3 shows a block diagram of the connection following the initial technical solution described above. Explain in detail the three working states of the invention:

1. When the external power supply device works normally and the input voltage is less than the minimum value of the adjustable voltage range of the adjustable drive circuit, the output voltage of the startup circuit and the input voltage have almost no pressure difference.

2. The external power supply device works normally. When the input voltage is within the adjustable voltage range of the adjustable drive circuit, the voltage difference between the output voltage of the startup circuit and the input voltage increases slowly with the increase of the input voltage.

3. The external power supply device works normally. When the input voltage exceeds the maximum value of the adjustable voltage range of the adjustable drive circuit, the output voltage of the startup circuit is stabilized at a voltage value or stabilized in an output voltage range, regardless of the change of the input voltage.

First embodiment

A starting circuit of the present invention comprises a P-MOS transistor TR1, an adjustable driving circuit and a voltage limiting circuit. For each circuit module, the following specific circuits are specifically described with reference to FIG. 5 as follows:

The adjustable driving circuit of the present invention comprises a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a first NPN transistor Q3, and a first PNP transistor Q2. The third resistor R3 is connected between the input voltage Vin and the collector of the first NPN transistor Q3; the fifth resistor R5 is connected between the input voltage Vin and the sixth resistor R6; the other end of the sixth resistor R6 is grounded; The emitter of an NPN transistor Q3 is connected to one end of the fourth resistor R4, the base is connected to the connection point of the fifth resistor R5 and the sixth resistor R6; the other end of the fourth resistor R4 is grounded; one end of the second resistor R2 is connected to the first NPN transistor The collector of Q3 is connected to the base of the first PNP transistor Q2; the emitter of the first PNP transistor Q2 is connected to the input voltage Vin, and the collector of the first PNP transistor Q2 is connected to one end of the first resistor R1 and is adjustable The output terminal of the driving circuit outputs a driving voltage Vg; the other end of the first resistor R1 is grounded.

The gate of the P-MOS transistor TR1 of the present invention is connected to the output end of the adjustable driving circuit, the source of the P-MOS transistor TR1 is connected to the input voltage Vin, and the drain of the P-MOS transistor TR1 is used as the output of the starting circuit. Voltage Vo.

The voltage limiting circuit of the present invention is a voltage clamping circuit that converts the input voltage Vin into a stable voltage range output, including the first chip IC1. The first chip IC1 can be selected with a three-terminal regulator IC 7805. The input end of the first chip IC1 is connected to the input voltage Vin, the ground end of the first chip IC1 is grounded, and the output end of the first chip IC1 is connected to the drain of the P-MOS transistor TR1 as the output voltage Vo of the starting circuit.

The working process of the present invention will be described below with reference to FIG. 5 as follows:

Working state 1 The power supply device works normally, and when the input voltage is less than the minimum value of the adjustable voltage interval of the adjustable driving circuit, the output voltage Vo of the starting circuit and the input voltage Vin have almost no pressure difference:

When the input voltage is less than the minimum value of the adjustable voltage range of the adjustable driving circuit, the NPN transistor Q3 is in the off state, the current flowing through the resistor R3 is small, the collector voltage of the NPN transistor Q3 basically follows the input voltage, and the base of the PNP transistor Q2 The voltage difference from the emitter is very small, the PNP transistor Q2 is turned off, the collector of Q2 is pulled down by the resistor R1; the output signal Vg of the adjustable driving circuit is low, so that the gate and the source of the P-MOS transistor are between The reverse voltage is large, the P-MOS transistor is saturated and turned on, and the voltage limiting circuit is short-circuited. The starting circuit output voltage Vo follows the input Vin, and the voltage difference is the saturation conduction voltage difference of the P-MOS tube, and there is almost no pressure difference.

Working state 2 The power supply device works normally. When the input voltage is within the adjustable voltage range of the adjustable driving circuit, the voltage difference between the output voltage Vo of the starting circuit and the input voltage Vin increases slowly with the increase of the input voltage:

When the input voltage is gradually increased, the NPN transistor Q3 enters the amplification region; the current flowing through the resistor R3 gradually increases, the voltage difference across the resistor R3 gradually increases, and the voltage difference between the base and the emitter of the PNP transistor Q2 gradually increases. The transistor Q2 enters the amplification region, and the current flowing through the collector of Q2 follows the input voltage to increase gradually, and the voltage of the collector collector of Q2 gradually increases with the voltage of the resistor R1; the output signal Vg of the adjustable driving circuit gradually increases, so that the P-MOS tube The reverse voltage between the gate and the source is gradually reduced, the P-MOS transistor enters the amplification region, and the current between Vin and Vo is provided by the P-MOS transistor circuit and IC1 7805; during the slow rise of Vin, the startup is started. The voltage difference between the circuit output voltage Vo and the input voltage Vin gradually increases as the P-MOS transistor enters the amplification region.

In the working state 3, the power supply device works normally, and when the input voltage exceeds the maximum value of the adjustable voltage range of the adjustable driving circuit, the output voltage Vo of the starting circuit is stabilized at a voltage value, which is independent of the change of the input voltage Vin:

When the input voltage exceeds the maximum value of the adjustable voltage range of the adjustable drive circuit, the collector circuit of the NPN transistor Q3 continues to increase, the current flowing through the resistor R3 continues to increase, and the voltage difference between the base and the emitter of the PNP transistor Q2 enters. The saturation conduction interval (PN junction voltage difference), the transistor Q2 is saturated and turned on, the collector follows the input voltage Vin and the voltage difference is small; the output signal Vg of the adjustable driving circuit is approximately equal to the input voltage Vin, so that the gate of the P-MOS tube The voltage difference between the pole and the source is approximately 0, and the P-MOS transistor is turned off; the current between Vin and Vo is directly provided by IC1 7805, and the output voltage of the startup circuit Vo is directly determined by the regulation characteristics of IC1 7805, and The output voltage is stable at 5V.

Second embodiment

Based on the first embodiment, the second embodiment of the present invention can be obtained by modifying the voltage limiting circuit. The adjustable driving circuit and the PNP transistor circuit described in this embodiment are consistent with the first embodiment.

Different from the first embodiment, the voltage limiting circuit of the present invention is a voltage stabilizing circuit including a second chip. The second chip can be any chip that has the function of stabilizing the input voltage to a fixed voltage value output. The second embodiment does not provide a separate figure. The connection relationship of the second chip can be referred to the replacement voltage limiting circuit in FIG. 5. The input end of the second chip is connected to the input voltage Vin, and the second chip is grounded. The terminal is grounded, and the output terminal of the second chip is connected to the drain of the P-MOS transistor TR1 as the output voltage Vo of the startup circuit.

The following three working states of the second embodiment are specifically described below with reference to FIG. 5 (after the second chip replaces the voltage limiting circuit):

This embodiment is substantially the same as the working process of the first embodiment, and the same portions will not be described again. The difference is that the voltage limiting circuit is replaced with the second chip having the voltage stabilizing function. When the voltage limiting circuit operates, the input voltage Vin After the voltage limiting circuit, the output voltage Vo is not stabilized at a value but stabilized in an output voltage range; mainly affects the working state 3, as follows:

When the power supply device works normally and the input voltage exceeds the maximum value of the adjustable voltage range of the adjustable drive circuit, the output voltage Vo of the startup circuit is stabilized in an output voltage range, which is independent of the change of the input voltage:

When the input voltage exceeds the voltage range of the adjustable drive circuit, the collector circuit of the NPN transistor Q3 continues to increase, the current flowing through the resistor R3 continues to increase, and the voltage difference between the base and the emitter of the PNP transistor Q2 enters the saturation conduction. Interval (PN junction voltage difference), transistor Q2 is saturated, the collector follows the input voltage Vin and the voltage difference is small; the output signal Vg of the adjustable driving circuit is approximately equal to the input voltage Vin, so that the gate and source of the P-MOS tube The voltage difference between the poles is approximately 0, and the P-MOS transistor is turned off; the current between Vin and Vo is directly provided by the second chip, and the output voltage Vo of the startup circuit is directly determined by the voltage regulation characteristic of the second chip, and the output is output. The voltage is stable over an output voltage range.

Third embodiment

Based on the first embodiment and the second embodiment, the third embodiment of the present invention can be obtained by modifying the voltage limiting circuit. The voltage limiting circuit of the third embodiment will be described below with reference to FIG. 6 below:

The voltage limiting circuit in this embodiment is also a voltage stabilizing circuit, including a seventh resistor R7, an eighth resistor R8, a second NPN transistor Q4, a first capacitor C1 and a first diode Z1, and the first diode Z1 is available. 10V regulator tube. One end of the seventh resistor R7 is connected to the collector of the second NPN transistor Q4, and the other end is connected to Vin; the other end of the eighth resistor R8 is connected to Vin, and the other end is connected to the base of the second NPN transistor Q4; the first capacitor C1 One end is connected to the base of the second NPN transistor Q4, and the other end is connected to the input ground; the cathode of the first diode Z1 is connected to the base of the second NPN transistor Q4, the anode is connected to the input ground; and the emitter of the second NPN transistor Q4 is connected to the P The drain of the MOS transistor TR1 serves as the output voltage Vo of the startup circuit.

The working principle is the same as that of the first embodiment and the second embodiment. When the voltage limiting circuit is operated, the output voltage Vin is stabilized at a value after the input voltage Vin passes through the voltage limiting circuit, and details are not described herein.

The first resistor R1, the second resistor R2, the third resistor R3, the fourth resistor R4, the fifth resistor R5, the sixth resistor R6, the first NPN transistor Q3, and the first embodiment described in the first embodiment and the second embodiment The controllable adjustment circuit formed by the PNP transistor Q2, as long as the sampling input voltage is low, the voltage difference between Vg and the input voltage Vin is greater than the saturation conduction voltage of the P-MOS tube, and the input voltage is high voltage, Vg and the The input voltage Vin has a voltage difference of 0, and the circuit can be replaced by other forms of judging circuit; the first chip IC1 is composed of a seventh resistor, an eighth resistor, a second NPN transistor Q4, a first capacitor C1 and a first two A voltage limiting circuit composed of a voltage regulator circuit composed of a pole tube Z1 or a second chip having a voltage stabilizing function, as long as it can clamp a voltage limit of a wide input range to a voltage value, or a circuit that satisfies a post-stage boost circuit The range of voltage ranges can be directly replaced by a wide input voltage regulator module, or other types of regulator ICs and regulator circuits, and can achieve the same function.

The above is only a preferred embodiment of the present invention. It should be noted that the above preferred embodiments should not be construed as limiting the present invention. On the basis of the functional block diagram of FIG. 3 of the present invention and the application block diagram of FIG. 1, it is common to the technical field. Other improvements and refinements may be made by those skilled in the art without departing from the spirit and scope of the present invention. These modifications and refinements are also within the scope of the present invention, and the present invention is not described herein again. The scope should be determined by the scope defined by the claims.

Claims (8)

A starting circuit, comprising: a P-MOS tube, an adjustable driving circuit and a voltage limiting circuit; The input end of the adjustable driving circuit is connected to the input voltage Vin, and the input voltage Vin is subjected to voltage sampling to generate a driving voltage Vg, and the driving voltage Vg is output to the gate of the P-MOS transistor, and the P-MOS The source of the tube is connected to the input voltage Vin, and the drain of the P-MOS tube is connected as an output end of the startup circuit to the subsequent stage circuit to supply power to the subsequent stage circuit; the input end and the output end of the voltage limiting circuit are respectively connected to the a source and a drain of the P-MOS transistor; The voltage limiting circuit is a voltage stabilizing circuit that outputs a fixed voltage value, or a voltage limiting circuit that outputs a fixed voltage range; when the clock is stable, the output voltage of the voltage limiting circuit is a fixed voltage or a fixed voltage that meets the normal operation of the latter circuit. range; The adjustable driving circuit is provided with a determining voltage interval. When the input voltage Vin is smaller than the minimum value of the adjustable driving circuit, the driving voltage Vg outputted by the adjustable driving circuit and the input voltage The Vin voltage difference is greater than the saturation turn-on voltage of the P-MOS transistor, the P-MOS transistor enters the saturation region to conduct, shorts the voltage limiting circuit, and the drain of the P-MOS transistor supplies power to the subsequent circuit; When the input voltage Vin is within the adjustable voltage interval of the adjustable driving circuit, the voltage difference between the driving voltage Vg outputted by the adjustable driving circuit and the input voltage Vin is gradually decreased, and the P-MOS transistor enters Amplifying the region, and at the same time, the voltage limiting circuit is gradually turned on, and the drain of the P-MOS and the output of the voltage limiting circuit jointly supply power to the subsequent circuit; When the input voltage Vin is greater than the maximum value of the adjustable voltage interval of the adjustable driving circuit, the driving voltage Vg outputted by the adjustable driving circuit has no voltage difference with the input voltage Vin, and the P-MOS transistor enters As the area is turned off, the output of the voltage limiting circuit supplies power to the subsequent stage circuit. A starting circuit according to claim 1, wherein the input voltage of the P-MOS transistor, that is, the driving voltage Vg and the input of the starting circuit, are allowed when the voltage of the input voltage Vin is excessively large. The voltage Vin pressure difference is gradually decreased; the voltage difference between the input voltage of the P-MOS transistor and the input voltage Vin of the starting circuit is also allowed to be changed from a saturation conduction voltage greater than the P-MOS tube to a no-voltage difference; When the driving voltage Vg is excessive from a low potential to a high potential, the P-MOS transistor is allowed to enter the amplification region from the saturation conduction region and then gradually enter the cut-off region; the P-MOS transistor is also allowed to jump directly from the saturated conduction state. Becomes an off state; When the operating state of the P-MOS transistor changes, the interval in which the voltage limiting circuit and the P-MOS transistor are simultaneously turned on is allowed, and only the P-MOS transistor or the voltage limiting circuit is independently turned on. A start-up circuit according to claim 2, wherein said voltage limiting circuit comprises a first chip, said first chip having a function of converting an input voltage Vin into a stable voltage range output; The input end of the first chip is connected to the input voltage Vin, the ground end of the first chip is grounded, and the output end of the first chip is connected to the drain of the P-MOS tube. A startup circuit according to claim 2, wherein said voltage limiting circuit comprises a second chip, said second chip having a function of converting an input voltage Vin into a fixed output voltage; said second The input end of the chip is connected to the input voltage Vin, the ground end of the second chip is grounded, and the output end of the second chip is connected to the drain of the P-MOS tube. A starting circuit according to claim 2, wherein said voltage limiting circuit comprises a seventh resistor, an eighth resistor, a second NPN transistor, a first capacitor and a first diode; said One end of the seven resistor is connected to the collector of the second NPN transistor, and the other end of the seventh resistor is connected to the input voltage Vin; one end of the eighth resistor is connected to the input voltage Vin, and the other end of the eighth resistor is connected to the base of the second NPN transistor; One end of a capacitor is connected to the base of the second NPN transistor, and the other end of the first capacitor is connected to the ground; the cathode of the first diode is connected to the base of the second NPN transistor, and the anode of the first diode is connected to the ground; The emitter of the two NPN transistor is connected to the drain of the P-MOS transistor. A start-up circuit according to claim 5, wherein said first diode is a Zener diode. A start-up circuit according to any one of claims 1 to 6, wherein the ground of the start-up circuit is shared with an external power supply device and a rear-stage circuit. A starting circuit according to claim 7, wherein said adjustable driving circuit comprises a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, and a first An NPN transistor and a first PNP transistor; the third resistor is connected between the input voltage Vin and the collector of the first NPN transistor; the fifth resistor is connected between the input voltage Vin and the sixth resistor; and the other end of the sixth resistor Grounding; the emitter of the first NPN transistor is connected to one end of the fourth resistor, the base of the first NPN transistor is connected to the connection point of the fifth resistor and the sixth resistor; the other end of the fourth resistor is grounded; The collector of the NPN transistor, the other end of the second resistor is connected to the base of the first PNP transistor; the emitter of the first PNP transistor is connected to the input voltage Vin, and the collector of the first PNP transistor is connected to one end of the first resistor and serves as The output terminal of the modulation drive circuit outputs a driving voltage Vg; the other end of the first resistor is grounded.

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