WO2018220940A1 - Image capture device - Google Patents

Abstract

This image capture device comprises: an image capture element 21 for capturing images of a subject; a plurality of power-source generation circuits 52-54 that each generate the power-source voltages supplied to the image capture element 21; an A/D converter 55 that detects the power-source voltages supplied to the image capture element 21 by the plurality of power-source generation circuits 52-54; and an FPGA 51 that detects an increase amount ΔV of the power-source voltages using the power-source voltages detected by the A/D converter 55, and that, on the basis of the detected increase amount ΔV, controls the sequence in which the plurality of power-source generation circuits 52-54 are caused to sequentially activate.

Description

Imaging device

The present invention relates to an imaging apparatus including an imaging device to which a plurality of different power sources are turned on.

2. Description of the Related Art Conventionally, an endoscope system that includes an endoscope that captures a subject inside a subject, and an image processing device that generates an observation image of the subject captured by the endoscope, such as a medical field and an industrial field, etc. Widely used.

As an endoscope of such an endoscope system, conventionally, an image sensor (for example, a CMOS image sensor) driven by a predetermined clock signal is employed, and an image signal output from the image sensor is transmitted. An endoscope having a cable disposed therein is known.

An electronic device such as an image pickup element generally requires a plurality of different power sources such as a digital power source, an I / O (Input / Output) power source, and an analog power source. Electronic devices that require multiple different power supplies are usually designated with a power supply sequence such as the rising / falling order of multiple different power supplies and potential relations in order to avoid malfunction and breakdown due to electrical stress. Yes.

As such a power supply sequence, a time control method is used in which the power supply rise time is predicted in advance, and the power supply of the subsequent stage is turned on after the time when the power supply of the previous stage is predicted to have surely elapsed has elapsed.

When executing power supply sequence control by time control, it is necessary to ensure a rise time with a large margin including the temperature characteristics of the power supply in the previous stage and variations in the elements of the electronic device. Furthermore, when the power supply sequence control is executed by time control, if the power supply in the previous stage is out of the design range (for example, out of design temperature, delayed or immobile due to a failure, etc.), The electronic device may be turned on and the electronic device may be destroyed.

For example, International Publication No. 2013/042647 includes an image sensor to which a plurality of different power supplies are turned on, detects a plurality of different power supply voltages to be input to the image sensor, compares them with a predetermined threshold, and has an abnormality. In such a case, an endoscope is disclosed in which the power supply to the image sensor is stopped. Using such a configuration, the power supply sequence is not controlled by time control, but the power supply voltage of the previous stage is monitored, and after detecting that the power supply voltage of the previous stage is within the recommended operating voltage range, A power supply sequence for starting up the power supply is also common.

However, the power supply sequence that monitors the power supply voltage and controls the start-up of the power supply depends on the variation in the power supply voltage of the previous stage and the accuracy of the AD converter that detects the power supply voltage of the previous stage. There is a possibility that it is impossible to detect whether it has sufficiently risen.

That is, the power supply sequence that monitors the power supply voltage and controls the start-up of the power supply is recommended for the power supply voltage of the previous stage depending on the variation of the power supply voltage of the previous stage and the accuracy of the AD converter that detects the power supply voltage of the previous stage. There is a possibility that it cannot be detected that the voltage is within the voltage range. If it is not possible to detect that the power supply voltage of the previous stage is within the range of the recommended operating voltage, the power supply voltage of the subsequent stage is not turned on forever, causing a problem that the operation of the electronic device cannot be started.

Therefore, the present invention reliably detects the rise of each power supply and supplies the power with an appropriate power supply sequence, regardless of variations in power supply voltage and the accuracy of the AD converter, for electronic devices that start up with a plurality of different power supplies. An object of the present invention is to provide an imaging device capable of performing the above.

According to an imaging device of one embodiment of the present invention, an imaging element that captures an image of a subject, a plurality of power generation circuits that respectively generate power supply voltages to be supplied to the imaging element, and the plurality of power generation circuits that supply the imaging element A voltage detection circuit for detecting a power supply voltage; and an amount of increase in the power supply voltage is detected using the power supply voltage detected by the voltage detection circuit, and the plurality of power generation circuits are configured based on the detected increase amount. A sequence control circuit for controlling a sequence to be sequentially activated.

1 is a diagram illustrating a configuration of an endoscope system including an imaging device (endoscope) according to a first embodiment of the present invention. It is a block diagram which shows the electric constitution of the endoscope system of 1st Embodiment. It is a flowchart for demonstrating an example of the process of the power supply sequence of this embodiment. It is a flowchart for demonstrating an example of the process of the power supply sequence of this embodiment. It is a figure for demonstrating the change of the power supply voltage of the digital power supply detected by the A / D converter. It is a flowchart for demonstrating an example of the detection process of the overvoltage of a digital power supply. It is a figure for demonstrating the change of the power supply voltage of the digital power supply detected by the A / D converter. It is a block diagram which shows the electric constitution of the endoscope system of a modification. It is a figure for demonstrating the change of the electric current value detected with the electric current detection part 61 and the A / D converter 62. FIG.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
FIG. 1 is a diagram illustrating a configuration of an endoscope system including an imaging apparatus (endoscope) according to a first embodiment of the present invention. In the present embodiment, an example of an endoscope that has a solid-state imaging device and images a subject inside a subject will be described as an imaging device.

As shown in FIG. 1, an endoscope system 1 having an imaging apparatus (endoscope) according to the first embodiment includes an endoscope 2 that observes a subject and outputs an imaging signal, and an endoscope. 2, a video processor 3 that performs predetermined image processing on the imaging signal from the endoscope 2, a light source device 4 that supplies illumination light for illuminating the subject, and observation according to the imaging signal And a monitor device 5 for displaying an image.

The endoscope 2 includes an elongated insertion portion 6 that is inserted into a body cavity or the like of a subject, and an endoscope operation portion 10 that is disposed on the proximal end side of the insertion portion 6 and is operated by being grasped by an operator. The universal cord 41 is provided with one end so as to extend from the side of the endoscope operation unit 10.

The insertion portion 6 includes a rigid distal end portion 7 provided on the distal end side, a bendable bending portion 8 provided at the rear end of the distal end portion 7, and a long and flexible portion provided at the rear end of the bending portion 8. And a flexible tube portion 9 having flexibility.

A connector 42 is provided on the base end side of the universal cord 41, and the connector 42 is connected to the light source device 4. That is, a base (not shown) serving as a connection end of a fluid conduit projecting from the tip of the connector 42 and a light guide base (not shown) serving as an illumination light supply end are detachable from the light source device 4. It is to be connected with.

Furthermore, one end of the connection cable 43 is connected to the electrical contact portion provided on the side surface of the connector 42. For example, a signal line for transmitting an imaging signal from the endoscope 2 is provided in the connection cable 43, and the connector at the other end is connected to the video processor 3.

The connector 42 is provided with a connector circuit 50 (see FIG. 2) described later. The configuration of the connector circuit 50 will be described later.

Hereinafter, the electrical configuration of the endoscope system 1 according to the first embodiment will be described with reference to FIG. FIG. 2 is a block diagram illustrating an electrical configuration of the endoscope system according to the first embodiment.

As shown in FIG. 2, an image pickup element 21 for picking up an image of the subject is disposed at the distal end portion 7. In the present embodiment, the image sensor 21 is a solid-state image sensor constituted by a rolling shutter system, that is, a CMOS image sensor that sequentially reads out line by line. In addition, the image pick-up element 21 is not limited to a CMOS image sensor, For example, the solid-state image pick-up element comprised by a CCD image sensor may be sufficient.

The image sensor 21 is turned on by a plurality of different power sources. The image sensor 21 is an electronic device that starts up when a plurality of different power supplies are turned on in a predetermined order. Specifically, a 1.05 V digital power source, a 1.8 V I / O power source, and a 2.7 V analog power source are turned on for the image sensor 21. Then, the image pickup device 21 starts up when the power is turned on in the order of digital power, I / O power, and analog power.

As described above, in this embodiment, the power supply sequence of the image sensor 21 to which a plurality of different power sources are turned on will be described. However, if this power sequence is an electronic device to which a plurality of different power sources are turned on, the image sensor 21 is used. It can be applied to other than.

The connector 42 is provided with a connector circuit 50. The connector circuit 50 includes an FPGA 51, a first power generation circuit 52, a second power generation circuit 53, a third power generation circuit 54, and an A / D converter 55.

The FPGA 51 is configured by a so-called FPGA (Field Programmable Gate Gate Array), receives operation control from the video processor 3, and functions for driving the image sensors 21 and 31 and processing image signals from the image sensors 21 and 31. In addition, it has a function of controlling various circuits in the endoscope 2. Further, the FPGA 51 has a function of controlling various circuits in the connector circuit 50 and controlling a power supply sequence of power supplied to the image sensor 21.

The first power generation circuit 52, the second power generation circuit 53, and the third power generation circuit 54 are supplied with power from the video processor 3. The first power generation circuit 52, the second power generation circuit 53, and the third power generation circuit 54 are supplied with an enable signal from the FPGA 51. The first power supply generation circuit 52, the second power supply generation circuit 53, and the third power supply generation circuit 54 generate a predetermined power supply in response to an enable signal indicating ON or OFF from the FPGA 51, and supply the image pickup device 21 with the predetermined power supply. Supply.

Specifically, when an enable signal indicating ON from the FPGA 51 is input, the first power supply generation circuit 52 generates a 1.05 V power supply from the power supply supplied from the video processor 3, and passes through the power supply line 56. Output to the image sensor 21. This 1.05 V power supply is a digital power supply for the image sensor 21.

Similarly, when the enable signal indicating ON from the FPGA 51 is input, the second power supply generation circuit 53 generates a 1.8 V power supply from the power supplied from the video processor 3, and captures an image via the power supply line 57. Output to the element 21. The 1.8 V power source is an I / O power source for the image sensor 21.

Similarly, when an enable signal indicating ON from the FPGA 51 is input, the third power generation circuit 54 generates 2.7 V power from the power supplied from the video processor 3, and performs imaging via the power line 56. Output to the element 21. This 2.7 V power supply is an analog power supply for the image sensor 21. As described above, the first power generation circuit 52, the second power generation circuit 53, and the third power generation circuit 54 constitute a plurality of power generation circuits that respectively generate power supply voltages to be supplied to the image sensor 21.

The A / D converter 55 detects the voltage value generated by the first power supply generation circuit 52, AD converts the detected voltage value, and outputs it to the FPGA 51. The A / D converter 55 detects the voltage value generated by the second power supply generation circuit 53, AD-converts the detected voltage value, and outputs it to the FPGA 51. Further, the A / D converter 55 detects the voltage value generated by the third power supply generation circuit 54, AD-converts the detected voltage value, and outputs it to the FPGA 51. Thus, the A / D converter 55 constitutes a voltage detection circuit that detects the power supply voltage supplied to the image sensor 21 by the first power generation circuit 52, the second power generation circuit 53, and the third power generation circuit 54. .

The FPGA 51 uses the voltage value detected by the A / D converter 55 and the fluctuation of the voltage value (an increase amount of the power supply voltage per certain time), and the first power supply generation circuit 52 and the second power supply generation circuit 53. Then, ON or OFF of the enable signal output to the third power generation circuit 54 is changed, and activation of the first power generation circuit 52, the second power generation circuit 53, and the third power generation circuit 54 is controlled. That is, the FPGA 51 detects an increase amount of the power supply voltage using the power supply voltage detected by the A / D converter 55, and based on the detected increase amount of the power supply voltage, the first power supply generation circuit 52 and the second power supply A sequence control circuit that controls a sequence for sequentially starting the generation circuit 53 and the third power generation circuit 54 is configured.

Next, the power supply sequence of the endoscope 2 configured as described above will be described with reference to FIGS.

3 and 4 are flowcharts for explaining an example of processing of the power supply sequence of the present embodiment, and FIG. 5 explains changes in the power supply voltage of the digital power supply detected by the A / D converter 55. FIG. FIG.

3 and 4 are started when the endoscope 2 is connected to the video processor 3 and the power of the endoscope 2 is supplied from the video processor 3.

First, in step S1, the FPGA 51 turns on the enable signal to the first power supply generation circuit 52 and starts to start up the digital power supply. The first power supply generation circuit 52 generates a digital power supply to be supplied to the image sensor 21 according to an enable signal indicating ON from the FPGA 51, in the example of the present embodiment, a 1.05 V power supply and outputs the generated power to the image sensor 21. To do.

In step S 2, the A / D converter 55 detects the power supply voltage for the digital power supply of the image sensor 21 output from the first power supply generation circuit 52, and outputs the detection result to the FPGA 51. Specifically, the A / D converter 55 measures the power supply voltage for the digital power supply of the image sensor 21 output from the first power supply generation circuit 52, performs AD conversion, and then outputs the power supply voltage to the FPGA 51.

Next, in step S3, the FPGA 51 determines whether the detection result of the power supply voltage is equal to or higher than the threshold value V1. If the FPGA 51 determines that the detection result of the power supply voltage is greater than or equal to the threshold value V1, the FPGA 51 proceeds to step S6, turns on the enable signal to the second power supply generation circuit 53, and starts to start up the I / O power supply. On the other hand, when the FPGA 51 determines that the detection result of the power supply voltage is not equal to or greater than the threshold value V1, the FPGA 51 proceeds to step S4 and calculates an increase amount (power supply voltage change amount) ΔV per certain time. This fixed time is set to 1 ms, for example.

Next, the FPGA 51 determines whether or not the increase amount ΔV is equal to or less than the threshold value v1 in step S5. When the FPGA 51 determines that the increase amount ΔV is equal to or less than the threshold value v1, the FPGA 51 proceeds to step S6, turns on the enable signal to the second power supply generation circuit 53, and starts to start up the I / O power supply. On the other hand, if the FPGA 51 determines that the increase amount ΔV is not equal to or less than the threshold value v1, the FPGA 51 proceeds to step S2 and repeats the same processing.

As described above, the FPGA 51 determines that the rise of the digital power supply of the image sensor 21 is completed when the detection result of the power supply voltage of the first power supply generation circuit 52 detected by the A / D converter 55 is equal to or greater than the threshold value V1. Then, the enable signal of the second power supply generation circuit 53 is turned ON.

Further, even when the detection result of the power supply voltage of the first power supply generation circuit 52 is not the threshold value V1, the FPGA 51 causes the digital power supply of the image sensor 21 to rise when the increase amount ΔV of the power supply voltage per certain time is equal to or less than the threshold value v1. It is determined that the processing is completed, and the enable signal of the second power generation circuit 53 is turned ON.

Here, the threshold value V1 and the increase amount ΔV will be described. As shown in FIG. 5, the digital power supplied to the image sensor 21 varies due to the power supply voltage variation unique to the circuit of the first power generation circuit 52. In FIG. 5, an example in which the power supply voltage variation is on the max side is displayed as Vmax, and an example on the min side is displayed as Vmin. The threshold value V1 is set to Vmax × X% (for example, 80%) + AD conversion error. The FPGA 51 detects the rise of the digital power supply of the image sensor 21 using the threshold value V1.

On the other hand, when the power supply voltage variation is on the min side, the threshold value V1 may not be reached as shown in FIG. 5 due to the power supply voltage variation and the AD conversion error by the A / D converter 55. In this case, the FPGA 51 cannot detect the rise of the digital power supply of the image sensor 21 for any number of times, and the design of the power supply sequence control may fail. Even if the design of the power supply sequence does not fail, the FPGA 51 needs to wait until the power supply voltage becomes close to 100%, and it takes a long time to complete the power supply sequence.

Therefore, in the present embodiment, the FPGA 51 calculates the increase amount ΔV of the power supply voltage per fixed time (for example, 1 ms), and determines whether or not the increase amount ΔV is equal to or less than the threshold value v1. In order to reduce the processing of the FPGA 51, the increase amount ΔV is calculated according to the detection result of the power supply voltage or the increase amount ΔV without calculating the increase amount ΔV of the power supply voltage per fixed time (for example, 1 ms). The interval may be changed.

The increase amount ΔV of the power supply voltage increases immediately after the power is turned on, and converges and decreases with time. Therefore, when the increase amount ΔV is equal to or less than the threshold value v1, the FPGA 51 detects the convergence of the power source voltage of the digital power source that is input to the image sensor 21, and determines that the rise of the digital power source is completed.

Thereby, the FPGA 51 reliably detects the completion of the rise of the digital power supply of the image sensor 21 regardless of the power supply inherent in the circuit of the first power supply generation circuit 52 and the AD conversion error of the A / D converter 55. be able to.

When the FPGA 51 detects the rise of the digital power supply of the image sensor 21, the FPGA 51 turns on the enable signal to the second power generation circuit 53 in order to start up the I / O power supply of the image sensor 21. When the FPGA 51 detects the rise of the I / O power supply of the image sensor 21, the FPGA 51 turns on the enable signal to the third power supply generation circuit 54 in order to start up the analog power supply of the image sensor 21.

Returning to FIG. 3, the FPGA 51 turns on the enable signal to the second power generation circuit 53 in step S <b> 6 and starts to start up the I / O power. The second power generation circuit 53 generates an I / O power to be input to the image sensor 21 according to an enable signal indicating ON from the FPGA 51, in the example of the present embodiment, a 1.8 V power source. Output to.

In step S 7, the A / D converter 55 detects the power supply voltage for the I / O power supply of the image sensor 21 output from the second power supply generation circuit 53, and outputs the detection result to the FPGA 51. Specifically, the A / D converter 55 measures the power supply voltage for the I / O power supply of the image sensor 21 output from the second power supply generation circuit 53, performs AD conversion, and then outputs the power supply voltage to the FPGA 51.

Next, the process proceeds to FIG. 4, and the FPGA 51 determines in step S <b> 8 whether or not the detection result of the power supply voltage is equal to or higher than the threshold value V <b> 2. Although the threshold value V1 is set in step S3, the threshold voltage is also different because the power supply voltage applied between the digital power source and the I / O power source of the image sensor 21 is different. In the present embodiment, the threshold value V <b> 2 is set according to the power supply voltage variation unique to the second power supply generation circuit 53 and the AD conversion error of the A / D converter 55.

If the FPGA 51 determines that the detection result of the power supply voltage is equal to or greater than the threshold value V2, the FPGA 51 proceeds to step S11, turns on the enable signal to the third power supply generation circuit 54, and starts to start up the analog power supply. On the other hand, when the FPGA 51 determines that the detection result of the power supply voltage is not equal to or higher than the threshold value V2, the FPGA 51 proceeds to step S9 and calculates the increase amount ΔV of the power supply voltage per fixed time. This fixed time is set to 1 ms, for example.

Next, in step S10, the FPGA 51 determines whether or not the increase amount ΔV is equal to or less than the threshold value v1. When the FPGA 51 determines that the increase amount ΔV is equal to or less than the threshold value v1, the FPGA 51 proceeds to step S11, turns on the enable signal to the third power supply generation circuit 54, and starts to start up the analog power supply. On the other hand, if the FPGA 51 determines that the increase amount ΔV is not equal to or less than the threshold value v1, the FPGA 51 proceeds to step S7 and repeats the same processing. Note that although the power supply voltage to be applied is different between the digital power supply and the I / O power supply, since the conditions for convergence of the power supply voltage are the same, the threshold value v1 in step S10 is the same value as the threshold value v1 in step S5.

When the FPGA 51 detects the rise of the I / O power supply of the image sensor 21, the FPGA 51 starts the analog power supply of the image sensor 21.

In step S11, the FPGA 51 turns on the enable signal to the third power supply generation circuit 54 and starts to start up the analog power supply. The third power supply generation circuit 54 generates an analog power supply to be input to the image sensor 21 in accordance with an enable signal indicating ON from the FPGA 51, in the example of the present embodiment, a power supply of 2.7 V, and outputs it to the image sensor 21. To do.

In step S12, the A / D converter 55 detects the power supply voltage for the analog power supply of the image sensor 21 output from the third power supply generation circuit 54, and outputs the detection result to the FPGA 51. Specifically, the A / D converter 55 measures the analog power supply voltage of the image sensor 21 output from the third power supply generation circuit 54, performs AD conversion, and outputs the analog power supply voltage to the FPGA 51.

Next, in step S13, the FPGA 51 determines whether or not the detection result of the power supply voltage is greater than or equal to the threshold value V3. Although the threshold value V1 is set in step S3, the threshold voltage is also different because the power supply voltage applied between the digital power source and the analog power source of the image sensor 21 is different. In the present embodiment, the threshold value V <b> 3 is set according to the power supply voltage variation inherent to the third power supply generation circuit 54 and the AD conversion error of the A / D converter 55.

If the FPGA 51 determines that the detection result of the power supply voltage is equal to or higher than the threshold value V3, the FPGA 51 determines that the analog power supply has finished rising, and ends the process. On the other hand, when the FPGA 51 determines that the detection result of the power supply voltage is not equal to or greater than the threshold value V3, the FPGA 51 proceeds to step S14 and calculates the increase amount ΔV of the power supply voltage per fixed time. This fixed time is set to 1 ms, for example.

Next, the FPGA 51 determines whether or not the increase amount ΔV is equal to or less than the threshold value v1 in step S15. When the FPGA 51 determines that the increase amount ΔV is equal to or less than the threshold value v1, the FPGA 51 determines that the start-up of the analog power supply is completed, and ends the process. On the other hand, when the FPGA 51 determines that the increase amount ΔV is not equal to or less than the threshold value v1, the FPGA 51 proceeds to step S12 and repeats the same processing. Note that although the power supply voltage to be applied differs between the digital power supply and the analog power supply, since the conditions for convergence of the power supply voltage are the same, the threshold value v1 in step S15 is the same value as the threshold value v1 in step S5.

With the above processing, the power supply inherent in the circuits of the first power generation circuit 52, the second power generation circuit 53, and the third power generation circuit 54, and the A / D for the image sensor 21 that starts up with a plurality of different power sources. Regardless of the AD conversion error of the converter 55, the digital power supply, the I / O power supply, and the analog power supply can be started up.

Therefore, according to the imaging apparatus (endoscope 2) of the present embodiment, for each device that starts up with a plurality of different power sources, each power source can be reliably started up regardless of variations in power supply voltage and the accuracy of the AD converter. It can be detected and powered with an appropriate power sequence.

In the present embodiment, the FPGA 51 detects an overvoltage when the image pickup device 21 is powered on, and shuts down the power supply of the image pickup device 21 when the overvoltage is detected. In the following description, processing when an overvoltage occurs in the digital power source of the image sensor 21 will be described. However, when an overvoltage occurs in the I / O power source and the analog power source, the power source of the image sensor 21 is controlled by the same processing. Can be shut down.

FIG. 6 is a flowchart for explaining an example of the detection process of the overvoltage of the digital power source, and FIG. 7 is a diagram for explaining the change in the power source voltage of the digital power source detected by the A / D converter 55. is there.

Note that the process of FIG. 6 is executed when the FPGA 51 determines in step S3 of FIG. 3 that the detection result of the power supply voltage is equal to or higher than the threshold value V1. When the detection result of the power supply voltage is not equal to or higher than the threshold value V1, there is no need to execute the process of FIG.

First, in step S 21, the A / D converter 55 detects the power supply voltage for the digital power supply of the image sensor 21 output from the first power supply generation circuit 52, and outputs the detection result to the FPGA 51. Note that the process of step S21 may be replaced with the process of step S2 of FIG.

In step S22, the FPGA 51 determines whether the detection result of the power supply voltage is equal to or higher than the threshold value V4. When the FPGA 51 determines that the detection result of the power supply voltage is equal to or higher than the threshold value V4, the FPGA 51 proceeds to step S25, turns off the enable signal to the first power supply generation circuit 52, and ends the process. On the other hand, if the FPGA 51 determines that the detection result of the power supply voltage is not equal to or greater than the threshold value V4, the FPGA 51 proceeds to step S23 and calculates the increase amount ΔV of the power supply voltage per fixed time. This fixed time is set to 1 ms, for example.

Next, the FPGA 51 determines whether or not the increase amount ΔV is greater than or equal to the threshold value v2 in step S24. If the FPGA 51 determines that the increase amount ΔV is greater than or equal to the threshold value v2, the FPGA 51 proceeds to step S25, turns off the enable signal to the first power supply generation circuit 52, and ends the process. On the other hand, if the FPGA 51 determines that the increase amount ΔV is not greater than or equal to the threshold value v2, the FPGA 51 proceeds to step S21 and repeats the same processing.

As shown in FIG. 7, the threshold value V4 in step S22 is set in consideration of the AD conversion error of the A / D converter 55 in the power supply voltage variation (Vmax) on the max side inherent to the circuit of the first power supply generation circuit 52. Is done. By simply comparing the detection result of the power supply voltage with the threshold value V4, the shutdown cannot be performed until the power supply voltage supplied to the digital power supply of the image sensor 21 becomes V5. In this case, the power supply voltage exceeding the absolute maximum rating may be applied to the digital power supply of the image sensor 21 due to a steep increase in power supply voltage or a delay in control, and the image sensor 21 may be destroyed.

On the other hand, in the process of FIG. 6, the amount of increase ΔV in the power supply voltage per fixed time is compared with the threshold value v <b> 2 to detect an abnormal change in the power supply voltage, and the digital power supply that is input to the image sensor 21. Can be shut down. In other words, the FPGA 51 can detect an abnormality of the digital power supply of the image sensor 21 at an early stage, and can shut down the digital power source input to the image sensor 21 at an early stage. As a result, a power supply voltage exceeding the absolute maximum rating is not applied to the digital power supply of the image sensor 21, the image sensor 21 is prevented from being destroyed, and the safety of the endoscope 2 can be improved.

(Modification)
Next, a modification of the first embodiment will be described.

FIG. 8 is a block diagram showing an electrical configuration of an endoscope system according to a modification. In FIG. 8, the same components as those in FIG. 2 are denoted by the same reference numerals and description thereof is omitted.

FIG. 5 is a block diagram showing an electrical configuration of an endoscope system according to a modification of the first embodiment. The endoscope 2 of the endoscope system 1 includes a connector circuit 50a instead of the connector circuit 50 shown in FIG.

The connector circuit 50a is configured by adding a current detection unit 61 and an A / D converter 62 to the connector circuit 50 of FIG. The current detection unit 61 detects the current value of the power supply voltage supplied from the video processor 3 to the endoscope 2 and outputs the current value to the A / D converter 62. The current detection unit 61 includes, for example, a sense resistor and a detection circuit that detects a current value from a potential difference between both ends of the sense resistor. The A / D converter 62 AD-converts the current value detected by the current detection unit 61 and outputs it to the FPGA 51. As described above, the current detection unit 61 and the A / D converter 62 include a current detection circuit that detects a current value supplied to the first power generation circuit 52, the second power generation circuit 53, and the third power generation circuit 54. Constitute.

FIG. 9 is a diagram for explaining changes in the current value detected by the current detection unit 61 and the A / D converter 62. The FPGA 51 detects an overcurrent from the current values detected by the current detection unit 61 and the A / D converter 62, and shuts down the power supply of the image sensor 21 when the overcurrent is detected.

Specifically, as shown in FIG. 9, the FPGA 51 determines whether or not the current value detected by the current detection unit 61 and the A / D converter 62 is equal to or greater than the threshold value A1, and the current value is equal to or greater than the threshold value A1. When it determines, the power supply of the image pick-up element 21 is shut down. The threshold value A1 is determined in consideration of the current fluctuation Amax on the max side and the AD conversion error of the A / D converter 62.

Further, the FPGA 51 calculates the increase amount ΔA of the current value per certain time using the current value detected by the current detection unit 61 and the A / D converter 62. Then, the FPGA 51 determines whether or not the increase amount ΔA is equal to or greater than the threshold value a1, for example. If the increase amount ΔA is determined to be equal to or greater than the threshold value a1, for example, the FPGA 51 shuts down the power source of the image sensor 21.

In the overcurrent detection using the threshold A1, the FPGA 51 cannot detect the overcurrent until the current value detected by the current detection unit 61 and the A / D converter 62 becomes A2. On the other hand, the FPGA 51 can detect an abnormal current value change amount from a current increase amount ΔA per fixed time, and can stop the power supply to the image sensor 21.

As described above, the endoscope 2 according to the modified example can further improve the safety than the first embodiment by detecting the overcurrent in addition to the detection of the overvoltage of the first embodiment described above. it can.

The present invention is not limited to the above-described embodiment, and various changes and modifications can be made without departing from the scope of the present invention.

This application is filed on the basis of priority claim of Japanese Patent Application No. 2017-107541 filed in Japan on May 31, 2017, and the above disclosure is included in the present specification and claims. Shall be quoted.

Claims (6)

An image sensor for imaging a subject;
A plurality of power generation circuits that respectively generate power supply voltages to be supplied to the image sensor;
A voltage detection circuit for detecting a power supply voltage supplied to the image sensor by the plurality of power generation circuits;
A sequence control circuit that detects an increase amount of the power supply voltage using the power supply voltage detected by the voltage detection circuit, and controls a sequence for sequentially starting the plurality of power supply generation circuits based on the detected increase amount When,
An imaging apparatus comprising: The sequence control circuit activates a power generation circuit to be activated next when a power supply voltage generated by the currently activated power generation circuit exceeds a predetermined threshold among the plurality of power generation circuits. The imaging apparatus according to claim 1, wherein: 2. The imaging apparatus according to claim 1, wherein the sequence control circuit activates a power generation circuit to be activated next when the convergence of the power supply voltage is detected based on an increase amount of the power supply voltage. 4. The sequence control circuit according to claim 3, wherein the sequence control circuit predicts an overvoltage according to a change amount of the power supply voltage detected by the voltage detection circuit, and stops activation of the plurality of power supply generation circuits. 5. Imaging device. A current detection circuit for detecting a current value supplied to the plurality of power generation circuits;
4. The sequence control circuit according to claim 3, wherein the sequence control circuit detects an overcurrent according to a change amount of the current value detected by the current detection circuit, and stops activation of the plurality of power generation circuits. 5. Imaging device. The imaging apparatus according to claim 1, wherein the power supply voltages generated by the plurality of power supply generation circuits are different from each other.

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