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WO2018201539A1 - 显示驱动方法、显示驱动装置 - Google Patents

显示驱动方法、显示驱动装置 Download PDF

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Publication number
WO2018201539A1
WO2018201539A1 PCT/CN2017/086166 CN2017086166W WO2018201539A1 WO 2018201539 A1 WO2018201539 A1 WO 2018201539A1 CN 2017086166 W CN2017086166 W CN 2017086166W WO 2018201539 A1 WO2018201539 A1 WO 2018201539A1
Authority
WO
WIPO (PCT)
Prior art keywords
image signal
display panel
sub
pixels
display
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2017/086166
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English (en)
French (fr)
Inventor
郭东胜
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
HKC Co Ltd
Chongqing HKC Optoelectronics Technology Co Ltd
Original Assignee
HKC Co Ltd
Chongqing HKC Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by HKC Co Ltd, Chongqing HKC Optoelectronics Technology Co Ltd filed Critical HKC Co Ltd
Priority to US16/609,806 priority Critical patent/US11335235B2/en
Publication of WO2018201539A1 publication Critical patent/WO2018201539A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2007—Display of intermediate tones
    • G09G3/2074—Display of intermediate tones using sub-pixels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3614—Control of polarity reversal in general
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0254—Control of polarity reversal in general, other than for liquid crystal displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0275—Details of drivers for data electrodes, other than drivers for liquid crystal, plasma or OLED displays, not related to handling digital grey scale data or to communication of data to the pixels by means of a current
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0247—Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2340/00—Aspects of display data processing
    • G09G2340/04—Changes in size, position or resolution of an image
    • G09G2340/0407—Resolution change, inclusive of the use of different resolutions for different screen areas

Definitions

  • the present application relates to the field of display technologies, and in particular, to a display driving method and a display driving device.
  • the ultra-high-definition display panel will use the full-HD logic board to assemble the printed circuit board design to display the ultra-high-definition screen.
  • the ultra-high-definition glass panel is equivalent to copying one input display pixel into four pixels.
  • the resolution will become When the original 1/4 is displayed on the ultra high definition display panel, the red, green and blue pixels in the adjacent column direction have opposite polarities. At this time, the screen display of one of the polarities cannot be turned off separately, and the flicker cannot be performed. Confirmation and optimization adjustments.
  • the present application provides a method for driving display panel display performed by a computer device, which can perform flashing confirmation on an ultra high definition display panel when the ultra high definition display panel is driven by a full HD logic board.
  • the present application proposes a method for driving display panel display performed by a computer device, comprising the following steps:
  • the processor sets an image signal, so that when the image signal is driven on the display panel, the first sub-pixel display of the positive polarity is displayed, and the remaining sub-pixels are not displayed;
  • the gate drive signal input is controlled to display an image.
  • the step of setting the image signal to display the first sub-pixel display of the positive polarity when the image signal is driven on the display panel, and the remaining sub-pixels are not displayed specifically includes:
  • the step of inputting the image signal to the display panel after being copied by the logic board includes:
  • Receiving the image signal, and decoding is divided into a first partition image signal and a second partition image signal;
  • the third divided image signal, the fourth divided image signal, and the fifth divided image signal and the sixth divided image signal are input to the display panel.
  • the gate drive signal is driven in pairs on scan lines of the display panel.
  • the second, first, and third sub-pixel columns of the display panel are grouped in groups of 2n+1th column and 2n+2th column, 0 ⁇ n ⁇ 5759, in row inversion and two columns.
  • the polarities of the second, first, and third sub-pixels in the same group are the same, and the polarities of the second, first, and third sub-pixels in the adjacent groups are opposite.
  • the driving polarity of the sub-pixels of the display panel is controlled by an input data signal.
  • the present application provides a driving device for a display panel, the driving device comprising a processor and a non-volatile memory, the non-volatile memory storing executable instructions, the processor executing executable instructions, the executable instructions comprising:
  • the image signal setting module sets an image signal, and when the image signal is driven on the display panel, displays a first sub-pixel display of positive polarity, and the remaining sub-pixels are not displayed;
  • An image signal input module the image signal is copied to the display panel after being copied by a logic board;
  • the display module controls the gate drive signal input to display the image.
  • the image signal setting module is further configured to:
  • the image signal input module includes:
  • a decoding unit that receives the image signal, and after decoding, is divided into a first partition image signal and a second partition image signal;
  • the timing processing unit copies the first partition image signal to obtain the third partition image signal and the fourth partition image signal, and copies the second partition image signal to obtain the fifth partition image signal and the sixth partition image signal;
  • the signal input unit inputs the third divided image signal, the fourth divided image signal, and the fifth divided image signal and the sixth divided image signal to the display panel.
  • the gate drive signal is driven in pairs on scan lines of the display panel.
  • the display driving method of the present application displays a first sub-pixel display of positive polarity when the image signal is driven on the display panel by setting an image signal to be input, and the remaining sub-pixels are not displayed, and then the set image is displayed.
  • the signal is copied to the display panel through the logic board, and finally, by inputting the gate drive signal, the image display of the light and dark interlaced can be seen, that is, the flashing confirmation is realized, so as to optimize the voltage of the display electrode of the ultra high definition display panel.
  • FIG. 1 is a flow chart of an embodiment of a display driving method of the present application.
  • FIG. 2 is a schematic diagram showing image signals displayed on a full HD and ultra high definition display panel during line inversion driving
  • FIG. 3 is a schematic diagram showing image signals displayed on a full HD and ultra high definition display panel when two columns are reversely driven;
  • step S20 in FIG. 1 is a specific flowchart of step S20 in FIG. 1;
  • Figure 5 is a functional block diagram showing the panel driving
  • FIG. 6 is a schematic structural view of a display driving device according to the present application.
  • Figure 7 is a schematic view showing the connection of the line on the right side of Figure 6;
  • FIG. 8 is a functional block diagram of an embodiment of a display driving apparatus according to the present application.
  • the display driving method and the display driving device proposed by the present application can be applied to an ultra high definition display panel, and the ultra high definition display panel can be driven by a logic board of a full high definition display panel.
  • the display panel can be, for example, an LCD display panel, an OLED display panel, a QLED display panel, a curved display panel, or other display panel.
  • FIG. 1 is a flowchart of an embodiment of a display driving method according to the present application.
  • the display driving method includes the following steps:
  • the image signal is set such that when the image signal is driven by row inversion on the display panel, the first sub-pixel display of the odd-numbered column of pixels of the positive polarity is displayed, and the remaining sub-pixels are not displayed; or in the display When the panel is driven in reverse by two columns, the first sub-pixels of the intersecting pixel points showing the odd-numbered odd-numbered rows and the even-numbered even-numbered rows of the positive polarity are displayed, and the remaining sub-pixels are not displayed.
  • the display driving method is based on Full HD TCON (Timer Control) Register, logic board), the display on the full HD display panel is copied and displayed on the ultra high definition display panel, because the implementation of flicker needs to display sub-pixels of the same polarity, and must be positive sub-pixels, and generally
  • a full HD input of one RGB pixel such as P11R, P11G, P11B
  • TCON Timer Control Register, logic board
  • P11R-, P11G+, P11B- at this time, it is not possible to turn off the display of one of the polarities separately, so one RGB pixel of the full HD input must be displayed when it is displayed on the ultra high definition display panel via TCON.
  • P11R+, P11G+, P11B-/ P11R-, P11G+, P11B+ that is, set the image signal so that when the line is reversely driven on the full HD display panel, the green sub-pixel display of the odd-numbered column of pixels of positive polarity is displayed, and the remaining sub-pixels are not displayed, such as As shown by 71 in FIG.
  • the image signal is input to the ultra high definition display panel through the full HD logic board and the gate drive signal input is controlled.
  • the image is displayed, the image is displayed as shown in FIG.
  • the display screen that is, the drive display on the ultra high definition display panel
  • the drive signal drives the ultra high definition display panel to display the screen, it can see flicker on the display screen.
  • the green sub-pixels of the cross-pixels of the odd-numbered odd-numbered rows and the even-numbered even-numbered rows of the positive polarity are displayed, and the remaining sub-pixels are not displayed.
  • the display driving method of the present application displays a positive green sub-pixel display when the image signal is driven on the full HD display panel by setting an image signal to be input, and the remaining sub-pixels are not displayed, and then the setting is performed.
  • the image signal is input to the ultra-high-definition panel through the full-HD logic board.
  • the gate driving signal the image display of the light and dark interlaced can be seen, that is, the flashing confirmation is realized, so as to display the voltage of the display electrode of the ultra-high-definition display panel. Optimize debugging.
  • step S20 specifically includes:
  • S21 receiving the image signal, and decoding is divided into a first partition image signal and a second partition image signal;
  • the full-HD TCON Timer Control Register, logic board
  • the input image signals are displayed on the full HD display panel with pixels 11, 12, 13, 21, 22, 23, 31, 32, 33, 41, 42, 43 after full HD.
  • TCON decoding and copy processing a single pixel is copied into four, and the display effect of the same resolution is displayed on the ultra-high-definition display panel, and the image signal is driven by the full HD image to drive the ultra-high definition display panel. Displaying, saving costs.
  • the driving of display panel 70 is typically accomplished by a combination of source driver 50 and gate driver 60.
  • the logic board After the register, the logic board generates a data signal for controlling the driving polarity of the sub-pixel of the ultra high definition display panel, the clock control signal DSP/DCK of the source driver 50, and the clock control signal of the gate driver 60.
  • GSP/GCK the data driver is loaded by the source driver 50 to control the driving polarity of the RGB sub-pixels
  • the timing is controlled by the gate driver 60
  • the scanning lines of the ultra-high-definition display panel are driven in pairs to display an ultra-high-definition display panel.
  • the frame is lit and a frame of dark flashing is displayed.
  • UD Ultra High
  • Definition, Ultra HD) 1D1G (where D represents the data line, G represents the scan line, and the number of independent inputs of the data line and scan line are both 1) drive architecture scheme.
  • the drive architecture consists of 12 source drivers and 12 gate drivers. Among them, 12 source drivers and 12 gate drivers are symmetrically arranged.
  • the 12 source drivers are divided into two groups, each of which includes 6 source drivers. Among them, every 3 source drivers share a data interface. Thus the 12 source drivers comprise a total of four data interfaces to receive full HD respectively.
  • the right group includes source drivers S1, S2, S3, S4, S5, S6 arranged in order from the left.
  • Each source driver includes one clock line, six data lines, and one data transfer trigger line.
  • the source drivers S1, S2, and S3 share one data interface, and S4, S5, and S6 share one data interface.
  • the six data lines of S1, S2, and S3 are short-circuited one by one, the clock lines are short-circuited, and the data transmission trigger lines are short-circuited one by one, and the short-circuited one is taken out from the A interface and connected to the TCON board.
  • S4, S5, and S6 are shorted and then extracted from the B interface.
  • the lead line of the A interface includes one clock line R-ACLK, and the six data lines are respectively R-ALV0 ⁇ R-ALV5;
  • the lead line of the B interface includes one clock line R-BCLK, and the six data lines are respectively R-B BLV0 ⁇ R-BLV5.
  • the A and B interfaces also include data transmission trigger lines S3-DIO1, S4-DIO2.
  • the right group also includes the mode switching line UCFT Mode(unsteady cooperative flow type Mode, unsteady coupled flow type), the switching line is respectively connected with S1, S2, S3, S4, S5, S6, in order to switch between the two display driving modes of the ultra high definition mode and the full high definition mode.
  • UCFT Mode unsteady cooperative flow type Mode, unsteady coupled flow type
  • the left group includes the C interface and the D interface; the C interface leads include one clock line R-CCLK, and the six data lines are R-CLV0 ⁇ R-CLV5; the D interface leads include One clock line R-DCLK, six data lines are R-DLV0 ⁇ R-DLV5.
  • the C and D interfaces also include data transmission trigger lines S9-DIO3 and S10-DIO4.
  • the left group also includes the mode switching line UCFT Mode, the switching line is respectively connected with S7, S8, S9, S10, S11, S12, so as to switch between the two display driving modes of the ultra high definition mode and the full high definition mode.
  • Each source driver drives 320 columns of pixels, and the 12 source drivers drive a total of 3840 columns of pixels.
  • the 12 gate drivers are respectively GR1 ⁇ GR6 and GL1 ⁇ GL6, wherein GR1 ⁇ GR6 are located on the right side of the display panel, and GL1 ⁇ GL6 are located on the left side of the display panel.
  • Each gate driver drives 360 rows of pixels.
  • the gate driving signal is driven in pairs on the scan lines of the display panel. That is, drive P1/P2 first, then P3/P4, P5/P6•••••• until P2159/P2160.
  • the third partition image signal and the fourth partition image signal are both differential signals. That is, the interfaces A, B, C, and D are input as miniature low voltage differential signals (mini-Low). Voltage Differential Signal, mini-LVDS).
  • the third divided image signal, the fourth divided image signal, the fifth divided image signal, and the sixth divided image signal each include two RGB pixel signals.
  • R-ALV0 ⁇ R-ALV2 input 1 RGB pixel signal
  • R-ALV3 ⁇ R- ALV5 inputs 1 RGB pixel signal.
  • the second, first, and third sub-pixel columns of the display panel are grouped in groups of 2n+1th column and 2n+2th column, 0 ⁇ n ⁇ 5759, in row inversion and two columns.
  • the polarities of the second, first, and third sub-pixels in the same group are the same, and the polarities of the second, first, and third sub-pixels in the adjacent groups are opposite.
  • the resolution of the ultra high definition display panel is 3840 ⁇ 2160, that is, the ultra high definition display panel has 3840 ⁇ 2160 pixel points, and each pixel point includes 3 RGB sub-pixels, that is, 1&2
  • the 3&4, 5&6, ... 2n+1 & 2n+2 columns are respectively grouped, the columns being defined as being all grouped by the same sub-pixel, the rows being defined as being arranged in groups by different sub-pixels, and in some embodiments, rows and columns are A certain angle is formed on the same plane, and optionally, the rows are perpendicular to the columns.
  • the polarities of the red, green, and blue sub-pixel columns in the same group are the same, and the polarities of the red, green, and blue sub-pixels in the adjacent group are opposite, as shown in FIG. 2, the sub-pixels R and P11 of the first group.
  • G shows positive polarity
  • the sub-pixels B and R of P11 to P41 in the second group all show negative polarity.
  • the green sub-pixels of P11 to P41 in the third group and B show positive polarity
  • the P12 to P42 in the fourth group are both show negative polarity.
  • the present application also proposes a display driving device.
  • FIG. 8 is a functional block diagram of an embodiment of a display driving apparatus according to the present application.
  • the display driving apparatus 100 includes:
  • the image signal setting module 10 sets an image signal, and when the image signal is driven on the display panel, displays a positive first sub-pixel display, and the remaining sub-pixels are not displayed;
  • the image signal input module 20 converts the image signal to the display panel after being copied by a logic board
  • the display module 30 controls the gate drive signal input to display an image.
  • the image signal setting module 10 is further configured to: set an image signal, and when the image signal is driven by a row inversion on the display panel, display the first of the odd-numbered columns of pixels of the positive polarity Sub-pixel display, the remaining sub-pixels are not displayed; or when the display panel is driven by two columns of inversion, the first sub-pixels of the cross-pixels of the odd-numbered odd-numbered rows and the even-numbered even-numbered rows of the positive polarity are displayed, and the rest Subpixels are not displayed.
  • the display driving device 100 copies the display screen on the full HD display panel and displays it on the ultra high definition display panel based on the full HD TCON, because the implementation of the flicker needs to display sub-pixels of the same polarity, and Must be a positive sub-pixel, and in general, an RGB pixel of the full HD input, such as P11R, P11G, P11B, will display two sets of P11R+, P11G- when displayed on the ultra-high-definition display panel via TCON.
  • P11B+/ P11R-, P11G+, P11B- at this time, it is not possible to turn off the display of one of the polarities separately, so one RGB pixel of the full HD input must be displayed when it is displayed on the ultra high definition display panel via TCON.
  • P11R+, P11G+, P11B-/ P11R-, P11G+, P11B+ that is, the image signal is set by the image signal setting module 10 to display the green sub-pixel display of the odd-numbered column of pixels of the positive polarity when the line is reversely driven on the full-HD display panel. The remaining sub-pixels are not displayed.
  • the image signal input module 20 inputs the image signal to the ultra high definition display panel through the full HD logic board, and the display module 30 controls the gate driving signal input, and displays the image when the image is displayed.
  • the display screen shown in FIG. 2 is driven display on the ultra high definition display panel, brightness is displayed between the green sub-pixels displaying the positive polarity in the odd column and the negative green sub-pixels not displayed in the next frame. The difference is that flicker can be seen on the display screen when the gate drive signal drives the ultra high definition display panel to display the screen.
  • the image signal setting module 10 sets the green color of the intersecting pixel points of the odd-numbered odd-numbered rows and the even-numbered-even-numbered rows of the odd-numbered columns when the image signals are driven in two columns inversion on the full-HD display panel. Sub-pixel display, the remaining sub-pixels are not displayed.
  • the image signal input module 20 inputs the image signal to the ultra-high-definition display panel through the full HD logic board, and the display module 30 controls the gate driving signal input to perform image processing.
  • the display is displayed, the display screen as shown in FIG.
  • the display driving device 100 of the present application sets an image signal to be input by the image signal setting module 10, and when the image signal is driven on the full HD display panel, displays a positive green sub-pixel display, and the remaining sub-pixels are not displayed. Then, the image signal input module 20 inputs the set image signal to the ultra high definition panel through the full HD logic board, and finally controls the gate driving signal input through the display module 30, so that the light and dark interlaced image display can be seen, that is, A flashing confirmation is implemented to optimize the voltage of the display electrodes of the ultra high definition display panel.
  • the image signal input module 20 includes:
  • the decoding unit 21 receives the image signal, and after decoding, is divided into a first partition image signal and a second partition image signal;
  • the timing processing unit 22 copies the first partition image signal to obtain the third partition image signal and the fourth partition image signal, and copies the second partition image signal to obtain the fifth partition image signal and the sixth partition image signal;
  • the signal input unit 23 inputs the third divided image signal, the fourth divided image signal, and the fifth divided image signal and the sixth divided image signal to the display panel.
  • the image signal that needs to be input by the ultra high definition display panel is set on the display panel of the full high definition
  • the image signal is finally divided into four signals by the full HD TCON, which are respectively the third partition image signals.
  • the fourth partition image signal, and the fifth partition image signal and the sixth partition image signal, each of the partition image signals are respectively responsible for 1/4 of the screen display to match the ultra high definition display panel.
  • the input image signals are displayed on the full HD display panel with pixels 11, 12, 13, 21, 22, 23, 31, 32, 33, 41, 42, 43 after full HD.
  • TCON decoding and copy processing a single pixel is copied into four, and the display effect of the same resolution is displayed on the ultra-high-definition display panel, and the image signal is driven by the full HD image to drive the ultra-high definition display panel. Displaying, saving costs.
  • the driving of the display panel is typically accomplished by a combination of a source driver and a gate driver.
  • the data signal for controlling the driving polarity of the sub-pixel of the ultra high definition display panel is generated after the conversion processing, the clock control signal of the source driver is DSP/DCK, and the gate driver Clock control signal GSP/GCK.
  • the driving polarity of the RGB sub-pixel is controlled by loading the data signal of the source driver, and the timing of the ultra-high-definition display panel is driven in pairs by the gate driver to control the timing, so that a frame of light is displayed on the ultra-high-definition display panel. , a frame of dark flashing display.
  • the second, first, and third sub-pixel columns of the display panel are grouped in groups of 2n+1th column and 2n+2th column, 0 ⁇ n ⁇ 5759, in row inversion and two columns.
  • the polarities of the second, first, and third sub-pixels in the same group are the same, and the polarities of the second, first, and third sub-pixels in the adjacent groups are opposite.
  • the resolution of the ultra high definition display panel is 3840 ⁇ 2160, that is, the ultra high definition display panel has 3840 ⁇ 2160 pixel points, and each pixel point includes 3 RGB sub-pixels, that is, 1&2 The 3&4, 5&6...2n+1&2n+2 columns are respectively grouped, the columns being defined as groups all arranged by the same sub-pixel, the rows being defined as groups arranged by different sub-pixels, and in some embodiments, rows and The columns form a certain angle on the same plane, optionally, the rows are perpendicular to the columns.
  • the red, green, and blue sub-pixel columns in the same group have the same polarity, and the polarities of the red, green, and blue sub-pixels in the adjacent group are opposite, as shown in FIG. 2, the sub-pixels R and G of P11 to P41 in the first group. Both show positive polarity.
  • the sub-pixels B and R of P11 to P41 in the second group all show negative polarity.
  • the green sub-pixels of P11 to P41 in the third group and B show positive polarity, and the sub-pixels of P12 to P42 in the fourth group. Both pixels R and G show negative polarity.
  • the present application further provides a driving device for a display panel, the driving device comprising a processor and a non-volatile memory, the non-volatile memory storing executable instructions, the processor executing executable
  • the instructions are used to implement the methods described in the various embodiments described above.
  • the modules/units 10, 20, 21, 22, 23, 30 shown in Figure 8 of the present application can be software modules or software units.
  • various software modules or software units may be inherently stored in a non-volatile memory and executed by a processor.

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Abstract

一种显示驱动方法、显示驱动装置，其中，该显示驱动方法通过设定需要输入的图像信号，使该图像信号在显示面板上驱动时，显示正极性的第一子像素显示，其余子像素不显示（S10），然后将设定好的图像信号通过逻辑板复制后输入至显示面板（S20），最后通过控制栅极驱动信号输入，对图像进行显示（S30）。

Description

显示驱动方法、显示驱动装置
技术领域
本申请涉及显示技术领域，特别涉及一种显示驱动方法、显示驱动装置。
背景技术
目前，超高清的显示面板，会采用全高清的逻辑板进行装配印刷电路板的设计，来显示超高清的屏幕。
但是， 超高清的玻璃面板在通过全高清的逻辑板进行设计时，相当于将一个输入显示像素复制成4个像素，以列反转为例，若仍旧采用全高清的驱动方式，分辨率会变成原来的1/4，且在超高清的显示面板上显示时，相邻列方向的红绿蓝像素的极性相反，此时，就无法单独关闭其中一个极性的画面显示，无法进行闪烁的确认、及最佳化的调整。
发明内容
本申请提供一种由计算机设备执行的驱动显示面板显示的方法，其可在超高清显示面板通过全高清的逻辑板驱动时，对超高清显示面板进行闪烁确认。
本申请提出一种由计算机设备执行的驱动显示面板显示的方法，包括以下步骤：
处理器设定图像信号，使所述图像信号在显示面板上驱动时，显示正极性的第一子像素显示，其余子像素不显示；
将所述图像信号经逻辑板复制后输入至所述显示面板；
控制栅极驱动信号输入，对图像进行显示。
在一实施例中，所述设定图像信号，使所述图像信号在显示面板上驱动时，显示正极性的第一子像素显示，其余子像素不显示的步骤，具体包括：
设定图像信号，使所述图像信号在显示面板上以行反转驱动时，显示正极性的奇数列像素点的第一子像素显示，其余子像素不显示；或者在所述显示面板上以两列反转驱动时，显示正极性的奇数列奇数行和偶数列偶数行的交叉像素点的第一子像素显示，其余子像素不显示。
在一实施例中，所述将所述图像信号经逻辑板复制后输入至所述显示面板的步骤，具体包括：
接收所述图像信号，解码后分为第一分区图像信号及第二分区图像信号；
将第一分区图像信号复制得到第三分区图像信号及第四分区图像信号，将第二分区图像信号复制得到第五分区图像信号及第六分区图像信号；
将所述第三分区图像信号、第四分区图像信号，及第五分区图像信号、第六分区图像信号输入至所述显示面板。
在一实施例中，所述栅极驱动信号对所述显示面板的扫描线成对驱动。
在一实施例中，将所述显示面板的第二、第一、第三子像素列按第2n＋1列和第2n＋2列的组合分别成组，0≤n≤5759，在行反转和两列反转驱动模式下，同一组内第二、第一、第三子像素的极性相同，相邻组间第二、第一、第三子像素的极性相反。
在一实施例中，所述显示面板的子像素的驱动极性由输入的数据信号控制。
本申请提出一种显示面板的驱动装置，该驱动装置包括处理器和非易失性存储器，该非易失性存储器存储可执行指令，该处理器执行可执行指令，该可执行指令包括：
图像信号设定模块，设定图像信号，使所述图像信号在显示面板上驱动时，显示正极性的第一子像素显示，其余子像素不显示；
图像信号输入模块，将所述图像信号经逻辑板复制后输入至所述显示面板；
显示模块，控制栅极驱动信号输入，对图像进行显示。
在一实施例中，所述图像信号设定模块还用于：
设定图像信号，使所述图像信号在显示面板上以行反转驱动时，显示正极性的奇数列像素点的第一子像素显示，其余子像素不显示；或者在所述显示面板上以两列反转驱动时，显示正极性的奇数列奇数行和偶数列偶数行的交叉像素点的第一子像素显示，其余子像素不显示。
在一实施例中，所述图像信号输入模块包括：
解码单元，接收所述图像信号，解码后分为第一分区图像信号及第二分区图像信号；
时序处理单元，将第一分区图像信号复制得到第三分区图像信号及第四分区图像信号，将第二分区图像信号复制得到第五分区图像信号及第六分区图像信号；
信号输入单元，将所述第三分区图像信号、第四分区图像信号，及第五分区图像信号、第六分区图像信号输入至所述显示面板。
在一实施例中，所述栅极驱动信号对所述显示面板的扫描线成对驱动。
本申请的显示驱动方法，通过设定需要输入的图像信号，使该图像信号在显示面板上驱动时，显示正极性的第一子像素显示，其余子像素不显示，然后将设定好的图像信号通过逻辑板复制后输入至显示面板，最后通过输入栅极驱动信号，就能够看到明暗交错的图像显示，也即实现了闪烁确认，以便对超高清显示面板的显示电极的电压进行最佳化调试。
附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图示出的步骤获得其他的附图。
图1为本申请的显示驱动方法一实施例的流程图；
图2为行反转驱动时图像信号在全高清和超高清显示面板上显示的示意图；
图3为两列反转驱动时图像信号在全高清和超高清显示面板上显示的示意图；
图4为图1中步骤S20的具体流程图；
图5为显示面板驱动的功能模块图；
图6为本申请显示驱动装置的结构示意图；
图7为图6中右侧部分线路的连接示意图；
图8为本申请显示驱动装置一实施例的功能模块图。
本申请目的的实现、功能特点及优点将结合实施例，参照附图做进一步说明。
具体实施方式
下面结合附图并通过具体实施方式来说明本申请的技术方案。可以理解的是，此处所描述的具体实施例仅仅用于解释本申请，而非对本申请的限定。另外还需要说明的是，为了便于描述，附图中仅示出了与本申请相关的部分而非全部结构。在不冲突的情况下，以下实施例以及实施例中的特征可以任意相互组合。
本申请提出的显示驱动方法和显示驱动装置，可以应用于超高清显示面板，所述超高清显示面板可采用全高清显示面板的逻辑板驱动。其中，显示面板可例如为LCD显示面板、OLED显示面板、QLED显示面板、曲面显示面板或其他显示面板。
参照图1，图1为本申请的显示驱动方法一实施例的流程图。
在本申请中，该显示驱动方法包括以下步骤：
S10：设定图像信号，使所述图像信号在显示面板上驱动时，显示正极性的第一子像素显示，其余子像素不显示；
具体为：设定图像信号，使所述图像信号在显示面板上以行反转驱动时，显示正极性的奇数列像素点的第一子像素显示，其余子像素不显示；或者在所述显示面板上以两列反转驱动时，显示正极性的奇数列奇数行和偶数列偶数行的交叉像素点的第一子像素显示，其余子像素不显示。
S20：将所述图像信号经逻辑板复制后输入至所述显示面板；
S30：控制栅极驱动信号输入，对图像进行显示。
在本实施例中，该显示驱动方法基于全高清的TCON（Timer Control Register，逻辑板）实现，将全高清显示面板上的显示画面复制后在超高清显示面板上显示，因为闪烁的实现需要显示同一极性的子像素，且必须是正极性的子像素，而一般情况下，全高清输入的一个RGB像素点，如P11R、P11G、P11B，在经TCON（Timer Control Register，逻辑板）输入至超高清显示面板上进行显示时会显示两组P11R＋、P11G－、P11B＋/ P11R－、P11G＋、P11B－，此时，无法单独关闭其中一个极性的画面显示，所以必须将全高清输入的一个RGB像素点在经TCON输入至超高清显示面板上进行显示时会显示两组P11R＋、P11G＋、P11B－/ P11R－、P11G＋、P11B＋，也即设定图像信号，使其在全高清显示面板上以行反转驱动时，显示正极性的奇数列像素点的绿色子像素显示，其余子像素不显示，如图2中的71所示，此时，将该图像信号经全高清的逻辑板输入至超高清显示面板并控制栅极驱动信号输入，对图像进行显示时会显示如图2中72所示的显示画面，也即在超高清显示面板上进行驱动显示时，在奇数列内显示正极性的绿色子像素与下一帧不显示的负极性的绿色子像素之间会存在亮度差异，在栅极驱动信号驱动超高清显示面板进行画面显示时就能够在显示画面上看到闪烁。
在一实施例中，在图像信号在全高清显示面板上以两列反转驱动时，显示正极性的奇数列奇数行和偶数列偶数行的交叉像素点的绿色子像素显示，其余子像素不显示，如图3中的73所示，此时，将该图像信号经全高清的逻辑板输入至超高清显示面板并控制栅极驱动信号输入，对图像进行显示时会显示如图3中74所示的显示画面，也即在在超高清显示面板上显示图像时，也即在超高清显示面板上进行驱动显示时，在奇数列奇数行和偶数列偶数行的交叉像素点内显示正极性的绿色子像素与下一帧不显示的负极性的绿色子像素之间会存在亮度差异，在栅极驱动信号驱动超高清显示面板进行画面显示时就能够在显示画面上看到闪烁。
本申请的显示驱动方法，通过设定需要输入的图像信号，使该图像信号在全高清显示面板上驱动时，显示正极性的绿色子像素显示，其余子像素不显示，然后将设定好的图像信号通过全高清的逻辑板输入至超高清面板，最后通过输入栅极驱动信号，就能够看到明暗交错的图像显示，也即实现了闪烁确认，以便对超高清显示面板的显示电极的电压进行最佳化调试。
在一实施例中，参照图4，基于上述实施例的显示驱动方法，步骤S20具体包括：
S21：接收所述图像信号，解码后分为第一分区图像信号及第二分区图像信号；
S22：将第一分区图像信号复制得到第三分区图像信号及第四分区图像信号，将第二分区图像信号复制得到第五分区图像信号及第六分区图像信号；
S23：将所述第三分区图像信号、第四分区图像信号，及第五分区图像信号、第六分区图像信号输入至所述显示面板。
在本实施例中，在全高清的显示面板上设定好超高清显示面板需要输入的图像信号后，由全高清的TCON（Timer Control Register，逻辑板）将所述图像信号最终分成四路信号，分别为第三分区图像信号、第四分区图像信号，及第五分区图像信号、第六分区图像信号，每一分区图像信号各负责1/4的画面显示，以匹配超高清显示面板。
参照图2和图3，输入的图像信号在全高清的显示面板上显示的像素为11、12、13、21、22、23、31、32、33、41、42、43，经过全高清的TCON解码及复制处理后，单个像素均被复制成了四个，在超高清显示面板上呈现相邻像素点均显示相同解析度的显示效果，实现了利用全高清的图像信号驱动超高清显示面板进行显示，节省了成本。
参照图5，显示面板70的驱动的通常由源极驱动器50和栅极驱动器60共同配合完成的。在设定好的全高清图像信号输入至TCON（Timer Control Register，逻辑板）40后，经变换处理后生成控制超高清显示面板的子像素的驱动极性的数据信号，源极驱动器50的时钟控制信号DSP/DCK，及栅极驱动器60的时钟控制信号GSP/GCK。具体是，通过源极驱动器50装载数据信号控制RGB子像素的驱动极性，通过栅极驱动器60控制时序，对超高清显示面板的扫描线成对驱动，即可在超高清显示面板上显示一帧亮、一帧暗的闪烁显示。
参照图6中的显示驱动装置80及图7中显示驱动装置80的右侧部分线路81，本申请实施例中，采用UD（Ultra High Definition，超高清） 的1D1G（其中，D表示数据线，G表示扫描线，数据线和扫描线独立输入的数量均为1）驱动架构方案。该驱动架构包括12颗源极驱动器以及12颗栅极驱动器。其中，12颗源极驱动器以及12颗栅极驱动器呈对称设置。
实际设置中，12颗源极驱动器分成左右两组，每一组均包括6颗源极驱动器。其中，每3颗源极驱动器共用一个数据接口。因而12颗源极驱动器总共包括四个数据接口，以分别接收全高清 TCON输入的四路图像信号。
由于左右两组源极驱动结构完全相同，这里以右边的一组进行说明。
右边的一组包括由向左依次排列的源极驱动器S1、S2、S3、S4、S5、S6。每一源极驱动器包括1路时钟线、6路数据线及1路数据传输触发线。源极驱动器S1、S2、S3共用一个数据接口，S4、S5、S6则共用一个数据接口。
其中S1、S2、S3的各自6路数据线一一短接、时钟线一一短接、数据传输触发线一一短接，短接之后的从A接口引出，与TCON板连接。同理，S4、S5、S6短接之后从B接口引出。A接口的引出线包括1路时钟线R-ACLK，6路数据线分别为R-ALV0~R-ALV5；B接口的引出线包括1路时钟线R-BCLK，6路数据线分别为R-BLV0~R-BLV5。A、B接口还各包括数据传输触发线S3-DIO1、S4-DIO2。此外，右边的一组还包括有模式切换线UCFT mode（unsteady cooperative flow type mode，非定常耦合流型），该切换线分别与S1、S2、S3、S4、S5、S6连接，以便于切换超高清模式和全高清模式两种显示驱动模式。
易于理解的是，左边的一组包括C接口及D接口；C接口的引出线包括1路时钟线R-CCLK，6路数据线分别为R-CLV0~R-CLV5；D接口的引出线包括1路时钟线R-DCLK，6路数据线分别为R-DLV0~R-DLV5。C、D接口还各包括数据传输触发线S9-DIO3、S10-DIO4。此外，左边的一组还包括有模式切换线UCFT mode，该切换线分别与S7、S8、S9、S10、S11、S12连接，以便于切换超高清模式和全高清模式两种显示驱动模式。
每一个源极驱动器驱动320列像素，12个源极驱动器总共驱动3840列像素。
本实施例中，还包括12颗栅极驱动器分别为GR1~GR6，GL1~GL6，其中GR1~GR6位于显示面板的右侧，GL1~GL6位于显示面板的左侧。每一栅极驱动器驱动360行像素。本实施例中，共有2160行像素，P1~P2160。具体地，所述栅极驱动信号对显示面板的扫描线成对驱动。即先驱动P1/P2，然后依次P3/P4、P5/P6••••••一直到P2159/P2160。
本实施例中，所述第三分区图像信号及所述第四分区图像信号均为差分信号。即接口A、B、C、D输入为微型低电压差动讯号(mini-Low Voltage Differential Signal，mini-LVDS)。
具体地， 将第三分区图像的信号线与第四分区图像信号的信号线一一连接后接收输入的所述第一分区图像信号；将第五分区图像的信号线与第六分区图像信号的信号线一一连接后接收输入的第二分区图像信号。本实施例中是通过短接每个源极驱动器对应的输入线来复制信号。
具体地，所述第三分区图像信号、第四分区图像信号、第五分区图像信号、第六分区图像信号均包括两路RGB像素信号。
需要说明的是，例如R-ALV0~R-ALV2输入1路RGB像素信号，R-ALV3~R- ALV5输入1路RGB像素信号。
在一实施例中，将所述显示面板的第二、第一、第三子像素列按第2n＋1列和第2n＋2列的组合分别成组，0≤n≤5759，在行反转和两列反转驱动模式下，同一组内第二、第一、第三子像素的极性相同，相邻组间第二、第一、第三子像素的极性相反。
如图2和图3所述，超高清显示面板的分辨率为3840×2160，也即超高清显示面板共有3840×2160个像素点，每个像素点包含3个RGB子像素，也即将第1＆2、3＆4、5＆6……2n＋1＆2n＋2列分别成组，所述列定义为全部由同一子像素排列成组，所述行定义为由不同子像素排列成组，在某些实施方式中，行与列在同一平面上形成一定的角度，可选的，行与列垂直。则同一组内的红、绿、蓝子像素列的极性相同，相邻组间红、绿、蓝子像素的极性相反，如图2中第一组内P11到P41的子像素R和G均显示正极性，第二组内P11到P41的子像素B和R均显示负极性，第三组内P11到P41的绿色子像素和B均显示正极性，第四组内P12到P42的子像素R和G均显示负极性。
基于上述显示驱动方法，本申请还提出一种显示驱动装置。
参照图8，图8为本申请的显示驱动装置一实施例的功能模块图。
在本实施例中，该显示驱动装置100包括：
图像信号设定模块10，设定图像信号，使所述图像信号在显示面板上驱动时，显示正极性的第一子像素显示，其余子像素不显示；
图像信号输入模块20，将所述图像信号经逻辑板复制后输入至所述显示面板；
显示模块30，控制栅极驱动信号输入，对图像进行显示。
在一实施例中，所述图像信号设定模块10还用于：设定图像信号，使所述图像信号在显示面板上以行反转驱动时，显示正极性的奇数列像素点的第一子像素显示，其余子像素不显示；或者在所述显示面板上以两列反转驱动时，显示正极性的奇数列奇数行和偶数列偶数行的交叉像素点的第一子像素显示，其余子像素不显示。
在本实施例中，该显示驱动装置100基于全高清的TCON，将全高清显示面板上的显示画面复制后在超高清显示面板上显示，因为闪烁的实现需要显示同一极性的子像素，且必须是正极性的子像素，而一般情况下，全高清输入的一个RGB像素点，如P11R、P11G、P11B，在经TCON输入至超高清显示面板上进行显示时会显示两组P11R＋、P11G－、P11B＋/ P11R－、P11G＋、P11B－，此时，无法单独关闭其中一个极性的画面显示，所以必须将全高清输入的一个RGB像素点在经TCON输入至超高清显示面板上进行显示时会显示两组P11R＋、P11G＋、P11B－/ P11R－、P11G＋、P11B＋，也即由图像信号设定模块10设定图像信号，使其在全高清显示面板上以行反转驱动时，显示正极性的奇数列像素点的绿色子像素显示，其余子像素不显示，此时，图像信号输入模块20将该图像信号经全高清的逻辑板输入至超高清显示面板，且显示模块30控制栅极驱动信号输入，对图像进行显示时会显示如图2所述的显示画面，也即在超高清显示面板上进行驱动显示时，在奇数列内显示正极性的绿色子像素与下一帧不显示的负极性的绿色子像素之间会存在亮度差异，在栅极驱动信号驱动超高清显示面板进行画面显示时就能够在显示画面上看到闪烁。
在一实施例中，图像信号设定模块10在图像信号在全高清显示面板上以两列反转驱动时，设定显示正极性的奇数列奇数行和偶数列偶数行的交叉像素点的绿色子像素显示，其余子像素不显示，此时，在图像信号输入模块20将该图像信号经全高清的逻辑板输入至超高清显示面板，且显示模块30控制栅极驱动信号输入，对图像进行显示时会显示如图3所述的显示画面，也即在在超高清显示面板上显示图像时，也即在超高清显示面板上进行驱动显示时，在奇数列奇数行和偶数列偶数行的交叉像素点内显示正极性的绿色子像素与下一帧不显示的负极性的绿色子像素之间会存在亮度差异，在栅极驱动信号驱动超高清显示面板进行画面显示时就能够在显示画面上看到闪烁。
本申请的显示驱动装置100，通过图像信号设定模块10设定需要输入的图像信号，使该图像信号在全高清显示面板上驱动时，显示正极性的绿色子像素显示，其余子像素不显示，然后由图像信号输入模块20将设定好的图像信号通过全高清的逻辑板输入至超高清面板最后通过显示模块30控制栅极驱动信号输入，就能够看到明暗交错的图像显示，也即实现了闪烁确认，以便对超高清显示面板的显示电极的电压进行最佳化调试。
在一实施例中，参照图8，所述图像信号输入模块20包括：
解码单元21，接收所述图像信号，解码后分为第一分区图像信号及第二分区图像信号；
时序处理单元22，将第一分区图像信号复制得到第三分区图像信号及第四分区图像信号，将第二分区图像信号复制得到第五分区图像信号及第六分区图像信号；
信号输入单元23，将所述第三分区图像信号、第四分区图像信号，及第五分区图像信号、第六分区图像信号输入至所述显示面板。
在本实施例中，在全高清的显示面板上设定好超高清显示面板需要输入的图像信号后，由全高清的TCON将所述图像信号最终分成四路信号，分别为第三分区图像信号、第四分区图像信号，及第五分区图像信号、第六分区图像信号，每一分区图像信号各负责1/4的画面显示，以匹配超高清显示面板。
参照图2和图3，输入的图像信号在全高清的显示面板上显示的像素为11、12、13、21、22、23、31、32、33、41、42、43，经过全高清的TCON解码及复制处理后，单个像素均被复制成了四个，在超高清显示面板上呈现相邻像素点均显示相同解析度的显示效果，实现了利用全高清的图像信号驱动超高清显示面板进行显示，节省了成本。
参照图5，显示面板的驱动的通常由源极驱动器和栅极驱动器共同配合完成的。在设定好的全高清图像信号输入至TCON后，经变换处理后生成控制超高清显示面板的子像素的驱动极性的数据信号，源极驱动器的时钟控制信号DSP/DCK，及栅极驱动器的时钟控制信号GSP/GCK。具体是，通过源极驱动器装载数据信号控制RGB子像素的驱动极性，通过栅极驱动器控制时序，对超高清显示面板的扫描线成对驱动，即可在超高清显示面板上显示一帧亮、一帧暗的闪烁显示。
在一实施例中，将所述显示面板的第二、第一、第三子像素列按第2n＋1列和第2n＋2列的组合分别成组，0≤n≤5759，在行反转和两列反转驱动模式下，同一组内第二、第一、第三子像素的极性相同，相邻组间第二、第一、第三子像素的极性相反。
如图2和图3所述，超高清显示面板的分辨率为3840×2160，也即超高清显示面板共有3840×2160个像素点，每个像素点包含3个RGB子像素，也即将第1＆2、3＆4、5＆6……2n＋1＆2n＋2列分别成组，所述列定义为全部由同一子像素排列成的组，所述行定义为由不同子像素排列成的组，在某些实施方式中，行与列在同一平面上形成一定的角度，可选的，行与列垂直。同一组内的红、绿、蓝子像素列的极性相同，相邻组间红、绿、蓝子像素的极性相反，如图2中第一组内P11到P41的子像素R和G均显示正极性，第二组内P11到P41的子像素B和R均显示负极性，第三组内P11到P41的绿色子像素和B均显示正极性，第四组内P12到P42的子像素R和G均显示负极性。
本领域普通技术人员应当理解，本申请还提供一种显示面板的驱动装置，该驱动装置包括处理器和非易失性存储器，该非易失性存储器存储可执行指令，该处理器执行可执行指令用以实现以上所描述的各实施例所记载的方法。本领域普通技术人员应当进一步理解，本申请附图8中所显示的模块/单元10、20、21、22、23、30可为软件模块或软件单元。此外，各种软件模块或软件单元可以固有地存储在非易失性存储器中并通过处理器进行执行。
以上仅为本申请的优选实施例，并非因此限制本申请的专利范围，凡是利用本申请说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本申请的专利保护范围内。

Claims (20)

  1. 一种通过计算设备执行的驱动显示的方法，其中，所述方法包括以下步骤：
    处理器设定图像信号，使所述图像信号在显示面板上驱动时，显示正极性的第一子像素显示，其余子像素不显示；
    将所述图像信号经逻辑板复制后输入至所述显示面板；
    控制栅极驱动信号输入，对图像进行显示。
  2. 如权利要求1所述的方法，其中，所述设定图像信号，使所述图像信号在显示面板上驱动时，显示正极性的第一子像素显示，其余子像素不显示，包括：
    设定图像信号，使所述图像信号在显示面板上以行反转驱动时，显示正极性的奇数列像素点的第一子像素显示，其余子像素不显示；或者在所述显示面板上以两列反转驱动时，显示正极性的奇数列奇数行和偶数列偶数行的交叉像素点的第一子像素显示，其余子像素不显示。
  3. 如权利要求1所述的方法，其中，所述将所述图像信号经逻辑板复制后输入至所述显示面板，包括：
    接收所述图像信号，解码后分为第一分区图像信号及第二分区图像信号；
    将第一分区图像信号复制得到第三分区图像信号及第四分区图像信号，将第二分区图像信号复制得到第五分区图像信号及第六分区图像信号；
    将所述第三分区图像信号、第四分区图像信号，及第五分区图像信号、第六分区图像信号输入至所述显示面板。
  4. 如权利要求1所述的方法，其中，所述栅极驱动信号对所述显示面板的扫描线成对驱动。
  5. 如权利要求1所述的方法，其中，将所述显示面板的第二、第一、第三子像素列按第2n＋1列和第2n＋2列的组合分别成组，0≤n≤5759，在行反转和两列反转驱动模式下，同一组内第二、第一、第三子像素的极性相同，相邻组间第二、第一、第三子像素的极性相反。
  6. 如权利要求1所述的方法，其中，所述显示面板的子像素的驱动极性由输入的数据信号控制。
  7. 如权利要求2所述的方法，其中，所述显示面板的子像素的驱动极性由输入的数据信号控制。
  8. 如权利要求3所述的方法，其中，所述显示面板的子像素的驱动极性由输入的数据信号控制。
  9. 如权利要求4所述的方法，其中，所述显示面板的子像素的驱动极性由输入的数据信号控制。
  10. 如权利要求5所述的方法，其中，所述显示面板的子像素的驱动极性由输入的数据信号控制。
  11. 一种显示驱动装置，其中，所述显示驱动装置包括处理器和存储器，所述存储器存储可执行指令，所述处理器执行所述可执行指令，所述可执行指令包括：
    图像信号设定模块，用以设定图像信号，使所述图像信号在显示面板上驱动时，显示正极性的第一子像素显示，其余子像素不显示；
    图像信号输入模块，用以将所述图像信号经逻辑板复制后输入至所述显示面板；
    显示模块，用以控制栅极驱动信号输入，对图像进行显示。
  12. 根据权利要求11所述的装置，其中，所述图像信号设定模块设置为：
    设定图像信号，使所述图像信号在显示面板上以行反转驱动时，显示正极性的奇数列像素点的第一子像素显示，其余子像素不显示；或者在所述显示面板上以两列反转驱动时，显示正极性的奇数列奇数行和偶数列偶数行的交叉像素点的第一子像素显示，其余子像素不显示。
  13. 根据权利要求11所述的装置，其中，所述图像信号输入模块包括：
    解码单元，接收所述图像信号，解码后分为第一分区图像信号及第二分区图像信号；
    时序处理单元，将第一分区图像信号复制得到第三分区图像信号及第四分区图像信号，将第二分区图像信号复制得到第五分区图像信号及第六分区图像信号；
    信号输入单元，将所述第三分区图像信号、第四分区图像信号，及第五分区图像信号、第六分区图像信号输入至所述显示面板。
  14. 根据权利要求11所述的装置，其中，所述栅极驱动信号对所述显示面板的扫描线成对驱动。
  15. 根据权利要求11所述的装置，其中，将所述显示面板的第二、第一、第三子像素列按第2n＋1列和第2n＋2列的组合分别成组，0≤n≤5759，在行反转和两列反转驱动模式下，同一组内第二、第一、第三子像素的极性相同，相邻组间第二、第一、第三子像素的极性相反。
  16. 根据权利要求11所述的装置，其中，所述显示面板的子像素的驱动极性由输入的数据信号控制。
  17. 根据权利要求12所述的装置，其中，所述显示面板的子像素的驱动极性由输入的数据信号控制。
  18. 根据权利要求13所述的装置，其中，所述显示面板的子像素的驱动极性由输入的数据信号控制。
  19. 根据权利要求14所述的装置，其中，所述显示面板的子像素的驱动极性由输入的数据信号控制。
  20. 根据权利要求15所述的装置，其中，所述显示面板的子像素的驱动极性由输入的数据信号控制。
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