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WO2018199601A1 - Tranche montée sur un capteur - Google Patents

Tranche montée sur un capteur Download PDF

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Publication number
WO2018199601A1
WO2018199601A1 PCT/KR2018/004753 KR2018004753W WO2018199601A1 WO 2018199601 A1 WO2018199601 A1 WO 2018199601A1 KR 2018004753 W KR2018004753 W KR 2018004753W WO 2018199601 A1 WO2018199601 A1 WO 2018199601A1
Authority
WO
WIPO (PCT)
Prior art keywords
wafer
electrode
recess
sensor
bonded
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/KR2018/004753
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English (en)
Korean (ko)
Inventor
배정운
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sntek Co Ltd
Original Assignee
Sntek Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from KR1020170055160A external-priority patent/KR101807492B1/ko
Priority claimed from KR1020170057403A external-priority patent/KR101807495B1/ko
Application filed by Sntek Co Ltd filed Critical Sntek Co Ltd
Publication of WO2018199601A1 publication Critical patent/WO2018199601A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere

Definitions

  • the present invention relates to a sensor-mounted wafer in which wafers are bonded to support processes performed at different temperature conditions while mounting sensor circuits for monitoring a semiconductor process.
  • the uniformity of wafer temperature in the semiconductor manufacturing process is an important factor in managing the material surface structure and the properties of deposition and etching.
  • the temperature in the chamber was indirectly measured in semiconductor manufacturing, but researches for directly measuring the internal temperature of the chamber or the temperature of the wafer loaded in the chamber have continued to improve semiconductor yield.
  • the method of connecting a lead wire to each conventional sensor as mentioned above had a structure which mounts a sensor on a test wafer, and connects each sensor with a lead wire.
  • This structure has the advantage of low cost in the case of single product production, but in the case of mass production, the production cost is increased by additional fixing such as a manual process for connecting lead wires or a process for electrical insulation of lead wires.
  • Japanese Patent Laid-Open No. 2011-59132 introduces an apparatus for detecting temperature on an integrated circuit fabrication tool substrate.
  • 1 is a diagram illustrating a structure for detecting a temperature on a substrate according to the prior art, in which a sensor 30 is bonded in a cavity 28 formed in the substrate 20, and the sensor 30 is sealed with a sealing compound.
  • the filling is a configuration in which the sensor lead wire 36 is provided through a sealing layer 38, and the sensor lead wire 36 is connected to an electrode for transmitting a sensing value.
  • a process of bonding a sensor to a cavity formed in a substrate is required, and a process of filling a cavity inner space in which a sensor is bonded with a sealing layer is required, and an electrical connection for transferring a sensing value of the sensor is required.
  • a process of connecting a lead wire to an electrode provided outside the cathy was required.
  • a cavity of sufficient depth larger than the size of the sensor was required.
  • the temperature sensing device according to the prior art has a limit range that normally operates only at a specific process temperature, it is not possible to use it in various processes. That is, the temperature sensing device of the prior art cannot be used universally in different processes performed under different temperature conditions, and the temperature sensing device should be used exclusively according to the process temperature conditions. For example, it was not possible to use a temperature sensing device that withstands low process temperatures in a high temperature process.
  • An object of the present invention has been made in view of the above points, in particular, such as bonding process for the electrical connection between the sensor and the electrode, connecting the lead wire to the sensor and sealing process for filling the cavity interior space while improving the semiconductor yield It is to provide a sensor-mounted wafer that can be manufactured without unnecessary processes.
  • Still another object of the present invention is to provide a sensor-mounted wafer that can be used universally in a process performed at a high temperature or a low temperature without limiting the process temperature.
  • a sensor-mounted wafer in accordance with the present invention for achieving the above objects comprises: a first wafer having at least one recess; And a second wafer of an upper portion having at least one recess and bonded to the first wafer, wherein the first wafer has a first recess, an inner side of the first recess, and the first wafer.
  • the first wafer and the second wafer may be bonded in a vacuum atmosphere.
  • the first wafer and the second wafer has a different thickness
  • the second wafer may have a relatively larger thickness than the first wafer.
  • the second wafer may include a second recess formed to face the first recess so as to cover the first sensor circuit at the time of bonding with the first wafer.
  • the first wafer further includes a third recess, a second sensor circuit inside the third recess, and a third electrode electrically contacting the second sensor circuit.
  • the second wafer may include a bridge electrode for crosslinking the second electrode and the third electrode.
  • the first sensor circuit may be welded to the first electrode and the second electrode on the bottom surface of the first recess.
  • the recess provided in the first wafer or the second wafer may have an inclined inner wall.
  • the first wafer and the second wafer may have at least one bonding pad facing each other up and down on the outer side.
  • the second wafer may include a fourth recess, a second insulating layer formed on the inner surface of the fourth recess and the upper surface of the second wafer, and from one side of the upper surface of the second wafer.
  • a fourth electrode formed on the second insulating layer over one inner wall of one side of the fourth recess and one side of the bottom surface, and an upper portion of the second wafer while being spaced apart from the fourth electrode on the bottom surface of the fourth recess;
  • a fifth electrode formed on the second insulating layer from the other side of the surface to the other inner wall of the fourth recess and the other side of the bottom surface; and the fifth electrode and the fifth electrode on the bottom surface of the fourth recess. It may have a third sensor circuit in electrical contact.
  • the first wafer further includes a sixth electrode formed to be spaced apart from the second electrode on an upper surface thereof, when the first wafer and the second wafer are bonded to each other, the first wafer is electrically connected to the second wafer.
  • the sixth electrode may contact the fourth electrode of the second wafer for connection.
  • the second wafer further includes a seventh electrode formed on an upper surface of the second wafer to be spaced apart from the fourth electrode. When the first wafer and the second wafer are bonded to each other, the second wafer may be electrically connected to the first wafer.
  • the seventh electrode may be in contact with the second electrode of the first wafer.
  • the third sensor circuit may be welded to the fourth electrode and the fifth electrode on the bottom surface of the fourth recess.
  • the first wafer and the second wafer are further provided with electrodes which are in contact with each other for electrical connection between the first wafer and the second wafer. can do.
  • the complexity in the overall structure of the wafer for measuring the temperature in the chamber is significantly reduced.
  • the wafer of the present invention when the wafer of the present invention is mounted for monitoring a semiconductor process, only a simple operation of changing the vertical arrangement structure can be used universally in processes performed at high or low temperatures without limiting the process temperature.
  • FIG. 1 is a diagram for explaining a structure for detecting a temperature on a substrate according to the prior art
  • FIG. 2 is a cross-sectional view showing the structure of a sensor-mounted wafer according to an embodiment of the present invention
  • FIG. 3 is a cross-sectional view illustrating bonded shapes of wafers in the embodiment of FIG. 2;
  • FIG. 4 is a cross-sectional view illustrating a structure of a sensor-mounted wafer according to another embodiment of the present invention.
  • FIG. 5 is a cross-sectional view illustrating bonded shapes of wafers in the embodiment of FIG. 4;
  • FIG. 6 is a plan view for explaining the electrical connection structure between the electrodes in FIG.
  • FIG. 7 is a cross-sectional view illustrating a structure of a low temperature wafer in a sensor-mounted wafer according to an embodiment of the present invention.
  • FIG. 8 is a cross-sectional view illustrating a structure of a high temperature wafer in a sensor-mounted wafer according to an embodiment of the present invention.
  • FIG. 9 is a cross-sectional view illustrating a face-to-face structure of a low temperature wafer and a high temperature wafer in a sensor-mounted wafer according to an embodiment of the present invention.
  • FIG. 10 is a cross-sectional view illustrating bonded shapes of wafers in the embodiment of FIG. 9;
  • FIG. 11 is a cross-sectional view illustrating another example of an electrical connection structure between wafers in a sensor-mounted wafer according to an embodiment of the present invention
  • FIG. 12 is a plan view illustrating an electrical connection structure between wafers in a sensor-mounted wafer according to the present invention.
  • FIG. 2 is a cross-sectional view illustrating a structure of a sensor-mounted wafer according to an embodiment of the present invention
  • FIG. 3 is a cross-sectional view illustrating bonded shapes of wafers in the embodiment of FIG. 2.
  • the sensor-mounted wafer according to an embodiment of the present invention is formed by bonding the first wafer 10 and the second wafer 20.
  • the first wafer 10 and the second wafer 20 are bonded in a vacuum atmosphere, and thus the space formed between the first wafer 10 and the second wafer 20 may be in a vacuum shielded from the outside. .
  • the first wafer 10 forms a lower structure, and the second wafer 20 is bonded to the upper portion of the first wafer 10.
  • the first wafer 10 has a first recess 11 forming a recess of a predetermined depth.
  • the first recess 11 may have an inclined inner wall.
  • the first wafer 10 having the first recess 11 includes the first insulating layer 12 on the entire upper surface thereof.
  • the first insulating layer 12 is formed on the inner surface including the bottom surface and the inner wall of the first recess 11 and the upper surface of the first wafer 10.
  • the first insulating layer 12 may be a silicon oxide layer (SiO 2 ) or a silicon nitride layer (SiNx).
  • the first wafer 10 includes the first electrode 15 and the second electrode 16 in the region where the first recess 11 is formed.
  • the first electrode 15 is formed on the first insulating layer 12 from one side of the upper surface of the first wafer 10 to one side of the inner wall and the bottom surface of the first recess 11.
  • the second electrode 16 is formed on the first insulating layer 12 from the other side of the upper surface of the first wafer to the other inner wall of the first recess 11 and the other side of the bottom surface.
  • the first electrode 15 and the second electrode 16 is preferably formed to be spaced apart from the bottom surface of the first recess (11).
  • the first wafer 10 includes a first sensor circuit 18 inside the first recess 11.
  • the first sensor circuit 18 is in electrical contact with the first electrode 15 and the second electrode 16 at the bottom surface of the first recess 11.
  • the first sensor circuit 18 may be welded to the first electrode 15 and the second electrode 16 at the bottom surface of the first recess 11.
  • the first wafer 10 may include a ball grid array that electrically contacts the first sensor circuit 18 to the first electrode 15 and the second electrode 16.
  • the first wafer 10 may have at least one bonding pad 13 and 14 at an outer side thereof.
  • the bonding pad may be formed of the same material as the first electrode 15 and the second electrode 16, and thus may be formed by the same process as the first electrode 15 and the second electrode 16.
  • the second wafer 20 bonded to the first wafer 10 has a second recess 21 forming a recess of a predetermined depth.
  • the second recess 21 may also have an inclined inner wall in the same manner as the first recess 11.
  • the second recess 21 is formed to cover the first sensor circuit 18 from above, and for this purpose, the second recess 21 is formed in the first wafer 10. It is preferably formed opposite to.
  • the size of the first recess 11 and the second recess 21 is preferably formed in consideration of the size of the sensor circuit 18.
  • the first wafer 10 and the second wafer 20 are formed.
  • the width and depth of the internal space formed by the first recess 11 and the second recess 21 may be formed in consideration of the size of the sensor circuit 18.
  • the second wafer 20 may have at least one bonding pad 23 and 24 on the outer side thereof.
  • the bonding pads 23.24 may be formed of the same material as the bonding pads 13 and 14 of the first wafer 10.
  • the bonding pads 23 and 24 of the second wafer 20 may be formed by the same process as the fourth electrode 27 and the fifth electrode 28 described later.
  • the bonding pads 13 and 14 of the first wafer 10 and the bonding pads 23 and 24 of the second wafer 20 are provided to face each other up and down, and the first wafer 10 and the second wafer 20 are provided to face each other. ) Is bonded, the bonding pads 13 and 14 of the first wafer 10 and the bonding pads 23 and 24 of the second wafer 20 are physically coupled.
  • FIG. 4 is a cross-sectional view illustrating a structure of a sensor-mounted wafer according to another embodiment of the present invention
  • FIG. 5 is a cross-sectional view illustrating bonded shapes of wafers in the embodiment of FIG. 4, and
  • FIG. It is a top view for demonstrating an electrical connection structure.
  • the sensor-mounted wafer according to another embodiment of the present invention has a configuration in which an electrode for electrical connection between sensor circuits is added as compared to the sensor-mounted wafer described in FIGS. 2 and 3. Therefore, in the description of the sensor-mounted wafers of FIGS. 4 to 6, the same reference numerals are used for the same configuration as the sensor-mounted wafers of FIGS. 2 and 3, and the description of the same configuration is omitted.
  • the sensor-mounted wafer according to the present invention may include a micro control unit (MCU), a wireless data communication circuit, a battery, a wireless charging circuit, a memory, etc. in addition to the sensor circuit 18, and electrically connect them via electrodes or electrode lines. do.
  • MCU micro control unit
  • the electrode lines must be designed to overlap, and for the electrical separation at the overlapping portion, a method of bypassing some electrode lines by forming a via hole must be used.
  • the electrode for the electrical connection between the circuit is formed by dividing the first wafer 10 and the second wafer 20, and bonding the first wafer 10 and the second wafer 20 Apply a structure that allows the electrodes to be connected. 4 to 6 are used bridge electrodes 25 which serve as bridges for the connection between these electrodes.
  • the first wafer 10 may further include a third recess (not shown) for forming another circuit, that is, the second sensor circuit 40. Accordingly, the second sensor circuit 40 is provided inside the third recess (not shown).
  • the first wafer 10 includes electrodes having the same structure as the first electrode 15 and the second electrode 16 as well as the third recess (not shown).
  • the third electrode 17 shown in FIGS. 4 to 6 may be one of them.
  • the third electrode 17 is formed on the first wafer 10 to be in electrical contact with the second sensor circuit 40.
  • the second electrode 16 and the third electrode 17 In order to electrically connect the first sensor circuit 18 and the second sensor circuit 40, the second electrode 16 and the third electrode 17 must be physically connected, but the first wafer 10 is There is no physical connection means.
  • the second wafer 20 includes a bridge electrode 25 for physically connecting the second electrode 16 and the third electrode 17.
  • the bridge electrode 25 is for crosslinking the second electrode 16 and the third electrode 17, and one end of the bridge electrode 25 is bonded as the first wafer 10 and the second wafer 20 are bonded. It is physically connected to the second electrode 16 and the other end of the bridge electrode 25 is physically connected to the third electrode 17. Accordingly, the first sensor circuit 18 and the second sensor circuit 40 are electrically connected through the second electrode 16, the bridge electrode 25, and the third electrode 17.
  • FIG. 7 is a cross-sectional view illustrating a structure of a low temperature wafer in a sensor-mounted wafer according to an embodiment of the present invention
  • FIG. 8 is a cross-sectional view illustrating a structure of a high temperature wafer in a sensor-mounted wafer according to an embodiment of the present invention
  • 9 is a cross-sectional view illustrating a facing structure of a low temperature wafer and a high temperature wafer in a sensor-mounted wafer according to an embodiment of the present invention
  • FIG. 10 is a view illustrating bonded shapes of wafers in the embodiment of FIG. 9. It is a cross section.
  • the sensor-mounted wafer according to an embodiment of the present invention has a configuration in which an electrode for electrical connection between the sensor circuit and the sensor circuit is added as compared to the sensor-mounted wafer described in FIGS. 2 to 6. Therefore, in the description of the sensor-mounted wafer of FIGS. 7 to 10, the same reference numerals are used for the same configuration as the sensor-mounted wafer of FIGS. 2 to 6, and the description of the same configuration is omitted.
  • the first wafer 10 and the second wafer 20 are bonded to each other.
  • the first wafer 10 and the second wafer 20 to be bonded may have different thicknesses.
  • the second wafer 20 may have a relatively larger thickness than the first wafer 10.
  • the first sensor circuit 18 may be welded to electrically contact the first electrode 15 and the second electrode 16 at the bottom surface of the first recess 11.
  • the first wafer 10 includes a welding unit 19 for welding the first electrode 15, the second electrode 16, and the first sensor circuit 18.
  • the welding unit 19 may be a ball grid array that electrically contacts the first sensor circuit 18 to the first electrode 15 and the second electrode 16.
  • the second wafer 20 bonded to the first wafer 10 includes a second recess 21 and a fourth recess 26 forming recesses having a predetermined depth.
  • the second recess 21 may also have an inclined inner wall in the same manner as the first recess 11.
  • the fourth recess 26 may also have an inclined inner wall.
  • the second wafer 20 includes a third sensor circuit 29 inside the fourth recess 26.
  • the second wafer 20 having the second recess 21 and the fourth recess 26 includes a second insulating layer 22 on the entire upper surface thereof.
  • the second insulating layer 22 may include an inner side including the bottom and inner walls of the second recess 21 and an inner side and the second wafer 20 including the bottom and inner walls of the fourth recess 26. It is formed on the upper surface.
  • the second insulating layer 22 may be formed of the same oxide or nitride as the first insulating layer 12, and may be a silicon oxide layer (SiO 2 ) or a silicon nitride layer (SiNx).
  • the second wafer 20 includes a fourth electrode 27 and a fifth electrode 28 in the region where the fourth recess 26 is formed.
  • the fourth electrode 27 is formed from one side of the upper surface of the second wafer 20 to one side of the inner wall and the bottom surface of one side of the fourth recess 26.
  • the fifth electrode 28 is formed from the other side of the upper surface of the second wafer 20 to the other inner wall and the other side of the bottom surface of the fourth recess 26.
  • the fourth electrode 27 and the fifth electrode 28 is preferably formed to be spaced apart from the bottom surface of the fourth recess (26).
  • the third sensor circuit 29 is in electrical contact with the fourth electrode 27 and the fifth electrode 28 on the bottom surface of the fourth recess 26.
  • the third sensor circuit 29 may be welded to the fourth electrode 27 and the fifth electrode 28 on the bottom surface of the fourth recess 26.
  • the second wafer 20 includes a welding part 30 for welding the fourth electrode 27, the fifth electrode 28, and the third sensor circuit 29.
  • the second wafer 20 may include a ball grid array that electrically contacts the third sensor circuit 29 to the fourth electrode 27 and the fifth electrode 28.
  • the bonding pads 13 and 14 of the first wafer 10 and the bonding pads 23 and 24 of the second wafer 20 are moved up and down. Opposing each other, the bonding pads 13 and 14 of the first wafer 10 and the bonding pads 23 and 24 of the second wafer 20 are physically coupled.
  • FIG. 11 is a cross-sectional view illustrating another example of an electrical connection structure between wafers in a sensor-mounted wafer according to an embodiment of the present invention
  • FIG. 12 illustrates an electrical connection structure between wafers in a sensor-mounted wafer according to the present invention. It is a top view for doing this.
  • the first wafer 10 is spaced apart from the second electrode 16 for electrical connection between the first wafer 10 and the second wafer 20.
  • the sixth electrode 31 may be further provided, and the second wafer 20 may further include a seventh electrode 32 spaced apart from the fourth electrode 27.
  • the sixth electrode 31 may be formed on the upper surface of the first wafer 10
  • the seventh electrode 32 may be formed on the upper surface of the second wafer 20.
  • a sixth electrode formed on the upper surface of the first wafer 10. 31 may be in contact with and electrically connected to the fourth electrode 27 formed on the upper surface of the second wafer 20.
  • the second wafer 20 may not further include a seventh electrode 32 spaced apart from the fourth electrode 27.
  • the seventh electrode 32 formed on the upper surface of the second wafer 20 is formed. In contact with the second electrode 16 formed on the upper surface of the first wafer 10 may be electrically connected. In this case, the first wafer 10 may not further include a third electrode 17 spaced apart from the second electrode 16.
  • the seventh electrode 32 formed on the upper surface of the second wafer 20 may be in contact with and electrically connected to the seventh electrode 32.
  • the second electrode 16 and the fourth electrode 27 are in direct contact with each other so as not to be contacted between separate electrodes such as the sixth electrode 31 or the seventh electrode 32 described above, and thus have an electrical connection structure. Can be formed.
  • the first wafer 10 or the second wafer 20 may be a silicon-based wafer or a ceramic-based wafer having good insulation, robustness, and thermal conductivity.
  • the electrodes or bonding pads may be formed of a metal or an alloy including a metal or magnetic material having good electrical conductivity.
  • Microcontrol unit not the sensor circuits (18, 29, 40), wireless data communication circuits for wirelessly transmitting sensing data by the sensor circuits, a battery for supplying power to the various circuits, necessary for the battery It may be a wireless charging circuit for charging the power, or a memory for storing the sensing data by the sensor circuit and log data for sensing or data transmission. Therefore, the electrical connection between the circuits may be variously changed by the bridge role of the bridge electrode 25.
  • the sensor-mounted wafer does not require a lead wire for connecting the sensor circuit to the electrode and is not required for the bonding process for coupling the sensor circuit to the electrode. Only through welding welding the sensor circuit to the electrode, physical fixation and electrical connection of the sensor circuit is realized simultaneously. In addition, since the durable space can be maintained in a vacuum state by bonding two wafers in a vacuum atmosphere, a sealing process for filling the internal space between the two wafers is not required.
  • the first wafer 10 may be bonded to the lower portion of the second wafer 20 so that the first wafer 10 may be used for low temperature, and the second wafer 20 may be used for high temperature.
  • This may be realized by the second wafer 20 having a relatively larger thickness than the first wafer 10, but may be determined according to the arrangement structure in which the sensor-mounted wafer of the present invention is mounted in a chamber for semiconductor process monitoring. have.
  • the first wafer 10 is placed at the bottom and the second wafer 20 is disposed at the top. It is preferable. Accordingly, since the second wafer 20 can withstand high temperatures, the second wafer 20 is exposed to the plasma, and the first wafer 10 is loaded to face the chuck provided in the chamber so that monitoring (measurement) can be performed at a lower temperature. have. By changing the vertical arrangement of the first wafer 10 and the second wafer 20 upside down and loading them into the chamber can be used in general for process monitoring at various temperature conditions.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Pressure Sensors (AREA)

Abstract

La présente invention concerne une tranche montée sur capteur ayant une forme dans laquelle des tranches sont liées de façon à supporter des processus effectués dans différentes conditions de température tandis que des circuits de capteur pour surveiller un processus de semi-conducteurs sont montés à l'intérieur de celles-ci, et comprend : une première tranche de partie inférieure ayant au moins un évidement; et une seconde tranche de partie supérieure ayant au moins un évidement et liée à la première tranche, la première tranche comprenant : un premier évidement; un premier film isolant formé sur l'intérieur du premier évidement et la surface supérieure de la première tranche; une première électrode formée, d'un côté de la surface supérieure de la première tranche, sur le premier film isolant sur une paroi interne latérale du premier évidement et un côté de la surface inférieure de celui-ci; une seconde électrode espacée de la première électrode sur la surface inférieure du premier évidement et formée, de l'autre côté de la surface supérieure de la première tranche, sur le premier film isolant sur l'autre paroi interne latérale du premier évidement et l'autre côté de la surface inférieure de celui-ci; et un premier circuit de capteur établissant un contact électrique avec la première électrode et la seconde électrode sur la surface inférieure du premier évidement.
PCT/KR2018/004753 2017-04-28 2018-04-24 Tranche montée sur un capteur Ceased WO2018199601A1 (fr)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
KR10-2017-0055160 2017-04-28
KR1020170055160A KR101807492B1 (ko) 2017-04-28 2017-04-28 센서 탑재 웨이퍼
KR10-2017-0057403 2017-05-08
KR1020170057403A KR101807495B1 (ko) 2017-05-08 2017-05-08 듀얼타입 센서 탑재 웨이퍼

Publications (1)

Publication Number Publication Date
WO2018199601A1 true WO2018199601A1 (fr) 2018-11-01

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PCT/KR2018/004753 Ceased WO2018199601A1 (fr) 2017-04-28 2018-04-24 Tranche montée sur un capteur

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TW (1) TWI679712B (fr)
WO (1) WO2018199601A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113506760A (zh) * 2021-06-18 2021-10-15 电子科技大学 一种双层结构的晶圆温度场重建装置

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Publication number Priority date Publication date Assignee Title
US20010012639A1 (en) * 1998-02-27 2001-08-09 Salman Akram Methods of semiconductor Processing
KR20020009365A (ko) * 2000-07-24 2002-02-01 석창길 기판온도측정 장치 및 제작 방법
JP2007178253A (ja) * 2005-12-28 2007-07-12 Tokyo Electron Ltd 温度測定装置および温度測定方法
US20070251339A1 (en) * 2006-05-01 2007-11-01 Sensarray Corporation Process Condition Measuring Device with Shielding
KR20140133775A (ko) * 2013-05-09 2014-11-20 (주)유우일렉트로닉스 웨이퍼레벨 패키징 소자

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TWI313078B (en) * 2005-03-17 2009-08-01 Yamaha Corporatio Magnetic sensor and manufacturing method therefor
TW200737506A (en) * 2006-03-07 2007-10-01 Sanyo Electric Co Semiconductor device and manufacturing method of the same
WO2011045836A1 (fr) * 2009-10-14 2011-04-21 国立大学法人東北大学 Dispositif de capteur et procédé pour fabriquer le dispositif de capteur

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20010012639A1 (en) * 1998-02-27 2001-08-09 Salman Akram Methods of semiconductor Processing
KR20020009365A (ko) * 2000-07-24 2002-02-01 석창길 기판온도측정 장치 및 제작 방법
JP2007178253A (ja) * 2005-12-28 2007-07-12 Tokyo Electron Ltd 温度測定装置および温度測定方法
US20070251339A1 (en) * 2006-05-01 2007-11-01 Sensarray Corporation Process Condition Measuring Device with Shielding
KR20140133775A (ko) * 2013-05-09 2014-11-20 (주)유우일렉트로닉스 웨이퍼레벨 패키징 소자

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113506760A (zh) * 2021-06-18 2021-10-15 电子科技大学 一种双层结构的晶圆温度场重建装置
CN113506760B (zh) * 2021-06-18 2023-05-09 电子科技大学 一种双层结构的晶圆温度场重建装置

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TW201907503A (zh) 2019-02-16
TWI679712B (zh) 2019-12-11

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