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WO2018194367A1 - Procédé de fabrication de carte de circuit imprimé - Google Patents

Procédé de fabrication de carte de circuit imprimé Download PDF

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Publication number
WO2018194367A1
WO2018194367A1 PCT/KR2018/004492 KR2018004492W WO2018194367A1 WO 2018194367 A1 WO2018194367 A1 WO 2018194367A1 KR 2018004492 W KR2018004492 W KR 2018004492W WO 2018194367 A1 WO2018194367 A1 WO 2018194367A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
peeling
release layer
circuit pattern
base substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/KR2018/004492
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English (en)
Korean (ko)
Inventor
정광춘
문병웅
김수한
하성인
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
InkTec Co Ltd
Original Assignee
InkTec Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by InkTec Co Ltd filed Critical InkTec Co Ltd
Publication of WO2018194367A1 publication Critical patent/WO2018194367A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/022—Processes for manufacturing precursors of printed circuits, i.e. copper-clad substrates
    • H05K3/025—Processes for manufacturing precursors of printed circuits, i.e. copper-clad substrates by transfer of thin metal foil formed on a temporary carrier, e.g. peel-apart copper
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/02—Details related to mechanical or acoustic processing, e.g. drilling, punching, cutting, using ultrasound
    • H05K2203/0264—Peeling insulating layer, e.g. foil, or separating mask

Definitions

  • the present invention relates to a method for manufacturing a printed circuit board, and more particularly, to a method for manufacturing a printed circuit board which can prevent damage to a circuit pattern in a process of removing a release layer.
  • the copper foil circuit is embedded in the insulating layer rather than being formed by protruding the surface of the insulating layer, it is possible to reduce the width and pitch of the copper foil, to implement a fine circuit pattern embedded trace substrate (hereinafter referred to as an embedded trace substrate)
  • an embedded trace substrate The technique is called 'ETS'.
  • Figure 1 is a view showing a printed circuit board manufacturing method using a conventional ETS method.
  • Figure 1 (a) shows a detachable core (detachable core), the detachable core 100 is a core 100a acting as a support, a carrier copper foil (100b) bonded on the core (100a), carrier It includes a base copper foil (100c) bonded on the copper foil (100b), the base copper foil (100c) is temporarily bonded to the carrier copper foil (100b) by an adhesive, applying a slight physical force to the carrier copper foil (100b) Can be separated from.
  • the core 100a and the carrier copper foil 100b may use copper clad laminate (CCL).
  • a buildup layer formed of the circuit patterns 110 and 150 and the insulating layers 130 and 160 is formed on the base copper foil 100c of the detachable core 100, thereby forming the circuit patterns 110 and 150.
  • Printed circuit boards embedded in the insulating layers 130 and 160 are manufactured on both sides of the build-up layer, respectively.
  • the detachable core 100 is required to easily peel off the base copper foil 100c from the carrier copper foil 100b, a process of applying an adhesive, a process of laminating a carrier copper foil on the adhesive, and a laminating process are required.
  • the unit price will rise.
  • the base copper foil (100c) attached to the build-up layer is made of the same copper material as the circuit pattern 110, the circuit pattern 110 in the process of removing the base copper foil (100c) by a chemical method such as etching There is a problem of exposure to the etchant.
  • the pad of the semiconductor chip is manufactured by applying the ETS method according to the prior art, the pad is recessed inwardly based on the surface of the insulating layer, which is a semiconductor die and a Bump on Lead during the electronic component packaging process ) Will cause a non-wet issue in the solder joint process, the yield of the manufacturing process is lowered.
  • an object of the present invention is to provide a method for manufacturing a printed circuit board which can prevent damage to a circuit pattern in the process of removing the exfoliation layer.
  • the object of the present invention is a peeling layer forming step of forming a peeling layer with a first conductive material on a base substrate; and a circuit pattern forming step of forming a circuit pattern with a second conductive material on the peeling layer; and A resin layer forming step of forming an insulating resin layer on the release layer on which the circuit pattern is formed; and a base substrate peeling step of peeling and removing the base substrate from the release layer; And a release layer removing step of removing the release layer.
  • the peeling strength for peeling the base substrate from the peeling layer is preferably set to 10 gf / cm to 100 gf / cm.
  • the release layer and the circuit pattern is preferably formed of a conductive material of different materials.
  • etching solution composition capable of dissolving only the release layer.
  • the release layer may be formed of silver (Ag), and the circuit pattern may be formed of copper (Cu).
  • the base substrate is preferably made of a copper clad laminated film (Copper Clad Laminate) in which copper foil is laminated on at least one surface of the resin layer.
  • a copper clad laminated film Copper Clad Laminate
  • the release layer forming step it is preferable to form a release layer by coating silver (Ag) on the copper foil of the copper foil laminated film.
  • a method of manufacturing a printed circuit board capable of preventing damage to a circuit pattern in a process of removing a release layer is provided.
  • FIG. 1 is a view showing a printed circuit board manufacturing method using a conventional ETS method.
  • FIG. 2 is a flowchart of a method of manufacturing a printed circuit board according to the first embodiment of the present invention.
  • FIG 3 is a cross-sectional view for each process step of the method of manufacturing a printed circuit board according to the first embodiment of the present invention.
  • FIG. 5 is a cross-sectional view showing a manufacturing process of a circuit board for testing the peel strength according to the present invention
  • Figure 6 is a test example showing the peel strength of the peeling layer produced by the present invention.
  • FIG. 7 is an enlarged photograph showing a cross section of a circuit pattern after a release layer removing step according to the present invention.
  • 10 base base material
  • 10a insulating layer
  • 10b copper foil
  • FIG. 2 is a flowchart of a method of manufacturing a printed circuit board according to the first embodiment of the present invention
  • FIG. 3 is a cross-sectional view of each method of the method of manufacturing a printed circuit board according to the first embodiment of the present invention.
  • the printed circuit board manufacturing method according to the first embodiment of the present invention as shown in the drawings is a peeling layer forming step (S10), a circuit pattern forming step (S20), a resin layer forming step (S30), the base It includes a substrate peeling step (S40) and the peeling layer removal step (S50).
  • a first conductive material made of silver (Ag) is coated on one surface of the base substrate 10 to form a release layer 20. do.
  • the release layer 20 may include gravure printing, screen printing, slot die coating, spincoating, dip coating, spray coating, or the like. It can be formed by.
  • the first conductive material is made of silver (Ag), but is described as an example.
  • the metals having excellent electrical conductivity such as iron, copper, aluminum, nickel, lead, zinc, tin, gold titanium, etc. It can be configured as either.
  • the circuit pattern is formed of a second conductive material of copper (Cu) material different from the first conductive material on the release layer 20. 30 is formed.
  • the circuit pattern 30 may be formed through various methods of subtractive process or additive process.
  • the second conductive material is composed of copper (Cu), but the present invention is not limited thereto.
  • the second conductive material may include silver, iron, aluminum, nickel, lead, zinc, tin, Among metals having excellent electrical conductivity, such as gold titanium, the second conductive material may not be dissolved in the process of dissolving the first conductive material.
  • the resin layer 40 is formed on the release layer 20 on which the circuit pattern 30 is formed. 40 may surround the circuit pattern 30 formed on the release layer 20.
  • the resin layer 40 may be a prepreg reinforced with a polymer such as epoxy, urethane, ester resin, or UV curable resin or fiber. (PREPREG; Preimpregnated Materials) and the like can be used.
  • the prepreg resin in an uncured state is applied onto the release layer 20 on which the circuit pattern 30 is formed, and is bonded by applying pressure, followed by curing by applying heat. It is possible to form the resin layer 40, it is also possible to make the curing at the same time through the hot pressing process providing heat and pressure.
  • the resin layer 40 when the printed circuit board is applied to a transparent display, it will be preferable to form the resin layer 40 using a resin having high transmittance after curing.
  • the circuit pattern 30 having a single layer structure has been described.
  • the circuit pattern forming step (S20) and the resin layer forming step (S30) may be repeated, if necessary. It will also be possible to form the circuit pattern 30 of the structure.
  • the base substrate 10 is peeled off and removed from the peeling layer 20.
  • the peel strength for peeling the base substrate 10 from the release layer 20 is preferably set to 10 gf / cm to 100 gf / cm.
  • the peel strength is excessively high because it must be easily peeled from the peeling layer 20 in the base substrate peeling step (S40), but the circuit pattern forming step (S20) or the resin layer is formed.
  • the degree not to be peeled off arbitrarily in step S30 should be maintained.
  • the peeling strength for peeling the base substrate 10 from the peeling layer 20 is less than 10 gf / cm, there is a fear that the base substrate 10 may be arbitrarily peeled off during conveyance or processing, and the peel strength is 100 gf. If it exceeds / cm, there is a fear that the base substrate 10 is not easily peeled off in the base substrate peeling step (S40).
  • the said peeling strength is measured based on the 90 degree peeling strength measuring method prescribed
  • the peeling layer 20 is removed through the peeling layer removing step S50.
  • the release layer removing step (S50) as shown in (e) of Figure 3 using an etching solution composition that can dissolve only the release layer 20 made of a first conductive material of silver (Ag) material
  • the release layer 20 is dissolved and removed.
  • the second conductive material made of copper (Cu) exposed to the etching solution composition is not dissolved in the process of dissolving the release layer 20, the circuit pattern 30 is damaged during the removal of the release layer 20. You can prevent it.
  • the recess depth of the circuit pattern 30 can be prevented. have.
  • the exposed surface of the circuit pattern 30 forms the same surface as the surface of the resin layer 40, a non-wet issue in which solder bonding is not performed in the process of bonding the semiconductor die and the BOL (Bump on Lead) is performed. Can be prevented.
  • FIG. 4 is a cross-sectional view for each process step of the method of manufacturing a printed circuit board according to the second embodiment of the present invention.
  • the copper clad laminated film in which the base substrate 10 is a copper foil (10b) laminated on both sides of the insulating layer (10a) Laminate
  • the release layer forming step (S10) the circuit pattern forming step (S20), the resin layer forming step (S30), the base substrate peeling step (S40) and the peeling layer removal step (S50)
  • the circuit boards are formed on both surfaces of the base substrate 10, for example.
  • the release layer forming step (S10) as shown in (a) of Figure 4, by coating a first conductive material of silver (Ag) material on the copper foil (10b) provided on both sides of the insulating layer (10a)
  • the release layer 20 is formed.
  • the release layer 20 may be formed by various coating methods as in the first embodiment.
  • the first conductive material may be made of any one of metals having excellent electrical conductivity, such as iron, copper, aluminum, nickel, lead, zinc, tin, and gold titanium.
  • the circuit pattern 30 is formed on the release layer 20 by using a second conductive material made of copper (Cu) material different from the first conductive material.
  • the second conductive material is composed of copper (Cu), but the present invention is not limited thereto.
  • the second conductive material may be silver, iron, aluminum, nickel, lead, zinc, tin, or the like. It may be made of a material different from the first conductive material among metals having excellent electrical conductivity, such as gold and titanium.
  • the circuit pattern 30 may be formed through various subtractive processes or additive processes.
  • the circuit pattern forming step S20 may include forming a photosensitive layer forming step S21, an exposure and developing step S22, and a plating step in order to form the circuit pattern 30 by a semi additive process (SAP) method. (S23) and the photosensitive layer removing step (S24).
  • SAP semi additive process
  • S23 the photosensitive layer removing step
  • S21 as shown in FIG. 4B, a photosensitive material is coated on the release layer 20 to form a photosensitive layer 31, and the exposure and development steps (S22).
  • the pattern groove 32 in which the release layer 20 is selectively exposed is formed in the photosensitive layer 31.
  • the release layer 20 is selectively exposed through the pattern groove 32 of the photosensitive layer 31 in accordance with the pattern to form a circuit.
  • the second conductive material is plated in the pattern groove 32 to form the circuit pattern 30.
  • the second conductive material is preferably provided with copper having a very high electrical conductivity.
  • the second conductive material may be filled in the pattern groove 32 because the release layer 20 exposed through the pattern groove 32 in the plating process serves as an electrode.
  • the photosensitive layer removing step S24 as shown in FIG. 4E, the circuit pattern 30 is removed by removing the photosensitive layer 31 except for the second conductive material filled in the pattern groove 32. Can be formed.
  • the resin layer 40 is formed on the release layer 20 on which the circuit pattern 30 is formed. 40 may surround the circuit pattern 30 formed on the release layer 20.
  • a resin, an epoxy resin, or a fiber reinforced prepreg PREPREG
  • the prepreg resin in an uncured state is coated on the release layer 20 on which the circuit pattern 30 is formed, and is bonded by applying pressure, followed by curing by applying heat. It is possible to form the resin layer 40, it is also possible to make the curing at the same time through the hot pressing process providing heat and pressure.
  • the circuit pattern 30 having a single layer structure has been described.
  • the circuit pattern forming step (S20) and the resin layer forming step (S30) may be repeated, if necessary. It will also be possible to form the circuit pattern 30 of the structure.
  • the base substrate 10 is peeled off and removed from the peeling layer 20.
  • the peel strength for peeling the base substrate 10 from the release layer 20 is preferably set to 10 gf / cm to 100 gf / cm.
  • the base substrate peeling step (S40) is to separate the base substrate 10 from the release layer 20, the peel strength for peeling the base substrate 10 from the release layer 20 is a base It should be set to such an extent that the substrate 10 can be easily peeled off by a human hand.
  • the peel strength is excessively high because it must be easily peeled from the peeling layer 20 in the base substrate peeling step (S40), but the circuit pattern forming step (S20) or the resin layer is formed.
  • the degree not to be peeled off arbitrarily in step S30 should be maintained.
  • the peeling strength for peeling the base substrate 10 from the peeling layer 20 is less than 10 gf / cm, there is a fear that the base substrate 10 may be arbitrarily peeled off during conveyance or processing, and the peel strength is 100 gf. If it exceeds / cm, there is a fear that the base substrate 10 is not easily peeled off in the base substrate peeling step (S40).
  • the said peeling strength is measured based on the 90 degree peeling strength measuring method prescribed
  • the etching solution composition that can dissolve only the release layer 20 made of a first conductive material of silver (Ag) material It is used to dissolve and remove the release layer 20.
  • the second conductive material made of copper (Cu) exposed to the etching solution composition is not dissolved in the process of dissolving the release layer 20, the circuit pattern 30 is damaged during the removal of the release layer 20. You can prevent it.
  • the recess depth of the circuit pattern 30 can be prevented. have.
  • the exposed surface of the circuit pattern 30 forms the same surface as the surface of the resin layer 40, a non-wet issue that is not soldered during the process of bonding the semiconductor die and the BOL (Bump on Lead) is eliminated. It can be prevented.
  • test example will be described in more detail with respect to the peel strength of the peeling layer and the base substrate according to the present embodiment as described above.
  • the silver (Ag) release layer 20 is coated.
  • the copper circuit pattern 30 layer is plated on the silver (Ag) release layer 20 to have a thickness of 15 ⁇ m as shown in FIG.
  • the resin layer 40 is formed by stacking prepregs on the circuit pattern 30 layer and providing pressure and heat as shown in FIG.
  • the release layer 20 formed on the copper foil 10b of the base substrate 10 is a circuit pattern 30. Transition to the layer side.
  • a copper (Cu) specimen layer 50 is formed on the exposed surface of the release layer 20 to have a thickness of 20 ⁇ m as shown in FIG.
  • a copper (Cu) thin film 10b is formed on one surface of the insulating layer 10a and has a thickness of 0.3 ⁇ m on the copper foil 10b of the base substrate 10 having a thickness of 18 ⁇ m.
  • the silver (Ag) release layer 20 is coated by the thickness.
  • the photosensitive layer 31 is apply
  • the pattern groove 32 is formed on the photosensitive layer 31 through an exposure and development process as shown in FIG.
  • the circuit pattern 30 is formed by filling copper in the pattern groove 32 to a thickness of 13 ⁇ m through the plating process as shown in FIG. 4 (d).
  • Prepreg is laminated on the release layer 20 on which the circuit pattern 30 is formed as shown in FIG. 4 (f), and the resin layer 40 is formed by providing pressure and heat.
  • the release layer 20 formed on the copper foil 10b of the base substrate 10 is a circuit pattern 30. Transition to the layer side.
  • an etching solution composition containing an ammonium compound and an oxidizing agent described in the patent applicant 10-0712879 of the applicant may be used; Oxidizing agents such as oxidizing gases or peroxides or peroxyacids, aliphatic amines or aromatic amines or alkanol amines or ammonium compounds, chelating agents, antifoaming agents, wetting agents, pH adjusting agents and one other selected to improve the etching performance of the etching solution
  • Oxidizing agents such as oxidizing gases or peroxides or peroxyacids, aliphatic amines or aromatic amines or alkanol amines or ammonium compounds, chelating agents, antifoaming agents, wetting agents, pH adjusting agents and one other selected to improve the etching performance of the etching solution
  • the selective etching liquid composition containing the above additive and water can also be used. Each configuration of the selective etching solution will be described in detail below.
  • An oxidizing agent included in the etchant composition serves to oxidize the silver material on the surface of the release layer.
  • the prior art discloses an etchant composition using nitric acid, hydrochloric acid, sulfuric acid, phosphoric acid, iron nitrate, iron chloride, iron sulfate, iron phosphate, and the like.
  • these etchant compositions are not suitable as an etchant of a circuit for selectively etching silver only as a material for oxidizing and dissociating metals such as copper, nickel, and chromium.
  • the oxidizing agent is an oxidizing gas such as air, oxygen, ozone, sodium perborate, hydrogen peroxide, sodium bismuthate, sodium percarbonate, benzoyl peroxide, Peroxides such as Potassium peroxide, Sodium peroxide, Formic acid, Peroxyacetic acid, Perbenzoic acid, 3-Chloroperoxybenzoic acid ) And peroxy acid and potassium persulfate, such as trimethylacetic acid, and the like, it is preferable to use a mixture of at least one oxidizing agent.
  • an oxidizing gas such as air, oxygen, ozone, sodium perborate, hydrogen peroxide, sodium bismuthate, sodium percarbonate, benzoyl peroxide, Peroxides such as Potassium peroxide, Sodium peroxide, Formic acid, Peroxyacetic acid, Perbenzoic acid, 3-Chloroperoxybenzoic acid )
  • peroxy acid and potassium persulfate such as trimethylacetic acid, and the
  • the oxidizing agent is preferably contained in 1 to 30% by weight, more preferably 5 to 18% by weight based on the total weight of the etching liquid composition of the silver or silver alloy or silver compound.
  • the oxidizing agent is less than 1% by weight, the etching rate is slow and a perfect etching is not performed, so that a large amount of silver residue may occur.
  • Silver residues, if present between circuits, cause short circuits, resulting in product defects, and slow etch rates affect productivity. If it exceeds 30% by weight, the etching rate of the exposed release layer is high, but excessive undercut phenomenon occurs due to the exfoliation layer existing under the circuit layer. Since the undercut phenomenon is a factor affecting the adhesion of the circuit layer, it is preferable to suppress the occurrence.
  • Aliphatic amines or aromatic amines or alkanol amines or ammonium compounds included in the etching solution composition of the silver or silver alloy or silver compound dissociate the oxidized silver in the release layer. Do it. It is possible to selectively etch only silver or silver alloys or silver compounds through oxidation with oxidants and dissociation with aliphatic or aromatic amines. As described above, nitric acid, hydrochloric acid, sulfuric acid, phosphoric acid, iron nitrate, iron hydrochloride, iron sulfate, iron phosphate, and the like, which are included in the conventional etching solution composition, react with copper as a main etchant, and oxidation and dissociation occur simultaneously.
  • each of the two materials is responsible for the oxidation and dissociation reaction, and the dissociation reaction of the oxidized silver and the aliphatic or aromatic amine or alkanol amine or ammonium compound proceeds more violently than copper dissociation Only the release layer formed of the alloy or silver compound is selectively etched.
  • the aliphatic or aromatic amine or alkanol amine or ammonium compound is ethylamine, propylamine, isopropylamine, isopropylamine, n-butylamine, isobutylamine, sec-Butylamine, Diethylamine, Piperidine, Tyramine, N-Methyltyramine, Pyrroline, Pyrrolidine ), Imidazole, Indole, Pyrimidine, Ethanolamine, 6-Amino-2-methyl-2-heptanol , 1-amino-2-propanol (1-Amino-2-propanol), methanol amine (Methanolamine), dimethylethanolamine, N-methylethanolamine, 1-aminoethanol (1-Aminoethanol ), 2-amino-2-methyl-1-propanol, ammonium carbonate, ammonium phosphate, ammonium nitrate amines or ammonium compounds such as trate), ammonium fluoride, ammonium hydrox
  • the aliphatic or aromatic amine or alkanol amine or ammonium compound may be included in an amount of 1 to 75% by weight, more preferably 20 to 70% by weight, based on the total weight of the silver material release layer etchant composition.
  • the aliphatic or aromatic amine or alkanol amine or ammonium compound is less than 1% by weight, the dissociation reaction of oxidized silver does not occur well, so that the silver release layer etching rate is lowered. If it exceeds 75% by weight, there is no problem in the selective etching of the release layer, but the use of excessive amines or ammonium compounds may cause the oxidant to inhibit the oxidation of the silver or the silver alloy or the silver compound in the etching solution. Decrease. Therefore, it is preferable to use only the extent that the surface layer oxidation reaction of the release layer occurs and the oxidized silver is dissolved to facilitate selective etching.
  • the chelating agent, antifoaming agent, wetting agent, pH adjusting agent, and other one or more additives selected to improve the etching performance of the etching solution included in the etching solution composition of the silver or silver alloy or the silver compound of the present invention may be formed of bubbles that may occur during oxidation. Removal, the etchant serves to give the wettability that can be adsorbed well on the surface of the release layer, and in addition, it is possible to select and use a commonly used additive that can increase the effect of the present invention.
  • the additive may be included in an amount of 0.1 to 10% by weight, more preferably 1 to 7% by weight, depending on the type and role of the additive, based on the total weight of the silver material release layer etching solution composition.
  • the additives may not play a role of improving the selective etching properties, which is an effect of the present invention.
  • the etching solution may crosslink (or gelate) to significantly reduce the etching properties.
  • the etchant composition of the silver or silver alloy or silver compound of the present invention comprises the above materials and contains a residual amount of water in a total of 100% by weight. It is preferable to use deionized water for water.
  • Selective etching solution composition 2 was prepared by mixing 7% by weight of sodium percarbonate, 32.5% by weight of N-Methyldiethnaolamine, 0.5% by weight of wetting agent, 1% by weight of antifoaming agent, and 59% by weight of deionized water. It was.
  • Selective etching solution composition 3 was prepared by mixing 4 wt% sodium percarbonate, 60 wt% N-Methyldiethnaolamine, 1.5 wt% wetting agent, 0.5 wt% antifoaming agent, and 34 wt% deionized water.
  • Example 1 For comparison with the selective etchant compositions 1 to 3 prepared in Example 1, with reference to Example 1 described in Korean Patent Publication No. 10-2016-0115189, 10% by weight of ferric nitrate, 5% by weight nitric acid Comparative Example 1 was prepared by mixing 5 wt% acetic acid, 1 wt% EDTA, 1 wt% glycolic acid, and 78 wt% deionized water.
  • Example 2 For comparison with the selective etchant compositions 1 to 3 prepared in Example 1, with reference to Example 1 described in Korean Patent Publication No. 10-2010-0098409, 7% by weight of ammonia, 1.5% by weight of hydrogen peroxide and deionized water Comparative Example 2 was prepared by mixing 91.5 wt%.
  • the etching experiment was performed on the prepared selective etching solution composition and the comparative example prepared in Example 2 (FIG. 8).
  • the selective etching solution compositions 1 to 3 were etched with the etching time of 10 seconds to reveal the surface of the polyimide substrate material, and the Cu FCCL surface did not have any special discoloration or specificity, so that surface oxidation by the etching solution did not proceed. .
  • Comparative Examples 1 and 2 when etching was performed for the same time, silver was not etched 100%, and a residue was present, and the Cu FCCL surface was oxidized and discolored. In Comparative Example 3, silver was etched 100% during etching for the same time, but Cu FCCL also confirmed that the surface oxidation proceeded rapidly due to the fast etching rate.
  • Comparative Examples 1 and 2 When the silver and copper components present in the etching solution were detected and compared by ICP analysis, in Comparative Examples 1 and 2 in which silver was not 100% etched, silver of 170 ppm or less was detected, and Comparative Example 1 in which the Cu FCCL surface was oxidized and discolored progressed. In 3 to 3, it was confirmed that copper was detected. In particular, Comparative Examples 1 and 3, in which much silver was etched, could confirm that copper also had a high etching rate.
  • the metal circuit layer removal is suppressed to a minimum, and selectively etches only silver or silver alloy or silver compound, thereby providing an etching liquid composition having no damage to the copper circuit layer and having a high corrosion factor. can do. Therefore, by using this it is possible to design high-performance, high-integrated circuits and to manufacture products requiring light and small short.

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing Of Printed Circuit Boards (AREA)
  • Non-Metallic Protective Coatings For Printed Circuits (AREA)
  • Manufacturing Of Printed Wiring (AREA)

Abstract

La présente invention concerne un procédé de fabrication d'une carte de circuit imprimé. Le procédé de fabrication d'une carte de circuit imprimé, selon la présente invention, comprend : une étape de formation de couche de bande de formation, sur un substrat de base, d'une couche de bande avec un premier matériau conducteur ; une étape de formation de motif de circuit de formation, sur la couche de bande, d'un motif de circuit avec un deuxième matériau conducteur ; une étape de formation de couche de résine de formation d'une couche de résine isolante sur la couche de bande sur laquelle le motif de circuit est formé ; une étape de décapage de substrat de base consistant à décaper et retirer le substrat de base de la couche de bande ; et une étape de retrait de couche de bande consistant à retirer la couche de bande.
PCT/KR2018/004492 2017-04-18 2018-04-18 Procédé de fabrication de carte de circuit imprimé Ceased WO2018194367A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR10-2017-0050041 2017-04-18
KR20170050041 2017-04-18

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WO2018194367A1 true WO2018194367A1 (fr) 2018-10-25

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KR (1) KR102414959B1 (fr)
TW (1) TWI768029B (fr)
WO (1) WO2018194367A1 (fr)

Cited By (1)

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