WO2018192681A1

WO2018192681A1 - Method for manufacturing an organic photo detector arrangement

Info

Publication number: WO2018192681A1
Application number: PCT/EP2018/000213
Authority: WO
Inventors: Stefan Ruckmich
Original assignee: PLASTIC LOGIC GmbH
Current assignee: PLASTIC LOGIC GmbH
Priority date: 2017-04-20
Filing date: 2018-04-20
Publication date: 2018-10-25
Anticipated expiration: 2019-10-20

Abstract

A method for manufacturing of an organic photo detector arrangement (OPDA) comprising an organic photo detector (OPD) arranged on a backplane has the objective to produce an OPDA with a cost-effective procedure. This is solved by using a backplane as known from an electrophoretic display EPD comprising a first metal layer (9), a dielectric stack (11) a via (12) with a metal ring (13) at the bottom of the via and laser debris (14) on the upper side of the dielectric stack and a first top-pixel metallization layer (15); filling the via of the backplane with material covering the metal ring and the laser debris; creating a surface with no irregular topography in a region of a top pixel contact; making the surface conductive; and electrical connecting the conductive surface to the first metal layer.

Description

Method for manufacturing an organic photo detector

arrangement

The invention relates to a method for manufacturing an organic photo detector arrangement (OPDA) comprising an organic photo detector (OPD) arranged on a backplane driving the OPD.

The backplane consists of an array of pixels forming an active matrix. Each pixel is composed by a storage capacitor and at least one field-effect transistor FET, which can be formed indistinctly by organic or inorganic semiconductor and dielectric materials. The FET-based active-matrix backplane can be processed on a flexible substrate.

PRIOR ART

As shown in Fig. 1 the OPD 1 is comprising an electron injection layer (EIL) 2, an organic semiconductor (OSC) 3 and a hole injection layer (HIL) 4. The OPD 1 is exposed to electromagnetic radiation 5, which can be of visible, infrared or x-ray nature. In case of x-ray radiation a scintillator 6 can convert the radiation 5 into photon radiation. If the radiation already comprises a photon radiation like visible or infrared light the scintillator 6 may be omitted. The photons impact on the OPD 1 and generate an electric charge by the photoelectric effect within the OPD 1. The electric charge is stored in the pixel capacitor and is measured by means of the FET. At least the OSC 3 layer of the OPD 1 is deposited on top of the backplane 7 preferably by solution processing (i.e., deposition steps from the liquid phase) on top of a flexible backplane 7. This completes the OPDA. A backplane 7 is also used in an electrophoretic display (EPD) 8 as shown in Fig. 2.

Fig. 3 shows particular steps for establishing an electrical contact between the top-pixel and drain electrodes of each single pixel of such a backplane 7. As shown in Fig. 3 a) a first metal layer 9 is arranged on a substrate 10. The first metal layer 9 serves as a connection to the drain electrode of the field effect transistor (not shown) which is arranged within a pixel of the EPD 8. In a further step a dielectric stack 11 is deposited onto the first metal layer 9.

Fig. 3 b) depicts the opening of a via 12 into the

dielectric stack 11. To enable a cost-effective

manufacturing of the backplane 7, the via 12 is made e.g. by a laser ablation. The laser beam deepens the via 12 down to the surface of the substrate 10. Thereby a metal ring 13 of melted metal of the first metal layer 9 is generated at the bottom edge between the via 12 and the substrate 10.

Furthermore some laser debris 14 can be back scattered during the laser ablation process onto the upper surface (i.e., via upper edge) of the dielectric stack 11.

In a further step as shown in Fig. 3 c) a first top-pixel metal layer 15 is deposited onto the whole upper surface of the arrangement of Fig. 3 b) . The first top-pixel metal layer 15 is structured within a region 16 surrounding the via 12 by removing the material of the first top-pixel metal layer 15 in a stripe 17 (top-pixel isolation) bordering the region 16 to generate a top pixel electrode 18 as shown in Fig. 3 d) . The top-pixel is the top electrode of a pixel capacitor, whose charge is controlled by FE . Both the pixel capacitor and the FET are the main electric components of a single pixel in the backplane 7.

As shown in Fig. 2 an EPD 8 is completed by laminating an electrophoretic frontplane onto the upper surface of the arrangement of Fig. 1 d) by means of an optical clear adhesive (OCA) 23. In this arrangement the backplane 7 is used to drive the electrophoretic frontplane 19 to form a flexible electrophoretic display (EPD) 8. For this

particular EPD application the presence of via topography, metal ring 13 and laser debris 14 embedded in the OCA 23 do not affect the device performance.

The metal ring 13 and the laser debris 14 could be avoided by using a reactive ion etching or the like instead of laser ablation to form the vias, which is selective to the first metal layer 9 but the topography of the vias will still remain .

To produce an OPDA the invention uses the backplane 7 as known from an EPD 8 for manufacturing an OPDA. Both the capacitor and the FET are arranged in each pixel of the backplane, as described above.

If the backplane would be used for applying an OPD instead of the electrophoretic frontplane 19, the laser debris 14, the topography of the via 12 and the metal ring 13 would cause problems. During the OPD processing, if at least the OSC layer 3 is deposited from a solution, it can flow around these

positions, leaving the upper metallic surface of the metal ring 13 and laser debris 14 uncoated, as explained

graphically in Fig. 4 showing uncovered areas 22. The conseguence is electrical short circuits between the EIL and HIL of the OPD, as described below.

As shown in Fig. 5, during the OPD processing, a thin EIL layer 2 deposited (e.g., by physical deposition, sputtering or by a similar method) on top of the backplane covering the whole surface of the backplane. After this process step, all "topography"-relevant features like via 12, the metal ring 13 and the laser debris 14 are covered by the EIL layer 2. As explained in Fig. 4, the deposition the OSC layer 3 by deposition process from a solution (i.e., by printing, spin coating, slot-die coating or similar) cannot fully cover the topography so that uncovered areas 22 remain where the EIL metal layer 2 would be exposed, like EIL islands surrounded by OSC material 3. At these points, electrical shorts would be generated between the EIL 2 and the HIL layer 4 as shown schematically in Fig. 5. For proper device performance, the OSC layer 3 must physically separate the EIL layer 2 and the HIL layer 4, but first results indicate that electrical shorts between the EIL layer 2 and the HIL layer 4 are caused by the irregular topography.

Furthermore, the thickness of deposed layers would differ in the region of the walls and the bottom of the via 12, as shown in Fig. 5. DESCRIPTION OF THE INVENTION

To avoid direct electrical shorts between the EIL layer 2 and the HIL layer 4 an organic photo diode (OPD) can be processed on top of the backplane produced by the applicant of this patent application without detrimental of

performance .

To avoid these shorting points the via 12 is filled with material thereby covering the topography created by the via itself, the metal ring 13 and the laser debris 14. Thereby a surface with no irregular topography is created in the region 16 of the top pixel electrode 18 which is conductive and electrical connected to the first metal layer 9.

EMBODIMENT OF THE INVENTION

In one embodiment of the invention as shown in Fig. 6 a via plug 24 made of an electrically isolating material covering the topography of laser debris 14 and the metal ring 13 at the via bottom is deposited after the deposition of the first top-pixel metallization layer 15. After a second top pixel metallization 25 and the top pixel isolation 17 step, a surface with no irregular topography can be obtained. The via plug 24 itself is fully encapsulated by the first and the second top pixel metallisation 15 and 24.

As it is shown in Fig. 7 and Fig. 8 the wet deposition of the OSC layer 3 (i.e., by printing, spin coating, slot-die coating or similar) over the EIL layer 2 can now be done without exposing contact points between EIL layer 2 and the HIL layer 4 .

A second embodiment of this invention is that since the full region of the top-pixel electrode 16 is metallized by the second top-pixel metallization 25, the so called "fill factor" (i.e., the effective contact area for charge transfer between the backplane's top-pixel electrode and OPD) is maximized on each single backplane pixel, thus improving device performance.

Reference Numbers

1 organic photo detector (OPD)

2 electron injection layer (EIL)

3 organic semiconductor (OSC)

4 hole injection layer (HIL)

5 radiation

6 scintillator

7 flexible backplane

8 electrophoretic display (EPD)

9 first metal layer (source/drain metallization) 10 substrate

11 dielectric stack

12 via

13 metal ring

14 laser debris

15 first top-pixel metallization layer

16 region (around laser via)

17 stripe (top pixel isolation)

18 top pixel electrode

19 electrophoretic frontplane

20 particle

21 thin material layer deposited from the liquid phase

22 uncovered area

23 optical clear adhesive (OCA)

24 via plug

25 second top pixel metallization layer

Claims

Method for manufacturing of an organic photo detector arrangement (OPDA) comprising an organic photo detector (OPD) arranged on a backplane driving the OPD

comprising the steps

- using a backplane (7) as known from an EPD (8)

comprising a first metal layer (9), a dielectric stack (11) a via (12) with a metal ring (13) at the bottom of the via (12) and laser debris (14) on the upper side of the dielectric stack (11) and a first top-pixel metallization layer (15);

- filling the via (12) of the backplane (7) with

material covering the metal ring (13) and the laser debris ( 14 ) ;

- creating a surface with no irregular topography in a region (16) of a top pixel contact (18);

- making the surface conductive; and

- electrical connecting the conductive surface to the first metal layer (9) .

The method of claim 1 further comprising the steps

- manufacturing a via plug (23) made of an electrically isolating material covering the topography created by the via (12) itself, the metal ring (13) and the laser debris (14) after depositing the first top- pixel metallization layer (15) (the first top pixel metallisation) ;

- forming the surface with no irregular topography

after depositing a second top pixel metallisation (25) and a top pixel isolation (17) step whereby the via plug (24) itself is fully encapsulated by the first (15) and the second top pixel metallisation (24) .