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WO2018182733A1 - Résistance entre des grilles sur une architecture de bord de grille auto-alignée - Google Patents

Résistance entre des grilles sur une architecture de bord de grille auto-alignée Download PDF

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Publication number
WO2018182733A1
WO2018182733A1 PCT/US2017/025582 US2017025582W WO2018182733A1 WO 2018182733 A1 WO2018182733 A1 WO 2018182733A1 US 2017025582 W US2017025582 W US 2017025582W WO 2018182733 A1 WO2018182733 A1 WO 2018182733A1
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WIPO (PCT)
Prior art keywords
semiconductor
gate
forming
fins
resistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2017/025582
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English (en)
Inventor
Roman W. OLAC-VAW
Walid M. Hafez
Chia-Hong Jan
Nidhi NIDHI
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Intel Corp
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Intel Corp
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Priority to PCT/US2017/025582 priority Critical patent/WO2018182733A1/fr
Publication of WO2018182733A1 publication Critical patent/WO2018182733A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/811—Combinations of field-effect devices and one or more diodes, capacitors or resistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/40—Resistors
    • H10D1/47—Resistors having no potential barriers
    • H10D1/474—Resistors having no potential barriers comprising refractory metals, transition metals, noble metals, metal compounds or metal alloys, e.g. silicides
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/834—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET] comprising FinFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0135—Manufacturing their gate conductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0158—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including FinFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe

Definitions

  • shrinking transistor size allows for the incorporation of an increased number of memory or logic devices on a chip, leading to the fabrication of products with increased capacity.
  • the drive for ever-more capacity, however, is not without issue.
  • the necessity to optimize the performance of each device becomes increasingly significant.
  • Precision resistors are a fundamental component of integrated circuit structures, such as system-on-chip (SoC) technology.
  • SoC system-on-chip
  • such resistors enable high speed analog circuitry (e.g., CSI/SERDES) and scaled input/output (10) architecture due to characteristics such as low variation in resistivity and near-zero temperature coefficients.
  • the resistivity of the precision resistor does not change significantly over a range of operating temperatures of the device.
  • SoC system-on-chip
  • FIG. 1 illustrates a semiconductor structure including self-aligned gate edge isolation structures.
  • FIG. 2A illustrates a plan view of a semiconductor structure including a resistor between gates on a self-aligned gate edge isolation structure according to an embodiment of this disclosure.
  • FIG. 2B illustrates a cross-sectional view taken along the a-a' axis of the structure of FIG. 2A according to an embodiment of this disclosure.
  • FIG. 3 is a method for forming a semiconductor structure including a resistor between gates on self-aligned gate edge architecture according to an embodiment of this disclosure.
  • FIGS. 4 A to 4L illustrate structures that are formed when carrying out the method of FIG. 3, in accordance to an embodiment of this disclosure.
  • FIG. 5 illustrates a semiconductor structure including a resistor between gates on self- aligned gate edge architecture according to an embodiment of this disclosure.
  • FIG. 6 is a depiction of a computing system configured according to an embodiment of this disclosure.
  • a semiconductor structure includes a first semiconductor fin extending in a first direction, and a second semiconductor fin adjacent to the first semiconductor fin and extending in the first direction.
  • the semiconductor structure further includes a first gate structure proximal to a first end of the first semiconductor fin and over the first semiconductor fin in a second direction, the first gate structure orthogonal to the first direction, and a second gate structure proximal to a second end of the first semiconductor fin and over the first semiconductor fin in the second direction.
  • a first structure is centered between the first and second semiconductor fins, the first structure comprising isolation material.
  • a second structure is disposed on the first structure, the second structure extending at least between the first gate structure and the second gate structure and comprising resistive material, the second structure being electrically isolated from the first and second gate structures.
  • the resistor need not be placed in the metallization layer above the device layer as typically done, thereby avoiding the topography and scaling issues associated with such resistors.
  • the disclosed resistor structures and techniques may further provide various other advantages over standard resistor techniques, such as a larger area of resistive material, improved thermal conduction and heat dissipation, and reduced routing overhead to connect to active circuitry.
  • resistors are typically formed above the device layer in the lower back- end metallization layers, which are inherently planar.
  • the addition of a thin-film resistor at these locations introduces topography.
  • the relevant depth of focus associated with such topography creates patterning issues for the tightly spaced metallization lines.
  • Integrating resistors into a highly scaled self-aligned gate edge architecture avoids or otherwise lessens such scalability issues, while still allowing the resistor elements to be close to the device layer.
  • a self-aligned gate edge-based precision resistor structure enables a defect-free process with low variation in resistivity and good thermal conduction due to the proximity to the substrate, thereby allowing for better heat dissipation and further lowering the temperature coefficients of the precision resistors.
  • reduced routing overhead is needed to connect to active circuitry, due to the close proximity to active transistors.
  • FIG. 1 illustrates a cross- sectional view of a semiconductor structure 100 including self-aligned gate edge isolation structures 108, as taken through a fin cut perspective (perpendicular to the fins 104 and through the gate/channel region).
  • the semiconductor structure 100 includes a plurality of semiconductor fins 104 above a substrate 102.
  • the semiconductor substrate 102 may be implemented, for example, with a bulk silicon or a silicon-on-insulator substrate configuration. In some implementations, the semiconductor substrate 102 may be formed using crystalline silicon.
  • the semiconductor substrate 102 may be formed using alternate materials, which may or may not be combined with silicon, such as germanium, silicon germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, indium gallium arsenide (e.g., Ino .7 Gao .3 As), gallium arsenide, or gallium antimonide.
  • silicon such as germanium, silicon germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, indium gallium arsenide (e.g., Ino .7 Gao .3 As), gallium arsenide, or gallium antimonide.
  • any material that may serve as a foundation upon which a semiconductor device may be built or otherwise formed can be used in accordance with embodiments of the present disclosure.
  • the plurality of semiconductor fins 104 is continuous with and protrudes from the substrate 102, through an insulator layer 103.
  • Insulator layer 103 can be
  • a gate structure 106 is over a grouping of one or more of the plurality of semiconductor fins 104.
  • the gate structure 106 can include a gate dielectric layer (which may be high-k gate dielectric material) and a gate electrode (not shown).
  • the gate structure includes a silicon dioxide gate dielectric layer and a polysilicon or tungsten gate electrode.
  • the gate dielectric layer includes multiple components such as a lower layer of silicon dioxide on the channel region, and an upper layer of hafnium oxide on the silicon dioxide layer.
  • the gate electrode structure may include multiple components in some embodiments, such as work function metals and/or barrier materials surrounding a metal core or plug. Any number of gate stack configurations can be used, whether high-k or not, as will be appreciated. Other transistor features, such as
  • source/drain regions to either side of a given gate structure, channel region (area of fin underneath a gate structure), trench-based source/drain contacts, trench-based gate contact, interlayer dielectric or insulator fill, are not shown, but will be apparent.
  • a self-aligned gate edge isolation structure 108 laterally separates adjacent gate structures 106, the self-aligned gate edge isolation structure 108 centered between adjacent groupings of semiconductor fins 104. A portion of a second self-aligned gate edge isolation structure 108 is also shown in FIG. 1.
  • Self-aligned gate edge isolation structures 108 may be composed of a material or materials suitable to electrically isolate, or contribute to the isolation of, at least portions of neighboring permanent gate structures from one another.
  • Example materials or material combinations include a single material structure such as silicon dioxide, silicon oxy-nitride, silicon nitride, or carbon-doped silicon nitride.
  • example materials or material combinations include a multi-layer stack having a lower portion silicon dioxide, silicon oxy-nitride, silicon nitride, or carbon-doped silicon nitride and an upper portion higher dielectric constant material such as hafnium oxide.
  • high-k gate dielectric materials include, for instance, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.
  • Local conductive interconnects 1 10 may be formed above the gate electrodes 106 and, in some cases, over one or more of the self-aligned gate edge isolation structures 108.
  • local interconnects 1 10 may be formed using titanium nitride (TiN) or tungsten (W), although any number of suitable conductors can be used.
  • a dielectric capping layer 1 12 is formed over the local interconnects 1 10, as is depicted.
  • suitable dielectric materials include, but are not limited to, oxides of silicon (e.g., silicon dioxide (Si0 2 )), doped oxides of silicon, fluorinated oxides of silicon, carbon doped oxides of silicon, nitrides (e.g., silicon nitride (SiN)), low-k dielectric materials (e.g., polymers, porous Si0 2 ), and combinations thereof.
  • oxides of silicon e.g., silicon dioxide (Si0 2 )
  • doped oxides of silicon e.g., fluorinated oxides of silicon, carbon doped oxides of silicon, nitrides (e.g., silicon nitride (SiN)
  • low-k dielectric materials e.g., polymers, porous Si0 2
  • a semiconductor structure 200 includes self-aligned gate edge isolation structures 208.
  • the semiconductor structure 200 includes a plurality of semiconductor fins 204 continuous with and protruding from the substrate 202, through an insulator layer 203.
  • a first semiconductor fin 204a is shown extending in a first direction
  • a second semiconductor fin 204b is shown adjacent to the first semiconductor fin 204a and extending in the first direction.
  • a first gate structure 206a which may include a gate electrode and gate dielectric layer (not shown), is proximal to a first end of the first semiconductor fin 204a and over the first semiconductor fin 204a in a second direction, the first gate structure 206a orthogonal to the first direction.
  • a second gate structure 206b which may include a gate electrode and gate dielectric layer (not shown), is proximal to a second end of the first semiconductor fin 204a and over the first semiconductor fin 204a in the second direction.
  • third gate structure 206c which may include a gate electrode and gate dielectric layer (not shown), is proximal to a first end of the second semiconductor fin 204b and over the second semiconductor fin 204b in the second direction.
  • a fourth gate structure 206d which may include a gate electrode and gate dielectric layer (not shown), is proximal to a second end of the second semiconductor fin 204b and over the second
  • a first structure comprising a self-aligned gate edge structure 208a comprising isolation material laterally separates adjacent gate structures 206a and 206c (as well as adjacent gate structures 206b and 206d). Further note, in this example embodiment, that the self-aligned gate edge isolation structure 208a is generally centered between adjacent semiconductor fins 204a and 204b. A portion of a second self-aligned gate edge isolation structure 208b is also shown in FIG. 2A.
  • a second structure comprising a resistor 214 comprising resistive material is disposed on the self-aligned gate edge isolation structure 208a.
  • the resistor 214 extends at least between the first gate structure 206a and the second gate structure 206b. Further note that the resistor 214 is electrically isolated from the first and second gate structures 206a and 206b.
  • the resistor 214 may be composed of, for example, titanium nitride (TiN) or tungsten (W), or any other material suitable to provide a precision resistor having low variation in resistivity and a near-zero temperature coefficient, in that the resistivity of the resistor 214 does not change significantly over a range of operating temperatures of the resistor 214.
  • the resistor 214 may be formed as a thin film resistor.
  • the resistor 214 has an electrical resistivity in a range of between 1 ohm/sq and 1,000 ohms/sq, although any number of suitable resistivities per square can be configured, depending on the resistive material(s) used.
  • the dimensions of the resistor 214 can be set in conjunction with the resistivity/square rating to provide a desired resistance.
  • the resistor 214 has a lateral thickness (between the adjacent gate structures 206a and 206c) in a range of between 500 nm and 15 microns, and a height (between self-aligned gate edge isolation structure 208a and insulator layer 21 1 described further below) in a range of 10 nm to 1 micron, although the thickness and height can vary from one embodiment to the next as will be appreciated, depending on factors such as desired resistance and available space for the resistor 214 to occupy. To this end, the present disclosure is not intended to be limited to any particular range of resistivities or resistor dimensions.
  • the resistor 214 extends over the self-aligned gate edge isolation structure 208a, spanning the area between the gate structures 206a, 206b, 206c, and 206d.
  • the resistor 214 is electrically isolated from the gate structures 206a, 206b, 206c, and 206d by dielectric plugs 216a, 216b, 216c, and 216d, respectively.
  • suitable dielectric materials include, but are not limited to, oxides of silicon (e.g., Si0 2 ), doped oxides of silicon, fluorinated oxides of silicon, carbon doped oxides of silicon, various low-k dielectric materials known in the arts (e.g., porous Si0 2 ), and combinations thereof.
  • the resistor 214 is electrically isolated from the gate structures 206a, 206b, 206c, and 206d by the self-aligned gate edge isolation structure 208a.
  • the self-aligned gate edge isolation structure 208a can be composed of materials such as those previously discussed with respect to self-aligned gate edge isolation structure 108.
  • the dielectric material of plugs 216a, 216b, 216c, and 216d may or may not be distinguishable from the isolation material of the self-aligned gate edge structure 208a.
  • the resistor 214 is electrically connected by a first contact 220, also referred to as an anode, on a first location of the resistor 214, and a second contact 222, also referred to as a cathode, on a second location of the resistor 214.
  • the contacts 220 and 222 are formed of a conductive material, such as a metal species.
  • the metal species may be a pure metal, such as tungsten, nickel, or cobalt, or may be an alloy such as a metal-metal alloy or a metal-semiconductor alloy (e.g., such as a silicide material).
  • the term metal includes alloys, stacks, and other combinations of multiple metals.
  • the contacts 220 and 222 may be a multi -component structure having one or more barrier layers, liners, work function layers, in addition to a plug portion, and the present disclosure is not intended to be limited to any particular contact structure.
  • FIG. 2B illustrates a cross-sectional view taken along the a-a' axis of the structure of FIG. 2 A, showing, in addition to the elements shown in FIG. 2 A, an insulator layer 21 1 over the resistor 214.
  • Example materials or material combinations for the insulator layer 21 1 include a single material structure such as silicon dioxide, silicon oxy-nitride, silicon nitride, or carbon-doped silicon nitride.
  • insulator layer 21 1 may be composed of a low-k dielectric material or structure.
  • the substrate 202, local interconnects 210 and dielectric capping layer 212 are also shown in FIG. 2B. The previous relevant discussion with respect to the substrate 102, local interconnects 1 10, and dielectric capping layer 1 12 is equally applicable here as will be appreciated, and not all details and variations are repeated for sake of brevity.
  • FIG. 3 is a method for forming a semiconductor structure including a resistor between gates on self-aligned gate edge architecture in accordance with an embodiment of the present disclosure.
  • FIGS. 4A through 4L illustrate example structures that are formed as the method is carried out, and in accordance with some embodiments.
  • the method includes providing 305 a semiconductor structure including fins and a self-aligned gate edge isolation structure upon which a resistor may be formed between gates on self-aligned gate edge architecture.
  • FIG. 4A illustrates a semiconductor structure 400 including fins 404 and a self-aligned gate edge isolation structure 408a. Two groupings of fins 404, including adjacent fins 404a and 404b, with the self-aligned gate edge isolation structure 408a centered between them, are shown in FIG. 4A.
  • the semiconductor fins 404 are continuous with and protrude from the substrate 402, through an insulator layer 403, in this example embodiment.
  • the fins may be so-called replacement fins, such that those fins are composed of a semiconductor material different from the substrate (such as silicon germanium fins formed on a silicon substrate).
  • the fins can be native to the substrate or replacement fins or any combination of native and replacement fins.
  • a portion of a second self-aligned gate edge isolation structure 408b is also shown in FIG. 4A. The previous relevant discussion with respect to the substrate 102, insulator layer 103, fins 104, and self-aligned gate edge isolation structure 108, is equally applicable here as will be appreciated, and not all details and variations are repeated for sake of brevity.
  • the method further includes depositing 310 a high temperature carbon hardmask (HTCHM) material 450 over the semiconductor structure 400, as shown in FIG. 4B.
  • Suitable HTCHM materials include polymers of carbon, silicon, oxygen, and hydrogen having a cure temperature in a range of between 150 °C and 450 °C.
  • the HTCHM material layer 450 may be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), or by other deposition methods.
  • the method further includes etching 315 the HTCHM material 450 to recess the HTCHM material 450 to a level below the top surface of the self-aligned gate edge isolation structure 408a and over the semiconductor fins 404, as shown in FIG. 4C. Any wet and/or dry etching process selective to the HTCHM material over the self-aligned gate edge isolation structure 408 material is suitable for the etching step 315.
  • the method further includes depositing 320 a resistive material 455 over the semiconductor structure 400, as shown in FIG. 4D.
  • the resistive material layer 455 may be formed by CVD, PVD, or by other deposition methods capable of depositing a resistive material, such as titanium nitride (TiN) or tungsten (W), or any other material suitable to provide a resistor having low or otherwise acceptable variation in resistivity and a near-zero temperature coefficient, according to some embodiments.
  • the method further includes depositing 325 an insulator material 460 over the resistive material 455, as shown in FIG. 4E.
  • Example materials or material combinations for the insulator layer 460 include a single material structure such as silicon dioxide, silicon oxy-nitride, silicon nitride, low-k insulator such as porous silicon dioxide, or carbon-doped silicon nitride.
  • Other example materials or material combinations include a multi-layer stack having a lower portion silicon dioxide, silicon oxy-nitride, silicon nitride, or carbon-doped silicon nitride and an upper portion higher dielectric constant material such as hafnium oxide. Numerous materials and layer configurations will be apparent in light of this disclosure.
  • the insulator material layer 460 may be formed by CVD, PVD, or by other deposition methods capable of depositing such an insulator material.
  • the method further includes depositing 330 a carbon hardmask (CHM) material 465 over the area of the self-aligned gate edge isolation structure 408a where the resistor will be formed, as shown in FIG. 4F.
  • CHM materials include polymers of carbon, silicon, oxygen, and hydrogen having a cure temperature in a range of between 150 °C and 200 °C.
  • CHM material 465 can be patterned using any suitable techniques, such as one or more lithography and etch processes, for example, to deposit the CHM material 465 over the self-aligned gate edge isolation structure 408a.
  • the CHM material layer 465 may be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), or by other deposition methods.
  • the method further includes removing 335 the insulator material 460, resistive material 465, and CHTM material 450 from the portion of the
  • the method further includes removing 340 the CHM material 465, as shown in FIG. 4H. Any wet and/or dry etching process suitable for selectively removing the CHM material 465 can be used.
  • the method further includes depositing 345 a pattern of local-interconnect-to-trench (LIT) plugs and local-interconnect-to-gate (LIG) plugs over the self- aligned gate edge isolation structure, insulator layer, and resistor.
  • FIGS. 41 to 4L illustrate cross- sectional views taken along the b-b' axis of the structure of FIG. 2A, thereby showing the formation of the anode and cathode as described further below.
  • LIT plugs 470 and LIG plugs 475 can be patterned using any suitable techniques, such as one or more lithography and etch processes, to provide a pattern wherein the LIT plugs 470 are deposited over the self-aligned gate edge isolation structure 408a at the ends of the precision 414, and LIG plugs 475 alternate with LIT plugs 470 over the insulator layer 411, as shown in FIG. 41.
  • LIT plugs 470 and LIG plugs 475 are both formed of insulator materials, with LIG plugs 475 formed of the same material as the insulator layer 411, and LIT plugs 470 formed of a different insulator material.
  • Example materials or material combinations for the LIT plugs 470 and LIG plugs 475 include a single material structure such as silicon dioxide, silicon oxy-nitride, silicon nitride, or carbon- doped silicon nitride.
  • Other example materials or material combinations include a multi-layer stack having a lower portion silicon dioxide, silicon oxy-nitride, silicon nitride, or carbon-doped silicon nitride and an upper portion higher dielectric constant material such as hafnium oxide.
  • LIG plugs 475 and insulator layer 411 are formed of silicon nitride
  • LIT plugs 470 are formed of silicon dioxide.
  • the method further includes etching 350 the LIT plugs to the resistor, as shown in FIG. 4J.
  • the LIT plugs 470 and the portion of the insulator layer 411 under the LIT plugs 470 have been etched away to expose the portion of resistor 414 underneath the LIT plugs 470.
  • a wet etching process that etches silicon dioxide selectively over silicon nitride can be used to etch the LIT plugs 470, followed by a brief dry etching process that etches the portion of the insulator layer 411 under the LIT plugs 470, while removing a small amount (not shown) of the top of the LIG plugs 475.
  • the method further includes depositing 355 a first contact, also referred to as an anode, on a first location of the resistor, and a second contact, also referred to as a cathode, on a second location of the resistor, as shown in FIG. 4K.
  • a first contact also referred to as an anode
  • a second contact also referred to as a cathode
  • anode 420 is deposited between adjacent LIG plugs 475 on a first location of the resistor 414
  • cathode 422 is deposited between LIG plugs 475 on a second location of the resistor 414.
  • the method further includes depositing 360 LIT plugs over the self-aligned gate edge isolation structure and exposed portions of the resistor, as shown in FIG. 4L.
  • LIT plugs 416a and 416b are deposited at the ends of the resistor 414 to isolate the resistor 414 from adjacent structures, and LIT plugs 470 are deposited over the remaining exposed portion of the resistor 414.
  • the previous relevant discussion with respect to the dielectric plugs 216a and 216b is equally applicable here as will be appreciated, and not all details and variations are repeated for sake of brevity.
  • FIG. 5 illustrates a semiconductor structure including a resistor between gates on self- aligned gate edge architecture according to an embodiment of this disclosure.
  • the semiconductor fins 504a and 504b are tapered.
  • Resistor 514, contacts 520/522, local conductive interconnects 510, and dielectric capping layer 512 also show as-built shapes.
  • the previous discussion relevant to semiconductor fins 204a, and 204b, self- aligned gate edge structure 208, resistor 214, contacts 220/222, local conductive interconnects 210, and dielectric capping layer 212 is equally applicable here as will be appreciated.
  • FIG. 1 illustrates a semiconductor structure including a resistor between gates on self- aligned gate edge architecture according to an embodiment of this disclosure.
  • gate 5 also illustrates gate structures (gate electrode 506 and gate dielectric 505), dielectric plugs 516b and 516d, and the self-aligned gate edge structure 508.
  • gate structures 206, self-aligned gate edge structure 208, and dielectric plugs 216 is equally applicable here as will be appreciated.
  • Such tools may indicate the presence of resistors between gates on self-aligned gate edge architecture in a semiconductor integrated circuit, as variously described herein.
  • FIG. 6 is an example computing system implemented with one or more of the integrated circuit structures as disclosed herein, in accordance with some embodiments of the present disclosure.
  • the computing system 600 houses a motherboard 602.
  • the motherboard 602 may include a number of components, including, but not limited to, a processor 604 and at least one communication chip 606, each of which can be physically and electrically coupled to the motherboard 602, or otherwise integrated therein.
  • the motherboard 602 may be, for example, any printed circuit board, whether a main board, a daughterboard mounted on a main board, or the only board of system 600, etc.
  • computing system 600 may include one or more other components that may or may not be physically and electrically coupled to the motherboard 602.
  • volatile memory e.g., DRAM
  • non-volatile memory e.g., read only memory (ROM)
  • graphics processor e.g., a digital signal processor
  • crypto processor e.g., a chipset
  • an antenna e.g., a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth).
  • volatile memory e.g., DRAM
  • non-volatile memory e.g., read only memory (ROM)
  • a graphics processor e.g., a digital signal processor
  • crypto processor e.g., a graphics processor
  • chipset e.g., a graphics processor
  • any of the components included in computing system 600 may include one or more integrated circuit structures or devices configured in accordance with an example embodiment (e.g., to include one or more semiconductor structures including a resistor between gates on self-aligned gate edge architecture, as variously provided herein).
  • multiple functions can be integrated into one or more chips (e.g., for instance, note that the communication chip 606 can be part of or otherwise integrated into the processor 604).
  • the communication chip 606 enables wireless communications for the transfer of data to and from the computing system 600.
  • wireless and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non- solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not.
  • the communication chip 606 may implement any of a number of wireless standards or protocols, including, but not limited to, Wi-Fi (Institute of Electrical and Electronics Engineers (IEEE) 802.11 family), worldwide interoperability for microwave access (WiMAX) (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), lx evolution-data optimized (Ev-DO), high speed packet access (HSPA+), high speed downlink packet access (HSDPA+), high speed uplink packet access (HSUPA+), enhanced data rates for GSM evolution (EDGE), global system for mobile communication (GSM), general packet radio service (GPRS), code division multiple access (CDMA), time division multiple access (TDMA), digital enhanced cordless telecommunications (DECT), Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond.
  • Wi-Fi Institute of Electrical and Electronics Engineers (IEEE) 802.11 family
  • WiMAX IEEE 802.16 family
  • IEEE 802.20 long term evolution (L
  • the computing system 600 may include a plurality of communication chips 606.
  • a first communication chip 606 may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip 606 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.
  • communication chip 606 may include one or more semiconductor structures including a resistor between gates on self-aligned gate edge architecture as variously described herein.
  • the processor 604 of the computing system 600 includes an integrated circuit die packaged within the processor 604.
  • the integrated circuit die of the processor includes onboard circuitry that is implemented with one or more integrated circuit structures or devices as variously described herein.
  • the term "processor" may refer to any device or portion of a device that processes, for instance, electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.
  • the communication chip 606 also may include an integrated circuit die packaged within the communication chip 606.
  • the integrated circuit die of the communication chip includes one or more integrated circuit structures or devices as variously described herein.
  • multi -standard wireless capability may be integrated directly into the processor 604 (e.g., where functionality of any chips 606 is integrated into processor 604, rather than having separate communication chips).
  • processor 604 may be a chip set having such wireless capability.
  • any number of processor 604 and/or communication chips 606 can be used.
  • any one chip or chip set can have multiple functions integrated therein.
  • the computing system 600 may be a laptop, a netbook, a notebook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra-mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, a digital video recorder, or any other electronic device that processes data or employs one or more integrated circuit structures or devices formed using the disclosed techniques, as variously described herein.
  • PDA personal digital assistant
  • Example 1 is a semiconductor structure, comprising: a first semiconductor fin extending in a first direction; a second semiconductor fin adjacent to the first semiconductor fin and extending in the first direction; a first gate structure proximal to a first end of the first
  • the first gate structure orthogonal to the first direction; a second gate structure proximal to a second end of the first semiconductor fin and over the first semiconductor fin in the second direction; a first structure centered between the first and second semiconductor fins, the first structure comprising isolation material; and a second structure on the first structure, the second structure extending at least between the first gate structure and the second gate structure and comprising resistive material, the second structure being electrically isolated from the first and second gate structures.
  • Example 2 includes the subject matter of Example 1, wherein the second structure includes at least one of titanium nitride (TiN) and tungsten (W).
  • TiN titanium nitride
  • W tungsten
  • Example 3 includes the subject matter of Example 1 or Example 2, wherein the second structure has an electrical resistivity in a range of between 1 ohm/sq and 1,000 ohms/sq.
  • Example 4 includes the subject matter of any of Examples 1 to 3, wherein the first and second gate structures both include a gate dielectric and a gate electrode.
  • Example 5 includes the subject matter of any of Examples 1 to 4, further comprising a first contact on a first location of the second structure, and a second contact on a second location of the second structure.
  • Example 6 includes the subject matter of any of Examples 1 to 5, wherein the first structure includes a self-aligned gate edge isolation structure.
  • Example 7 includes the subject matter of any of Examples 1 to 6, wherein the second structure includes a precision resistor.
  • Example 8 includes the subject matter of any of Examples 1 to 6, wherein the second structure includes a thin film resistor.
  • Example 9 includes the subject matter of Example 8, wherein the thin film resistor has a thickness between the first gate structure and the second gate structure in a range of between 1 micron and 15 microns.
  • Example 10 includes the subject matter of any of Examples 1 to 9, wherein the second structure is electrically isolated from the first and second gate structures at least in part by dielectric plugs.
  • Example 1 1 includes a method for forming a semiconductor structure, the method comprising: forming a first semiconductor fin in a first direction; forming a second
  • the first gate structure orthogonal to the first direction; forming a second gate structure proximal to a second end of the first semiconductor fin and over the first semiconductor fin in the second direction; forming a first structure centered between the first and second semiconductor fins, the first structure comprising isolation material; and forming a second structure on the first structure, the second structure extending at least between the first gate structure and the second gate structure and comprising resistive material, the second structure being electrically isolated from the first and second gate structures.
  • Example 12 includes the subject matter of Example 11, wherein the second structure includes at least one of titanium nitride (TiN) and tungsten (W).
  • TiN titanium nitride
  • W tungsten
  • Example 13 includes the subject matter of either of Examples 1 1 or 12, wherein the second structure has an electrical resistivity in a range of between 1 ohm/sq and 1,000 ohms/sq.
  • Example 14 includes the subject matter of any of Examples 11 to 13, wherein the first and second gate structures both include a gate dielectric and a gate electrode.
  • Example 15 includes the subject matter of any of Examples 11 to 14, further including forming a first contact on a first location of the second structure, and forming a second contact on a second location of the second structure.
  • Example 16 includes the subject matter of any of Examples 11 to 15, wherein forming the first structure includes forming a self-aligned gate edge isolation structure.
  • Example 17 includes the subject matter of any of Examples 11 to 16, wherein forming the second structure includes forming a precision resistor.
  • Example 18 includes the subject matter of any of Examples 11 to 17, wherein forming the second structure includes forming a thin film resistor.
  • Example 19 includes the subject matter of any of Examples 11 to 18, further including forming dielectric plugs that electrically isolate the second structure from the first and second gate structures.
  • Example 20 includes a semiconductor structure, comprising: a first group of
  • semiconductor fins extending in a first direction; a second group of semiconductor fins adjacent to the first semiconductor fin and extending in the first direction; a first gate structure proximal to a first end of the first group of semiconductor fins and over the first group of semiconductor fins in a second direction, the first gate structure orthogonal to the first direction; a second gate structure proximal to a second end of the first group of semiconductor fins and over the first group of semiconductor fins in the second direction; a third gate structure proximal to a first end of the second group of semiconductor fins and over the second group of semiconductor fins in the second direction, the first gate structure orthogonal to the first direction; a fourth gate structure proximal to a second end of the second group of semiconductor fins and over the second group of semiconductor fins in the second direction; a first structure centered between the first and second groups of semiconductor fins, the first structure comprising isolation material; and a second structure on the first structure, the second structure spanning an area between the first, second, third, and fourth
  • Example 21 includes the subject matter of Example 20, further including a local interconnect layer.
  • Example 22 includes the subject matter of any of Examples 20 or 21, further including a dielectric capping layer.
  • Example 23 includes the subject matter of any of Examples 20 to 22, wherein the second structure includes at least one of titanium nitride (TiN) and tungsten (W).
  • TiN titanium nitride
  • W tungsten
  • Example 24 includes the subject matter of any of Examples 20 to 23, wherein the second structure has an electrical resistivity in a range of between 1 ohm/sq and 1,000 ohms/sq.
  • Example 25 includes the subject matter of any of Examples 20 to 24, wherein the first, second, third and fourth gate structures each include a gate dielectric and a gate electrode.
  • Example 26 includes the subject matter of any of Examples 20 to 25, wherein the first structure includes a self-aligned gate edge isolation structure.
  • Example 27 includes the subject matter of any of Examples 20 to 26, wherein the second structure includes a precision resistor.
  • Example 28 includes the subject matter of any of Examples 20 to 27, wherein the second structure includes a thin film resistor.
  • Example 29 includes the subject matter of Example 28, wherein the thin film resistor has a thickness between the first gate structure and the second gate structure in a range of between 1 micron and 15 microns.
  • Example 30 includes the subject matter of any of Examples 20 to 29, wherein the first group of semiconductor fins includes two semiconductor fins.
  • Example 31 includes the subject matter of any of Examples 20 to 30, wherein the second group of semiconductor fins includes two semiconductor fins.
  • Example 32 includes a computing device that includes the subject matter of any of Examples 1 to 10 and 20 to 30.

Landscapes

  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

L'invention concerne des techniques de formation de structures semiconductrices comprenant des résistances entre des grilles sur une architecture de bord de grille auto-alignée. Une structure semiconductrice comprend une première ailette semiconductrice s'étendant dans une première direction, et une seconde ailette semiconductrice adjacente à la première ailette semiconductrice, s'étendant dans la première direction. Une première structure de grille est disposée à proximité d'une première extrémité de la première ailette semiconductrice et sur la première ailette semiconductrice dans une seconde direction, orthogonale à la première direction, et une seconde structure de grille est disposée à proximité d'une seconde extrémité de la première ailette semiconductrice et sur la première ailette semiconductrice dans la seconde direction. Une première structure comprenant un matériau d'isolation est centrée entre les première et seconde ailettes semiconductrices. Une seconde structure comprenant un matériau résistif est disposée sur la première structure, la seconde structure s'étendant au moins entre la première structure de grille et la seconde structure de grille.
PCT/US2017/025582 2017-03-31 2017-03-31 Résistance entre des grilles sur une architecture de bord de grille auto-alignée Ceased WO2018182733A1 (fr)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100252895A1 (en) * 2007-04-11 2010-10-07 Ronald Kakoschke Apparatus of memory array using finfets
JP2012114321A (ja) * 2010-11-26 2012-06-14 Mitsubishi Electric Corp 半導体装置
US20140319623A1 (en) * 2011-12-28 2014-10-30 Curtis Tsai Methods of integrating multiple gate dielectric transistors on a tri-gate (finfet) process
KR20160043455A (ko) * 2014-10-13 2016-04-21 삼성전자주식회사 이종 게이트 구조의 finFET를 구비한 반도체 소자 및 그 제조방법
US20170040324A1 (en) * 2015-08-04 2017-02-09 Qualcomm Incorporated Finfet device and method of making the same

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100252895A1 (en) * 2007-04-11 2010-10-07 Ronald Kakoschke Apparatus of memory array using finfets
JP2012114321A (ja) * 2010-11-26 2012-06-14 Mitsubishi Electric Corp 半導体装置
US20140319623A1 (en) * 2011-12-28 2014-10-30 Curtis Tsai Methods of integrating multiple gate dielectric transistors on a tri-gate (finfet) process
KR20160043455A (ko) * 2014-10-13 2016-04-21 삼성전자주식회사 이종 게이트 구조의 finFET를 구비한 반도체 소자 및 그 제조방법
US20170040324A1 (en) * 2015-08-04 2017-02-09 Qualcomm Incorporated Finfet device and method of making the same

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