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WO2018176326A1 - 模数转换电路和方法 - Google Patents

模数转换电路和方法 Download PDF

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Publication number
WO2018176326A1
WO2018176326A1 PCT/CN2017/078801 CN2017078801W WO2018176326A1 WO 2018176326 A1 WO2018176326 A1 WO 2018176326A1 CN 2017078801 W CN2017078801 W CN 2017078801W WO 2018176326 A1 WO2018176326 A1 WO 2018176326A1
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WIPO (PCT)
Prior art keywords
voltage
capacitors
comparison
capacitor
capacitor array
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2017/078801
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English (en)
French (fr)
Inventor
范硕
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shenzhen Goodix Technology Co Ltd
Original Assignee
Shenzhen Goodix Technology Co Ltd
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Application filed by Shenzhen Goodix Technology Co Ltd filed Critical Shenzhen Goodix Technology Co Ltd
Priority to CN201780000180.5A priority Critical patent/CN108990427B/zh
Priority to EP17902662.0A priority patent/EP3432476A4/en
Priority to PCT/CN2017/078801 priority patent/WO2018176326A1/zh
Publication of WO2018176326A1 publication Critical patent/WO2018176326A1/zh
Priority to US16/168,774 priority patent/US10411725B2/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/34—Analogue value compared with reference values
    • H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
    • H03M1/46—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
    • H03M1/466—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter using switched capacitors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters
    • H03M1/1245—Details of sampling arrangements or methods
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters
    • H03M1/129—Means for adapting the input signal to the range the converter can handle, e.g. limiting, pre-scaling ; Out-of-range indication
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/002—Provisions or arrangements for saving power, e.g. by allowing a sleep mode, using lower supply voltage for downstream stages, using multiple clock domains or by selectively turning on stages when needed
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/34—Analogue value compared with reference values
    • H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
    • H03M1/46—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
    • H03M1/466—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter using switched capacitors
    • H03M1/468—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter using switched capacitors in which the input S/H circuit is merged with the feedback DAC array

Definitions

  • the present application belongs to the field of electronic circuit technologies, and in particular, to an analog-to-digital conversion circuit and method.
  • Analog-to-Digital Conversion converts the analog quantity of a connection into a discrete digital quantity.
  • the analog quantity can be an analog signal
  • the digital quantity can be a digital quantity. signal.
  • analog-to-digital conversion can be performed by successive approximation analog-to-digital converter, integral analog-to-digital converter and voltage-frequency conversion analog-to-digital converter; among them, successive approximation analog-to-digital converter (SAR ADC, Successive Approximation) Analog-to-Digital Converter) with medium conversion accuracy and medium conversion speed, CMOS process for small chip area and low power consumption, and easy multiplex conversion in terms of accuracy, speed, power consumption and cost With comprehensive advantages, it is widely used in industrial control, medical equipment and touch technology.
  • the basic principle of SARADC is to compare the analog input signal to be converted with a speculative signal, and determine whether to increase or decrease the speculative signal according to the size of the two to be forced into the analog input signal.
  • the speculative signal is obtained from the output of the D/A converter. When they are equal, the digital signal input to the D/A converter corresponds to the digital quantity of the analog input signal.
  • the dynamic range of the ADC means that when the analog input signal is within a certain range, the ADC can correctly convert the input analog signal into a digital signal. This signal range is the dynamic range of the ADC.
  • the dynamic range of the SARADC is determined by its reference voltage (Voltage Reference).
  • Voltage Reference the positive reference voltage
  • Vrefp the negative reference voltage
  • Vrefn the negative reference voltage
  • Vrefn its dynamic range
  • one of the technical problems solved by the embodiments of the present application is to provide an analog-to-digital conversion circuit and method for expanding the dynamic range of the ADC without changing the magnitude of the reference voltage.
  • An embodiment of the present application provides an analog-to-digital conversion circuit, including a first capacitor array, a logic circuit, and a comparator;
  • the first capacitor array connects the lower plates of the N capacitors to the first input voltage, the lower plates of the other capacitors are connected to the common mode voltage, and the upper plates of all the capacitors are connected to the common mode voltage.
  • the comparator provides a first comparison voltage to sample the first input voltage, the N being a positive integer less than the total number of capacitors;
  • the logic circuit controls the lower plate connection reference voltage or the ground voltage of the ith capacitor in the first capacitor array according to the stored i-th flag bit, so that the The magnitude of the first comparison voltage outputted by the first capacitor array approaches a magnitude of an analog voltage as a second comparison voltage, the i being a positive integer less than the total number of capacitors;
  • the comparator stores a comparison result of the first comparison voltage and the second comparison voltage to an i+1th flag bit of the logic circuit, and when i+1 is equal to all of the first capacitance array The analog-to-digital conversion is completed when the number of capacitors is reached.
  • An embodiment of the present application provides a method for analog-to-digital conversion, including:
  • the first capacitor array connects the lower plates of the N capacitors to the first input voltage, the lower plates of the other capacitors are connected to the common mode voltage, and the upper plates of all the capacitors are connected to the common mode voltage,
  • the first input voltage is sampled, and the comparator is provided with a first comparison voltage, where N is a positive integer less than the total number of capacitors;
  • the logic circuit controls the lower plate connection reference voltage or the ground voltage of the ith capacitor in the first capacitor array according to the stored i-th flag bit, so that the The magnitude of the first comparison voltage outputted by the first capacitor array approaches the magnitude of the second comparison voltage of the comparator, and the i is a positive integer smaller than the total number of capacitors;
  • the comparator stores a comparison result of the first comparison voltage and the second comparison voltage to an i+1th flag bit of the logic circuit, and when i+1 is equal to all of the first capacitance array The analog-to-digital conversion is completed when the number of capacitors is reached.
  • the first capacitor array connects the lower plate of the partial capacitor with the first input voltage, and the upper plate of all the capacitors in the first capacitor array is connected with the common mode voltage.
  • An input voltage is sampled; in the conversion phase, the lower plate of the capacitor in the first capacitor array is controlled one by one to be connected with a reference voltage or a ground voltage, so that the magnitude of the first comparison voltage approaches the magnitude of the second comparison voltage;
  • expanding the range of the first input voltage that is, expanding the dynamic range of the ADC.
  • 1A is a schematic diagram showing the circuit structure of a successive approximation digital-to-analog converter
  • FIG. 1B is a schematic diagram showing changes in output voltage of a successive approximation digital-to-analog converter
  • 1C is a schematic diagram showing the circuit structure of a successive approximation digital-to-analog converter
  • FIG. 2 is a schematic structural diagram of a circuit of a successive approximation digital-to-analog converter according to an embodiment of the present application
  • FIG. 3 is a schematic structural diagram of a circuit of another successive approximation digital-to-analog converter according to an embodiment of the present application
  • FIG. 4 is a schematic diagram of a circuit structure of another successive approximation digital-to-analog converter according to an embodiment of the present application
  • FIG. 5 is a schematic flowchart of a successive approximation digital-to-analog conversion method according to an embodiment of the present application
  • FIG. 6 is a schematic flow chart of another successive approximation digital-to-analog conversion method according to an embodiment of the present application.
  • FIG. 7 is a schematic flow chart of another successive approximation digital-to-analog conversion method according to an embodiment of the present application.
  • the first capacitor array connects the lower plate of the partial capacitor to the first input voltage, and the upper plate of all the capacitors in the first capacitor array is connected to the common mode voltage to sample the first input voltage;
  • the lower plates of the capacitors in the first capacitor array are controlled one by one to be connected with a reference voltage or a ground voltage, so that the magnitude of the first comparison voltage approaches the magnitude of the second comparison voltage; sampling according to the law of conservation of charge
  • the range of voltages that extend the dynamic range of the ADC.
  • FIG. 1A is a schematic diagram showing the circuit structure of a successive approximation digital-to-analog converter. As shown, it includes a digital to analog converter 101, a comparator 102, and a logic circuit 103.
  • the digital-to-analog converter 101 can provide an output voltage Vadc, the initial magnitude of the output voltage Vadc can be set according to the reference voltage Vref, the output voltage Vadc as the first comparison voltage of the comparator 102, and the input voltage Vi at the other end of the comparator 102 as the first Second, compare the voltage.
  • the comparator 102 obtains a comparison result of the first comparison voltage and the second comparison voltage. Alternatively, if Vi is greater than Vadc, the comparison result may be set to 1, otherwise, the comparison result is set to 0.
  • the logic circuit 103 obtains and stores the comparison result.
  • the number of comparisons required to complete one analog-to-digital conversion is xx, and the digital-to-analog converter 101 adjusts the output voltage Vadc according to the last comparison result so that the magnitude of the output voltage Vadc is close to the magnitude of the input voltage Vi.
  • FIG. 1B is a schematic diagram showing changes in the output voltage of a successive approximation digital-to-analog converter.
  • the horizontal axis of the coordinate axis is time, and the unit is the time when the digital-to-analog converter 101 completes the adjustment of the output voltage Vadc once; the vertical axis represents the output voltage Vadc of the comparator 102 in volts.
  • the comparator 102 sets the primary output voltage Vadc to half of the full scale voltage (Fu Sphere Voltage) V FS , that is, V FS /2.
  • the comparator 102 compares the magnitude of Vadc and the input voltage Vi, and adjusts Vdac according to the comparison result.
  • the input voltage Vi is greater than Vdac, which will adjust Vdac to the common mode voltage of V FS and V FS /2 (V FS +V FS /2)/2, ie 3V FS /4;
  • the common mode voltage of Vdac is V FS /2 and 3V FS /4 (V FS /2+3V FS /4)/2, that is, 5V FS /8; Steps until the adjustment is complete.
  • the logic circuit 103 stores the first comparison result of the comparator 102 to the most significant bit (MSB, Most Significant Bit), and stores the last comparison result of the comparator 102 to the least significant bit (LSB, Little Significant Bit). .
  • the digital-to-analog converter 101 adjusts the accuracy of the output voltage to V FS /2 i , that is, the difference between the output voltage Vadc and the input voltage Vi.
  • V FS /2 i the difference between the output voltage Vadc and the input voltage Vi.
  • the full-scale voltage V FS is a reference voltage Vref.
  • the illustrated logic circuit 103 is a shift register (ShiftRegister).
  • FIG. 1C is a schematic diagram showing the circuit structure of a successive approximation digital-to-analog converter. As shown, it includes a digital to analog converter 101, a comparator 102, and a logic circuit 103.
  • the digital to analog converter 101 includes a first capacitor array 111, a first switch array 121, a second capacitor array 131, and a second switch array 141.
  • the first capacitor array 111 and the second capacitor array 131 are respectively connected to the forward input terminal of the comparator 102 and Inverting the input terminal to provide the first comparison voltage and the second comparison voltage respectively for the comparator 102;
  • the logic circuit 103 is configured to store the comparison result of the comparator 102, and control the first switch array 121 and the second according to the comparison result
  • the opening or closing of the switch in the switch array 141 is such that the magnitude of the first comparison voltage approaches the magnitude of the second comparison voltage.
  • the first capacitor array 111 is configured to connect the lower plates of all the capacitors to the first input voltage Vip, and the upper plates of all the capacitors in the first capacitor array 111 are connected to the common mode voltage Vcm to the first input. The voltage is sampled. Taking the capacitor C1 in the first capacitor array 111 as an example, the arc side of the capacitor C1 is the lower plate, and the straight side of the C1 is the upper plate.
  • the first input voltage Vip may be a forward input voltage, that is, the input voltage Vi is used as the first input voltage Vip to provide a first comparison voltage to the forward input terminal of the comparator 102.
  • the sampling phase is a phase of charging the capacitor
  • the amount of charge of the first capacitor array 111 is:
  • the second capacitor array 131 is configured to connect the lower plates of all the capacitors to the second input voltage Vin, and the upper plates of all the capacitors in the second capacitor array 131 are connected to the common mode voltage Vcm to the second input. Voltage sampling;
  • the second input voltage Vin may be an inverted input voltage, that is, the input voltage Vi is used as the second input voltage Vin to provide a second comparison voltage for the inverting input terminal of the comparator 102, and the charge of the first capacitor array 111 at this stage.
  • the quantity is:
  • the first capacitor array 111 is further configured to disconnect the upper plate of all capacitors from the common mode voltage Vcm, and connect the lower plates of all capacitors to the common mode voltage Vcm, and all the capacitors in the first capacitor array 111
  • the upper plate is coupled to the comparator 102 to provide a first comparison voltage to the comparator.
  • the first comparison voltage can be a voltage input to the forward input of comparator 102.
  • the second capacitor array 131 is further configured to disconnect the upper plate of all capacitors from the common mode voltage Vcm, and connect the lower plates of all capacitors to the common mode voltage Vcm, and all the capacitors in the second capacitor array 131
  • the upper plate is coupled to the comparator 102 to provide a second comparison voltage to the comparator.
  • the second comparison voltage can be a voltage input to the inverting input of the comparator.
  • the comparison result of the first comparison voltage and the second comparison voltage is stored as a first flag bit of the logic circuit 103.
  • the first flag bit is the most significant bit in logic circuit 103.
  • the amount of charge of the first capacitor array 111 at this time is:
  • the logic circuit controls, according to the stored i-th flag bit, the lower plate of the ith capacitor in the first capacitor array to be connected with a reference voltage or a ground voltage, so that The magnitude of the first comparison voltage outputted by the first capacitor array approaches a magnitude of the second comparison voltage, and the i is a positive integer smaller than the total number of capacitors;
  • the lower plate connection reference of the first capacitor in the first capacitor array 111 (ie, the first to the ith-1th capacitors, i>1 is valid) Voltage or ground voltage, the lower plate of the i+1th to Nth capacitors is connected to the common mode voltage Vcm, and the lower plates of the i+1th to Nth capacitors are in an off state, and the first to Mth capacitors are
  • the upper plate is connected to the forward input terminal of the comparator 102;
  • the second plate array 131 has a lower plate connection reference voltage before the ith capacitor (ie, the first to the ith-1th capacitors, i>1 is valid)
  • the ground voltage the lower plate of the i+1th to Nth capacitors is connected to the common mode voltage Vcm, and the lower plates of the i+1th to Nth capacitors are in an off state, on the first to the Mth capacitors
  • the plates are connected to the inverting input of comparator 102.
  • the comparator 102 stores a comparison result of the first comparison voltage and the second comparison voltage to an i+1th flag bit of the logic circuit, and when i+1 is equal to the first capacitance array The analog-to-digital conversion is completed when all the capacitors are counted.
  • the comparator 102 performs the first comparison, if the first comparison voltage is greater than the second comparison voltage, the output result is 1, and the lower plate is connected to Vgnd, assuming that the voltage of the upper plate is Vx2.
  • the charge amount of the first capacitor array 111 is:
  • the Vin can be a reverse input voltage.
  • the range of Vip-Vin is [-(Vref-Vgnd), Vref-Vgnd].
  • the circuit includes a digital-to-analog converter (not shown), a comparator 202, and a logic circuit 203.
  • the converter includes a first capacitor array 211 and a switch array 221.
  • the first capacitor array 211 is configured to connect the lower plates of the N capacitors to the first input voltage Vip, the lower plates of the other capacitors are connected to the common mode voltage Vcm, and the upper plates of all the capacitors in the first capacitor array 211
  • a common mode voltage Vcm is connected to sample the first input voltage, the N being a positive integer less than the total number of capacitors M.
  • the sampling phase is a phase of charging the capacitor
  • the amount of charge of the first capacitor array 211 is:
  • the first capacitor array 211 is further configured to disconnect the upper plate of all capacitors from the common mode voltage Vcm, and connect the lower plates of all the capacitors to the common mode voltage Vcm, and connect the upper plates of all the capacitors.
  • the comparator 202 provides a first comparison voltage to the comparator; the first comparison voltage can be a voltage input to the forward input of the comparator 202.
  • the inverting input of the comparator 202 is connected to the common mode voltage Vcm.
  • the comparator 202 stores a comparison result of the first comparison voltage and the second comparison voltage to a first flag of the logic circuit 203.
  • the first flag bit is the most significant bit in logic circuit 103.
  • the amount of charge of the first capacitor array 211 is:
  • the logic circuit controls the lower plate of the ith capacitor in the first capacitor array to be connected with a reference voltage or a ground voltage according to the stored i-th flag bit, so that the first The magnitude of the first comparison voltage outputted by the capacitor array approaches a magnitude of the second comparison voltage, and the i is a positive integer smaller than the total number of capacitors;
  • the states of the other capacitors are specifically: the capacitance before the ith capacitor in the first capacitor array 211 (ie, the first to the ith-1th capacitors, i>1)
  • the lower plate is connected to the reference voltage or the ground voltage
  • the lower plate of the i+1th to Nth capacitors is connected to the common mode voltage Vcm
  • the lower plate of the i+1th to Nth capacitors is in the off state
  • the upper plate of the 1st to the Mth capacitor is connected to the forward input terminal of the comparator 102;
  • the capacitance of the ith capacitor of the second capacitor array 231 ie, the first to the ith-1th capacitor, i>1 is valid
  • Lower plate connection Reference voltage or ground voltage the lower plate of the i+1th to Nth capacitors is connected to the common mode voltage Vcm, and the lower plates of the i+1th to Nth capacitors are in an off state, the first to the Mth capacitors
  • the upper plate is connected to
  • the comparator stores a comparison result of the first comparison voltage and the second comparison voltage to an i+1th flag bit of the logic circuit, and when i+1 is equal to all of the first capacitance array The analog-to-digital conversion is completed when the number of capacitors is reached.
  • the value of the flag bit stored in the logic circuit is 0 or 1, for example, if the first voltage is greater than the second voltage when the i-th comparison is performed, the ith is The flag bit is 1, and if the first voltage is less than the second voltage in the i-th comparison, the ith flag is 0.
  • the lower plate of the ith capacitor in the first capacitor array 311 is connected to the ground voltage, and the ith capacitor in the second capacitor array 331 is connected.
  • the lower plate is connected to the reference voltage.
  • the lower plate of the ith capacitor in the first capacitor array 211 is controlled to be connected to a reference voltage or a ground voltage according to the flag bit, so that the first comparison voltage is
  • the size of the second comparison voltage is close to:
  • the lower plate of the ith capacitor in the first capacitor array 211 is connected to the ground voltage
  • the lower plate of the ith capacitor in the first capacitor array 211 is connected to the reference voltage.
  • the comparator is further configured to obtain a comparison result of the first comparison voltage and the second comparison voltage, and store the comparison result as a flag bit to the logic circuit.
  • the i+1th bit includes:
  • the comparison result is set to 1, otherwise, the comparison result is set to 0;
  • the comparison result is stored as a flag bit to the i+1th bit of the logic circuit.
  • the comparator 102 performs the first comparison, if the output result is 1, assuming that the voltage of the upper plate is V x2 and the lower plate is connected to Vgnd, the charge of the first capacitor array 211 at this time.
  • the quantity is:
  • the amount of charge of the first capacitor array 211 is:
  • the logic circuit is a shift register.
  • the value of the N is set according to a value range of the first input voltage.
  • the larger the value of N is, the smaller the value range of the first input voltage is, and vice versa, the larger the value range of the first input voltage is.
  • N can be set according to the actual application, and the value of N does not change during the conversion phase.
  • the N capacitors selected from the total capacitance (M capacitors) of the first capacitor array 211 may be discontinuous.
  • a capacitor of a common mode voltage Vcm (a capacitor that is not converted among the N capacitors) may be connected from the lower plate of the first capacitor array 211.
  • a capacitor is randomly selected for conversion.
  • each capacitor in the first capacitor array 211 is formed by a plurality of capacitor cells connected in series or in parallel, and the capacitor unit corresponding to each capacitor is in a binary arrangement or a non-binary row. cloth.
  • the capacitor C1 can be formed by connecting 2 5 (ie, 32) capacitor units in parallel, and all the capacitor units are arranged in a binary arrangement, and the analog-to-digital conversion can be completed by using a Binary Search method, which has an operation. Fast, efficient and so on.
  • the capacitor C1 can be formed by 31 capacitor units in parallel, and all the capacitor units are arranged in a non-binary manner.
  • the capacitor units When the capacitor unit is operated, the capacitor units are operated one by one, which has good fault tolerance and low power consumption. Other advantages, for example, when the output of one bit of the comparator is wrong, the subsequent capacitor unit can be adjusted to ensure the correctness of the analog-to-digital conversion result.
  • embodiments of the present application are applicable to single-ended ADCs.
  • the embodiment of the present application can expand the range of the first input voltage without changing the reference voltage, that is, expand the dynamic range of the ADC.
  • FIG. 3 is a schematic diagram showing the circuit structure of a successive approximation digital-to-analog converter. As shown, it includes a digital to analog converter 301, a comparator 302, and a logic circuit 303.
  • the digital to analog converter 301 includes a first capacitor array 311, a first switch array 321, a second capacitor array 331, and a second switch array 341.
  • the first capacitor array 311 is configured to connect the lower plates of the N capacitors to the first input voltage Vip, the lower plates of the other capacitors are connected to the common mode voltage Vcm, and the upper plates of all the capacitors in the first capacitor array 311 A common mode voltage Vcm is connected to sample the first input voltage, the N being a positive integer less than the total number of capacitors M.
  • the sampling phase is a phase of charging the capacitor
  • the amount of charge of the first capacitor array 311 is:
  • the second capacitor array 331 is further configured to connect the lower plates of the N capacitors to the second input voltage Vin, the lower plates of the other capacitors are connected to the common mode voltage Vcm, and the upper poles of all the capacitors in the second capacitor array 331
  • the board is connected to a common mode voltage Vcm to sample the second input voltage
  • the amount of charge of the second capacitor array 311 in the sampling phase is:
  • the first capacitor array 311 is further configured to disconnect the upper plate of all capacitors from the common mode voltage Vcm, and connect the lower plates of all capacitors to the common mode voltage Vcm, and all the capacitors in the first capacitor array 311
  • the upper plate is coupled to the comparator 302 to provide a first comparison voltage to the comparator; the first comparison voltage can be a voltage input to the forward input of the comparator 302.
  • the second capacitor array 331 is further configured to disconnect the upper plate of all capacitors from the common mode voltage Vcm, and connect the lower plates of all the capacitors to the common mode voltage Vcm, and all the capacitors in the second capacitor array 331
  • the upper plate is coupled to the comparator 302 to provide a second comparison voltage to the comparator.
  • the second comparison voltage can be a voltage input to the inverting input of comparator 302.
  • the comparison result of the first comparison voltage and the second comparison voltage is stored as a first flag bit of the logic circuit 303.
  • the first flag bit is the most significant bit in logic circuit 103.
  • the amount of charge of the first capacitor array 311 is:
  • the logic circuit 303 controls the lower plate of the ith capacitor in the first capacitor array 311 to be connected with a reference voltage or a ground voltage according to the stored i-th flag bit, to And causing the magnitude of the first comparison voltage output by the first capacitor array 311 to be closer to the magnitude of the second comparison voltage, where i is less than the total a positive integer of the number of capacitors;
  • the logic circuit controls the lower plate of the ith capacitor in the second capacitor array 331 to be connected with a reference voltage or a ground voltage according to the stored i-th flag bit, so that the second capacitor array 331
  • the magnitude of the output second comparison voltage approaches the magnitude of the first comparison voltage.
  • the value of the flag bit stored in the logic circuit is 0 or 1, for example, if the first comparison voltage is greater than the second comparison voltage when the i-th comparison is performed, The i flag bits are 1, and if the first comparison voltage is less than the second comparison voltage in the i-th comparison, the i-th flag bit is 0.
  • the ith flag is 1, the lower plate of the ith capacitor in the first capacitor array 311 is connected to the ground voltage, and the ith capacitor in the second capacitor array 331 is connected.
  • the lower plate is connected to the reference voltage; if the i-th flag is 0, the lower plate of the ith capacitor in the first capacitor array 311 is connected to the reference voltage, and the The lower plate of the ith capacitor in the second capacitor array 331 is connected to the ground voltage.
  • one of the capacitor arrays can obtain a value obtained by inverting the flag bit, and control the connection relationship of the capacitors in the capacitor array according to the inverted value.
  • the second capacitor array 331 obtains a pair. The value of the flag is inverted, and when the value of the i-th flag is inverted, the lower plate of the ith capacitor in the second capacitor array 331 is connected to the ground voltage. When the i-th flag is 0, the lower plate of the ith capacitor in the second capacitor array 331 is connected to the reference voltage.
  • the states of the other capacitors are specifically: the capacitance before the ith capacitor in the first capacitor array 311 (ie, the first to the ith-1th capacitors, and the i>1 is valid)
  • the lower plate is connected to the reference voltage or the ground voltage, and the lower plate of the i+1th to Nth capacitors is connected to the common mode voltage Vcm, and the lower plate of the i+1th to Nth capacitors is in the off state, the first
  • the upper plate of the Mth capacitor is connected to the forward input terminal of the comparator 102; the capacitance of the ith capacitor in the second capacitor array 331 (ie, the first to the ith-1th capacitors, i>1 is valid)
  • the lower plate is connected to the reference voltage or the ground voltage, and the lower plate of the i+1th to Nth capacitors is connected to the common mode voltage Vcm, and the lower plates of the i+1th to Nth capacitors are in the off state, the first to The upper plate
  • the comparator stores a comparison result of the first comparison voltage and the second comparison voltage to an i+1th flag bit of the logic circuit, and when i+1 is equal to all of the first capacitance array The analog-to-digital conversion is completed when the number of capacitors is reached.
  • the Vip is a forward input voltage and the Vin is an inverted input voltage.
  • embodiments of the present application are applicable to differential ADCs.
  • the embodiment of the present application can expand the range of the first input voltage without changing the reference voltage, that is, expand the dynamic range of the ADC; and the circuit of the embodiment of the present application has a simple structure and does not need to add an additional switch. achieve.
  • the digital to analog converter 401 includes a first capacitor array 411 and a second capacitor array 421.
  • C1 4C
  • C2 2C
  • C3 1C
  • C4 1C.
  • the reference voltage Vref 1.8V
  • the ground voltage Vgnd 0.2V.
  • Common mode power The voltage Vcm is 1V
  • the first input voltage Vip is 1.9V
  • the second input voltage is 0.1V.
  • C1 and C2 in the first capacitor array 411 are sampled, and C3 and C4 do not participate in sampling, that is, the lower plates of C1 and C2 are connected to the first input voltage Vip, and the lower plates of C3 and C4 are connected to the common mode voltage Vcm, C1.
  • the upper plates of C2, C3, and C4 are connected to the common mode voltage Vcm, and the amount of charge of the first capacitor array 411 is:
  • C1+C2 in the first capacitor array 411 is sampled, and C3 and C4 do not participate in sampling, that is, the lower plate of C1+C2 is connected to the first input voltage Vip, and the lower plates of C3 and C4 are connected to the common mode voltage Vcm, C1.
  • the upper plates of C2, C3, and C4 are connected to the common mode voltage Vcm, and the amount of charge of the second capacitor array 421 is:
  • the upper plates of C1, C2, C3, and C4 are disconnected from the common mode voltage Vcm, and the lower plates of C1, C2, C3, and C4 are connected to the common mode voltage Vcm, and C1, C2 are added.
  • the upper plates of C3 and C4 are connected to the forward comparator of comparator 402. Assume that the input voltage of the forward comparator of comparator 402 is Vx1, which is obtained according to the conservation of charge:
  • the upper plates of C1, C2, C3, and C4 are disconnected from the common mode voltage Vcm, and the lower plates of C1, C2, C3, and C4 are connected to the common mode voltage Vcm, and C1, C2 are added.
  • the upper plates of C3 and C4 are connected to the negative comparator of comparator 402. Assume that the input voltage of the negative comparator of comparator 402 is Vy1, which is obtained according to the conservation of charge:
  • the comparator 402 Since Vx1 ⁇ Vy1, the comparator 402 outputs 0 and stores 0 to the first flag of the logic circuit 403.
  • the lower plate of the first capacitor C1 in the first capacitor array 411 is connected to the reference voltage Vref, and the first one in the second capacitor array 421.
  • the lower plate of the capacitor C1 is connected to the ground voltage Vgnd.
  • the input voltage of the forward comparator of comparator 402 is Vx2, which is obtained according to the conservation of charge:
  • the comparator 402 Since Vx2 ⁇ Vy2, the comparator 402 outputs 0 and stores 0 to the second flag of the logic circuit 403.
  • the lower plate of the second capacitor C2 in the first capacitor array 411 is connected to the reference voltage Vref, and the second of the second capacitor array 421.
  • the lower plate of the capacitor C2 is connected to the ground voltage Vgnd.
  • the input voltage of the forward comparator of comparator 402 is Vx3, which is obtained according to the conservation of charge:
  • comparator 402 Since Vx3 ⁇ Vy3, comparator 402 outputs 0 and stores 0 to the third flag of logic circuit 403.
  • the lower plate of the third capacitor C3 in the first capacitor array 411 is connected to the reference voltage Vref, and the third of the second capacitor array 421.
  • the lower plate of the capacitor C3 is connected to the ground voltage Vgnd.
  • the input voltage of the forward comparator of comparator 402 is Vx4, which is obtained according to the conservation of charge:
  • comparator 402 Since Vx4 > Vy4, comparator 402 outputs 1 and stores 1 to the 4th flag of logic circuit 403.
  • FIG. 5 is a schematic flow chart of a successive approximation digital-to-analog conversion method. As shown, the method includes:
  • the first capacitor array connects the lower plates of the N capacitors to the first input voltage, the lower plates of the other capacitors are connected to the common mode voltage, and the upper plates of all the capacitors are connected to the common mode voltage. Sampling the first input voltage, where N is a positive integer less than the total number of capacitors;
  • the logic circuit controls the storing according to the stored i-th flag bit.
  • the lower plate of the ith capacitor in the first capacitor array is connected to the reference voltage to the ground voltage such that the magnitude of the first comparison voltage output by the first capacitor array approaches the second comparison voltage of the comparator Size, the i is a positive integer smaller than the total number of capacitors;
  • the comparator stores a comparison result of the first comparison voltage and the second comparison voltage to an i+1th flag bit of the logic circuit, and when i+1 is equal to the first capacitor array The analog-to-digital conversion is completed when all the capacitors are in the number.
  • the method of the embodiment may be the circuit of the corresponding embodiment of FIG. 2, and the specific steps are similar to those of the embodiment, and are not described herein again.
  • FIG. 6 is a schematic flow chart of a successive approximation digital-to-analog conversion method. As shown, the method further includes:
  • the first capacitor array connects the lower plates of all capacitors to the common mode voltage, and connects the upper plates of all capacitors to the comparator to provide a first comparison for the comparator. Voltage;
  • the comparator stores a comparison result of the first comparison voltage and the second comparison voltage to a first flag bit of the logic circuit.
  • S601, S604, and S605 are similar to S501, S502, and S503 in the corresponding embodiment of FIG. 5, and details are not described herein again.
  • the method of the embodiment may be the circuit of the corresponding embodiment of FIG. 2, and the specific steps are similar to those of the embodiment, and are not described herein again.
  • FIG. 7 is a schematic flow chart of a successive approximation digital-to-analog conversion method. As shown, the method further includes:
  • the second capacitor array connects the lower plates of the N capacitors to the second input voltage, and connects the upper plates of all the capacitors to the common mode voltage to sample the second input voltage.
  • the logic circuit controls, according to the stored i-th flag bit, the lower plate of the ith capacitor in the second capacitor array to be connected with a reference voltage or a ground voltage, The magnitude of the second comparison voltage is brought closer to the magnitude of the first comparison voltage.
  • S701, S702, and S705 are similar to S501, S502, and S503 in the corresponding embodiment of FIG. 5, and details are not described herein again.
  • the method of the embodiment may be the circuit of the embodiment of FIG. 3, and the specific steps are similar to those of the embodiment, and are not described herein again.
  • embodiments of the embodiments of the present application can be provided as a method, apparatus (device), or computer program product. Therefore, embodiments of the present application may adopt an entirely hardware embodiment, an entirely software embodiment, or a combination of soft A form of embodiment of hardware and hardware. Moreover, embodiments of the present application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) including computer usable program code.
  • computer-usable storage media including but not limited to disk storage, CD-ROM, optical storage, etc.
  • Embodiments of the present application are described with reference to flowchart illustrations and/or block diagrams of methods, apparatus, and computer program products according to embodiments of the present application. It will be understood that each flow and/or block of the flowchart illustrations and/or FIG.
  • These computer program instructions can be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing device to produce a machine for the execution of instructions for execution by a processor of a computer or other programmable data processing device.
  • the computer program instructions can also be stored in a computer readable memory that can direct a computer or other programmable data processing device to operate in a particular manner, such that the instructions stored in the computer readable memory produce an article of manufacture comprising the instruction device.
  • the apparatus implements the functions specified in one or more blocks of a flow or a flow and/or block diagram of the flowchart.
  • These computer program instructions can also be loaded onto a computer or other programmable data processing device such that a series of operational steps are performed on a computer or other programmable device to produce computer-implemented processing for execution on a computer or other programmable device.
  • the instructions provide steps for implementing the functions specified in one or more of the flow or in a block or blocks of a flow diagram.

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Abstract

一种模数转换的电路和方法，包括在采样阶段，第一电容阵列将N个电容的下极板连接第一输入电压，其它电容的下极板连接共模电压，并将全部电容的上极板连接共模电压，以对第一输入电压进行采样，N为小于全部电容个数的正整数（S501）；在转换阶段的第i次转换中，逻辑电路根据存储的第i个标志位控制第一电容阵列中的第i个电容的下极板连接参考电压或接地电压，以使第一电容阵列输出的第一比较电压的大小趋近于第二比较电压的大小（S502）；比较器将第一比较电压和第二比较电压的比较结果存储至逻辑电路的第i+1个标志位，且当i+1等于第一电容阵列中全部电容个数时模数转换完成（S503）。可在不改变参考电压大小的情况下，扩大了模数转换的动态范围。

Description

模数转换电路和方法 技术领域
本申请属于电子电路技术领域，尤其涉及一种模数转换电路和方法。
背景技术
模数转换(ADC,Analogue-to-Digital Conversion)，是将连接变化的模拟量(Analog Quantity)转换为离散的数字量(Digital Quantity)，例如，模拟量可以是模拟信号，数字量可以是数字信号。根据转换方式，可采用逐次逼近型模数转换器、积分型模数转换器和压频变换型模数转换器等进行模数转换；其中，逐次逼近型模数转换器(SAR ADC，Successive Approximation Analog-to-Digital Converter)，具有中等转换精度和中等转换速度，采用CMOS工艺实现可以保证较小的芯片面积和低功耗，而且易于实现多路转换，在精度、速度、功耗和成本方面具有综合优势，被广泛应用于工业控制、医疗仪器以及触控技术等领域。
SARADC基本原理是：将待转换的模拟输入信号与一个推测信号进行比较，根据二者大小决定增大还是减小所述推测信号，以便向所述模拟输入信号逼进。推测信号由D/A转换器的输出获得，当二者相等时，向D/A转换器输入的数字信号就对应的是模拟输入信号的数字量。
ADC的动态范围是指：当所述模拟输入信号在一定范围内的时候，ADC能够正确地将输入的模拟信号转换成为数字信号，这个信号范围就是ADC的动态范围。
现有技术中，SARADC的动态范围是由其参考电压(Voltage Reference)决定的。例如在一个全差分SARADC中，正参考电压为Vrefp，负参考电压为Vrefn，那么它的动态范围即为(Vrefp-Vrefn)。为确保所述模拟输入信号可被正确转换，通常需要扩大SARADC的范围，即增大参考电压，这种方式势必消耗更多的电量。
因此，如何在不改变参考电压大小的情况下，扩大ADC的动态范围，成为现有技术中亟需解决的技术问题。
发明内容
有鉴于此，本申请实施例所解决的技术问题之一在于提供一种模数转换的电路和方法，用以在不改变参考电压大小的情况下，扩大ADC的动态范围。
本申请实施例提供一种模数转换的电路，包括第一电容阵列、逻辑电路和比较器；
在采样阶段，所述第一电容阵列将N个电容的下极板连接第一输入电压，其它电容的下极板连接共模电压，并将全部电容的上极板连接共模电压，为所述比较器提供第一比较电压，以对所述第一输入电压进行采样，所述N为小于全部电容个数的正整数；
在转换阶段的第i次转换中，所述逻辑电路根据存储的第i个标志位控制所述第一电容阵列中的第i个电容的下极板连接参考电压或接地电压，以使所述第一电容阵列输出的第一比较电压的大小趋近于作为第二比较电压的的模拟电压的大小，所述i为小于所述全部电容个数的正整数；
所述比较器将所述第一比较电压和所述第二比较电压的比较结果存储至所述逻辑电路的第i+1个标志位，且当i+1等于所述第一电容阵列中全部电容个数时模数转换完成。
本申请实施例提供一种模数转换的方法，包括：
在采样阶段，所述第一电容阵列将N个电容的下极板连接第一输入电压，其它电容的下极板连接共模电压，并将全部电容的上极板连接共模电压，以对所述第一输入电压进行采样，为所述比较器提供第一比较电压，所述N为小于全部电容个数的正整数；
在转换阶段的第i次转换中，所述逻辑电路根据存储的第i个标志位控制所述第一电容阵列中的第i个电容的下极板连接参考电压或接地电压，以使所述第一电容阵列输出的第一比较电压的大小趋近于所述比较器的第二比较电压的大小，所述i为小于所述全部电容个数的正整数；
所述比较器将所述第一比较电压和所述第二比较电压的比较结果存储至所述逻辑电路的第i+1个标志位，且当i+1等于所述第一电容阵列中全部电容个数时模数转换完成。
由以上技术方案可见，本申请实施例在采样阶段，第一电容阵列将部分电容的下极板与第一输入电压，第一电容阵列中全部电容的上极板与共模电压连接，以对第一输入电压进行采样；在转换阶段，逐一控制第一电容阵列中电容的下极板与参考电压或接地电压连接，以使第一比较电压的大小趋近于所述第二比较电压的大小；根据电荷守恒定律,采样阶段的电荷量等于转换阶段的电荷量,即第一输入电压部分电容＝(参考电压-接地电压)全部电容，因此本申请实施例可在不改变参考电压大小的情况下，扩大了第一输入电压的取值范围，即扩大了ADC的动态范围。
附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对实施例或现有技 术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1A为一种逐次逼近数模转换器的电路结构示意图；
图1B为一逐次逼近数模转换器的输出电压的变化示意图；
图1C为一种逐次逼近数模转换器的电路结构示意图；
图2为本申请实施例一种逐次逼近数模转换器的电路结构示意图；
图3为本申请实施例另一种逐次逼近数模转换器的电路结构示意图；
图4为本申请实施例另一种逐次逼近数模转换器的电路结构示意图；
图5为本申请实施例一种逐次逼近数模转换方法的流程示意图；
图6为本申请实施例另一种逐次逼近数模转换方法的流程示意图；
图7为本申请实施例另一种逐次逼近数模转换方法的流程示意图。
具体实施方式
本申请实施例在采样阶段，第一电容阵列将部分电容的下极板连接第一输入电压，第一电容阵列中全部电容的上极板连接共模电压，以对第一输入电压进行采样；在转换阶段，逐一控制第一电容阵列中电容的下极板与参考电压或接地电压连接，以使第一比较电压的大小趋近于所述第二比较电压的大小；根据电荷守恒定律,采样阶段的电荷量等于转换阶段的电荷量,即第一输入电压部分电容＝(参考电压-接地电压)全部电容，因此本申请实施例可在不改变参考电压大小的情况下，扩大了第一输入电压的取值范围，即扩大了ADC的动态范围。
当然，实施本申请实施例的任一技术方案必不一定需要同时达到以上的所有优点。
为使得本申请的发明目的、特征、优点能够更加的明显和易懂，下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而非全部实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
图1A为一种逐次逼近数模转换器的电路结构示意图。如图所示，其包括：数模转换器101，比较器102和逻辑电路103。
数模转换器101可提供输出电压Vadc，输出电压Vadc的初始大小可根据参考电压Vref设定，输出电压Vadc作为比较器102的第一比较电压，将比较器102另一端的输入电压Vi作为第二比较电压。比较器102获得第一比较电压和第二比较电压的比较结果，可选地，如果Vi大于Vadc，所述比较结果可设置为1，否则，所述比较结果设置为0。
逻辑电路103获得并存储所述比较结果。完成一次模数转换所需的比较次数为xx，而数模转换器101根据最后一次的比较结果调整输出电压Vadc，以使输出电压Vadc的大小与输入电压Vi的大小接近。
图1B为一逐次逼近数模转换器的输出电压的变化示意图。如图所示，坐标轴的横轴为时间，单位为数模转换器101完成一次调整上述输出电压Vadc的时间；纵轴为比较器102的输出电压Vadc，单位为伏特。
具体地，比较器102将一次的输出电压Vadc设置为满量程电压(Full Scale Voltage)VFS的一半，即VFS/2。比较器102比较Vadc和输入电压Vi的大小，并根据比较结果调整Vdac。例如，第一次比较后，输入电压Vi大于Vdac，则将调整Vdac为VFS和VFS/2的共模电压(VFS+VFS/2)/2，即3VFS/4；第二次比较后，输入电压Vi小于Vdac，则将调整Vdac为VFS/2和3VFS/4的共模电压(VFS/2+3VFS/4)/2，即5VFS/8；重复上述步骤，直至调整完成。
可选地，逻辑电路103将比较器102的第一次比较结果存储到最高有效位(MSB，Most Significant Bit)，将比较器102的最后一次比较结果存储到最低有效位(LSB，Little SignificantBit)。
由上述步骤可得出，经过i次调整数模转换器101的输出电压Vadc后，数模转换器101调整输出电压的精度为VFS/2i，即输出电压Vadc与输入电压Vi的差值在VFS/2i内。例如，第一次调整后，输出电压Vadc与输入电压Vi的差值小于VFS/2，第二次调整后，输出电压Vadc与输入电压Vi的差值小于VFS/4，第三次调整后，输出电压Vadc与输入电压Vi的差值小于VFS/8，并依此类推。
可选地，所述满量程电压VFS为参考电压Vref。
可选地，所示逻辑电路103为移位寄存器(ShiftRegister)。
图1C为一种逐次逼近数模转换器的电路结构示意图。如图所示，其包括：数模转换器101，比较器102，逻辑电路103。数模转换器101包括第一电容阵列111、第一开关阵列121、第二电容阵列131和第二开关阵列141。
具体地，第一电容阵列111和第二电容阵列131分别连接比较器102的正向输入端和 反向输入端，以分别为比较器102提供第一比较电压和第二比较电压；逻辑电路103用于存储比较器102的比较结果，并根据所述比较结果控制第一开关阵列121和第二开关阵列141中开关的打开或闭合，以使第一比较电压的大小趋近于第二比较电压的大小，详细步骤如下：
采样阶段
所述第一电容阵列111设置为将全部电容的下极板连接第一输入电压Vip，所述第一电容阵列111中全部电容的上极板连接共模电压Vcm，以对所述第一输入电压进行采样；以所述第一电容阵列111中的电容C1为例，电容C1的弧线一侧为下极板，C1的直线一侧为上极板。
具体地，第一输入电压Vip可以是正向输入电压，即将输入电压Vi作为第一输入电压Vip，以为比较器102的正向输入端提供第一比较电压。
具体地，所述采样阶段即为电容充电的阶段，第一电容阵列111的电荷量为：
(-Vip+Vcm)*(C1+C2+…+CM)
其中，M为所述第一电容阵列111中全部电容的个数，图1C中以M＝11为例。
所述第二电容阵列131设置为将全部电容的下极板连接第二输入电压Vin，所述第二电容阵列131中全部电容的上极板连接共模电压Vcm，以对所述第二输入电压进行采样；
具体地，第二输入电压Vin可以是反向输入电压，即将输入电压Vi作为第二输入电压Vin，以为比较器102的反向输入端提供第二比较电压，本阶段第一电容阵列111的电荷量为：
(-Vin+Vcm)*(C1+C2+…+CM)
其中，M为所述第一电容阵列111中全部电容的个数，图1C中以M＝11为例。
预转换阶段
所述第一电容阵列111进一步设置为将全部电容的上极板与共模电压Vcm断开，并将全部电容的下极板连接所述共模电压Vcm，所述第一电容阵列111中全部电容的上极板连接所述比较器102，为所述比较器提供第一比较电压。该第一比较电压可以是输入到比较器102正向输入端的电压。
所述第二电容阵列131进一步设置为将全部电容的上极板与共模电压Vcm断开，并将全部电容的下极板连接所述共模电压Vcm，所述第二电容阵列131中全部电容的上极板连接所述比较器102，为所述比较器提供第二比较电压。该第二比较电压可以是输入到比较器反向输入端的电压。
将所述第一比较电压与所述第二比较电压的比较结果作为存储到所述逻辑电路103的第一个标志位。可选地，第一个标志位为逻辑电路103中的最高有效位。
假设上极板的电压为Vx1，则此时第一电容阵列111的电荷量为：
(Vx1-Vcm)*(C1+C2+…+CM)
根据电荷守恒定律可得出以下等式：
(-Vip+Vcm)*(C1+C2+…+CM)＝(Vx1-Vcm)*(C1+C2+…+CM)
转换阶段
在转换阶段的第i次转换中，所述逻辑电路根据存储的第i个标志位控制所述第一电容阵列中的第i个电容的下极板与参考电压或接地电压连接，以使所述第一电容阵列输出的第一比较电压的大小趋近于第二比较电压的大小，所述i为小于所述全部电容个数的正整数；
具体地，在转换阶段的第i次转换过程中，第一电容阵列111中第i个电容之前电容(即第1至第i-1个电容，i＞1时有效)的下极板连接参考电压或接地电压，第i+1至第N个电容的下极板连接共模电压Vcm，第i+1至第N个电容的下极板处于断开状态，第1至第M个电容的上极板连接比较器102的正向输入端；第二电容阵列131中第i个电容之前电容(即第1至第i-1个电容，i＞1时有效)的下极板连接参考电压或接地电压，第i+1至第N个电容的下极板连接共模电压Vcm，第i+1至第N个电容的下极板处于断开状态，第1至第M个电容的上极板连接比较器102的反向输入端。
所述比较器102将所述第一比较电压和所述第二比较电压的比较结果存储至所述逻辑电路的第i+1个标志位，且当i+1等于所述第一电容阵列中全部电容个数时模数转换完成。
例如，在本阶段，所述比较器102进行第一次比较后，如果第一比较电压大于第二比较电压，则输出结果为1，此时下极板接Vgnd，假设上极板的电压为Vx2，则第一电容阵列111的电荷量为：
(Vx2-Vgnd)C1+(Vx2-Vcm)*(C2+…+CM)
根据电荷守恒定律可得出：
(-Vip+Vcm)*(C1+C2+…+CM)
＝(Vx2-Vgnd)C1+(Vx2-Vcm)*(C2+…+CM)
＝(Vx2-(Vcm-(Vref-Vgnd)/2))*C1+(Vx2-Vcm)*(C2+…+CM)
如果输出结果为0，此时下极板接Vref，假设上极板的电压为Vx2，则第一电容阵列 111的电荷量为：
(Vx2-Vref)C1+(Vx2-Vcm)*(C2+…+CM)
根据电荷守恒定律可得出：
(-Vip+Vcm)*(C1+C2+…+CM)
＝(Vx2-Vref)C1+(Vx2-Vcm)*(C2+…+CM)
＝(Vx2-(Vcm+(Vref-Vgnd)/2))*C1+(Vx2-Vcm)*(C2+…+CM)
将上述两个公式合并，即假设第一次比较后的输出结果为1时，变量D1＝1，输出结果为0时，D1＝-1，则有等式：
(-Vip+Vcm)*(C1+C2+…+CM)
＝(Vx2-(Vcm-D1(Vref-Vgnd)/2))*C1+(Vx2-Vcm)*(C2+…+CM)
依次类推，则在最后一次比较完成时，得到等式：
(-Vip+Vcm)*(C1+C2+…+CM)
＝(Vx-(Vcm-D1*(Vref-Vgnd)/2))*C1+(Vx-(Vcm-D2*(Vref-Vgnd)/2))*C2+…+(Vx-(Vcm-DM*(Vref-Vgnd)/2))*CM
逻辑电路103对第二电容阵列131的控制与上述对第一电容阵列111的控制为相反的，在此不再赘述。可获得以下等式：
(-Vin+Vcm)*(C1+C2+…+CM)
＝(Vy-(Vcm-D1*(Vref-Vgnd)/2))*C1+(Vy-(Vcm-D2*(Vref-Vgnd)/2))*C2+…+(Vy-(Vcm-DM*(Vref-Vgnd)/2))*CM
具体地，所述Vin可以是反向输入电压。
在最后一次比较完成时，比较器102两端的电压相等或在一定误差范围内，则Vx＝Vy，则可得到等式：
(Vip-Vin)＝-(D1*C1+D2*C2+…+DM*CM)*(Vref-Vgnd)/(C1+C2+…+CM)
由于D1～D11的取值为-1或者1，因此可得到Vip-Vin的取值范围：
-(Vref-Vgnd)<＝Vip-Vin<＝Vref-Vgnd
即Vip-Vin的取值范围为[-(Vref-Vgnd),Vref-Vgnd]。
图2为本申请实施例一种逐次逼近数模转换器的电路结构示意图，如图所示，所述电路包括数模转换器(图中未标示)，比较器202以及逻辑电路203，数模转换器包括第一电容阵列211和开关阵列221。
下面依照采样阶段、预转换阶段以及转换阶段的时序对本实施例的电路进行描述：
采样阶段
所述第一电容阵列211设置为将N个电容的下极板连接第一输入电压Vip，其它电容的下极板连接共模电压Vcm，所述第一电容阵列211中全部电容的上极板连接共模电压Vcm，以对所述第一输入电压进行采样，所述N为小于全部电容个数M的正整数。以图2为例，N＝8，M＝11。具体地，所述采样阶段即为电容充电的阶段，第一电容阵列211的电荷量为：
(-Vi+Vcm)*(C1+C2+…+CN)
预转换阶段
所述第一电容阵列211进一步设置为将全部电容的上极板与共模电压Vcm断开，并将全部电容的下极板连接所述共模电压Vcm，并将全部电容的上极板连接所述比较器202，为所述比较器提供第一比较电压；该第一比较电压可以是输入到比较器202正向输入端的电压。
具体地，所述比较器202的反向输入端连接共模电压Vcm。
所述比较器202将所述第一比较电压与所述第二比较电压的比较结果存储到所述逻辑电路203的第一个标志位。可选地，第一个标志位为逻辑电路103中的最高有效位。
假设上极板的电压为Vx1，第一电容阵列211中全部电容个数为M，则此时第一电容阵列211的电荷量为：
(Vx1-Vcm)*(C1+C2+…+CM)
根据电荷守恒定律可得出以下等式：
(-Vi+Vcm)*(C1+C2+…+CN)＝(Vx1-Vcm)*(C1+C2+…+CM)
转换阶段
在第i次转换中，所述逻辑电路根据存储的第i个标志位控制所述第一电容阵列中的第i个电容的下极板与参考电压或接地电压连接，以使所述第一电容阵列输出的第一比较电压的大小趋近于第二比较电压的大小，所述i为小于所述全部电容个数的正整数；
具体地，在转换阶段的第i次转换过程中，其它电容的状态具体为：第一电容阵列211中第i个电容之前电容(即第1至第i-1个电容，i＞1时有效)的下极板连接参考电压或接地电压，第i+1至第N个电容的下极板连接共模电压Vcm，第i+1至第N个电容的下极板处于断开状态，第1至第M个电容的上极板连接比较器102的正向输入端；第二电容阵列231中第i个电容之前电容(即第1至第i-1个电容，i＞1时有效)的下极板连接 参考电压或接地电压，第i+1至第N个电容的下极板连接共模电压Vcm，第i+1至第N个电容的下极板处于断开状态，第1至第M个电容的上极板连接比较器202的反向输入端。
所述比较器将所述第一比较电压和所述第二比较电压的比较结果存储至所述逻辑电路的第i+1个标志位，且当i+1等于所述第一电容阵列中全部电容个数时模数转换完成。
具体地，在本实施例中，所述逻辑电路中存储的标志位的取值为0或1，例如，如第i次比较时所述第一电压大于所述第二电压，则第i个标志位为1，如第i次比较时所述第一电压小于所述第二电压，则第i个标志位为0。
如第i个标志位为1，则将所述第一电容阵列311中的第i个电容的下极板与所述接地电压连接，并将所述第二电容阵列331中的第i个电容的下极板与所述参考电压连接。
具体地，在本实施例中，所述根据所述标志位控制所述第一电容阵列211中的第i个电容的下极板与参考电压或接地电压连接，以使所述第一比较电压的大小趋近于所述第二比较电压的大小包括：
如所述标志位为1，则将所述第一电容阵列211中的第i个电容的下极板与所述接地电压连接；
否则，将所述第一电容阵列211中的第i个电容的下极板与参考电压连接。
具体地，在本实施例中，所述比较器进一步设置为获得所述第一比较电压与所述第二比较电压的比较结果，并将所述比较结果作为标志位存储到所述逻辑电路的第i+1位包括：
如所述第一比较电压大于所述第二比较电压，则将所述比较结果设置为1，否则，将所述比较结果设置为0；
将所述比较结果作为标志位存储到所述逻辑电路的第i+1位。
具体地，在本实施例中，所述共模电压Vcm为所述参考电压Vref与所述接地电压Vgnd的均值，即Vcm＝(Vref+Vgnd)/2。
例如，在本阶段，所述比较器102进行第一次比较后，如果输出结果为1，假设上极板的电压为Vx2，下极板接Vgnd，则此时第一电容阵列211的电荷量为：
(Vx2-Vgnd)C1+(Vx2-Vcm)*(C2+…+CM)
根据电荷守恒定律可得出：
(-Vi+VCM)*(C1+C2+…+CN)
＝(Vx2-Vgnd)C1+(Vx2-Vcm)*(C2+…+CM)
＝(Vx2-(Vcm-(Vref-Vgnd)/2))*C1+(Vx2-Vcm)*(C2+…+CM)
如果输出结果为0，假设上极板的电压为Vx2，下极板接Vref，则此时第一电容阵列211的电荷量为：
(Vx2-Vref)C1+(Vx2-Vcm)*(C2+…+CM)
根据电荷守恒定律可得出：
(-Vi+Vcm)*(C1+C2+…+CN)
＝(Vx2-Vref)C1+(Vx2-Vcm)*(C2+…+CM)
＝(Vx2-(Vcm+(Vref-Vgnd)/2))*C1+(Vx2-Vcm)*(C2+…+CM)
将上述两个公式合并，即假设第一次比较后的输出结果为1时，变量D1＝1，输出结果为0时，D1＝-1，则有等式：
(-Vi+Vcm)*(C1+C2+…+CM)
＝(Vx2-(Vcm-D1(Vref-Vgnd)/2))*C1+(Vx2-Vcm)*(C2+…+CM)
依次类推，则在最后一次比较完成时，得到等式：
(-Vi+Vcm)*(C1+C2+…+CN)
＝(Vx-(Vcm-D1*(Vref-Vgnd)/2))*C1+(Vx-(Vcm-D2*(Vref-Vgnd)/2))*C2+…+(Vx-(Vcm-DM*(Vref-Vgnd)/2))*CM
在最后一次比较完成时，比较器202两端的电压相等或在一定误差范围内，则可判定为Vx＝Vcm，则可得到等式：
(-Vi+Vcm)*(C1+C2+…+CN)
＝(Vref-Vgnd)/2))*(D1*C1+D2*C2+…+DM*CM)
化简后得到等式:
Figure PCTCN2017078801-appb-000001
由于D1～DN的取值为-1或者1，当D1～DN的取值全部为1时，Vi取最小值为:
Figure PCTCN2017078801-appb-000002
由于N<M，且(C1+C2+…+CM)/(C1+C2+…+CN)大于1，可得知Vi的最小值小于Vgnd。
当D1～DN的取值全部为-1时，Vi取最大值为：
Figure PCTCN2017078801-appb-000003
由于N<M，(C1+C2+…+CM)/(C1+C2+…+CN)大于1，可得知Vi的最大值大于Vref。
由此可得知，Vi的取值范围大于[Vgnd,Vref]，即ADC的动态范围已扩大。
具体地，在本实施例中，所述逻辑电路为移位寄存器。
具体地，在本实施例中，所述N的取值根据所述第一输入电压的取值范围设定。例如，当参考电压Vref固定、电容阵列中电容的总个数固定时，N的取值越大，第一输入电压的取值范围越小，反之则第一输入电压的取值范围越大，N可根据实际应用进行设置，在所述转换阶段，N的值不变。
具体地，在本实施例中，从所述第一电容阵列211全部电容(M个电容)中选择出的所述N个电容可以是不连续的。
具体地，在本实施例中，在转换阶段的第i次转换时，可从所述第一电容阵列211中下极板连接共模电压Vcm的电容(N个电容中未进行转换的电容)中随机选择一电容进行转换。
具体地，在本实施例中，所述第一电容阵列211中的每个电容由若干个电容单元(capacitor cell)串联或并联形成，每个电容对应的电容单元呈二进制排布或非二进制排布。例如，上述实施例中电容C1可由25(即32)个电容单元并联形成，全部的电容单元呈二进制排布，可使用二叉搜索(Binary Search)的方法快完成模数转换，其具有操作快捷、效率高等优点。再例如，上述实施例中电容C1可由31个电容单元并联形成，全部的电容单元呈非二进制排布，在对电容单元操作时，逐一对电容单元进行操作，其具有容错性好、功耗低等优点，例如，当比较器某一位输出错误时，可通过对后面的电容单元进行调整，以确保模数转换结果的正确性。
具体地，本申请实施例可应用于单端ADC。
本申请实施例可在不改变参考电压大小的情况下，扩大了第一输入电压的取值范围，即扩大了ADC的动态范围。
图3为一种逐次逼近数模转换器的电路结构示意图。如图所示，其包括：数模转换器301，比较器302，逻辑电路303。数模转换器301包括第一电容阵列311、第一开关阵列321、第二电容阵列331和第二开关阵列341。
采样阶段
所述第一电容阵列311设置为将N个电容的下极板连接第一输入电压Vip，其它电容的下极板连接共模电压Vcm，所述第一电容阵列311中全部电容的上极板连接共模电压Vcm，以对所述第一输入电压进行采样，所述N为小于全部电容个数M的正整数。以图 3为例，N＝8，M＝11。具体地，所述采样阶段即为电容充电的阶段，第一电容阵列311的电荷量为：
(-Vip+Vcm)*(C1+C2+…+CN)
所述第二电容阵列331进一步设置为将N个电容的下极板连接第二输入电压Vin，其它电容的下极板连接共模电压Vcm，所述第二电容阵列331中全部电容的上极板连接共模电压Vcm，以对所述第二输入电压进行采样；
具体地，在本实施例中，第一输入电压Vip与第二输入电压的差值可对应于图1A对应实施例中的输入电压Vi，即Vi＝Vip-Vin。
采样阶段第二电容阵列311的电荷量为：
(-Vin+Vcm)*(C1+C2+…+CN)
预转换阶段
所述第一电容阵列311进一步设置为将全部电容的上极板与共模电压Vcm断开，并将全部电容的下极板连接所述共模电压Vcm，所述第一电容阵列311中全部电容的上极板连接所述比较器302，以为所述比较器提供第一比较电压；该第一比较电压可以是输入到比较器302正向输入端的电压。
所述第二电容阵列331进一步设置为将全部电容的上极板与共模电压Vcm断开，并将全部电容的下极板连接所述共模电压Vcm，所述第二电容阵列331中全部电容的上极板连接所述比较器302，为所述比较器提供第二比较电压。该第二比较电压可以是输入到比较器302反向输入端的电压。
本实施例中，将所述第一比较电压与所述第二比较电压的比较结果作为存储到所述逻辑电路303的第一个标志位。可选地，第一个标志位为逻辑电路103中的最高有效位。
假设上极板的电压为Vx1，第一电容阵列311中全部电容个数为M，则此时第一电容阵列311的电荷量为：
(Vx1-Vcm)*(C1+C2+…+CM)
根据电荷守恒定律可得出以下等式：
(-Vip+Vcm)*(C1+C2+…+CN)＝(Vx1-Vcm)*(C1+C2+…+CM)
转换阶段
在转换阶段的第i次转换中，所述逻辑电路303根据存储的第i个标志位控制所述第一电容阵列311中的第i个电容的下极板与参考电压或接地电压连接，以使所述第一电容阵列311输出的第一比较电压的大小趋近于第二比较电压的大小，所述i为小于所述全部 电容个数的正整数；
进一步地，所述逻辑电路根据存储的第i个标志位控制所述第二电容阵列331中的第i个电容的下极板与参考电压或接地电压连接，以使所述第二电容阵列331输出的第二比较电压的大小趋近于第一比较电压的大小。
具体地，在本实施例中，所述逻辑电路中存储的标志位的取值为0或1，例如，如第i次比较时所述第一比较电压大于所述第二比较电压，则第i个标志位为1，如第i次比较时所述第一比较电压小于所述第二比较电压，则第i个标志位为0。
如第i个标志位为1，则将所述第一电容阵列311中的第i个电容的下极板与所述接地电压连接，并将所述第二电容阵列331中的第i个电容的下极板与所述参考电压连接；如第i个标志位为0，则将所述第一电容阵列311中的第i个电容的下极板与所述参考电压连接，并将所述第二电容阵列331中的第i个电容的下极板与所述接地电压连接。
应当理解的是，本实施例中以上对标识位的取值为0或1，并根据所述标识位控制第一电容阵列311和第二电容阵列331中电容的连接关系的描述是以说明本申请的一般原则为目的，并非用于限定本申请的范围。在其他一些实施例中，其中一个电容阵列可获得将标志位取反后的值，并根据所述取反后的值控制该电容阵列中电容的连接关系，例如，第二电容阵列331获得对所述标识位取反后的值，当第i个标识位取反后的值为1时，将所述第二电容阵列331中的第i个电容的下极板与所述接地电压连接，当第i个标识位为0时，将所述第二电容阵列331中的第i个电容的下极板与所述参考电压连接。
具体地，在转换阶段的第i次转换中，其它电容的状态具体为：第一电容阵列311中第i个电容之前电容(即第1至第i-1个电容，i＞1时有效)的下极板连接参考电压或接地电压，第i+1至第N个电容的下极板连接共模电压Vcm，第i+1至第N个电容的下极板处于断开状态，第1至第M个电容的上极板连接比较器102的正向输入端；第二电容阵列331中第i个电容之前电容(即第1至第i-1个电容，i＞1时有效)的下极板连接参考电压或接地电压，第i+1至第N个电容的下极板连接共模电压Vcm，第i+1至第N个电容的下极板处于断开状态，第1至第M个电容的上极板连接比较器302的反向输入端。
所述比较器将所述第一比较电压和所述第二比较电压的比较结果存储至所述逻辑电路的第i+1个标志位，且当i+1等于所述第一电容阵列中全部电容个数时模数转换完成。
与图2对应实施例的公式推导过程类似，在最后一次比较完成时，根据第一电容阵列上的电荷守恒，可获得等式：
(-Vip+Vcm)*(C1+C2+…+CN)
＝(Vx-(Vcm-D1*(Vref-Vgnd)/2))*C1+(Vx-(Vcm-D2*(Vref-Vgnd)/2))*C2+…+(Vx-(Vcm-DM*(Vref-Vgnd)/2))*CM
根据第二电容阵列上的电荷守恒，可获得等式：
(-Vin+Vcm)*(C1+C2+…+CN)
＝(Vy-(Vcm-D1*(Vref-Vgnd)/2))*C1+(Vy-(Vcm-D2*(Vref-Vgnd)/2))*C2+…+(Vy-(Vcm-DM*(Vref-Vgnd)/2))*CM
可选地，所述Vip为正向输入电压，所述Vin为反向输入电压。
在最后一次比较完成时，比较器302两端的电压相等或在一定误差范围内，则Vx＝Vy，则可得到等式：
(Vip-Vin)＝-(D1*C1+D2*C2+…+DN*CN)*(Vref-Vgnd)/(C1+C2+…+CM)
由于D1～DN的取值为-1或者1，当D1～DN的取值全部为1时，(Vip-Vin)取最小值为-(C1+C2+…+CN)*(Vref-Vgnd)/(C1+C2+…+CM)。
由于N<M，可得知(Vip-Vin)的最小值小于-(Vref-Vgnd)。
当D1～DN的取值全部为-1时，(Vip-Vin)取最大值(C1+C2+…+CN)*(Vref-Vgnd)/(C1+C2+…+CM)。
由于N<M，可得知(Vip-Vin)的最大值大于(Vref-Vgnd)。
由此可得知，Vip-Vin的取值范围大于[-(Vref-Vgnd),Vref-Vgnd]，即ADC的动态范围已扩大。
具体地，本申请实施例可应用于差分ADC。
本申请实施例可在不改变参考电压大小的情况下，扩大了第一输入电压的取值范围，即扩大了ADC的动态范围；并且本申请实施例电路结构简单，不需添加额外开关，易于实现。
图4为一种逐次逼近数模转换器的电路结构示意图。如图所示，其包括：数模转换器401，比较器402，逻辑电路403。数模转换器401包括第一电容阵列411、第二电容阵列421。
第一电容阵列411中电容的大小分别为：C1＝4C，C2＝2C，C3＝1C，C4＝1C，第二电容阵列421中电容大小分别与第一电容阵列411中电容大小相同，分别为：C1＝4C，C2＝2C，C3＝1C，C4＝1C。假设参考电压Vref取值为1.8V，接地电压Vgnd取值为0.2V，共模电 压Vcm取值为1V，第一输入电压Vip取值为1.9V，第二输入电压取值为0.1V。
采样阶段
对第一电容阵列411中的C1、C2进行采样，C3、C4不参与采样，即C1、C2的下极板连接第一输入电压Vip，C3、C4的下极板连接共模电压Vcm，C1、C2、C3和C4的上极板连接共模电压Vcm，则第一电容阵列411的电荷量为：
(-Vip+Vcm)(C1+C2)＝(-1.9+1)*6C＝-0.9*6C
对第一电容阵列411中的C1+C2进行采样，C3、C4不参与采样，即C1+C2的下极板连接第一输入电压Vip，C3、C4的下极板连接共模电压Vcm，C1、C2、C3和C4的上极板连接共模电压Vcm，，则第二电容阵列421的电荷量为：
(-Vin+Vcm)(C1+C2)＝(-0.1+1)*6C＝0.9*6C
预转换阶段
第一电容阵列411中，将C1、C2、C3和C4的上极板与共模电压Vcm断开，将C1、C2、C3和C4的下极板连接共模电压Vcm，并将C1、C2、C3和C4的上极板连接比较器402的正向比较端。假设比较器402的正向比较端的输入电压为Vx1，根据电荷守恒得到：
(-Vip+Vcm)(C1+C2)＝(Vx1-Vcm)*(C1+C2+C3+C4)
解得Vx1＝0.325V。
第二电容阵列421中，将C1、C2、C3和C4的上极板与共模电压Vcm断开，将C1、C2、C3和C4的下极板连接共模电压Vcm，并将C1、C2、C3和C4的上极板连接比较器402的负向比较端。假设比较器402的负向比较端的输入电压为Vy1，根据电荷守恒得到：
(-Vin+Vcm)(C1+C2)＝(Vy1-Vcm)*(C1+C2+C3+C4)
解得Vy1＝1.625V。
由于Vx1<Vy1，比较器402输出0，并将0存储到逻辑电路403的第1个标识位。
转换阶段
第1次转换中，由于逻辑电路403中第1个标识位为0，第一电容阵列411中的第1个电容C1的下极板连接参考电压Vref，第二电容阵列421中的第1个电容C1的下极板连接接地电压Vgnd。假设比较器402的正向比较端的输入电压为Vx2，根据电荷守恒得到：
(-Vip+Vcm)(C1+C2)＝(Vx2-Vref)*C1+(Vx2-Vcm)*(C2+C3+C4)
解得Vx2＝0.725V。
假设比较器402的正向比较端的输入电压为Vy2，根据电荷守恒得到：
(-Vin+Vcm)(C1+C2)＝(Vy2-Vgnd)*C1+(Vy2-Vcm)*(C2+C3+C4)
解得Vy2＝1.125V。
由于Vx2<Vy2，比较器402输出0，并将0存储到逻辑电路403的第2个标识位。
第2次转换中，由于逻辑电路403中第2个标识位为0，第一电容阵列411中的第2个电容C2的下极板连接参考电压Vref，第二电容阵列421中的第2个电容C2的下极板连接接地电压Vgnd。假设比较器402的正向比较端的输入电压为Vx3，根据电荷守恒得到：
(-Vip+Vcm)(C1+C2)＝(Vx3-Vref)*(C1+C2)+(Vx3-Vcm)*(C3+C4)
解得Vx3＝0.925V。
假设比较器402的正向比较端的输入电压为Vy3，根据电荷守恒得到：
(-Vin+Vcm)(C1+C2)＝(Vy3-Vgnd)*(C1+C2)+(Vy3-Vcm)*(C3+C4)
解得Vy3＝1.025V。
由于Vx3<Vy3，比较器402输出0，并将0存储到逻辑电路403的第3个标识位。
第3次转换中，由于逻辑电路403中第3个标识位为0，第一电容阵列411中的第3个电容C3的下极板连接参考电压Vref，第二电容阵列421中的第3个电容C3的下极板连接接地电压Vgnd。假设比较器402的正向比较端的输入电压为Vx4，根据电荷守恒得到：
(-Vip+Vcm)(C1+C2)＝(Vx4-Vref)*(C1+C2+C3)+(Vx4-Vcm)*(C4)
解得Vx4＝1.025V。
假设比较器402的正向比较端的输入电压为Vy4，根据电荷守恒得到：
(-Vin+Vcm)(C1+C2)＝(Vy4-Vgnd)*(C1+C2+C3)+(Vy3-Vcm)*(C4)
解得Vy4＝0.925V。
由于Vx4>Vy4，比较器402输出1，并将1存储到逻辑电路403的第4个标识位。
此时，4位全差分SAR ADC转换完成，输出信号为0001。
图5为一种逐次逼近数模转换方法的流程示意图。如图所示，所述方法包括：
S501、在采样阶段，所述第一电容阵列将N个电容的下极板连接第一输入电压，其它电容的下极板连接共模电压，并将全部电容的上极板连接共模电压，以对所述第一输入电压进行采样，所述N为小于全部电容个数的正整数；
S502、在转换阶段的第i次转换中，所述逻辑电路根据存储的第i个标志位控制所述 第一电容阵列中的第i个电容的下极板与参考电压连接接地电压，以使所述第一电容阵列输出的第一比较电压的大小趋近于所述比较器的第二比较电压的大小，所述i为小于所述全部电容个数的正整数；
S503、所述比较器将所述第一比较电压和所述第二比较电压的比较结果存储至所述逻辑电路的第i+1个标志位，且当i+1等于所述第一电容阵列中全部电容个数时模数转换完成。
执行本实施例方法的可以是图2对应实施例的电路，具体步骤与其类似，在此不再赘述。
图6为一种逐次逼近数模转换方法的流程示意图。如图所示，所述方法还包括：
S602、在预转换阶段，所述第一电容阵列将全部电容的下极板连接所述共模电压，并将全部电容的上极板连接所述比较器，为所述比较器提供第一比较电压；
S603、所述比较器将所述第一比较电压与所述第二比较电压的比较结果存储到所述逻辑电路的第一个标志位。
S601、S604、S605分别类似图5对应实施例中的S501、S502、S503，在此不再赘述。
执行本实施例方法的可以是图2对应实施例的电路，具体步骤与其类似，在此不再赘述。
图7为一种逐次逼近数模转换方法的流程示意图。如图所示，所述方法还包括：
S703、在采样阶段，第二电容阵列将N个电容的下极板连接第二输入电压，并将全部电容的上极板连接共模电压，以对所述第二输入电压进行采样，所述N个电容与所述第一阵列中的N个电容相对应；
S704、在转换阶段的第i次转换中，所述逻辑电路根据存储的第i个标志位控制所述第二电容阵列中的第i个电容的下极板与参考电压或接地电压连接，以使所述第二比较电压的大小趋近于所述第一比较电压的大小。
S701、S702、S705分别类似图5对应实施例中的S501、S502、S503，在此不再赘述。
执行本实施例方法的可以是图3对应实施例的电路，具体步骤与其类似，在此不再赘述。
本领域的技术人员应明白，本申请实施例的实施例可提供为方法、装置(设备)、或计算机程序产品。因此，本申请实施例可采用完全硬件实施例、完全软件实施例、或结合软 件和硬件方面的实施例的形式。而且，本申请实施例可采用在一个或多个其中包含有计算机可用程序代码的计算机可用存储介质(包括但不限于磁盘存储器、CD-ROM、光学存储器等)上实施的计算机程序产品的形式。
本申请实施例是参照根据本申请实施例的方法、装置(设备)和计算机程序产品的流程图和/或方框图来描述的。应理解可由计算机程序指令实现流程图和/或方框图中的每一流程和/或方框、以及流程图和/或方框图中的流程和/或方框的结合。可提供这些计算机程序指令到通用计算机、专用计算机、嵌入式处理机或其它可编程数据处理设备的处理器以产生一个机器，使得通过计算机或其它可编程数据处理设备的处理器执行的指令产生用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的装置。
这些计算机程序指令也可存储在能引导计算机或其它可编程数据处理设备以特定方式工作的计算机可读存储器中，使得存储在该计算机可读存储器中的指令产生包括指令装置的制造品，该指令装置实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能。
这些计算机程序指令也可装载到计算机或其它可编程数据处理设备上，使得在计算机或其它可编程设备上执行一系列操作步骤以产生计算机实现的处理，从而在计算机或其它可编程设备上执行的指令提供用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的步骤。
尽管已描述了本申请实施例的优选实施例，但本领域内的技术人员一旦得知了基本创造性概念，则可对这些实施例作出另外的变更和修改。所以，所附权利要求意欲解释为包括优选实施例以及落入本申请实施例范围的所有变更和修改。显然，本领域的技术人员可以对本申请实施例进行各种改动和变型而不脱离本申请实施例的精神和范围。这样，倘若本申请实施例的这些修改和变型属于本申请实施例权利要求及其等同技术的范围之内，则本申请实施例也意图包含这些改动和变型在内。

Claims (16)

  1. 一种模数转换电路，包括第一电容阵列、逻辑电路和比较器，其特征在于：
    在采样阶段，所述第一电容阵列将N个电容的下极板连接第一输入电压，其它电容的下极板连接共模电压，并将全部电容的上极板连接共模电压，以对所述第一输入电压进行采样，所述N为小于全部电容个数的正整数；
    在转换阶段的第i次转换中，所述逻辑电路根据存储的第i个标志位控制所述第一电容阵列中的第i个电容的下极板连接参考电压或接地电压，以使所述第一电容阵列输出的第一比较电压的大小趋近于第二比较电压的大小，所述i为小于所述全部电容个数的正整数；
    所述比较器将所述第一比较电压和所述第二比较电压的比较结果存储至所述逻辑电路的第i+1个标志位，且当i+1等于所述第一电容阵列中全部电容个数时模数转换完成。
  2. 根据权利要求1所述的电路，其特征在于，还包括：
    在预转换阶段，所述第一电容阵列将全部电容的下极板连接所述共模电压，并将全部电容的上极板连接所述比较器，为所述比较器提供第一比较电压,所述预转换阶段介于所述采样阶段和所述转换阶段的第一次转换之间；
    所述比较器将所述第一比较电压与所述第二比较电压的比较结果存储到所述逻辑电路的第一个标志位。
  3. 根据权利要求1所述的电路，其特征在于，所述比较器连接所述共模电压，以将所述共模电压作为第二比较电压。
  4. 根据权利要求1所述的电路，其特征在于，所述逻辑电路中存储的标志位的取值为0或1。
  5. 根据权利要求4所述的电路，其特征在于，所述逻辑电路根据存储的第i个标志位控制所述第一电容阵列中的第i个电容的下极板与参考电压或接地电压连接包括：
    如所述标志位为1，则将所述第一电容阵列中的第i个电容的下极板与所述接地电压连接；
    如所述标志位为0，则将所述第一电容阵列中的第i个电容的下极板与所述参考电压连接。
  6. 根据权利要求4所述的电路，其特征在于，所述比较器具体用于如所述第一比较电压大于所述第二比较电压，则将所述比较结果设置为1，否则，将所述比较结果设置为0。
  7. 根据权利要求1所述的电路，其特征在于，所述共模电压为所述参考电压与所述接地电压的均值。
  8. 根据权利要求1所述的电路，其特征在于，所述逻辑电路为移位寄存器。
  9. 根据权利要求1所述的电路，其特征在于，所述N的取值根据所述第一输入电压的取值范围设置。
  10. 根据权利要求1所述的电路，其特征在于，所述第一电容阵列为二进制排布电容阵列或非二进制排布电容阵列。
  11. 根据权利要求1所述的电路，还包括第二电容阵列，其特征在于：
    在采样阶段，所述第二电容阵列将N个电容的下极板连接第二输入电压，其它电容的下极板连接共模电压，并将全部电容的上极板连接共模电压，以对所述第二输入电压进行采样，所述N个电容与所述第一阵列中的N个电容相对应；
    在转换阶段的第i次转换中，所述逻辑电路根据存储的第i个标志位控制所述第二电容阵列中的第i个电容的下极板与参考电压或接地电压连接，以使所述第二比较电压的大小趋近于所述第一比较电压的大小。
  12. 根据权利要求11的电路，其特征在于，在预转换阶段，所述第二电容阵列将全部电容的下极板与所述共模电压连接，所述第二电容阵列中全部电容的上极板与所述比较器连接，以为所述比较器提供第二比较电压。
  13. 根据权利要求11的电路，其特征在于，所述所述逻辑电路根据存储的第i个标志位控制所述第二电容阵列中的第i个电容的下极板与参考电压或接地电压连接包括：
    如所述标志位为1，则将所述第二电容阵列中的第i个电容的下极板与所述参考电压连接；
    如所述标志位为0，则将所述第二电容阵列中的第i个电容的下极板与接地电压连接。
  14. 一种模数转换的方法，其特征在于，包括：
    在采样阶段，所述第一电容阵列将N个电容的下极板连接第一输入电压，其它电容的下极板连接共模电压，并将全部电容的上极板连接共模电压，以对所述第一输入电压进行采样，所述N为小于全部电容个数的正整数；
    在转换阶段的第i次转换中，所述逻辑电路根据存储的第i个标志位控制所述第一电容阵列中的第i个电容的下极板连接参考电压或接地电压，以使所述第一电容阵列输出的第一比较电压的大小趋近于所述比较器的第二比较电压的大小，所述i为小于所述全部电容个数的正整数；
    所述比较器将所述第一比较电压和所述第二比较电压的比较结果存储至所述逻辑电路的第i+1个标志位，且当i+1等于所述第一电容阵列中全部电容个数时模数转换完成。
  15. 根据权利要求14所述的方法，其特征在于，还包括：
    在预转换阶段，所述第一电容阵列将全部电容的下极板连接所述共模电压，并将全部电容的上极板连接所述比较器，为所述比较器提供第一比较电压；
    所述比较器将所述第一比较电压与所述第二比较电压的比较结果存储到所述逻辑电路的第一个标志位。
  16. 根据权利要求14所述的方法，其特征在于，还包括：
    在采样阶段，第二电容阵列将N个电容的下极板连接第二输入电压，其它电容的下极板连接共模电压，并将全部电容的上极板连接共模电压，以对所述第二输入电压进行采样，所述N个电容与所述第一阵列中的N个电容相对应；
    在转换阶段的第i次转换中，所述逻辑电路根据存储的第i个标志位控制所述第二电容阵列中的第i个电容的下极板连接参考电压或接地电压，以使所述第二比较电压的大小趋近于所述第一比较电压的大小。
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