[go: up one dir, main page]

WO2018163236A1 - Dispositif à semi-conducteur et procédé de fabrication de dispositif à semi-conducteur - Google Patents

Dispositif à semi-conducteur et procédé de fabrication de dispositif à semi-conducteur Download PDF

Info

Publication number
WO2018163236A1
WO2018163236A1 PCT/JP2017/008733 JP2017008733W WO2018163236A1 WO 2018163236 A1 WO2018163236 A1 WO 2018163236A1 JP 2017008733 W JP2017008733 W JP 2017008733W WO 2018163236 A1 WO2018163236 A1 WO 2018163236A1
Authority
WO
WIPO (PCT)
Prior art keywords
main surface
base electrode
region
semiconductor substrate
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2017/008733
Other languages
English (en)
Japanese (ja)
Inventor
晴久 齊藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Olympus Corp
Original Assignee
Olympus Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Olympus Corp filed Critical Olympus Corp
Priority to PCT/JP2017/008733 priority Critical patent/WO2018163236A1/fr
Publication of WO2018163236A1 publication Critical patent/WO2018163236A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F99/00—Subject matter not provided for in other groups of this subclass

Definitions

  • the present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.
  • imaging devices such as a CCD (Charge Coupled Devices) image sensor and a CMOS (Complementary Metal Oxide Semiconductor) image sensor
  • a front side illumination (FSI) type image sensor in which light is incident from the substrate surface side.
  • the image sensor includes a pixel circuit region including a pixel in which an element such as a photodiode is disposed and a peripheral circuit region in which a peripheral circuit is disposed.
  • circuits such as a vertical drive circuit, a horizontal drive circuit, a signal processing circuit, and an output circuit are arranged.
  • the signal processing circuit includes circuits such as a CDS (Correlated Double Sampling) circuit, an A / D conversion circuit, and an amplification circuit.
  • CDS Correlated Double Sampling
  • the signal processing circuit also includes a digital signal processing circuit. Further, in the peripheral circuit region, a light shielding film is formed so as to surround the pixel circuit region. The light shielding film in the peripheral circuit region serves to shield unnecessary light from being irradiated to the peripheral circuit region. As a result, the light shielding film in the peripheral circuit region prevents the electrical characteristics of the device such as a transistor in the peripheral circuit region from changing due to receiving unnecessary light. In the pixel circuit area, a light-shielding film having a lattice pattern for shielding light between the pixels is formed. The light shielding film in the pixel circuit area prevents crosstalk between the pixels. Further, color filters (R, G, B, etc.) and microlenses are two-dimensionally arranged in an array on the surface of the substrate. The color filter transmits light for each color, and the microlens efficiently collects light on the pixels.
  • BSI back side illumination
  • the light shielding film, the color filter, and the microlens are formed on the back side.
  • the stacked imager has a structure in which a photodiode substrate (PD substrate) and a readout substrate (RO substrate) are stacked in the vertical direction of each substrate with FtoF (Face to Face), and each substrate is electrically connected with a connection electrode.
  • PD substrate photodiode substrate
  • RO substrate readout substrate
  • a pixel region is disposed on the PD substrate.
  • a photodiode (PD) and a circuit for reading signal charges generated by photoelectric conversion by the PD are arranged.
  • a BSI image sensor is used for the PD substrate.
  • Circuits such as a vertical drive circuit, a horizontal drive circuit, a signal processing circuit, and an output circuit are arranged on the RO substrate.
  • FIG. 31 is an enlarged view of a part of the semiconductor device 1010.
  • the semiconductor device 1010 includes a first semiconductor substrate 1100, a second semiconductor substrate 1200, a connection layer 1300, a plurality of microlenses ML, and a plurality of color filters CF.
  • FIGS. 30 and 31 reference numerals of one microlens ML and one color filter CF are shown as representatives.
  • the first semiconductor substrate 1100 includes a first semiconductor layer 1110, a first wiring layer 1120, and a light shielding film 1130.
  • the first semiconductor layer 1110 and the first wiring layer 1120 are stacked in the direction Dr10.
  • the direction Dr10 is the thickness direction of the first semiconductor substrate 1100 and the second semiconductor substrate 1200.
  • the first semiconductor layer 1110 includes a plurality of photoelectric conversion elements 1111 and a plurality of first peripheral circuits 1112. In FIGS. 30 and 31, a symbol of one photoelectric conversion element 1111 is shown as a representative.
  • the photoelectric conversion element 1111 is disposed at the center of the first semiconductor layer 1110.
  • the photoelectric conversion element 1111 converts light incident on the photoelectric conversion element 1111 into a signal.
  • the first peripheral circuit 1112 is disposed in the peripheral portion of the first semiconductor layer 1110.
  • the light shielding film 1130 shields the first peripheral circuit 1112 from being irradiated with light.
  • the first wiring layer 1120 includes a plurality of first wirings 1121, a plurality of first vias 1122, and a first interlayer insulating film 1123.
  • FIG. 31 reference numerals of one first wiring 1121 and one first via 1122 are shown as representatives.
  • the first wiring 1121 transmits a signal generated by the photoelectric conversion element 1111.
  • the first via 1122 connects the first wirings 1121 of different layers.
  • portions other than the first wiring 1121 and the first via 1122 are configured by a first interlayer insulating film 1123.
  • the second semiconductor substrate 1200 includes a second wiring layer 1210 and a second semiconductor layer 1220.
  • the second wiring layer 1210 and the second semiconductor layer 1220 are stacked in the direction Dr10.
  • the second wiring layer 1210 has a plurality of second wirings 1211, a plurality of second vias 1212, and a second interlayer insulating film 1213.
  • FIG. 31 reference numerals of one second wiring 1211 and one second via 1212 are shown as representatives.
  • the second wiring 1211 transmits a signal output from the first semiconductor substrate 1100.
  • the second via 1212 connects the second wirings 1211 of different layers.
  • portions other than the second wiring 1211 and the second via 1212 are configured by the second interlayer insulating film 1213.
  • the second semiconductor layer 1220 includes a plurality of second peripheral circuits 1221.
  • the second peripheral circuit 1221 is disposed in the peripheral portion of the second semiconductor layer 1220.
  • connection layer 1300 is disposed between the first semiconductor substrate 1100 and the second semiconductor substrate 1200.
  • the connection layer 1300 includes a connection electrode 1310 and a resin layer 1330. In FIG. 31, a symbol of one connection electrode 1310 is shown as a representative.
  • the connection electrode 1310 includes a first base electrode 1311, a second base electrode 1312, and a bump electrode 1313.
  • the first base electrode 1311, the second base electrode 1312, and the bump electrode 1313 transfer a signal output from the first semiconductor substrate 1100 to the second semiconductor substrate 1200.
  • a portion other than the connection electrode 1310 is configured with a resin layer 1330.
  • the resin layer 1330 bonds the first semiconductor substrate 1100 and the second semiconductor substrate 1200.
  • the color filter CF is disposed so as to overlap a through hole provided in the light shielding film 1130.
  • the microlens ML is stacked on the color filter CF.
  • the structure of the second wiring 1211 having a plurality of layers is devised.
  • the second wiring 1211 of each layer is arranged so that the second wiring 1211 of one layer overlaps a portion where there is no pattern in the second wiring 1211 of the other layer.
  • the second wiring 1211 of one layer for light shielding is electrically insulated from the second wiring 1211 of other layers.
  • the second wiring 1211 for light shielding is electrically insulated from the second wiring 1211 for light shielding, and the other two It is difficult to form the second via 1212 that electrically connects the second wirings 1211 of the layers.
  • the semiconductor device 1010 is formed to have the structure shown in FIG.
  • FIG. 32 shows a cross section of the semiconductor device 1010 at the position indicated by line B10 in FIG.
  • the arrangement of each element when the second semiconductor substrate 1200 is viewed in the direction Dr10 perpendicular to the surface of the second semiconductor substrate 1200 is shown. That is, FIG. 32 shows an arrangement of elements when the second semiconductor substrate 1200 is viewed from the front of the second semiconductor substrate 1200. As shown in FIG. 32, the arrangement of elements in a cross section passing through the second wiring 1211 is shown.
  • the positions of the microlens ML and the photoelectric conversion element 1111 are indicated by broken lines.
  • reference numerals of one microlens ML and one photoelectric conversion element 1111 are shown.
  • FIG. 32 as a representative, reference numerals of one microlens ML and one photoelectric conversion element 1111 are shown. In FIG.
  • FIG. 32 a part of the photoelectric conversion element 1111 and a part of the microlens ML are omitted.
  • the position of the second peripheral circuit 1221 is indicated by a broken line.
  • Four second peripheral circuits 1221 are arranged.
  • the second wiring 1211 is arranged so as to surround the pixel circuit region. The second wiring 1211 overlaps the entire four second peripheral circuits 1221.
  • the second wiring 1211 except for the second wiring 1211 for light shielding needs to be electrically connected to the connection electrode 1310 in the pixel circuit region.
  • the second wiring 1211 for light shielding is electrically insulated from the second wiring 1211 and the connection electrode 1310 in other layers. It is difficult to form the second via 1212 that electrically connects the two. For this reason, the second wiring 1211 is not arranged in the pixel circuit region.
  • a manufacturing process of a wiring layer of a general semiconductor device includes a process of flattening each layer by using a chemical mechanical polishing, that is, a CMP (Chemical Mechanical Polishing) process.
  • a chemical mechanical polishing that is, a CMP (Chemical Mechanical Polishing) process.
  • the insulating layer is deposited after the second wiring 1211 is formed.
  • the surface of the insulating layer is planarized by CMP.
  • dishing or erosion occurs due to planarization. Dishing is a pattern dent that occurs after CMP. In this case, dishing occurs in the chip.
  • the thickness of the interlayer insulating film differs between the pixel circuit region and the peripheral circuit region. Alternatively, the thickness of the interlayer insulating film differs between chips.
  • FIG. 33 shows a cross section of the structure in the manufacturing process of the semiconductor device 1010.
  • FIG. 33 shows the structure after the second base electrode 1312 and the bump electrode 1313 are formed on the second wiring layer 1210.
  • the second wiring 1211 other than the second wiring 1211 for shielding light is not shown. Due to the influence of planarization by CMP, the thickness T10 of the second interlayer insulating film 1213 in the pixel circuit region is smaller than the thickness T11 of the second interlayer insulating film 1213 in the peripheral circuit region. As a result, a height difference H10 between the bump electrode 1313 in the pixel circuit region and the bump electrode 1313 in the peripheral circuit region occurs.
  • Patent Document 1 discloses a technique for ensuring flatness of an interlayer insulating film that has been flattened by CMP. Specifically, a technique is disclosed in which a dummy pattern is arranged in a region where there is no wiring pattern, thereby uniformizing the ratio of the area occupied by the pattern in each region.
  • the yield of electrical connection between the first semiconductor substrate 1100 and the second semiconductor substrate 1200 by the connection electrode 1310 in the pixel circuit region decreases.
  • the bump electrode 1313 is crushed by increasing the bonding load
  • distortion or cracks may occur in the bonded substrates.
  • it is difficult to arrange the second wiring 1211 in the pixel circuit region it is difficult to apply the technique disclosed in Patent Document 1 to the semiconductor device 1010. For the above reason, it is difficult to form a light-shielding film with the second wiring 1211.
  • Patent Document 2 discloses a technique for making the bump electrode height uniform by bite grinding in order to equalize the height difference H10 between the bump electrode 1313 in the pixel circuit region and the bump electrode 1313 in the peripheral circuit region. .
  • Patent Document 2 describes that the height position can be made uniform by cutting the tips of bumps with non-uniform heights with a cutting tool.
  • the bite cutting has a problem that a cutting residue called a burr is generated after the cutting or a bump is removed. This is not a problem for bumps having a size larger than 10 ⁇ m as mounted on a package.
  • a bump of 10 ⁇ m or less causes the above-described problem, and it is difficult to make the bump height position uniform.
  • a semiconductor device includes a first semiconductor substrate, a second semiconductor substrate, a first base electrode, a second base electrode, a first bump electrode, and a third base electrode. , A fourth base electrode, and a second bump electrode.
  • the first semiconductor substrate has a first main surface, a second main surface, a first region, and a second region. The first main surface and the second main surface face in opposite directions.
  • the first region includes a plurality of photoelectric conversion elements. When the first semiconductor substrate is viewed in a direction perpendicular to the first main surface, the second region surrounds the first region.
  • the second semiconductor substrate has a third main surface, a fourth main surface, a third region, and a fourth region.
  • the third main surface and the fourth main surface face in opposite directions.
  • the third main surface faces the second main surface.
  • the third region is opposite to the first region.
  • the fourth region includes a peripheral circuit.
  • the fourth region is opposite to the second region.
  • the fourth region surrounds the third region when the second semiconductor substrate is viewed in a direction perpendicular to the third main surface.
  • the first base electrode is disposed in the first region on the second main surface.
  • the second base electrode is disposed in the third region on the third main surface.
  • the first bump electrode is disposed between the first base electrode and the second base electrode.
  • the third base electrode is disposed in the second region on the second main surface.
  • the fourth base electrode is disposed in the fourth region on the third main surface, and the peripheral circuit when the second semiconductor substrate is viewed in a direction perpendicular to the third main surface. Overlapping with everything.
  • the second bump electrode is disposed between the third base electrode and the fourth base electrode.
  • the first semiconductor substrate has a first side surface connected to the first main surface and the second main surface. Also good.
  • the second semiconductor substrate may have a second side surface connected to the third main surface and the fourth main surface. The position of the end portion of the fourth base electrode may coincide with the second side surface.
  • only a part of the end portion of the fourth base electrode may coincide with the second side surface.
  • the position of only a part of the end portion of the third base electrode may coincide with the first side surface.
  • the position of the end of the third base electrode may coincide with the first side surface.
  • the first semiconductor substrate has a first side surface connected to the first main surface and the second main surface. Also good.
  • the second semiconductor substrate may have a second side surface connected to the third main surface and the fourth main surface. All of the end portions of the fourth base electrode may be separated from the second side surface.
  • all of the end portions of the third base electrode may be separated from the first side surface.
  • a method of manufacturing a semiconductor device having a first semiconductor substrate and a second semiconductor substrate includes a first step, a second step, a third step, and a fourth step. , 5th process, and 6th process.
  • the first semiconductor substrate has a first main surface, a second main surface, a first region, and a second region.
  • the first main surface and the second main surface face in opposite directions.
  • the first region includes a plurality of photoelectric conversion elements.
  • the second region surrounds the first region.
  • the second semiconductor substrate has a third main surface, a fourth main surface, a third region, and a fourth region.
  • the third main surface and the fourth main surface face in opposite directions.
  • the third main surface faces the second main surface.
  • the third region is opposite to the first region.
  • the fourth region includes a peripheral circuit.
  • the fourth region is opposite to the second region.
  • the fourth region surrounds the third region when the second semiconductor substrate is viewed in a direction perpendicular to the third main surface.
  • a first base electrode is formed in the first region on the second main surface, and a third base electrode is formed in the second region on the second main surface. Is done.
  • a second base electrode is formed in the third region on the third main surface, and a fourth base electrode is formed in the fourth region on the third main surface. Is done.
  • the fourth base electrode overlaps the entire peripheral circuit.
  • a first bump electrode is formed on one of the first base electrode and the second base electrode.
  • a second bump electrode is formed on any one of the third base electrode and the fourth base electrode.
  • the first bump electrode may be either the first base electrode or the second base electrode in a state where the third main surface is opposed to the second main surface.
  • the second bump electrode is connected to any one of the third base electrode and the fourth base electrode.
  • the first semiconductor substrate is thinned by cutting the first main surface.
  • the semiconductor device and the method for manufacturing the semiconductor device can reduce a decrease in the yield of electrical connection between the plurality of semiconductor substrates and can shield the peripheral circuits.
  • 1 is a cross-sectional view of a semiconductor device according to a first embodiment of the present invention.
  • 1 is a cross-sectional view of a semiconductor device according to a first embodiment of the present invention.
  • 1 is a cross-sectional view of a semiconductor device according to a first embodiment of the present invention.
  • 1 is a cross-sectional view of a semiconductor device according to a first embodiment of the present invention.
  • 1 is a cross-sectional view of a semiconductor device according to a first embodiment of the present invention. It is sectional drawing for demonstrating the manufacturing method of the semiconductor device of the 1st Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing method of the semiconductor device of the 1st Embodiment of this invention.
  • FIG. 1 and 2 show a configuration of the semiconductor device 10 according to the first embodiment of the present invention. 1 and 2, a cross section of the semiconductor device 10 is shown. FIG. 2 is an enlarged view of a part of the semiconductor device 10.
  • the dimensions of the parts constituting the semiconductor device 10 do not always follow the dimensions shown in FIGS.
  • the dimensions of the parts constituting the semiconductor device 10 may be arbitrary. The same applies to dimensions in other sectional views.
  • the semiconductor device 10 includes a first semiconductor substrate 100 and a second semiconductor substrate 200.
  • the first semiconductor substrate 100 has a first main surface 110a, a second main surface 120a, a first region A1, and a second region A2.
  • the first main surface 110a and the second main surface 120a face in opposite directions.
  • the first region A1 includes a plurality of photoelectric conversion elements 111.
  • the second region A2 surrounds the first region A1.
  • the second semiconductor substrate 200 has a third main surface 210a, a fourth main surface 220a, a third region A3, and a fourth region A4.
  • the third main surface 210a and the fourth main surface 220a face in opposite directions.
  • Third main surface 210a faces second main surface 120a.
  • the third area A3 faces the first area A1.
  • the fourth area A4 includes a second peripheral circuit 221.
  • the fourth area A4 is opposed to the second area A2.
  • the fourth region A4 surrounds the third region A3.
  • the semiconductor device 10 includes the first base electrode 311, the second base electrode 312, the first bump electrode 313, the third base electrode 321, the fourth base electrode 322, and the second bump electrode 323.
  • the first base electrode 311 is disposed in the first region A1 on the second main surface 120a.
  • the second base electrode 312 is disposed in the third region A3 on the third main surface 210a.
  • the first bump electrode 313 is disposed between the first base electrode 311 and the second base electrode 312.
  • the third base electrode 321 is disposed in the second region A2 on the second main surface 120a.
  • the fourth base electrode 322 is disposed in the fourth region A4 on the third main surface 210a.
  • the fourth base electrode 322 overlaps with all of the second peripheral circuits 221.
  • the second bump electrode 323 is disposed between the third base electrode 321 and the fourth base electrode 322.
  • the semiconductor device 10 includes a first semiconductor substrate 100, a second semiconductor substrate 200, a connection layer 300, a plurality of color filters CF, and a plurality of microlenses ML.
  • FIG. 1 and FIG. 2 reference numerals of one microlens ML and one color filter CF are shown as representatives.
  • the first semiconductor substrate 100 constitutes a BSI type image sensor.
  • the first semiconductor substrate 100 includes a first semiconductor layer 110, a first wiring layer 120, and a light shielding film 130.
  • the first semiconductor layer 110 and the first wiring layer 120 are stacked in the direction Dr1.
  • the direction Dr1 is the thickness direction of the first semiconductor substrate 100 and the second semiconductor substrate 200.
  • the direction Dr1 is a direction perpendicular to the first main surface 110a, the second main surface 120a, the third main surface 210a, and the fourth main surface 220a.
  • the first semiconductor layer 110 and the first wiring layer 120 are in contact with each other.
  • the first main surface 110 a and the second main surface 120 a are relatively wide surfaces among a plurality of surfaces constituting the surface of the first semiconductor substrate 100.
  • the first region A1 includes the center of the first semiconductor substrate 100.
  • the first area A1 constitutes a pixel circuit area including pixels.
  • the second area A2 is arranged around the first area A1.
  • the second area A2 constitutes a peripheral circuit area.
  • region A2 contain a part of 1st main surface 110a and 2nd main surface 120a.
  • the first semiconductor layer 110 is made of a semiconductor material.
  • the semiconductor material is at least one of silicon (Si) and germanium (Ge).
  • the first semiconductor layer 110 has a first main surface 110a.
  • the first semiconductor layer 110 includes a plurality of photoelectric conversion elements 111 (photodiodes) and a plurality of first peripheral circuits 112.
  • symbol of one photoelectric conversion element 111 is shown as a representative.
  • the photoelectric conversion element 111 constitutes a pixel.
  • the photoelectric conversion element 111 is disposed in the first region A1.
  • the photoelectric conversion element 111 is formed using a semiconductor material having an impurity concentration different from that of the semiconductor material forming the first semiconductor layer 110.
  • the photoelectric conversion element 111 converts light incident on the photoelectric conversion element 111 into a signal.
  • the first peripheral circuit 112 is a circuit such as a vertical drive circuit, a horizontal drive circuit, a signal processing circuit, and an output circuit.
  • the signal processing circuit may include circuits such as a CDS circuit, an A / D conversion circuit, and an amplifier circuit.
  • the signal processing circuit may also include a digital signal processing circuit.
  • the first peripheral circuit 112 is disposed in the second region A2.
  • the first wiring layer 120 is laminated with respect to the first semiconductor layer 110 in the direction Dr1.
  • the first wiring layer 120 has a second main surface 120a.
  • the second main surface 120a is in contact with the connection layer 300.
  • the first main surface 110a and the second main surface 120a face in opposite directions.
  • the first wiring layer 120 includes a plurality of first wirings 121, a plurality of first vias 122, and a first interlayer insulating film 123.
  • first wiring 121 and first via 122 are shown as representatives.
  • the first wiring 121 and the first via 122 are made of a first conductive material.
  • the first conductive material is a metal such as aluminum (Al) and copper (Cu).
  • the first wiring 121 and the first via 122 may be made of different conductive materials.
  • the first wiring 121 is a thin film on which a wiring pattern is formed.
  • the first wiring 121 transmits a signal generated by the photoelectric conversion element 111. Only one layer of the first wiring 121 may be disposed, or a plurality of layers of the first wiring 121 may be disposed. In the example shown in FIGS. 1 and 2, three layers of first wirings 121 are arranged.
  • the first via 122 connects the first wirings 121 of different layers.
  • portions other than the first wiring 121 and the first via 122 are constituted by the first interlayer insulating film 123.
  • the first interlayer insulating film 123 is made of an insulating material.
  • the insulating material is silicon dioxide (SiO2).
  • the light shielding film 130 is disposed on the first main surface 110a.
  • the light shielding film 130 is disposed at least in the second region A2. 1 and 2, the light shielding film 130 is also disposed in the first region A1.
  • the light shielding film 130 is a thin film.
  • the portion of the light shielding film 130 disposed in the first region A1 has a through hole.
  • the light shielding film 130 is made of a light shielding material.
  • the light shielding film 130 is made of metal such as copper (Cu), aluminum (Al), and tungsten (W).
  • the first semiconductor substrate 100 is viewed in the direction Dr1 perpendicular to the first major surface 110a, the light shielding film 130 overlaps all of the first peripheral circuits 112.
  • the light shielding film 130 shields the first peripheral circuit 112 from being irradiated with light.
  • the first semiconductor substrate 100 has two layers.
  • the first semiconductor substrate 100 may have only one layer.
  • the first semiconductor substrate 100 may have three or more layers.
  • the second semiconductor substrate 200 has a second wiring layer 210 and a second semiconductor layer 220.
  • the second wiring layer 210 and the second semiconductor layer 220 are stacked in the direction Dr1.
  • the second wiring layer 210 and the second semiconductor layer 220 are in contact with each other.
  • the third main surface 210 a and the fourth main surface 220 a are relatively wide surfaces among a plurality of surfaces constituting the surface of the second semiconductor substrate 200.
  • the third region A3 includes the center of the second semiconductor substrate 200.
  • the third area A3 constitutes a pixel circuit area.
  • the fourth area A4 is arranged around the third area A3.
  • the fourth area A4 constitutes a peripheral circuit area.
  • Third region A3 and fourth region A4 include a part of first main surface 110a and second main surface 120a.
  • the second wiring layer 210 has a third main surface 210a.
  • the third major surface 210 a is in contact with the connection layer 300.
  • the second wiring layer 210 includes a plurality of second wirings 211, a plurality of second vias 212, and a second interlayer insulating film 213.
  • reference numerals of one second wiring 211 and one second via 212 are shown as representatives.
  • the second wiring 211 and the second via 212 are made of a first conductive material.
  • the second wiring 211 and the second via 212 may be made of different conductive materials.
  • the second wiring 211 is a thin film on which a wiring pattern is formed.
  • the second wiring 211 transmits a signal output from the first semiconductor substrate 100. Only one layer of the second wiring 211 may be arranged, or a plurality of layers of the second wiring 211 may be arranged. In the example shown in FIGS. 1 and 2, three layers of second wirings 211 are arranged.
  • the second via 212 connects the second wiring 211 of a different layer.
  • portions other than the second wiring 211 and the second via 212 are configured by the second interlayer insulating film 213.
  • the second interlayer insulating film 213 is made of an insulating material.
  • the second semiconductor layer 220 is stacked in the direction Dr1 with respect to the second wiring layer 210.
  • the second semiconductor layer 220 is made of a semiconductor material.
  • the second semiconductor layer 220 has a fourth major surface 220a.
  • the third main surface 210a and the fourth main surface 220a face in opposite directions.
  • the second semiconductor layer 220 includes a plurality of second peripheral circuits 221.
  • the second peripheral circuit 221 is a circuit such as a vertical drive circuit, a horizontal drive circuit, a signal processing circuit, and an output circuit.
  • the second peripheral circuit 221 is disposed in the fourth area A4.
  • the second semiconductor substrate 200 has two layers.
  • the second semiconductor substrate 200 may have only one layer.
  • the second semiconductor substrate 200 may have three or more layers.
  • connection layer 300 is disposed between the first semiconductor substrate 100 and the second semiconductor substrate 200.
  • the connection layer 300 includes a first connection electrode 310, a second connection electrode 320, and a resin layer 330.
  • reference numerals of one first connection electrode 310 and one second connection electrode 320 are shown as representatives.
  • the first connection electrode 310 is disposed between the first region A1 and the third region A3.
  • the first connection electrode 310 includes a first base electrode 311, a second base electrode 312, and a first bump electrode 313.
  • the first base electrode 311, the second base electrode 312, and the first bump electrode 313 are made of a second conductive material.
  • the second conductive material is a metal such as gold (Au), aluminum (Al), and copper (Cu).
  • the first base electrode 311 and the second base electrode 312 are thin films.
  • the first base electrode 311 is in contact with the first via 122 on the second main surface 120a. For this reason, the first base electrode 311 is electrically connected to the first semiconductor substrate 100.
  • the second base electrode 312 is in contact with the second via 212 on the third main surface 210a. For this reason, the second base electrode 312 is electrically connected to the second semiconductor substrate 200.
  • the first bump electrode 313 is columnar or spherical.
  • the first bump electrode 313 is disposed between the first base electrode 311 and the second base electrode 312.
  • the first bump electrode 313 is in contact with the first base electrode 311 and the second base electrode 312.
  • the first base electrode 311, the second base electrode 312, and the first bump electrode 313 electrically connect the first semiconductor substrate 100 and the second semiconductor substrate 200.
  • the first base electrode 311, the second base electrode 312, and the first bump electrode 313 transfer a signal output from the first semiconductor substrate 100 to the second semiconductor substrate 200.
  • the second connection electrode 320 is disposed between the second region A2 and the fourth region A4.
  • the second connection electrode 320 includes a third base electrode 321, a fourth base electrode 322, and a second bump electrode 323.
  • the third base electrode 321, the fourth base electrode 322, and the second bump electrode 323 are made of a second conductive material.
  • the third base electrode 321 and the fourth base electrode 322 are thin films.
  • the third base electrode 321 does not contact the first via 122 on the second main surface 120a. For this reason, the third base electrode 321 is electrically insulated from the first semiconductor substrate 100.
  • the fourth base electrode 322 does not contact the second via 212 on the third main surface 210a. For this reason, the fourth base electrode 322 is electrically insulated from the second semiconductor substrate 200.
  • the area of the fourth base electrode 322 is larger than the sum of the areas of the plurality of third base electrodes 321. .
  • the second bump electrode 323 is columnar or spherical.
  • the second bump electrode 323 is disposed between the third base electrode 321 and the fourth base electrode 322.
  • the second bump electrode 323 is in contact with the third base electrode 321 and the fourth base electrode 322.
  • the fourth base electrode 322 shields the second peripheral circuit 221 from being irradiated with light.
  • the third base electrode 321, the fourth base electrode 322, and the second bump electrode 323 are set to be electrically floating. At least one of the third base electrode 321 and the fourth base electrode 322 may be connected to the ground. For example, at least one of the third base electrode 321 and the fourth base electrode 322 may be connected to a ground pad electrode.
  • the pad electrode is an electrode for connecting the semiconductor device 10 and an external package. When at least one of the first wiring 121 and the second wiring 211 includes a ground wiring, at least one of the third base electrode 321 and the fourth base electrode 322 may be connected to the ground wiring.
  • connection layer 300 a portion other than the first connection electrode 310 and the second connection electrode 320 is constituted by a resin layer 330.
  • the resin layer 330 is made of a resin material.
  • the resin layer 330 bonds the first semiconductor substrate 100 and the second semiconductor substrate 200.
  • the gap between the first connection electrode 310 and the second connection electrode 320 is filled with the resin layer 330.
  • the color filter CF is arranged on the first main surface 110a so as to overlap with the through hole provided in the light shielding film 130.
  • the microlens ML is stacked on the color filter CF.
  • the light from the subject that has passed through the imaging lens disposed optically in front of the semiconductor device 10 enters the microlens ML.
  • the micro lens ML forms an image of light that has passed through the imaging lens.
  • the color filter CF is disposed in a region corresponding to the microlens ML. That is, the color filter CF is disposed in a region through which light that has passed through the microlens ML passes.
  • the light that has passed through the microlens ML enters the color filter CF.
  • the color filter CF transmits light in a specific wavelength range.
  • the light transmitted through the color filter CF is incident on the first semiconductor layer 110.
  • the photoelectric conversion element 111 is disposed in a region corresponding to the microlens ML. That is, the photoelectric conversion element 111 is disposed in a region through which light that has passed through the microlens ML passes.
  • the light incident on the first semiconductor layer 110 is incident on the photoelectric conversion element 111.
  • the photoelectric conversion element 111 converts light incident on the photoelectric conversion element 111 into a signal.
  • the signal output from the photoelectric conversion element 111 is transferred to the connection layer 300 by the first wiring 121 and the first via 122.
  • the signal transferred to the connection layer 300 is transferred to the second semiconductor substrate 200 by the first connection electrode 310.
  • the first semiconductor substrate 100 has a first side surface 140 connected to the first main surface 110a and the second main surface 120a.
  • Second semiconductor substrate 200 has second main surface 210a and second side surface 230 connected to fourth main surface 220a. The position of the end portion of the fourth base electrode 322 matches the second side surface 230.
  • the first side surface 140 is an end surface of the first semiconductor substrate 100
  • the second side surface 230 is an end surface of the second semiconductor substrate 200.
  • the first side surface 140 and the second side surface 230 constitute a side surface of the semiconductor device 10.
  • the area of each of first side surface 140 and second side surface 230 is greater than the area of each of first main surface 110a, second main surface 120a, third main surface 210a, and fourth main surface 220a. Is also small.
  • the first side surface 140 and the second side surface 230 are substantially perpendicular to the first main surface 110a, the second main surface 120a, the third main surface 210a, and the fourth main surface 220a.
  • the first side surface 140 and the second side surface 230 are smoothly connected to the side surface of the resin layer 330.
  • first side surface 140 and the second side surface 230 are formed by dicing.
  • the first side surface 140 and the second side surface 230 are surfaces formed in the process of dividing one substrate into a plurality of chips.
  • a first side surface 140 and a second side surface 230 are a surface at the left end position of the first semiconductor substrate 100 and the second semiconductor substrate 200, and the first semiconductor substrate 100 and the second semiconductor substrate. And a surface at the right end position of the substrate 200.
  • First side 140 and second side 230 include two sides not shown in FIG. The two surfaces are arranged at the back side position and the near side position in FIG. 1.
  • Second region A ⁇ b> 2 includes first side surface 140.
  • the fourth region A4 includes the second side surface 230.
  • the fourth base electrode 322 is in contact with the second side surface 230. All positions of the end portion of the fourth base electrode 322 coincide with the second side surface 230. That is, all the end portions of the fourth base electrode 322 are exposed on the side surface of the semiconductor device 10. All of the end portions of the third base electrode 321 are separated from the first side surface 140.
  • the third base electrode 321 is not in contact with the first side surface 140. That is, the third base electrode 321 is not exposed on the side surface of the semiconductor device 10.
  • FIG. 3 shows a cross section of the semiconductor device 10 at the position indicated by line B1 in FIG.
  • FIG. 3 shows an arrangement of elements when the second semiconductor substrate 200 is viewed in the direction Dr1 perpendicular to the third major surface 210a. That is, in FIG. 3, the arrangement of each element when the second semiconductor substrate 200 is viewed from the front of the second semiconductor substrate 200 is shown.
  • the third main surface 210 a of the second semiconductor substrate 200 is covered with a second base electrode 312, a fourth base electrode 322, and a resin layer 330.
  • the positions of the microlens ML and the photoelectric conversion element 111 are indicated by broken lines.
  • symbols of one microlens ML and one photoelectric conversion element 111 are shown as representatives.
  • FIG. 3 a part of the photoelectric conversion element 111 and a part of the microlens ML are omitted.
  • a reference numeral of one second base electrode 312 is shown as a representative.
  • a part of the second base electrode 312 is omitted.
  • the position of the second peripheral circuit 221 is indicated by a broken line.
  • Four second peripheral circuits 221 are arranged.
  • the plurality of photoelectric conversion elements 111 and the plurality of microlenses ML are arranged in a matrix.
  • each of the plurality of photoelectric conversion elements 111 overlaps one of the plurality of microlenses ML.
  • One photoelectric conversion element 111 and one microlens ML correspond to each other.
  • the center of the photoelectric conversion element 111 coincides with the center of the microlens ML.
  • the plurality of photoelectric conversion elements 111 and the plurality of microlenses ML are arranged in the pixel circuit region.
  • the pixel circuit region is disposed at the center of the first semiconductor substrate 100.
  • the second base electrode 312 is disposed at a position corresponding to the photoelectric conversion element 111 and the microlens ML.
  • One second base electrode 312 may be disposed at a position corresponding to the plurality of photoelectric conversion elements 111 and the plurality of microlenses ML.
  • the fourth base electrode 322 is disposed so as to surround the pixel circuit region. That is, the fourth base electrode 322 is disposed so as to surround the third region A3 in a cross section parallel to the third major surface 210a. The fourth base electrode 322 is disposed so as to surround the second base electrode 312. The fourth base electrode 322 overlaps the entire four second peripheral circuits 221.
  • the second semiconductor substrate 200 has four second side surfaces 230. Four ends of the fourth base electrode 322 coincide with each of the four second side surfaces 230. In FIG. 3, the position of the outer periphery of the fourth base electrode 322 is the same as the position of the second side surface 230.
  • FIG. 4 shows a cross section of the semiconductor device 10 at the position indicated by line B2 in FIG.
  • FIG. 4 shows an arrangement of elements when the first semiconductor substrate 100 is viewed in the direction Dr1 perpendicular to the first main surface 110a. That is, FIG. 4 shows an arrangement of elements when the first semiconductor substrate 100 is viewed from the front of the first semiconductor substrate 100.
  • the position of the microlens ML is indicated by a broken line.
  • reference numerals of one microlens ML and one photoelectric conversion element 111 are shown as representatives.
  • a part of the photoelectric conversion element 111 and a part of the microlens ML are omitted.
  • the second area A2 surrounds the first area A1.
  • FIG. 5 shows a cross section of the semiconductor device 10 at the position indicated by line B3 in FIG.
  • FIG. 5 shows an arrangement of elements when the second semiconductor substrate 200 is viewed in the direction Dr1 perpendicular to the third major surface 210a. That is, FIG. 5 shows an arrangement of elements when the second semiconductor substrate 200 is viewed from the front of the second semiconductor substrate 200.
  • the positions of the microlens ML and the photoelectric conversion element 111 are indicated by broken lines.
  • reference numerals of one microlens ML and one photoelectric conversion element 111 are shown as representatives.
  • a part of the photoelectric conversion element 111 and a part of the microlens ML are omitted.
  • the fourth area A4 surrounds the third area A3.
  • the first peripheral circuit 112 may not be arranged in the first semiconductor layer 110.
  • the light shielding film 130 in the second region A2 may not be disposed.
  • a third semiconductor substrate may be stacked on the fourth major surface 220a. Therefore, the semiconductor device 10 may have three or more semiconductor substrates.
  • FIGS. 6 to 19 show cross sections of portions constituting the semiconductor device 10. 6 to 19, a cross section of one chip is shown.
  • a first semiconductor substrate 100 is prepared.
  • a metal film 400 is formed on the second main surface 120a so as to cover the second main surface 120a.
  • a resist film 401 is formed on the surface of the metal film 400. Specifically, after a resist film 401 is formed so as to cover the metal film 400, a pattern is formed on the resist film 401 by photolithography. In the resist film 401, the resist film 401 in a region other than the region where the first base electrode 311 and the third base electrode 321 are formed is removed.
  • the first base electrode 311 is formed in the first region A1 on the second main surface 120a, and the third base electrode 321 is formed in the second region A2 on the second main surface 120a.
  • the resist film 401 functions as an etching mask. In the etching of the metal film 400, portions other than the portion covered with the resist film 401 in the metal film 400 are removed. Thereby, the first base electrode 311 and the third base electrode 321 are formed simultaneously. A part of second main surface 120a is exposed by etching of metal film 400. Thereafter, the resist film 401 is removed. As a result, the surfaces of the first base electrode 311 and the third base electrode 321 are exposed.
  • a second semiconductor substrate 200 is prepared.
  • a metal film 402 is formed on the third main surface 210a so as to cover the third main surface 210a.
  • a resist film 403 is formed on the surface of the metal film 402. Specifically, after a resist film 403 is formed so as to cover the metal film 402, a pattern is formed on the resist film 403 by photolithography. In the resist film 403, the resist film 403 in a region other than a region where the second base electrode 312 and the fourth base electrode 322 are formed is removed.
  • the second base electrode 312 is formed in the third region A3 in the third main surface 210a, and the fourth base electrode 322 in the fourth region A4 in the third main surface 210a.
  • the resist film 403 functions as an etching mask. In the etching of the metal film 402, portions other than the portion covered with the resist film 403 in the metal film 402 are removed. As a result, the second base electrode 312 and the fourth base electrode 322 are formed simultaneously. A part of the third major surface 210a is exposed by etching the metal film 402. Thereafter, the resist film 403 is removed.
  • the surfaces of the second base electrode 312 and the fourth base electrode 322 are exposed.
  • the fourth base electrode 322 overlaps with the entire second peripheral circuit 221.
  • the first bump electrode 313 is formed on the second base electrode 312, and the second bump electrode 323 is formed on the fourth base electrode 322 (the third step and the fourth step). Process).
  • the first bump electrode 313 and the second bump electrode 323 are simultaneously formed by plating.
  • the first bump electrode 313 may be formed on the first base electrode 311, and the second bump electrode 323 may be formed on the third base electrode 321. Therefore, the first bump electrode 313 is formed on any one of the first base electrode 311 and the second base electrode 312.
  • the second bump electrode 323 is formed on any one of the third base electrode 321 and the fourth base electrode 322.
  • the first bump electrode 313 is formed on the first base electrode 311, the second bump electrode 323 is formed on the third base electrode 321.
  • the second bump electrode 323 is formed on the fourth base electrode 322.
  • the first semiconductor substrate 100 and the second semiconductor substrate 200 are arranged so that the third main surface 210a faces the second main surface 120a.
  • the first bump electrode 313 is connected to the first base electrode 311 and the second bump electrode 323 is connected to the third base electrode 321 (fifth step).
  • pressure and heat are applied to the first semiconductor substrate 100 and the second semiconductor substrate 200.
  • the first semiconductor substrate 100 and the second semiconductor substrate 200 are bonded.
  • the first bump electrode 313 may be formed on the first base electrode 311, and the second bump electrode 323 may be formed on the third base electrode 321.
  • the first bump electrode 313 is connected to the second base electrode 312, and the second bump electrode 323 is connected to the fourth base electrode 322. Therefore, in the above process, the first bump electrode 313 is connected to any one of the first base electrode 311 and the second base electrode 312, and the second bump electrode 323 is the third base electrode. 321 and the fourth base electrode 322 are connected.
  • the first bump electrode 313 is connected to an electrode to which the first bump electrode 313 is not connected.
  • the second bump electrode 323 is connected to an electrode of the third base electrode 321 and the fourth base electrode 322 to which the second bump electrode 323 is not connected.
  • resin is injected between the second main surface 120a and the third main surface 210a. Thereby, the resin layer 330 is formed, and the first semiconductor substrate 100 and the second semiconductor substrate 200 are bonded.
  • the first semiconductor substrate 100 is thinned by cutting the first main surface 110a (sixth step).
  • the thickness T2 (FIG. 17) of the first semiconductor substrate 100 after the sixth step is performed is greater than the thickness T1 (FIG. 16) of the first semiconductor substrate 100 before the sixth step is performed. Is also small.
  • a light shielding film 130 is formed on the first main surface 110a.
  • the metal film constituting the light shielding film 130 is formed so as to cover the first main surface 110a on the first main surface 110a.
  • a pattern is formed on the resist film by photolithography.
  • the resist film in the region other than the region where the light shielding film 130 is formed is removed.
  • the metal film is etched.
  • the light shielding film 130 is formed.
  • the resist film is removed.
  • the color filter CF and the microlens ML are formed in order. Thereafter, dicing is performed on the dicing line DL1.
  • the dicing line DL1 is set at the boundary position of each chip constituting the semiconductor device 10.
  • a plurality of semiconductor devices 10 are formed from one wafer by dicing.
  • the first side surface 140 and the second side surface 230 are formed by dicing.
  • the semiconductor device of each aspect of the present invention may not have a configuration corresponding to at least one of the first peripheral circuit 112, the light shielding film 130, the resin layer 330, the color filter CF, and the microlens ML.
  • the method for manufacturing a semiconductor device according to each aspect of the present invention may not include steps other than the first to sixth steps.
  • the fourth base electrode 322 when the second semiconductor substrate 200 is viewed in the direction Dr1 perpendicular to the third major surface 210a, the fourth base electrode 322 includes all of the second peripheral circuits 221. And overlap. That is, the fourth base electrode 322 shields the second peripheral circuit 221 from light. Since it is not necessary to arrange the second wiring 211 for shielding light, it is not necessary to planarize the second wiring layer 210 by CMP. Accordingly, a difference in height between the first bump electrode 313 and the second bump electrode 323 hardly occurs. As a result, the semiconductor device 10 can reduce a decrease in the yield of electrical connection between a plurality of semiconductor substrates, and can shield the peripheral circuits from light.
  • the pattern of the second wiring 211 in the fourth region A4 is not easily limited.
  • the fourth base electrode 322 is exposed on the side surface of the semiconductor device 10. Thereby, the heat dissipation effect of the semiconductor device 10 is enhanced.
  • FIGS. 20 and 21 show the configuration of the semiconductor device 11 according to the first modification of the first embodiment of the present invention. 20 and 21, a cross section of the semiconductor device 11 is shown. FIG. 21 is an enlarged view of a part of the semiconductor device 11. The configurations shown in FIGS. 20 and 21 will be described while referring to differences from the configurations shown in FIGS. 1 and 2.
  • the first semiconductor substrate 100 shown in FIG. 1 is changed to the first semiconductor substrate 101.
  • the first semiconductor layer 110 shown in FIG. 1 is changed to the first semiconductor layer 113, and the first wiring layer 120 shown in FIG. 1 is changed to the first wiring layer 124.
  • the first main surface 110a shown in FIG. 1 is changed to the first main surface 113a.
  • the first semiconductor layer 113 has a through hole 114 formed in the second region A2.
  • the through hole 114 penetrates the first semiconductor layer 113.
  • the first wiring layer 124 is exposed.
  • Other portions of the first semiconductor layer 113 are configured in the same manner as the first semiconductor layer 110 shown in FIG.
  • the second main surface 120a shown in FIG. 1 is changed to the second main surface 124a.
  • the patterns of the first wiring 121 and the first via 122 are different from the patterns in the first wiring layer 120 shown in FIG.
  • the first wiring 121 is exposed.
  • the first wiring 121 exposed in the through hole 114 constitutes a pad electrode for electrically connecting the semiconductor device 11 and an external package.
  • Other portions of the first wiring layer 124 are configured in the same manner as the first wiring layer 120 shown in FIG.
  • connection layer 300 shown in FIG. 1 is changed to the connection layer 301.
  • the connection layer 301 includes a third connection electrode 340.
  • the symbol of one third connection electrode 340 is shown as a representative.
  • the third connection electrode 340 is disposed between the second region A2 and the fourth region A4.
  • the third connection electrode 340 is disposed outside the second connection electrode 320.
  • the third connection electrode 340 includes a fifth base electrode 341, a sixth base electrode 342, and a third bump electrode 343.
  • the fifth base electrode 341, the sixth base electrode 342, and the third bump electrode 343 are made of a second conductive material.
  • the fifth base electrode 341 and the sixth base electrode 342 are thin films.
  • the fifth base electrode 341 is in contact with the first via 122 on the second main surface 124a. Therefore, the fifth base electrode 341 is electrically connected to the first semiconductor substrate 101.
  • the sixth base electrode 342 contacts the second via 212 on the third main surface 210a. For this reason, the sixth base electrode 342 is electrically connected to the second semiconductor substrate 200.
  • the third bump electrode 343 is columnar or spherical.
  • the third bump electrode 343 is disposed between the fifth base electrode 341 and the sixth base electrode 342.
  • the third bump electrode 343 is in contact with the fifth base electrode 341 and the sixth base electrode 342.
  • the pattern of the fourth base electrode 322 is different from the pattern of the fourth base electrode 322 shown in FIG.
  • the fourth base electrode 322 is not in contact with the sixth base electrode 342. That is, the fourth base electrode 322 is electrically insulated from the sixth base electrode 342.
  • the fourth base electrode 322 is connected to the sixth base electrode 342 electrically connected to the pad electrode. Also good.
  • a fourth base electrode 322 is also arranged outside the third connection electrode 340.
  • the outer portion of the third connection electrode 340 is not shown for convenience of illustration.
  • Other portions of the connection layer 301 are configured in the same manner as the connection layer 300 shown in FIG.
  • FIGS. 20 and 21 are the same as the configuration shown in FIGS.
  • FIG. 22 shows a cross section of the semiconductor device 11 at the position indicated by line B4 in FIG.
  • the configuration shown in FIG. 22 will be described while referring to differences from the configuration shown in FIG.
  • the third main surface 210 a of the second semiconductor substrate 200 is covered with the second base electrode 312, the fourth base electrode 322, the sixth base electrode 342, and the resin layer 330. ing.
  • a symbol of one sixth base electrode 342 is shown as a representative.
  • a part of the sixth base electrode 342 is omitted.
  • the fourth base electrode 322 a plurality of through holes are formed in a region near the outer periphery.
  • a sixth base electrode 342 is disposed inside the through hole.
  • the semiconductor device 11 has a pad electrode. For this reason, the semiconductor device 11 can be electrically connected to an external package.
  • FIG. 23 shows a configuration of the semiconductor device 12 of the second modification example of the first embodiment of the present invention.
  • a cross section of the semiconductor device 12 is shown. The configuration shown in FIG. 23 will be described while referring to differences from the configuration shown in FIG.
  • the first semiconductor substrate 100 shown in FIG. 1 is changed to the first semiconductor substrate 102.
  • the first wiring layer 120 illustrated in FIG. 1 is changed to the first wiring layer 124.
  • the configuration of the first wiring layer 124 is the same as the configuration shown in FIGS.
  • the second semiconductor substrate 200 shown in FIG. 1 is changed to the second semiconductor substrate 201.
  • the second semiconductor layer 220 illustrated in FIG. 1 is changed to the second semiconductor layer 222.
  • the fourth main surface 220a shown in FIG. 1 is changed to the fourth main surface 222a.
  • the second semiconductor layer 222 includes a through electrode 223 (Through-Silicon-Via).
  • the through electrode 223 is made of a conductive material.
  • the through electrode 223 penetrates the second semiconductor layer 222.
  • the through electrode 223 is in contact with the second wiring 211.
  • the through electrode 223 is disposed in the fourth region A4.
  • Other portions of the second semiconductor layer 222 are configured in the same manner as the second semiconductor layer 220 shown in FIG.
  • the semiconductor device 12 has solder bumps 500.
  • the solder bump 500 is disposed on the fourth main surface 222a.
  • the solder bump 500 is electrically connected to the through electrode 223.
  • the through electrode 223 transfers a signal input to the second semiconductor substrate 201 to an external package via the solder bump 500.
  • the solder bump 500 is electrically connected to an external package.
  • connection layer 300 shown in FIG. 1 is changed to the connection layer 301.
  • the connection layer 301 is the same as the connection layer 301 shown in FIGS.
  • FIG. 23 the configuration shown in FIG. 23 is the same as the configuration shown in FIG.
  • the semiconductor device 12 has the solder bumps 500. For this reason, the semiconductor device 12 can be electrically connected to an external package.
  • FIG. 24 shows the configuration of the semiconductor device 13 of the third modification example of the first embodiment of the present invention.
  • a cross section of the semiconductor device 13 is shown.
  • the configuration shown in FIG. 24 will be described while referring to differences from the configuration shown in FIG.
  • the second semiconductor substrate 200 shown in FIG. 1 is changed to the second semiconductor substrate 202.
  • the second semiconductor substrate 202 constitutes an FSI type image sensor.
  • the second semiconductor layer 220 illustrated in FIG. 1 is changed to the second semiconductor layer 224.
  • the fourth major surface 220a shown in FIG. 1 is changed to the fourth major surface 224a.
  • the second semiconductor layer 224 includes a plurality of photoelectric conversion elements 225. In FIG. 24, the symbol of one photoelectric conversion element 225 is shown as a representative.
  • the photoelectric conversion element 225 constitutes a pixel.
  • the photoelectric conversion element 225 is disposed in the third region A3.
  • the photoelectric conversion element 225 is formed using a semiconductor material having an impurity concentration different from that of the semiconductor material forming the second semiconductor layer 224.
  • the photoelectric conversion element 225 converts light incident on the photoelectric conversion element 225 into a signal.
  • the photoelectric conversion element 225 can function as a phase difference autofocus pixel.
  • the imaging device includes a semiconductor device 13.
  • the imaging device can estimate the position of the imaging target with respect to the focal position of the imaging lens based on the signal generated by the photoelectric conversion element 225.
  • the imaging apparatus can adjust the focal position of the imaging lens according to the estimation result.
  • the photoelectric conversion element 225 may acquire a signal based on special light.
  • the special light is fluorescence.
  • ICG indocyanine green
  • ICG is a fluorescent material.
  • ICG is administered into the body of the subject to be tested in advance. ICG is excited in the infrared region by excitation light and emits fluorescence.
  • the administered ICG is accumulated in a lesion such as cancer. Since intense fluorescence is generated from the lesion, the examiner can determine the presence or absence of the lesion based on the captured fluorescence image.
  • a filter that transmits only fluorescence is disposed between the photoelectric conversion element 225 and the photoelectric conversion element 111.
  • the photoelectric conversion element 225 generates a signal based on fluorescence.
  • Special light may be narrowband light.
  • the blood vessel is irradiated with blue narrow-band light or green narrow-band light.
  • a filter that transmits only narrowband light is disposed between the photoelectric conversion element 225 and the photoelectric conversion element 111.
  • the photoelectric conversion element 225 generates a signal based on narrowband light.
  • FIG. 24 the configuration shown in FIG. 24 is the same as the configuration shown in FIG.
  • the semiconductor device 13 includes a plurality of photoelectric conversion elements 225. For this reason, the semiconductor device 13 can obtain a signal generated by the photoelectric conversion element 111 and a signal generated by the photoelectric conversion element 225.
  • FIGS. 25 and 26 show the configuration of the semiconductor device 14 according to the second embodiment of the present invention. 25 and 26, a cross section of the semiconductor device 14 is shown. The configurations shown in FIGS. 25 and 26 will be described while referring to differences from the configurations shown in FIGS. 1 and 2.
  • the pattern of the third base electrode 321 is different from the pattern of the third base electrode 321 shown in FIG.
  • the position of the end portion of the third base electrode 321 coincides with the first side surface 140.
  • the third base electrode 321 is in contact with the first side surface 140. All positions of the end portion of the third base electrode 321 coincide with the first side surface 140. That is, all the end portions of the third base electrode 321 are exposed on the side surfaces of the semiconductor device 14.
  • FIGS. 25 and 26 are the same as the configurations shown in FIGS. 1 and 2.
  • FIG. 27 shows a cross section of the semiconductor device 14 at the position shown by line B5 in FIG.
  • FIG. 27 shows an arrangement of elements when the first semiconductor substrate 100 is viewed in a direction perpendicular to the second main surface 120a (a direction perpendicular to the direction Dr1). That is, in FIG. 27, the arrangement of each element when the first semiconductor substrate 100 is viewed from the front of the first semiconductor substrate 100 is shown.
  • the second main surface 120 a of the first semiconductor substrate 100 is covered with a first base electrode 311, a third base electrode 321, and a resin layer 330.
  • the positions of the microlens ML and the photoelectric conversion element 111 are indicated by broken lines.
  • FIG. 27 shows an arrangement of elements when the first semiconductor substrate 100 is viewed in a direction perpendicular to the second main surface 120a (a direction perpendicular to the direction Dr1). That is, in FIG. 27, the arrangement of each element when the first semiconductor substrate 100 is viewed from the front of the first semiconductor substrate 100 is shown.
  • reference numerals of one microlens ML and one photoelectric conversion element 111 are shown as representatives. In FIG. 27, a part of the photoelectric conversion element 111 and a part of the microlens ML are omitted. In FIG. 27, a symbol of one first base electrode 311 is shown as a representative. In FIG. 27, a part of the first base electrode 311 is omitted. In FIG. 27, the position of the first peripheral circuit 112 is indicated by a broken line. Four first peripheral circuits 112 are arranged.
  • the first base electrode 311 is disposed at a position corresponding to the photoelectric conversion element 111 and the microlens ML.
  • One first base electrode 311 may be disposed at a position corresponding to the plurality of photoelectric conversion elements 111 and the plurality of microlenses ML.
  • the third base electrode 321 is arranged so as to surround the pixel circuit region. That is, the third base electrode 321 is arranged so as to surround the third region A3 in a cross section parallel to the second major surface 120a.
  • the third base electrode 321 is disposed so as to surround the first base electrode 311.
  • the first semiconductor substrate 100 has four first side surfaces 140. The four end portions of the third base electrode 321 coincide with each of the four first side surfaces 140. In FIG. 27, the position of the outer periphery of the third base electrode 321 is the same as the position of the first side surface 140.
  • the semiconductor device 14 of the second embodiment can reduce a decrease in the yield of electrical connection of a plurality of semiconductor substrates and can shield the peripheral circuits from light. .
  • the third base electrode 321 is exposed on the side surface of the semiconductor device 14. Thereby, the heat dissipation effect of the semiconductor device 14 is enhanced.
  • FIG. 28 shows the configuration of the semiconductor device 15 according to the third embodiment of the present invention.
  • FIG. 28 shows a cross section of the semiconductor device 15 at a position similar to the position shown by line B1 in FIG.
  • the configuration shown in FIG. 28 will be described while referring to differences from the configuration shown in FIG.
  • the position of only a part of the end portion of the fourth base electrode 322 coincides with the second side surface 230.
  • the second semiconductor substrate 200 is viewed in the direction Dr1 perpendicular to the third main surface 210a, only a part of the fourth base electrode 322 is in contact with the second side surface 230. That is, only a part of the end portion of the fourth base electrode 322 is exposed on the side surface of the semiconductor device 15.
  • the resin layer 330 is disposed outside a part of the end portion of the fourth base electrode 322.
  • the position of the end portion of the third base electrode 321 coincides with the first side surface 140.
  • the position of only a part of the end portion of the third base electrode 321 coincides with the first side surface 140.
  • all the positions of the end portions of the third base electrode 321 coincide with the first side surface 140. All of the end portions of the third base electrode 321 may be separated from the first side surface 140.
  • the semiconductor device 15 of the third embodiment can reduce a decrease in the yield of electrical connection of a plurality of semiconductor substrates and can shield the peripheral circuits from light. .
  • the semiconductor device 15 of the third embodiment a part of the end portion of the fourth base electrode 322 is exposed on the side surface of the semiconductor device 15. Thereby, the heat dissipation effect of the semiconductor device 15 is enhanced.
  • FIG. 29 shows the configuration of the semiconductor device 16 according to the fourth embodiment of the present invention. 29 shows a cross section of the semiconductor device 16 at the same position as that indicated by the line B1 in FIG. The configuration shown in FIG. 29 will be described while referring to differences from the configuration shown in FIG.
  • All the ends of the fourth base electrode 322 are separated from the second side surface 230.
  • the fourth base electrode 322 is not in contact with the second side surface 230. That is, the fourth base electrode 322 is not exposed on the side surface of the semiconductor device 16.
  • a resin layer 330 is disposed outside the end portion of the fourth base electrode 322.
  • the position of the end portion of the third base electrode 321 coincides with the first side surface 140.
  • the position of only a part of the end portion of the third base electrode 321 coincides with the first side surface 140.
  • all the positions of the end portions of the third base electrode 321 coincide with the first side surface 140. All of the end portions of the third base electrode 321 may be separated from the first side surface 140.
  • the semiconductor device 16 of the fourth embodiment can reduce a decrease in the yield of electrical connection of a plurality of semiconductor substrates and can shield the peripheral circuits from light. .
  • a semiconductor device and a method for manufacturing a semiconductor device can reduce a decrease in the yield of electrical connection between a plurality of semiconductor substrates and can shield a peripheral circuit from light.

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Solid State Image Pick-Up Elements (AREA)

Abstract

L'invention concerne un dispositif à semi-conducteur dans lequel une deuxième région entoure une première région lorsqu'un premier substrat semi-conducteur est vu depuis la direction perpendiculaire à une première surface principale. Une quatrième région entoure une troisième région lorsqu'un deuxième substrat semi-conducteur est vu depuis la direction perpendiculaire à une troisième surface principale. La quatrième région comprend un circuit périphérique. Une troisième électrode de base est disposée dans la deuxième région d'une deuxième surface principale du premier substrat semi-conducteur. Une quatrième électrode de base est disposée dans la quatrième région de la troisième surface principale du deuxième substrat semi-conducteur, et chevauche le circuit périphérique entier lorsque le deuxième substrat semi-conducteur est vu depuis la direction perpendiculaire à la troisième surface principale. Une deuxième électrode à bosse est disposée entre la troisième électrode de base et la quatrième électrode de base.
PCT/JP2017/008733 2017-03-06 2017-03-06 Dispositif à semi-conducteur et procédé de fabrication de dispositif à semi-conducteur Ceased WO2018163236A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/JP2017/008733 WO2018163236A1 (fr) 2017-03-06 2017-03-06 Dispositif à semi-conducteur et procédé de fabrication de dispositif à semi-conducteur

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2017/008733 WO2018163236A1 (fr) 2017-03-06 2017-03-06 Dispositif à semi-conducteur et procédé de fabrication de dispositif à semi-conducteur

Publications (1)

Publication Number Publication Date
WO2018163236A1 true WO2018163236A1 (fr) 2018-09-13

Family

ID=63447379

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2017/008733 Ceased WO2018163236A1 (fr) 2017-03-06 2017-03-06 Dispositif à semi-conducteur et procédé de fabrication de dispositif à semi-conducteur

Country Status (1)

Country Link
WO (1) WO2018163236A1 (fr)

Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005044861A (ja) * 2003-07-23 2005-02-17 Seiko Epson Corp 半導体装置、半導体装置の使用方法、半導体装置の製造方法および電子機器
JP2009283902A (ja) * 2008-04-25 2009-12-03 Panasonic Corp 光学デバイスとこれを備えた電子機器
JP2010098376A (ja) * 2008-10-14 2010-04-30 Olympus Corp 固体撮像装置
JP2011198862A (ja) * 2010-03-17 2011-10-06 Nikon Corp 固体撮像装置
JP2012033878A (ja) * 2010-06-30 2012-02-16 Canon Inc 固体撮像装置および固体撮像装置の製造方法
JP2012164870A (ja) * 2011-02-08 2012-08-30 Sony Corp 固体撮像装置とその製造方法、及び電子機器
JP2013016963A (ja) * 2011-07-01 2013-01-24 Olympus Corp 固体撮像装置、固体撮像装置の制御方法、および撮像装置
JP2013021031A (ja) * 2011-07-07 2013-01-31 Sony Corp 固体撮像装置、電子機器
JP2013168623A (ja) * 2012-01-17 2013-08-29 Olympus Corp 固体撮像装置、撮像装置および固体撮像装置の製造方法
JP2013175540A (ja) * 2012-02-24 2013-09-05 Nikon Corp 固体撮像装置および固体撮像装置の製造方法

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005044861A (ja) * 2003-07-23 2005-02-17 Seiko Epson Corp 半導体装置、半導体装置の使用方法、半導体装置の製造方法および電子機器
JP2009283902A (ja) * 2008-04-25 2009-12-03 Panasonic Corp 光学デバイスとこれを備えた電子機器
JP2010098376A (ja) * 2008-10-14 2010-04-30 Olympus Corp 固体撮像装置
JP2011198862A (ja) * 2010-03-17 2011-10-06 Nikon Corp 固体撮像装置
JP2012033878A (ja) * 2010-06-30 2012-02-16 Canon Inc 固体撮像装置および固体撮像装置の製造方法
JP2012164870A (ja) * 2011-02-08 2012-08-30 Sony Corp 固体撮像装置とその製造方法、及び電子機器
JP2013016963A (ja) * 2011-07-01 2013-01-24 Olympus Corp 固体撮像装置、固体撮像装置の制御方法、および撮像装置
JP2013021031A (ja) * 2011-07-07 2013-01-31 Sony Corp 固体撮像装置、電子機器
JP2013168623A (ja) * 2012-01-17 2013-08-29 Olympus Corp 固体撮像装置、撮像装置および固体撮像装置の製造方法
JP2013175540A (ja) * 2012-02-24 2013-09-05 Nikon Corp 固体撮像装置および固体撮像装置の製造方法

Similar Documents

Publication Publication Date Title
JP4383959B2 (ja) 光電変換装置およびその製造方法
TWI401793B (zh) Semiconductor device
US10134794B2 (en) Image sensor chip sidewall interconnection
CN110957333B (zh) 晶圆级图像传感器封装件
US9634060B2 (en) Stacked solid-state image sensor and imaging apparatus including the same
US9029183B2 (en) Method and apparatus for image sensor packaging
US8502335B2 (en) CMOS image sensor big via bonding pad application for AlCu Process
US9142690B2 (en) Semiconductor device having a bonding pad and shield structure and method of manufacturing the same
CN103208498B (zh) 成像装置及其制造方法
US20100237452A1 (en) Semiconductor device and backside illumination solid-state imaging device
JP4534484B2 (ja) 固体撮像素子及びその製造方法
CN111788689B (zh) 摄像元件和摄像元件的制造方法
WO2017126024A1 (fr) Dispositif de capture d'image à semi-conducteurs, et dispositif de capture d'image
TW201826512A (zh) 固體攝像元件及製造方法、以及電子機器
US9287318B2 (en) Solid-state imaging sensor, method of manufacturing the same, and camera
JP2009176949A (ja) 裏面照射型固体撮像装置及びその製造方法
WO2015022795A1 (fr) Dispositif de capture d'images à semiconducteurs, procédé pour sa fabrication et dispositif de capture d'images
TWI861247B (zh) 攝像元件及攝像裝置
WO2018163236A1 (fr) Dispositif à semi-conducteur et procédé de fabrication de dispositif à semi-conducteur
JP5225233B2 (ja) 光電変換装置
JP6701149B2 (ja) 撮像装置およびカメラ
CN101442063A (zh) 半导体装置及影像感测装置
WO2024203101A1 (fr) Dispositif à semi-conducteur et son procédé de fabrication, et appareil électronique
WO2017068713A1 (fr) Dispositif de prise de vues à semi-conducteurs, et dispositif de prise de vues
JP2020129688A (ja) 撮像装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 17899391

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 17899391

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: JP