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WO2017200639A1 - Ensembles comportant des lignes de blindage d'un niveau de câblage supérieur couplées électriquement à des lignes de blindage d'un niveau de câblage inférieur - Google Patents

Ensembles comportant des lignes de blindage d'un niveau de câblage supérieur couplées électriquement à des lignes de blindage d'un niveau de câblage inférieur Download PDF

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Publication number
WO2017200639A1
WO2017200639A1 PCT/US2017/024835 US2017024835W WO2017200639A1 WO 2017200639 A1 WO2017200639 A1 WO 2017200639A1 US 2017024835 W US2017024835 W US 2017024835W WO 2017200639 A1 WO2017200639 A1 WO 2017200639A1
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WO
WIPO (PCT)
Prior art keywords
wiring
shield
lines
line
segment
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2017/024835
Other languages
English (en)
Inventor
Makoto Sato
Ryota Suzuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Micron Technology Inc
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US15/155,334 external-priority patent/US9754872B1/en
Priority claimed from US15/456,254 external-priority patent/US10304771B2/en
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Priority to KR1020187025272A priority Critical patent/KR102105785B1/ko
Priority to CN201780013788.1A priority patent/CN108701676B/zh
Publication of WO2017200639A1 publication Critical patent/WO2017200639A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
    • H01L23/5225—Shielding layers formed together with wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D88/00—Three-dimensional [3D] integrated devices

Definitions

  • Integrated circuitry may comprise multiple levels of stacked wiring.
  • the levels may include signal lines alternately arranged with shield lines.
  • the shield lines may be utilized to alleviate cross-talk between adjacent signal lines.
  • An example configuration comprising three stacked wiring levels is shown in FIG. 1. Specifically, the configuration shows a first level of wiring Ml, a second level of wiring M2, and a third level of wiring M3; with M3 being over M2 which in turn is over Ml.
  • three wiring levels are shown, it is to be understood that there may be other wiring levels below the illustrated levels and/or above the illustrated levels.
  • the illustrated wiring levels are labeled M1-M3, if other wiring levels are present the shown levels may in fact be M2- M4; M3-M6; etc., depending on the number of wiring levels present beneath the illustrated wiring levels.
  • Each of the illustrated levels comprises signal lines alternately arranged with shield lines. It may be desired for the shield lines within one level to be electrically connected with shield lines at other levels above and below said one level. For instance, it may be desired for the shield lines within level M2 to be electrically connected with shield lines within level Ml and shield lines within level M3, as such may alleviate coupling noises between the vertically-stacked levels.
  • FIG. 1 is a diagrammatic three-dimensional view of a prior art arrangement of wiring levels.
  • FIGS. 2-2C are diagrammatic views of an example embodiment arrangement of wiring levels.
  • FIG. 2 is a top view.
  • FIGS. 2A-2C are diagrammatic cross-sectional views along the lines 2A-2A, 2B-2B and 2C-2C of FIG. 2, respectively.
  • FIG. 3 is an enlarged view of a region "3" of FIG. 2.
  • FIGS. 4 and 4 A are diagrammatic views of an example embodiment arrangement of wiring levels.
  • FIG. 4 is a top view.
  • FIG. 4A is a diagrammatic cross-sectional view along the line 4A-4A of FIG.4.
  • FIG. 5 is an exploded view of an example embodiment assembly of wiring levels. Three levels are stacked in the view of FIG. 5.
  • FIGS. 6-8 are diagrammatic top views of the individual levels of FIG. 5.
  • FIG. 9 is a diagrammatic top view showing an example mesh containing interconnected shield lines of the three levels of FIG. 5.
  • FIG. 10 is an exploded view of another example embodiment assembly of wiring levels. Three levels are stacked in the view of FIG. 10.
  • FIGS. 11-13 are diagrammatic top views of the individual levels of FIG. 10.
  • FIG. 14 is a diagrammatic top view showing an example mesh containing interconnected shield lines of the three levels of FIG. 10.
  • FIG. 15A is a diagrammatic top view of an assembly of wiring layers across a substrate
  • FIG. 15B is a view of an expanded region of FIG. 15A to illustrate alternating signal lines and shield lines.
  • the three wiring layers of FIG. 5 are stacked in the top view of FIG. 15A, with the portion shown in FIG. 5 being within a region "FIG. 5" of FIG. 15A.
  • FIG. 16A is a diagrammatic top view of an example arrangement of circuitry across a substrate.
  • FIG. 16B is a view of an expanded region of FIG. 16A to illustrate alternating signal lines and shield lines, and to show a redundant (or dummy) structure.
  • FIG. 17 is a diagrammatic top view of an example arrangement of circuitry from two stacked wiring layers.
  • FIG. 18 is a view of an expanded region of FIG. 17 to illustrate alternating signal and shield wiring lines within the stacked wiring layers, and to show redundant (or dummy) structures.
  • FIG. 19 shows diagrammatic top views comparing example circuit arrangements.
  • FIG. 20 shows diagrammatic top views comparing a pair of example circuit arrangements.
  • FIG. 21 is an exploded view of an assembly of example wiring layers that may be utilized in one of the circuit arrangements of FIG. 20. Three wiring layers are stacked in the view of FIG. 21.
  • FIGS. 22-24 are diagrammatic top views of the individual wiring layers of FIG.
  • FIG. 25 is a diagrammatic cross-sectional side view along a line 25-25 shown in FIGS. 23 and 24, and through the wiring layers M2 and M3 of FIGS. 23 and 24.
  • FIG. 26 is a view of an expanded region of FIGS. 23 and 24, and shows the wiring layer of FIG. 24 stacked over that of FIG. 23.
  • the region of FIG. 26 is indicated by a dashed line "FIG. 26" in FIGS. 23 and 24.
  • FIGS. 27A-27C are expanded diagrammatic top views of a region of the M2 wiring layer of FIG. 23 showing example alternative configurations.
  • FIG. 28 is an exploded view of an assembly of example wiring layers that may be utilized in one of the circuit arrangements of FIG. 20. Three layers are stacked in the view of FIG. 28.
  • FIGS. 29-31 are diagrammatic top views of the individual layers of FIG. 28.
  • FIGS. 32A-C are diagrammatic cross-sectional side views along lines 32A-32A, 32B-32B and 32C-32C of FIGS. 30 and 31, and are through the wiring layers M2 and M3 of FIGS. 30 and 31.
  • FIGS. 33 and 34 are expanded diagrammatic top views of regions of the wiring layer M3 of FIG. 31 showing example alternative configurations.
  • FIGS. 35 and 36 are expanded diagrammatic top views of regions of the wiring layer M2 of FIG. 30 showing example alternative configurations.
  • Some embodiments include architectures in which the signal lines and shield lines within wiring layers are configured to have offset regions. Such offset regions may enable a vertical overlap to occur between shield lines of an upper wiring layer and shield lines of a lower wiring layer, even though the shield lines within both wiring layers run substantially parallel with one another, and even though the shield lines within the lower wiring layer are staggered relative to the shield lines within the upper wiring layer in a configuration analogous to that of FIG. 1.
  • Example embodiments are described with reference to FIGS. 2-36.
  • the assembly 510 includes a pair of vertically-stacked wiring levels M2 and M3.
  • the level M2 is shown in dashed-line in the top-down view of FIG. 2 to indicate that such level is beneath the level M3.
  • Level M3 comprises a shield line 512 and a signal line 514 immediately adjacent the shield line.
  • the lines 512 and 514 may be representative of a large plurality of shield lines and signal lines formed in alternating relationship within the wiring level M3.
  • Level M2 comprises a shield line 516 and a signal line 518 immediately adjacent the shield line.
  • the lines 516 and 518 may be representative of a large plurality of shield lines and signal lines formed in alternating relationship within the wiring level M2.
  • the wiring level M3 may be referred to as a first wiring level
  • the wiring level M2 may be referred to as a second wiring level beneath the first wiring level.
  • the shield line 512 and signal line 514 within the first wiring level may be referred to as a first shield line and a first signal line, and such may be representative of a plurality of first shield lines and first signal lines formed in alternating arrangement across the first wiring level.
  • the shield line 516 and signal line 518 of the second wiring level be referred to as a second shield line and second signal line, and such may be representative of a plurality of second shield lines and second signal lines formed in alternating arrangement across the second wiring level.
  • the first shield line 512 has a first segment 520 and a second segment 522 laterally offset from the first segment.
  • the first and second segments 520 and 522 are connected to one another through a linking segment 524.
  • the linking segment 524 may be arranged to connect an end of the first segment 520 and an end of the second segment 522.
  • the first segment 520 may be elongated from one end of the linking segment 524.
  • the second segment 522 may be elongated oppositely against the first segment 520 from another end of the linking segment 524.
  • the first signal line 514 has a first segment 526, a second segment 528 laterally offset from the first segment, and a linking segment 530 which interconnects the first and second segments 526 and 528 to one another.
  • the linking segment 530 may be arranged to connect an end of the first segment 526 and an end of the second segment 528.
  • the first segment 526 may be elongated from one end of the linking segment 530.
  • the second segment 528 may be elongated oppositely against the first segment 526 from another end of the linking segment 530.
  • the second shield line and second signal line within the second wiring level M2 have segments similar to those of the first wiring level M3.
  • the segments of the second shield line and second signal line will be referred to as third and fourth segments to distinguish them from the first and second segments of the first shield line 512 and first signal line 514.
  • the second shield line 516 has a third segment 532 and a fourth segment 534 laterally offset from the third segment.
  • the third and fourth segments 532 and 534 are connected to one another through a linking segment 536.
  • the linking segment 536 may be arranged to connect an end of the third segment 532 and an end of the fourth segment 534.
  • the third segment 532 may be elongated from one end of the linking segment 536.
  • the fourth segment 534 may be elongated oppositely against the third segment 532 from another end of the linking segment 536.
  • the second signal line 518 has a third segment 538, a fourth segment 540 laterally offset from the third segment, and a linking segment 542 which interconnects the third and fourth segments 538 and 540 to one another.
  • the linking segment 542 may be arranged to connect an end of the third segment 538 and an end of the fourth segment 540.
  • the third segment 538 may be elongated from one end of the linking segment 542.
  • the fourth segment 540 may be elongated oppositely against the third segment 538 from another end of the linking segment 542.
  • the linking segments 524 and 530 within the first wiring level M3 may be referred to as first linking segments
  • the linking segments 536 and 542 within the second wiring level M2 may be referred to as second linking segments so that linking segments within the different wiring levels may be distinguished from one another.
  • the axis system shows a first axis 503 and a second axis 505 which extends orthogonally relative to the first axis.
  • the first and second segments 520, 522, 526 and 528 extend primarily along a first direction corresponding to the axis 503, and the linking segments 524 and 530 extend primarily along a second direction corresponding to the axis 505.
  • the segments are indicated to extend "primarily" along the indicated directions to indicate that the overall course of the segments is along the indicated directions even if the segments are wavy or otherwise not straight.
  • the segments may be substantially straight, with the term "substantially straight" meaning that the segments are straight to within reasonable tolerances of fabrication and measurement.
  • the third and fourth segments 532, 534, 538 and 540 also extend primarily along the first direction corresponding to the axis 503, and the linking segments 536 and 542 extend primarily along the second axis 505 in the illustrated embodiment.
  • the linking segment 524 extends substantially orthogonally to the first and second segments 520 and 522 of shield line 512
  • the linking segment 530 extends substantially orthogonally to the first and second segments 526 and 528 of signal line 514
  • the linking segment 536 extends substantially orthogonally to the third and fourth segments 532 and 534 of the second shield line 516
  • the linking segment 542 extends substantially orthogonally to the segments 538 and 540 of the second signal line 518.
  • substantially orthogonally means that the linking segments extend orthogonally to the other indicated segments to within reasonable tolerances of fabrication and measurement.
  • one or both of the linking segments may extend at an angle other than orthogonal relative to the primary direction of the segments interconnected by such linking segment.
  • An advantage of the architecture of FIG. 2 is that the offsets (i.e. bends) provided in the signal lines and shield lines enable a region of a shield line from the upper wiring level M3 to vertically overlap a region of a shield line from the lower wiring level M2.
  • the shield line 512 of the upper wiring level vertically overlaps a region of the shield line 516 of the lower wiring level within an illustrated overlap region 544; with the illustrated fourth segment 534 of the second shield line 516 extending to under the first segment 520 of the first shield line 512.
  • Vertical interconnects 546 are provided within the overlap region 544 to electrically couple the shield lines 516 and 512 to one another.
  • the vertical interconnects 546 are illustrated in dashed-line (phantom) in the top view of FIG. 2 to indicate that the interconnects are beneath line 512.
  • the vertical interconnects may extend substantially vertically, with the term "substantially vertically” meaning that the interconnects are vertical to within reasonable tolerances of fabrication and measurement.
  • the illustrated embodiment shows two vertical interconnects within the overlap region 544. In other embodiments there may be only a single interconnect provided within the overlap region, or there may be more than two interconnects provided within the overlap region. Also, although the interconnects 546 are square along the top view of FIG. 2, in other embodiments the interconnects may have other shapes, including, for example, rectangular, circular, elliptical, etc.
  • the first shield line 512 within the upper wiring level may be considered to have a first portion 548 extending in the first direction of axis 503, a second portion 550 which extends in a second direction (e.g., the direction of axis 505), and a third portion 552 which extends in the first direction.
  • the second portion 550 interconnects the first portion 548 with the third portion 552.
  • the first signal line 514 within the upper wiring layer is immediately adjacent the first shield line, and has a fourth portion 554, a fifth portion 556, and a sixth portion 558.
  • the fourth, fifth and sixth portions (554, 556 and 558) are substantially parallel to the third, second and first portions (552, 550 and 548), respectively.
  • substantially parallel means parallel to within reasonable tolerances of fabrication and measurement.
  • the second shield line 516 within the lower wiring level comprises a seventh portion 560 and an eighth portion 562; with the seventh portion 560 being substantially vertically aligned with the third portion 552 of first shield line 512, and the eighth portion 562 being substantially vertically aligned with the fourth portion 554 of the first signal line 514.
  • the second shield line 516 also comprises a ninth portion 564 which interconnects the seventh portion 560 with the eighth portion 562.
  • the seventh portion 560 extends continuously from under the third portion 552 of first shield line 512 to under the sixth portion 558 of first signal line 514; with the seventh portion 560 being substantially vertically aligned with the third portion 552 of first shield line 512.
  • the overlap region 544 extends across the third portion 552 of first shield line 512 and the seventh portion 560 of second shield line 516, and the vertical interconnects 546 electrically connect the third portion 552 with the seventh portion 560.
  • FIG. 3 shows an enlarged view of a region "3" of the assembly 510 of FIG. 2, and will be used to describe some of the dimensional relationships within such assembly.
  • the shield line 512 may be considered an individual first shield line
  • the signal line 514 may be considered an individual first signal line representative of a plurality of signal lines within the upper wiring level.
  • the second shield line 516 may be considered an individual second shield line representative of a plurality of second shield lines within the lower wiring level
  • the second signal line 518 may be considered an individual second signal line representative of a plurality of second signal lines within the lower wiring level.
  • the first signal line 514 is immediately adjacent the first shield line 512, with the term "immediately adjacent” indicating that there are no other signal lines between signal line 514 and shield line 512 within the upper wiring level (i.e., that signal line 514 is the signal line closest to shield line 512 within the upper wiring level).
  • the first shield line 512 has the first shield line first segment 520, the first shield line second segment 522, and the linking segment 524 between the first and second segments 520 and 522.
  • the linking segment 524 may be referred to as a first shield line linking segment.
  • the signal line 514 includes the first signal line first segment 526, the first signal line second segment 528, and the linking segment 530 between the first and second segments 526 and 528.
  • the linking segment 530 may be referred to as a first signal line linking segment.
  • the first shield line linking segment 524 is offset from the first signal line linking segment 530 along the first direction of axis 503 by a first distance Di.
  • the second shield line 516 comprises a third segment 532 that is under a region of the first signal line first segment 526.
  • the second shield line 516 also has a fourth segment 534 that extends to under a region of the signal line second segment 528, and that also extends to under a region of the first shield line first segment 520.
  • a second shield line linking segment 536 connects the third segment 532 with the fourth segment 534.
  • the vertical interconnects 546 extend between the first shield line first segment 520 and the second shield line fourth segment 534 to electrically couple the first and second shield lines 512 and 516 to one another (i.e., to electrically couple the shield line 512 from the upper wiring layer with the shield line 516 from the lower wiring layer).
  • the second shield line linking segment 536 is offset from the first signal line linking segment 530 along the first direction of axis 503 by a second distance D 2 .
  • the second distance D 2 is larger than the first distance Di, and in some embodiments may be at least double the first distance.
  • FIG. 3 also shows that the first shield line 512 and first signal line 514 are spaced from one another by a third distance D 3 corresponding to a pitch, and shows that adjacent corners of shield line 512 and signal line 514 are spaced by a fourth distance D 4 which extends along a direction corresponding to an axis 507.
  • the direction of axis 507 is intermediate the directions of axes 503 and 505, and in some embodiments may be about 45° (i.e., halfway between axes 503 and 505).
  • the D 4 shift may be considered equivalent to a D 3 shift in combination with a Di shift.
  • the illustrated linking segments may be considered to define steps or bridge paths along the various shield lines and signal lines.
  • the wiring level M2 of FIGS. 2 and 3 may be over another wiring level analogous to the level Ml of FIG. 1.
  • FIGS. 4 and 4A show a region of assembly 510 beneath the region illustrated in FIGS. 2 and 3, and specifically show a third wiring level Ml under the second wiring level M2 (the level M3 is not shown in FIGS. 4 and 4A in order to simplify the drawings).
  • the illustrated region of the wiring level M2 of FIG. 4 has the second shield line 516 between a pair of second signal lines 518.
  • the wiring level Ml includes a signal line 566 between a pair of shield lines 568.
  • the signal lines and shield lines within the third wiring level Ml may be referred to as third signal lines and third shield lines in order to distinguish them from the second shield lines and second signal lines within the second wiring level M2, and to distinguish them from the first shield lines and first signal lines within the first wiring level M3 (FIG. 2).
  • the shield lines and signal lines within the wiring level Ml extend primarily along the direction of axis 505, or in other words extend substantially orthogonally to the third and fourth segments 532 and 534 of the second shield line 516.
  • the third shield lines 568 are electrically coupled to the third and fourth segments 532 and 534 of the second shield line 516 through vertical interconnects 570 (or alternatively considered, are electrically coupled to the seventh and eighth portions 560 and 562 of the second shield line through the vertical interconnects 570).
  • the vertical interconnects 546 i.e., the interconnects utilized to connect shield lines within the first wiring level M3 to shield lines within the second wiring level M2
  • the interconnects 570 may be referred to as a second set of interconnects in order to distinguish the interconnects 570 from the interconnects 546.
  • the interconnects 546 and 570 are shown to be square and circular in the top view of FIG.
  • interconnects 546 and 570 may be the same shape as one another or may be different shapes; and may be of any suitable shapes, including, for example, square, rectangular, circular, elliptical, etc.
  • the vertical interconnects 570 are illustrated in dashed-line (phantom) in the top view of FIG. 4 to indicate that the interconnects 570 are beneath line 516, and the interconnects 546 are illustrated in dashed-line view to indicate that it is locations of interconnects 546 illustrated in such view (the interconnects 546 may or may not be visible in the view of FIG. 4 depending on the particular architecture of the interconnects 546 and on whether the location chosen for the view of FIG. 4 is a cross-section through the interconnects 546).
  • FIGS. 5-8 further illustrate an assembly 510 comprising the wiring levels Ml
  • FIG. 5 is an exploded view showing the wiring levels stacked one atop another; while FIGS. 6-8 show each of the individual wiring levels Ml, M2 and M3 in isolation.
  • the wiring within level M3 is shown to be slightly thicker than the wiring within levels M2 and Ml. In practice the wiring within levels M1-M3 may all be the same thickness or some wiring may be of different thickness relative to other wiring, depending on the application.
  • the assembly 510 of FIGS. 5-8 may be considered to comprise a connecting region 572 which encompasses the interconnects 546, and more specifically
  • the linking regions of the shield lines and signal lines within the levels M2 and M3 are within the connecting region 572 (such linking regions are described above with reference to FIG. 2, and may be alternatively referred to as bending regions, bridge regions, etc.).
  • the connecting region may be considered to comprise a first boundary 571 and a second boundary 573.
  • a first shield region 574 extends outwardly from the connecting region 572 along the direction of axis 505, and a second shield region 576 extends outwardly from the connecting region 572 along the direction of axis 503.
  • the signal lines 514 of level M3 vertically overlap the shield lines 516 of level M2 within the first and second shield regions 574 and 576; and the shield lines 512 of level M3 vertically overlap the signal lines 518 of level M2 within the first and second shield regions.
  • all of the shield lines within the wiring levels M3, M2 and Ml are electrically connected with Vss (the voltage Vss may be any suitable voltage, and in some embodiments may be ground or a negative supply voltage).
  • the various shield lines from the wiring levels M3, M2 and Ml together may form a three-dimensional mesh 578 of the type shown in FIG. 9, with such mesh having consistent voltage throughout.
  • the mesh of FIG. 9 comprises the first shield lines 512 from the upper wiring level M3, the second shield lines 516 from the intermediate wiring level M2, and the third shield lines 568 from the lower wiring level Ml.
  • the shield lines 512, 516 and 568 are illustrated with different thicknesses of lines so they may be distinguished from one another in the diagram of FIG. 9.
  • the shield lines may all have substantially the same thickness as one another (or in some embodiments, some of the shield lines may have different thicknesses than others if such is suitable for particular applications).
  • Regions where shield lines from level M3 connect with shield lines from level M2 are shown as overlap regions 544, and such would comprise the vertical interconnects 546 (shown in FIGS. 5-8, but not shown in FIG. 9).
  • each of the first shield lines 512 from the top wiring level M3 is directly connected to a pair of the second shield lines 516 from the intermediate wiring level M2; and conversely, each of the second shield lines 516 from the intermediate wiring level is directly connected to a pair of the first shield lines 512 from the top wiring level.
  • the shield lines 512 and 516 comprise the bridging regions (i.e. linking regions) 524 and 536 described previously.
  • FIG. 9 shows two of the first shield lines 512 labeled as 512a and 512b to distinguish them from others of the first shield lines, and shows two of the second shield lines 516 labeled as 516a and 516b to distinguish them from others of the second shield lines.
  • the first shield line 512a extends primarily along a first direction corresponding to the axis 503, and extends along two first paths 580 and 582 which are laterally offset relative to one another.
  • the second shield line 516b extends primarily along the first direction of axis 503, and extends along two second paths 590 and 592 which are laterally offset relative to one another.
  • the first shield line 512a is primarily laterally offset from the second shield lines 516 except that the first paths 580 and 582 have overlap regions 544 where portions of the first shield line 512a overlap portions of the second shield lines 516a and 516b. Specific overlap regions where portions of the first shield line 512a overlap portions of second shield lines 516a and 516b are labeled as 584 and 586.
  • the path 580 of shield line 512a overlaps a second shield line 516a, while the path 582 of the same first shield line 512a overlaps a different second shield line 516b.
  • the second shield line 516b connects with two different first shield lines 512a and 512b.
  • Vertical interconnects 546 are provided within the overlap regions 544 to connect the first shield lines 512 with the second shield lines 516.
  • the shield lines 568 of the bottom wiring level Ml may be connected to the shield lines 516 of the intermediate wiring level M2 through vertical contacts 570 (not shown in FIG. 9) of the type described above with reference to FIG. 4.
  • the interwoven interconnections between the first, second and third wiring levels within mesh 578 enable consistent voltage to be maintained throughout all of the shield lines that are intertwined within such mesh. Such may alleviate or prevent the problems described above in the "Background" section of this disclosure.
  • FIGS. 5-9 illustrate an embodiment in which all of the shield lines are maintained at a common voltage (illustrated as being Vss, but in other embodiments it may be a common voltage other than Vss).
  • the shield lines maybe subdivided amongst groups maintained at different voltages relative to one another. For instance, in some embodiments some of the shield lines may be maintained at Vss while others are maintained at Vdd. An example embodiment in which some shield lines are electrically connected with Vss while others are electrically connected with Vdd is described with reference to FIGS. 10-14.
  • FIGS. 10-13 The wiring levels Ml, M2 and M3 of assembly 10 are illustrated in FIGS. 10-13.
  • FIG. 10 is an exploded view showing the wiring levels stacked one atop another; while FIGS. 11-13 show each of the individual wiring levels Ml, M2 and M3 in isolation.
  • FIGS. 10-13 The general architecture of FIGS. 10-13 is similar to that described above with service to FIGS. 5-8, except that additional complexity is introduced so that the shield lines within the various levels M1-M3 may comprise some shield lines electrically connected with Vdd and others are electrically connected with Vss.
  • the various shield lines from the wiring levels M3, M2 and Ml together may form a pair of three-dimensional meshes similar to the mesh shown in FIG. 9.
  • One of such meshes is electrically connected with Vss and the other is electrically connected with Vdd.
  • FIG. 14 shows a three-dimensional mesh 88 which is electrically connected with Vss, and a similar mesh (not shown) would be electrically connected with Vdd.
  • the assemblies discussed above may be incorporated into integrated circuitry supported by an underlying semiconductor substrate (not shown).
  • the substrate may, for example, comprise, consist essentially of, or consist of monocrystalline silicon.
  • semiconductor substrate means any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials), and semiconductive material layers (either alone or in assemblies comprising other materials).
  • substrate refers to any supporting structure, including, but not limited to, the semiconductor substrates described above.
  • the invention includes architectures which reduce distances between interconnects coupling the shield lines of an upper wiring layer (e.g., M3) to the shield lines of a lower wiring layer (e.g., M2), which enables decreased via- bypass pitch.
  • the signal lines within a given via-bypass pitch may be coupled with a common bus. Accordingly, decreasing the via-bypass pitch may lead to a reduction of the number of signal lines associated with each bus, and thus may lead to reduced resistance across the signal lines and associated buses.
  • FIGS. 15A and 15B show the assembly 510 comprising the arrangement of FIG. 5, but illustrated in an alternative manner relative to FIG. 5.
  • the assembly 510 is shown in top view in FIG. 15 A, with the lines of the wiring layers being heavily compressed.
  • An expanded region of the top wiring layer M3 is shown in cross-sectional side view in FIG. 15B to assist the reader in understanding the top view of FIG. 15A.
  • An approximate location of the illustrated portion of FIG. 5 is diagrammatically illustrated in FIG. 15A as corresponding to region labeled "FIG. 5".
  • the connecting region 572 is
  • FIG. 15 A diagrammatically illustrated with a line traversing the top view of FIG. 15 A.
  • a continuing goal of semiconductor fabrication is to increase circuit density (i.e., to increase the level of integration).
  • a problem with the architecture of FIGS. 5, 15A and 15B is that there may be a large distance along individual shield lines of a given wiring layer (e.g., shield lines 512 of wiring layer M3 shown in FIGS. 5 and 6) between the interconnects (546 of FIG. 5) utilized to couple the shield lines to shield lines of other wiring layers (e.g., shield lines 516 of wiring layer M2, shown in FIGS. 5 and 7).
  • Such problem is illustrated in the top view of FIG. 15A with an arrow 320 indicating a pitch between interconnects (i.e., a via-bypass pitch).
  • the arrow 320 is open-ended to indicate that the full via-bypass pitch is not visible in the top view of FIG. 15A.
  • the signal lines are coupled with associated buses (i.e., electrical pathways), and the number of signal lines coupled with an individual bus may be correlated with the via-bypass pitch.
  • buses i.e., electrical pathways
  • the shield lines e.g., increased voltage along the shield lines and/or increased current along the shield lines.
  • increased density of signal lines may lead to increased resistance along the signal lines and the associated buses. Accordingly, it would be desired to develop new architectures which reduce distances between interconnects coupling shield lines of one wiring layer to the shield lines of another wiring layer, and which reduce resistances along the signal lines and associated buses.
  • one or more redundant (dummy) lanes are provided within the shield line/signal line circuitry of wiring layers (e.g., M2 and M3) in order to enable a reduction of the via-bypass pitch.
  • bus lines may be considered to be arranged amongst subgroups by providing one or more redundant (dummy) lanes within the signal line/shield line circuitry.
  • the number of bus lines may be represented as "n”, and the bus lines may be arranged into "m” subgroups; with each of the "m” subgroups having "k” signal lines.
  • the via-bypass pitch on the shield lines may be 1/m as compared to architectures in which the bus lines are not consolidated into the subgroups.
  • the term “dummy” may be utilized to describe the redundant lanes, with such term indicating that the redundant lanes are different than the other lanes comprising shield/signal lines.
  • the label “dummy” is utilized to identify structures which have no function other than to serve as spacers (i.e., which are not utilized as wiring or components of integrated circuitry). Such is generally not the case in the present context.
  • the "dummy" structures may include circuitry (for instance, shield lines), and the label “dummy” may be utilized to indicate that a structure (for instance, a shield line) within a wiring layer has a different configuration and/or use than other similar structures across the wiring layer having more traditional
  • the dummy (i.e., redundant) structures may be configured as "lanes", or may correspond to other suitable structures and regions.
  • Example calculations relative to a configuration having 288 signal lines indicate that a single group (i.e., only one sub-group) leads to a worst resistance value of 40.95 ohms, two subgroups leads to the worst resistance value being 21.85 ohms, eight subgroups leads to the worst resistance value being 12.23 ohms, and 16 subgroups leads to the worst resistance value being 6.73 ohms. Accordingly, arrangement of the signal lines amongst subgroups may lead to substantial improvement (specifically, reduction in resistance).
  • the calculated resistance values are provided to assist the reader in understanding the invention, and are not to be utilized for limiting the claims that follow; except to the extent, if any, that such values are expressly recited in the claims.
  • FIGS. 16A and 16B show an assembly 10 analogous to the assembly 510 of FIGS. 15A and 15B.
  • Such assembly may comprise the wiring layers Ml, M2 and M3 (analogous to those of FIG. 5) stacked one atop another.
  • FIG. 16A shows a top view with the lines of the upper wiring layer M3 being heavily compressed (analogous to the top view of FIG. 15A), and
  • FIG. 16B shows an expanded region of the top wiring layer M3 in cross-sectional side view.
  • the wiring layer M3 of FIG. 16B comprises shield lines 12 and signal lines 14 analogous to the shield lines 512 and signal lines 514 of FIG. 15B.
  • the wiring layer M3 of FIGS. 16A and 16B comprises a redundant
  • (dummy) lane 15 which segregates the shield lines/signal lines of the wiring layer M3 into subgroups 16a and 16b.
  • a connecting region 18a is associated with subgroup 16a, and a connecting region 18b is associated with subgroup 16b; and such connecting regions 18a/18b are diagrammatically illustrated with lines traversing the top view of FIG. 16A.
  • the connecting regions 18a/18b are analogous to the connecting region 372 of FIG 15A.
  • the connecting regions 18a/18b are on a reduced pitch relative to the connecting region 372 of FIG. 15A, which reduces the via-bypass pitch.
  • an arrow 21 is provided in FIG. 16A to diagrammatically illustrate a via-bypass pitch.
  • Such via-bypass pitch 21 is substantially reduced (and in some embodiments may be reduced by about half) as compared to the via-bypass pitch 320 of the assembly 510 of FIG. 15A.
  • the reduction of the via-bypass pitch may substantially reduce resistance along the signal lines and associated buses of assembly 10 of FIG. 16A as compared to the assembly 510 of FIG. 15A.
  • FIGS. 17 and 18 illustrate an alternative view of the assembly 10 of FIG. 16; with the view of FIG. 18 being an expanded region of FIG. 17.
  • FIGS. 17 and 18 show wiring layer M3 overlaid on wiring layer M2; and show interconnects 20 and 22 analogous to the interconnects 546 and 570, respectively, which were described above with reference to FIG. 5.
  • the interconnects 20 vertically connect shield lines of wiring layer M2 with shield lines of wiring layer M3
  • the interconnects 22 vertically connect shield lines of wiring layer M2 with shield lines of wiring layer Ml (not shown in FIGS. 17 and 18).
  • the interconnects 20 and 22 are shown as square features and circular features, respectively, to enable the interconnects 20 to be readily distinguished from interconnects 22 in the illustrations, but in other applications the interconnects 20 and 22 may have other shapes; and may be the same shape as one another, or different shapes relative to one another.
  • the wiring layers M2 and M3 are shown in dashed-line view and solid-line view, respectively, in FIGS. 17 and 18 so that they may be distinguished from one another.
  • FIG. 18 shows a pair of lines (Linel and Line2) provided across the assembly 10, with the status (configuration) of materials in the M2 and M3 wiring layers at locations of each line being described in a table beneath the diagram of assembly 10.
  • the signal lines are represented as "Sig”
  • the shield lines are represented as "Vss”.
  • Vss is chosen in that it is common for the shield lines of the wiring layers M3, M2 and Ml to be electrically connected with Vss (with it being understood that the voltage Vss may be any suitable voltage, and in some embodiments may be ground or a negative supply voltage).
  • the shield lines may be coupled with voltage other than Vss in some embodiments.
  • the table of FIG. 18 shows that the redundant lane 15 differs from other locations of the wiring layers M2/M3 along the position of Linel.
  • the redundant lane 15 comprises a space below a signal line of wiring layer M3, and comprises a space above the shield line of wiring layer M2.
  • the redundant lane 15 has a same configuration as other locations of the wiring layers M2/M3 at the position of Line2 and simply comprises a Vss line of M3 over a signal line of M2, and a signal line of M3 over a Vss line of M2.
  • space is utilized to describe locations along Linel, it is to be understood that the locations indicated as “space” may comprise insulative materials (e.g., silicon nitride, silicon dioxide, etc.).
  • FIG. 19 compares the assembly 510 (described above with reference to FIG. 15A) with example assemblies 10, 10a and 10b of other embodiments.
  • the assembly 10 is similar to that described above with reference to FIG. 16A.
  • the assemblies 10a and 10b incorporate additional redundant lanes 15 to thereby form additional subgroups.
  • assembly 10 has two subgroups 16a and 16b; assembly 10a has four subgroups 16a, 16b, 16c and 16d; and assembly 10b has eight subgroups 16a, 16b, 16c, 16d, 16e, 16f, 16g and 16h.
  • Example resistances across signal lines and associated buses within the subgroups are estimated to be about 40.95 ohms for assembly 300; 21.85 ohms for assembly 10; 12.23 ohms for assembly 10a; and 6.73 ohms for assembly 10b. Accordingly, arrangement of the signal lines into subgroups within the assemblies 10, 10a and 10b may lead to substantial improvement (specifically, reduction in resistance across signal lines and associated buses).
  • FIG. 20 shows top views of a pair of example assemblies 10c and lOd which may be utilized in some embodiments.
  • the assembly 10c has connecting regions 18a and 18b which are mirrored about a first plane 5 through a middle of the assembly, and which are also mirrored about a second plane 7 through the middle of the assembly and orthogonal to the first plane 5.
  • the connecting region 18b is shown with a heavier line than the connecting region 18a so that the connecting regions 18a and 18b can be distinguished from one another.
  • a region A is identified in assembly 10c, and such region is discussed in more detail below with reference to FIGS. 21-27.
  • the assembly lOd has connecting regions 18a and 18b which are mirrored about the plane 5 through the middle of the assembly. Regions B and B' are identified in assembly lOd, and such regions are discussed in more detail below with reference to FIGS. 28-36.
  • FIGS. 21-24 illustrate assembly 10c, and show the wiring layers Ml, M2 and M3.
  • FIG. 21 is an exploded view showing the wiring layers stacked one atop another; while FIGS. 22-24 show each of the individual wiring layers Ml, M2 and M3 in isolation.
  • the wiring layer Ml includes signal lines 30 alternating with shield lines 32.
  • the signal lines and shield lines are spaced from one another by insulative material 34.
  • the shield lines 32 are shown supplied with (i.e., coupled with) a fixed voltage identified as Vss, but may be supplied with any suitable voltage.
  • the signal lines 30 and shield lines 32 may comprise any suitable electrically conductive composition(s), such as, for example, one or more of various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, etc.), metal-containing compositions (e.g., metal silicide, metal nitride, metal carbide, etc.), and/or conductively-doped
  • the conductive materials of the signal lines 30 and shield lines 32 may be homogenous, or may comprise two or more discrete compositions.
  • the conductive material of the shield lines 32 may be the same as the conductive material of the signal lines 30, or may be different from the conductive material of the signal lines.
  • the insulative material 34 may comprise any suitable composition, and in some embodiments may comprise, consist essentially of, or consist of one or both of silicon dioxide and silicon nitride.
  • the insulative material 34 may be homogenous, or may comprise two or more discrete compositions.
  • the interconnects 22 (only some of which are labeled) are shown along the shield lines 32, with such interconnects 22 being utilized to vertically connect shield lines 32 of wiring layer Ml with shield lines 42 of wiring layer M2 (shown in FIG. 23).
  • the wiring layer M2 includes signal lines 40 alternating with shield lines 42.
  • the signal lines and shield lines are spaced from one another by the insulative material 34.
  • the shield lines 42 are shown coupled with a fixed voltage identified as Vss, but may be coupled with any suitable voltage.
  • the signal lines 40 and shield lines 42 may comprise any suitable electrically conductive composition(s), such as, for example, one or more of various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, etc.), metal-containing compositions (e.g., metal silicide, metal nitride, metal carbide, etc.), and/or conductively-doped
  • the conductive materials of the signal lines 40 and shield lines 42 may be homogenous, or may comprise two or more discrete compositions.
  • the conductive material of the shield lines 42 may be the same as the conductive material of the signal lines 40, or may be different from the conductive material of the signal lines.
  • the lines 40/42 of layer M2 may be the same composition as one or both of the lines 30/32 of layer Ml, or may be different compositions from one or both of the lines 30/32 of layer Ml.
  • the interconnects 22 are shown along the shield lines 42, with such interconnects 22 being utilized to vertically connect shield lines 42 of wiring layer M2 with shield lines 32 of wiring layer Ml (shown in FIG. 22).
  • the interconnects 20 are also shown along the shield lines 42, with such interconnects 20 being utilized to vertically connect shield lines 42 of wiring layer M2 with shield lines 12 of wiring layer M3 (shown in FIG. 24).
  • the interconnects 20 are shown in paired arrangements (i.e., two interconnects 20 are in each location where shield lines 42 of wiring layer M2 connect with shield lines 12 of wiring layer M3). In other embodiments, only a single interconnect 20 may be in at least some of such locations; and in some embodiments, more than two interconnects 20 may be in at least some of such locations.
  • the wiring layer M3 includes signal lines 14 alternating with shield lines 12.
  • the signal lines and shield lines are spaced from one another by the insulative material 34.
  • the shield lines 12 are shown coupled with a fixed voltage identified as Vss, but may be coupled with any suitable voltage.
  • the signal lines 14 and shield lines 12 may comprise any suitable electrically conductive composition(s), such as, for example, one or more of various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, etc.), metal-containing compositions (e.g., metal silicide, metal nitride, metal carbide, etc.), and/or conductively-doped
  • the conductive materials of the signal lines 14 and shield lines 12 may be homogenous, or may comprise two or more discrete compositions.
  • the conductive material of the shield lines 12 may be the same as the conductive material of the signal lines 14, or may be different from the conductive material of the signal lines.
  • the lines 12/14 of wiring layer M3 may be the same composition as one or more of the lines 30/32 and 40/42 of wiring layers Ml and M2, or may be different compositions from one or more of the lines 30/32 and 40/42 of wiring layers Ml and M2.
  • the interconnects 20 are shown along the shield lines 12, with such interconnects 20 being utilized to vertically connect shield lines 12 of wiring layer M3 with shield lines 42 of wiring layer M2 (shown in FIG. 23).
  • the overlay regions 18a and 18b are diagrammatically indicated in FIGS. 23 and 24, and such correspond to regions where the interconnects 20 vertically connect shield lines 12 of wiring layer M3 with the shield lines 42 of wiring layer M2.
  • Region A is diagrammatically illustrated relative to the wiring layers M2 and M3 of FIGS. 23 and 24, and such region comprises a redundant (dummy) region (e.g., lane).
  • a redundant region e.g., lane.
  • One of the shield lines 42 of FIG. 23 is identified with a label 42a to distinguish such shield line from the others, and the redundant region of wiring layer M2 includes a widened structure 45 along the shield line 42a.
  • One of the shield lines 12 of FIG. 24 is identified with a label 12a to distinguish such shield line from the others, and the redundant region of wiring layer M3 includes a widened structure 17 along the shield line 12a.
  • the wiring layers M2 and M3 of FIGS. 23 and 24 may be referred to as a lower-level wiring layer and an upper-level wiring layer, respectively; and may be considered to comprise the shown first wiring tracks, second wiring tracks, third wiring tracks and fourth wiring tracks (labeled as first, second, third and fourth tracks in FIGS. 23 and 24).
  • the first, second, third and fourth wiring tracks of the upper wiring layer M3 directly overlay the first, second, third and fourth wiring tracks of the lower wiring layer M2, and are within the redundant regions (i.e., redundant lanes).
  • the first, second, third and fourth wiring tracks extend in a first direction along an x-axis (with the x-axis being shown adjacent the portions of assembly 10c along FIGS.
  • the first and third wiring tracks sandwich the second wiring track therebetween; and the second and fourth wiring tracks sandwich the third wiring track therebetween.
  • the lower-level wiring layer M2 may be considered to comprise a first wiring corresponding to the wiring of shield line 42a.
  • the first wiring may be considered to have a first portion 50 extending along the second wiring track, a second portion 52 extending along the first wiring track, and a third portion 54 extending along the third wiring track.
  • the first portion 50 may be considered to comprise a first side 51 and a second side 53 in opposing relation to the first side.
  • the second portion 52 may be considered to be offset from the first side 51 of the first portion 50 by a first offset region 56
  • the third portion 54 may be considered to be offset from the second side 53 by a second offset region 58.
  • the first, second and third portions 50, 52 and 54 extend along the direction of the x-axis.
  • the second portion 52 is offset from the second wiring track by projections 55 and 57 which extend along a y-axis.
  • the third portion 54 is offset from the second wiring track by projections 59 and 61 which extend along the y-axis.
  • the first, second and third portions 50, 52 and 54 may be considered to extend along a first direction (the direction of the x-axis); and the projections 55, 57, 59 and 61 may be considered to extend along a second direction (the direction of the y-axis).
  • the second direction is orthogonal to the first direction. In other embodiments, the first and second directions may intersect one another without being orthogonal to one another.
  • the upper-level wiring layer M3 may be considered to comprise a second wiring (i.e., the wiring of shield line 12a).
  • the second wiring 12a is connected to the first wiring 42a through the interconnects 20a and 20b (with interconnects 20a and 20b being identical to the other interconnects 20, but being labeled 20a and 20b so that they may be separately identified from the other interconnects).
  • the second wiring 12a may be considered to comprise a fourth portion 60 which extends along the third wiring track, and to comprise a fifth portion 62 which extends along the second wiring track.
  • the third portion 54 of the first wiring 42a (FIG. 23) is electrically coupled to the fourth portion 60 of the second wiring 12a (FIG.
  • FIG. 26 shows an overlay of an expanded region of FIGS. 23 and 24; and shows the overlap of the third portion 54 with the fourth portion 60, and the overlap of the first portion 50 and fifth portion 62.
  • FIG. 25 shows a cross-section along the line 25-25 of FIGS. 23 and 24, and shows the interconnects 20a/20b extending through insulative material 34 to electrically couple shield line 12a of the upper-level wiring layer M3 with the shield line 42a of the lower-level wiring layer M2.
  • the illustrated embodiment shows two contact plugs corresponding to interconnects 20a/20b, in other embodiments there may be only a single contact plug, and in yet other embodiments there may be more than two contact plugs.
  • the first wiring 42a of lower-level wiring layer M2 may be considered to comprise the first portion 50, second portion 52 and third portion 54 described above; and may be further considered to comprise a fourth portion
  • the second wiring 12a of the upper-level wiring layer M3 may be considered to comprise portion 60 as a sixth portion extending along the third wiring track, and portion 62 as a seventh portion extending along the second wiring track.
  • the second wiring 12a also comprises an eighth portion 64 extending along the fourth wiring track, a ninth portion 66 extending along the y-axis and coupling the sixth portion 60 with the seventh portion 62, and a tenth portion 68 extending along the y-axis and coupling the sixth portion 60 with the eighth portion 64.
  • the contact plugs 20b may be considered to penetrate the insulative layer corresponding to insulative material 34 and couple the first portion 50 of the first wiring 42a with the seventh portion 62 of the second wiring 12a.
  • the lower-level wiring layer M2 may be considered to further comprise a third wiring 40a (i.e., one of the signal lines) which is electrically disconnected from the first wiring 42a; and which has an eleventh portion 70 along the third wiring track, a twelfth portion 72 along the fourth wiring track, and a thirteenth portion 71 which extends along the y-axis and couples the eleventh portion 70 with the twelfth portion 72.
  • a third wiring 40a i.e., one of the signal lines
  • the upper-level wiring layer M3 may be considered to further comprise a fourth wiring 14a (i.e., one of the signal lines) which is electrically disconnected from the first wiring 12a, and which has a fourteenth portion 80 along the second wiring track, a fifteenth portion 82 along the first wiring track, and a sixteenth portion 83 which extends along the y-axis and couples the fourteenth portion 80 with the fifteenth portion 82.
  • a fourth wiring 14a i.e., one of the signal lines
  • the shield line 12a of the upper-level wiring layer M3 may be referred to as a first shield line, and another shield line 12b may be referred to as a second shield line.
  • the second shield line 12b has a portion 90 extending along the first wiring track and vertically overlapping the second portion 52 of the shield line 42a of the lower-level wiring layer M2.
  • the portion 90 of shield line 12b is coupled with the portion 52 of shield line 42a through interconnects labeled as 20c (shown in FIGS. 23 and 24, and also shown in FIG. 26).
  • the first, second and third portions 50, 52 and 54 of the shield line 42a within wiring layer M2, together with the projections 55, 57, 59 and 61 of the shield line 42a, may be considered to comprise the widened structure 45 along the shield line 42a (shown in FIG. 23).
  • FIGS. 27A-C illustrate some example embodiments of such widened structure 45.
  • FIG. 27A shows the widened structure 45 of FIG. 23.
  • FIG. 27B shows a widened structure 45a having a configuration in which a region of projection 55 is aligned with a region of projection 59, and a region of projection 57 is aligned with a region of projection 61.
  • each insulative region 102 may be considered to comprise a first void region 104 corresponding to a first offset region 101 between the first portion 50 of shield line 42a and the second portion 52 of the shield line 42a, and to comprise a second void region 106 corresponding to a second offset region 103 between the first portion 50 and the third portion 54.
  • the regions 104 and 106 are referred to as "void" regions to indicate that the regions do not comprise conductive material. It is to be understood that such regions may or may not be empty; and, for example, in some embodiments the void regions 104 and 106 may comprise insulative material, such as, for example, one or both of silicon dioxide and silicon nitride.
  • the insulative region 102 within the widened structures (45/45a) is optional, and may be replaced with conductive material.
  • FIG. 27C shows a widened structure 45b having a configuration in which conductive material of shield line 42a fills the first and second offset regions 101 and 103 (i.e., a configuration in which the first and second offset regions 101 and 103 are entirely comprised by conductive material).
  • the sixth, seventh, eighth, ninth and tenth portions 60, 62, 64, 66 and 68 of the shield line 12a within wiring layer M3 may be considered to comprise the widened structure 17 of FIG. 24.
  • the ninth and tenth portions 66 and 68 include respective parts that are aligned along the y-axis, and include parts that are not aligned along the y-axis.
  • an entirety of the ninth portion 66 may be aligned with an entirety of the tenth portion 68 along the y-axis; and in some embodiments, an entirety of the ninth portion 66 may be out of alignment with an entirety of the tenth portion 68 along the y-axis (i.e., may be displaced along the x-axis relative to the tenth portion).
  • conductive material of shield line 12a extends entirely across the widened structure 17.
  • an insulative region analogous to the region 102 of FIGS. 27A and 27B may be provided within the widened structure 17.
  • FIGS. 28-31 illustrate assembly lOd (previously described in FIG. 20), and show the wiring layers Ml, M2 and M3.
  • FIG. 28 is an exploded view showing the wiring layers stacked one atop another; while FIGS. 29-31 show each of the individual wiring layers Ml, M2 and M3 in isolation.
  • the wiring layer Ml includes signal lines 30 alternating with shield lines 32.
  • the signal lines and shield lines are spaced from one another by insulative material 34.
  • the shield lines 32 are shown coupled with a fixed voltage identified as Vss, but may be coupled with any suitable voltage.
  • the interconnects 22 are shown along the shield lines 32, with such interconnects 22 being utilized to vertically connect shield lines 32 of wiring layer Ml with shield lines 42 of wiring layer M2 (shown in FIG. 30).
  • the wiring layer M2 includes signal lines 40 alternating with shield lines 42.
  • the signal lines and shield lines are spaced from one another by the insulative material 34.
  • the shield lines 42 are shown coupled with a fixed voltage identified as Vss, but may be coupled with any suitable voltage.
  • the interconnects 22 are shown along the shield lines 42, with such interconnects 22 being utilized to vertically connect shield lines 42 of wiring layer M2 with shield lines 32 of wiring layer Ml (shown in FIG. 29).
  • the interconnects 20 are also shown along the shield lines 42, with such interconnects 20 being utilized to vertically connect shield lines 42 of wiring layer M2 with shield lines 12 of wiring layer M3 (shown in FIG. 31).
  • the interconnects 20 are shown in paired arrangements (i.e., two interconnects 20 are in each location where shield lines 42 of wiring layer M2 are to connect with shield lines 12 of wiring layer M3). In other embodiments, only a single interconnect 20 may be in at least some of such locations; and in some embodiments, more than two interconnects 20 may be in at least some of such locations.
  • the wiring layer M3 includes signal lines 14 alternating with shield lines 12.
  • the signal lines and shield lines are spaced from one another by the insulative material 34.
  • the shield lines 12 are shown coupled with a fixed voltage identified as Vss, but may be coupled with any suitable voltage.
  • the interconnects 20 are also shown along the shield lines 12, with such interconnects 20 being utilized to vertically connect shield lines 12 of wiring layer M3 with shield lines 42 of wiring layer M2 (shown in FIG. 30).
  • the overlay regions 18a and 18b are diagrammatically indicated in FIGS. 30 and 31, and such correspond to regions where the interconnects 20 vertically connect shield lines 12 of wiring layer M3 with the shield lines 42 of wiring layer M2.
  • Regions B and B' are diagrammatically illustrated relative to the wiring layers M2 and M3 of FIGS. 30 and 31, and such regions comprise redundant (dummy) regions (e.g., lanes).
  • one of the shield lines 42 of FIG. 30 is identified with a label 42a to distinguish such shield line from the others.
  • the redundant region of wiring layer M2 includes a widened structure 125 along the shield line 42a in region B, and includes a widened structure 127 along the shield line 42a in region B'.
  • One of the shield lines 12 of FIG. 31 is identified with a label 12a to distinguish such shield line from the others, and the redundant region of wiring layer M3 includes widened structures 131 and 133 along the shield line 12a in regions B and B', respectively.
  • the wiring layers M2 and M3 of FIGS. 30 and 31 may be referred to as a lower-level wiring layer and an upper-level wiring layer, respectively; and may be considered to comprise the shown first wiring tracks, second wiring tracks, third wiring tracks and fourth wiring tracks (labeled as first, second, third and fourth tracks in FIGS. 30 and 31).
  • the first, second, third and fourth wiring tracks of the upper wiring layer M3 directly overlay the first, second, third and fourth wiring tracks of the lower wiring layer M2.
  • the first, second, third and fourth wiring tracks extend in a first direction along an x-axis, and extend parallel to one another (or at least substantially parallel to one another).
  • the first and third wiring tracks sandwich the second wiring track
  • the lower-level wiring layer M2 may be considered to comprise first wiring corresponding to the wiring of shield line 42a.
  • the first wiring may be considered to have portions 50, 52 and 54 analogous to those described above relative to the embodiment of FIGS. 21-24.
  • the first wiring 42a has the first portion 50 extending along the second wiring track (and extending across both of regions B and B'), the second portion 52 extending along the first wiring track (and within the region B'), and the third portion 54 extending along the third wiring track (and within the region B).
  • the first portion 50 may be considered to comprise the first side 51 and the second side 53 in opposing relation to the first side.
  • the second portion 52 may be considered to be offset from the first side 51 of the first portion 50 by the first offset region 56, and the third portion 54 may be considered to be offset from the second side 53 by the second offset region 58.
  • the first, second and third portions 50, 52 and 54 extend along the direction of the x-axis.
  • the second portion 52 is offset from the second wiring track by the projections 55 and 57 which extend along a y-axis.
  • the third portion 54 is offset from the second wiring track by the projections 59 and 61 which extend along the y-axis.
  • the upper-level wiring layer M3 may be considered to comprise second wiring corresponding to the wiring of shield line 12a.
  • the second wiring 12a is connected to the first wiring 42a, and may be considered to have a fourth portion 60 analogous to that described above relative to the embodiment of FIGS. 21-24.
  • the fourth portion 60 extends along the third wiring track, and is electrically coupled to the third portion 54 of the first wiring 42a (FIG. 18) through the interconnects 20a.
  • FIG. 32A shows a cross-section along the line 32A-32A of FIGS. 30 and 31, and shows an interconnect 20a extending through insulative material 34 to electrically couple shield line 12a of the upper- level wiring layer M3 with the shield line 42a of the lower- level wiring layer M2.
  • the upper-level wiring layer M3 (FIG. 31) comprises a third wiring 12b having a fifth portion 62 analogous to the portion 62 of the embodiment of FIGS. 21-24.
  • the fifth portion 62 of third wiring 12b extends along the first wiring track, and is electrically coupled with the second portion 52 of the lower-level wiring layer M2 (FIG. 30) through the interconnects 20b.
  • a cross-section along the line 32B-32B is shown in FIG. 32B, and such shows the coupling of the fifth portion 62 and the second portion 52 through an interconnect 20b.
  • the first wiring 42a of lower-level wiring layer M2 may be considered to comprise the first portion 50, second portion 52 and third portion 54.
  • the upper- level wiring layer M3 may be considered to comprise the wiring 12b as the second wiring, and to comprise the wiring 12a as the third wiring.
  • the second wiring 12b comprises a fourth portion 62 along the first wiring track
  • the third wiring 12a comprises a fifth portion 60 extending along the third wiring track.
  • At least one contact plug 20b penetrates insulative layer of material 34 to couple the second portion 52 of the first wiring 42a with the fourth portion 62 of the second wiring 12b; and at least one contact plug 20a penetrates insulative layer of material 34 to couple the third portion 54 of the first wiring 42a with the fifth portion 60 of the third wiring 12a.
  • the third wiring 12a has a sixth portion 64 which extends along the second wiring track, and which is electrically coupled with the first portion 50 of the lower-level wiring 42a (FIG. 30) through the interconnects 20c.
  • a cross-section along the line 32C- 32C is shown in FIG. 32C, and such shows the coupling of the sixth portion 64 and the first portion 50 through an interconnect 20c.
  • the third wiring 12a of the upper-level wiring layer M3 may be considered to further comprise a seventh portion 66 extending along the fourth wiring track.
  • the fifth and sixth portions (60 and 64) are offset from one another by a first offset region 200, and the fifth and seventh portions (60 and 66) are offset from one another by a second offset region 202.
  • the first and second offset regions 200 and 202 may comprise void regions, as shown in FIG. 31.
  • the first and second offset regions 200 and 202 may be filled with conductive material of shield line 12a (i.e., may entirely comprise such conductive material), as shown in FIGS. 33 and 34.
  • regions 64 and 66 of FIG. 31 may be referred to as seventh and eighth regions, respectively; that extend along the second wiring track and the fourth wiring track, respectively.
  • the first wiring 42a of the lower-level wiring layer M2 may be considered to further comprise a ninth portion (corresponding to projection 55 or 57) extending along the y-axis to couple the first and second portions 50 and 52 to one another, and tenth portion (corresponding to projection 59 or 61) extending along the along the y-axis to couple the first and third portions 50 and 54 to one another.
  • first and second portions (50 and 52) of first wiring 42a may be considered to be offset from one another by a third offset region 204, and the first and third portions (50 and 44) of first wiring 42a may be considered to be offset from one another by a fourth offset region 206.
  • the third and fourth offset regions 204 and 206 may comprise void regions, as shown in FIG. 30.
  • the third and fourth offset regions 204 and 206 may be filled with conductive material of shield line 42a (i.e., may entirely comprise such conductive material), as shown in FIGS. 35 and 36.
  • the assemblies discussed above may be utilized in electronic systems.
  • Such electronic systems may be used in, for example, memory modules, device drivers, power modules, communication modems, processor modules, and application- specific modules, and may include multilayer, multichip modules.
  • the electronic systems may be any of a broad range of systems, such as, for example, cameras, wireless devices, displays, chip sets, set top boxes, games, lighting, vehicles, clocks, televisions, cell phones, personal computers, automobiles, industrial control systems, aircraft, etc.
  • Some embodiments include an assembly (e.g., 510) having a first wiring level (e.g., M3) with a plurality of first shield lines (e.g., 512) and first signal lines (e.g., 514) in alternating arrangement.
  • the first shield lines and first signal lines have first segments (e.g., 520, 526) extending along a first direction (e.g., the direction of axis 503), second segments (e.g., 522, 528) extending along the first direction and laterally offset from the first segments, and first linking segments (e.g., 524, 530) interconnecting the first and second segments to one another.
  • the assembly includes a second wiring level (e.g., M2) below the first wiring level and having a plurality of second shield lines (e.g., 516) and second signal lines (e.g., 518) in alternating arrangement.
  • the second shield lines and second signal lines have third segments (e.g., 532, 538) extending along the first direction, fourth segments (e.g., 534, 540) extending along the first direction and laterally offset from the third segments, and second linking segments (e.g., 536, 542) interconnecting the third and fourth segments to one another.
  • the fourth segments of the second shield lines extend to under the first segments of the first shield lines and are electrically coupled to the first segments of the first shield lines through vertical interconnects (546).
  • Some embodiments include an assembly (e.g., 510) having a first wiring level (e.g., M3) which includes a plurality of first shield lines (e.g., 512) and first signal lines (e.g., 514) in alternating arrangement.
  • the assembly has a second wiring level (e.g., M2) below the first wiring level and which includes a plurality of second shield lines (e.g.,
  • first shield lines has a first portion (e.g., 548) extending in a first direction (e.g., the direction of axis 503), a second portion (e.g., 550) extending in a second direction (e.g., the direction of axis 505), and a third portion (e.g., 552) extending in the first direction.
  • the second portion interconnects the first and third portions with each other.
  • One of the first signal lines is immediately adjacent said one of the first shield lines.
  • Said one of the first signal lines has fourth, fifth and sixth portions (e.g., 554, 556, 558) that are substantially parallel to the third, second and first portions, respectively, of said one of the first shield lines.
  • One of the second shield lines includes seventh and eighth portions (e.g., 560, 562) that are under and substantially vertically aligned with the third portion of the first shield line and the fourth portion of the first signal line, respectively.
  • a vertical interconnect e.g., 546) electrically connects the third portion of said one of the first shield lines to the seventh portion of said one of the second shield lines.
  • Some embodiments include an assembly (e.g., 510) which has a first wiring level
  • the assembly has second wiring level (e.g., M2) below the first wiring level and which includes a plurality of second shield lines (e.g., 516) and second signal lines (e.g., 518) in alternating arrangement.
  • a mesh structure (e.g., 578) comprises the first shield lines electrically coupled with the second shield lines.
  • Each of the first shield lines of the mesh structure extends primarily along a first direction (e.g., the direction of axis 503), and extends along two first paths (e.g., 580, 582) which are laterally offset relative to one another.
  • Each of the second shield lines of the mesh structure extends primarily along the first direction and extends along two second paths (e.g., 590, 592) which are laterally offset relative to one another.
  • the first shield lines of the mesh structure are primarily laterally offset from the second shield lines of the mesh structure except that each of the first paths of each of the first shield lines have overlap regions (e.g., 544) where portions of the first shield lines vertically overlap portions the second shield lines.
  • Vertical interconnects e.g., 546) are within said overlap regions to connect the first shield lines with the second shield lines.
  • One of the first paths of an individual first shield line has an overlap region which is over a different second shield line than is the other of the first paths of the individual first shield line.
  • Some embodiments include an assembly having first, second, third and fourth wiring tracks over a substrate.
  • the first, second, third and fourth wiring tracks extend in a first direction.
  • the first and third wiring tracks sandwich the second wiring track therebetween, and the second and fourth wiring tracks sandwich the third wiring track therebetween.
  • a lower-level wiring layer includes a first wiring which has a first portion extending along the second wiring track, a second portion extending along the first wiring track, and a third portion extending along the third wiring track.
  • the second portion is offset along a first side of the first portion by a first offset region
  • the third portion is offset along a second side of the first portion by a second offset region.
  • the first side is in opposing relation to the second side.
  • An upper-level wiring layer includes a second wiring electrically connected to the first wiring and having a fourth portion extending along the third wiring track.
  • the third portion of the first wiring is electrically coupled with the fourth portion of the second wiring.
  • Some embodiments include an assembly having first, second, third and fourth wiring tracks over a substrate.
  • the first, second, third and fourth wiring tracks extend in a first direction and are substantially parallel to one another.
  • the first and third wiring tracks sandwich the second wiring track therebetween, and the second and fourth wiring tracks sandwich the third wiring track therebetween.
  • a lower-level wiring layer comprises a first wiring.
  • the first wiring comprises a first portion extending along the second wiring track, a second portion extending along the first wiring track, a third portion extending along the third wiring track, a fourth portion extending in a second direction crossing the first direction to couple the first portion and the second portion, and a fifth portion extending in the second direction to couple the first portion and the third portion.
  • An upper-level wiring layer comprises a second wiring electrically connected to the first wiring.
  • the second wiring comprises a sixth portion extending along the third wiring track, a seventh portion extending along the second wiring track, an eighth portion extending along the fourth wiring track, a ninth portion extending in the second direction to couple the sixth portion and the seventh portion, and a tenth portion extending in the second direction to couple the sixth portion and the eighth portion.
  • Some embodiments include an assembly having first, second, third and fourth wiring tracks over a substrate.
  • the first, second, third and fourth wiring tracks extend in a first direction and are substantially parallel to one another.
  • the first and third wiring tracks sandwich the second wiring track therebetween, and the second and fourth wiring tracks sandwich the third wiring track therebetween.
  • a lower-level wiring layer comprises a first wiring.
  • the first wiring comprises a first portion extending along the second wiring track, a second portion extending along the first wiring track, and a third portion extending along the third wiring track.
  • An upper-level wiring layer comprises second and third wirings electrically connected to the first wiring.
  • the second wiring comprises a fourth portion extending along the first wiring track
  • the third wiring comprises a fifth portion extending along the third wiring track.
  • An insulating layer is between the lower-level wiring layer and the upper-level wiring layer. At least one contact plug penetrates the insulating layer to couple the second portion of the first wiring and the fourth portion of the second wiring. At least one contact plug penetrates the insulating layer to couple the third portion of the first wiring and the fifth portion of the third wiring.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

Certains modes de réalisation comprennent un ensemble ayant un premier niveau de câblage avec une pluralité de premières lignes de blindage et de premières lignes de signal. Les premières lignes de blindage et les premières lignes de signal comportent des premiers segments s'étendant le long d'une première direction et des deuxièmes segments s'étendant le long de la première direction et décalés latéralement par rapport aux premiers segments. L'ensemble comprend un second niveau de câblage au-dessous du premier niveau de câblage et ayant une pluralité de secondes lignes de blindage et de secondes lignes de signal. Les secondes lignes de blindage et les secondes lignes de signal comportent des troisièmes segments s'étendant le long de la première direction et des quatrièmes segments s'étendant le long de la première direction et décalés latéralement par rapport aux troisièmes segments. Les quatrièmes segments des secondes lignes de blindage s'étendent jusqu'en dessous des premiers segments des premières lignes de blindage et sont électriquement couplés aux premiers segments des premières lignes de blindage par l'intermédiaire d'interconnexions verticales.
PCT/US2017/024835 2016-05-16 2017-03-29 Ensembles comportant des lignes de blindage d'un niveau de câblage supérieur couplées électriquement à des lignes de blindage d'un niveau de câblage inférieur Ceased WO2017200639A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
KR1020187025272A KR102105785B1 (ko) 2016-05-16 2017-03-29 하측 배선 레벨의 실드 라인에 전기적으로 결합된 상측 배선 레벨의 실드 라인을 갖는 어셈블리
CN201780013788.1A CN108701676B (zh) 2016-05-16 2017-03-29 具有与下部布线层的屏蔽线电耦合的上部布线层的屏蔽线的组合件

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US15/155,334 2016-05-16
US15/155,334 US9754872B1 (en) 2016-05-16 2016-05-16 Assemblies having shield lines of an upper wiring level electrically coupled with shield lines of a lower wiring level
US15/456,254 2017-03-10
US15/456,254 US10304771B2 (en) 2017-03-10 2017-03-10 Assemblies having shield lines of an upper wiring layer electrically coupled with shield lines of a lower wiring layer

Publications (1)

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WO2017200639A1 true WO2017200639A1 (fr) 2017-11-23

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PCT/US2017/024835 Ceased WO2017200639A1 (fr) 2016-05-16 2017-03-29 Ensembles comportant des lignes de blindage d'un niveau de câblage supérieur couplées électriquement à des lignes de blindage d'un niveau de câblage inférieur

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KR (1) KR102105785B1 (fr)
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KR102555883B1 (ko) * 2018-10-29 2023-07-17 셀링크 코포레이션 가요성 하이브리드 상호 연결 회로
US10607923B1 (en) * 2018-12-07 2020-03-31 Micron Technology, Inc. Integrated assemblies comprising redundant wiring routes, and integrated circuit decks having openings extending therethrough
CN110110659A (zh) * 2019-05-07 2019-08-09 京东方科技集团股份有限公司 阵列基板及显示装置

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KR20180101725A (ko) 2018-09-13
CN108701676A (zh) 2018-10-23
CN108701676B (zh) 2021-07-23
KR102105785B1 (ko) 2020-06-29

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