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WO2017110619A1 - Dispositif de contrôle d'un dispositif de transfert de paquets comportant une unité centrale de traitement (uct) multicoeur, et support de stockage lisible par ordinateur - Google Patents

Dispositif de contrôle d'un dispositif de transfert de paquets comportant une unité centrale de traitement (uct) multicoeur, et support de stockage lisible par ordinateur Download PDF

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Publication number
WO2017110619A1
WO2017110619A1 PCT/JP2016/087229 JP2016087229W WO2017110619A1 WO 2017110619 A1 WO2017110619 A1 WO 2017110619A1 JP 2016087229 W JP2016087229 W JP 2016087229W WO 2017110619 A1 WO2017110619 A1 WO 2017110619A1
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WO
WIPO (PCT)
Prior art keywords
cores
packet transfer
packet
computer
control device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2016/087229
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English (en)
Japanese (ja)
Inventor
カリカ スクソブーン
林　通秋
正機 福嶋
修一 岡本
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KDDI Corp
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KDDI Corp
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Filing date
Publication date
Application filed by KDDI Corp filed Critical KDDI Corp
Publication of WO2017110619A1 publication Critical patent/WO2017110619A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]

Definitions

  • the present disclosure relates to a control technology for a packet transfer apparatus having a multi-core CPU.
  • an ordinary computer is used as a packet transfer device, not a device specially designed for packet transfer such as a router.
  • a computer used as a packet transfer apparatus is used not only for packet transfer but also for other applications. At this time, among the resources of the entire computer, it is necessary to appropriately set resources to be allocated for packet transfer.
  • Non-Patent Documents 1 and 2 disclose a method for estimating the maximum throughput when a computer is used as a packet transfer apparatus.
  • Non-Patent Documents 1 and 2 only disclose estimating the maximum throughput, and disclose how to allocate resources for packet transfer to a computer used as a packet transfer apparatus. is not.
  • a control device that determines the number of cores to be allocated to packet transfer processing among the cores of a computer having a multi-core CPU and performs control for configuring the computer includes: a target range of packet transfer throughput; And N (N is an integer of 2 or more) cores based on the number of reference cycles required for transfer processing of one reference packet when only one core is assigned to packet transfer processing.
  • the block diagram of the control apparatus by one Embodiment The flowchart of the process in the control apparatus by one Embodiment.
  • FIG. 1 is a configuration diagram of a control device 1 according to the present embodiment.
  • the control device 1 controls the packet transfer device 50.
  • the packet transfer device 50 is a computer including a multi-core CPU, and the control device 1 determines the number of CPU cores to be assigned to packet transfer processing based on the target throughput range set by the user.
  • the packet transfer apparatus 50 is configured so that the number of cores is used for packet transfer processing.
  • FIG. 2 is a flowchart of processing of the control device 1 in the present embodiment.
  • the user sets a target range for the maximum throughput and inputs it to the control device 1.
  • the resource allocation unit 12 holds this target range.
  • the resource allocation unit 12 sets the number N of cores used for packet transfer processing among the cores of the packet transfer apparatus 50 to an initial value.
  • the estimation unit 11 estimates the maximum throughput ⁇ . Details of the process for estimating the maximum throughput ⁇ will be described later.
  • the resource allocation unit 12 determines whether or not the estimated maximum throughput ⁇ is within the target range.
  • the resource allocation unit 12 determines whether the estimated maximum throughput ⁇ is larger or smaller than the target range. If the estimated maximum throughput ⁇ is larger than the target range, it means that the number of cores assigned to the packet transfer process is large. Therefore, in S15, the resource assignment unit 12 decreases N by 1 and performs the process from S12. repeat. On the other hand, if the estimated maximum throughput ⁇ is smaller than the target range, it means that the number of cores assigned to the packet transfer process is small. Therefore, in S16, the resource allocating unit 12 increases N by 1 from S12. Repeat the process. Further, in the determination of S13, when the estimated maximum throughput ⁇ is within the target range, the control device 1 ends the process.
  • the processing of FIG. 2 can be performed before or during operation of the packet transfer apparatus 50.
  • the processing of FIG. 2 is performed only once, the number of cores whose maximum throughput is within the target range is obtained, and the packet transfer apparatus can be operated with the obtained number of cores.
  • the process for obtaining the number of cores for which the maximum throughput is within the target range can be repeated. In that case, first, the process of FIG. 2 is performed as it is. For the second and subsequent times, S10 and S11 in FIG. 2 are omitted, and the processing from S12 is repeated.
  • Non-Patent Document 1 is based on the premise that the computer to be used is a single core, and when applied to a packet transfer apparatus 50 having a multi-core CPU which is the current mainstream, the estimation accuracy of the maximum throughput is degraded. To do.
  • Non-Patent Document 2 for example, in the case of a CPU having two cores, the maximum throughput can be accurately estimated. However, as the number of cores increases, the actual maximum throughput, the estimated maximum throughput, and The difference becomes larger. This is because the method of Non-Patent Document 2 assumes that all packets are affected by cache contention.
  • FIG. 3 is a diagram illustrating a cache configuration of the packet transfer apparatus 50 according to the present embodiment.
  • the number of cores assigned to packet transfer processing is N cores # 1 to #N, and all cores # 1 to #N share the same last level cache (LLC). It shall be.
  • a level 1 cache (L1) and a level 2 cache (L2) are provided corresponding to each core.
  • the packet transfer apparatus 50 uses the system memory as a cache. It should be noted that the time for accessing the system memory is very large compared to the time for accessing the cache.
  • the maximum throughput is limited by the interface speed and CPU speed.
  • the maximum throughput limited by the interface speed is referred to as S1
  • the maximum throughput limited by the CPU speed is referred to as S2.
  • the estimation unit 11 of the present embodiment obtains the maximum throughput S1 and the maximum throughput S2, respectively, and sets the smaller of the maximum throughput S1 and the maximum throughput S2 as the maximum throughput ⁇ of the packet transfer apparatus 50.
  • the maximum throughput S1 can be obtained by dividing the interface speed of the packet transfer apparatus 50 by the reference packet length. When the interface speeds of a plurality of interfaces are different, the minimum value is used.
  • the maximum throughput S2 when only one core is operating, the number of core cycles necessary to transfer one reference packet is C solo .
  • f the core speed (number of cycles per second).
  • this longer cycle number is represented by ⁇ .
  • h is a cache hit rate
  • ⁇ is a time required for accessing the system memory.
  • the first term of equation (1) corresponds to the number of cycles that increases when a cache miss occurs in LLC due to the operation of another core but a cache hit occurs in LLC when only one core is operating. To do.
  • the second term of the equation (1) corresponds to the number of cycles that increases due to a cache miss that increases by operating a plurality of cores.
  • u 1 to u N are% utilization ratios (Utilization) of the cores # 1 to #N.
  • the estimation part 11 calculates
  • the estimation unit 11 temporarily sets the number of cores to be assigned to packet transfer through the resource allocation unit 12, causes the test packet generation unit 13 to transmit the reference packet, and causes the test packet reception unit 14 to transmit the reference packet. To receive.
  • the maximum throughput ⁇ solo when only a single core is operating is measured.
  • the estimation unit 11 measures the CPU cycle C solo spent for transferring the reference packet and the cache hit rate h up to the last level cache (LLC) when only a single core is operating.
  • LLC last level cache
  • sudo ocount -s --events cpl_cycles: ring0, cpl_cycles: ring123 Similarly, h can be obtained by the following command line.
  • sudo ocount -s -events mem_uops_retired: all_loads, mem_load_uops_retired: l1_hit, mem_load_uops_retired: l2_hit, mem_load_uops_retired: l3_hit
  • the estimation unit 11 returns the number of cores allocated to packet transfer to the original number via the resource allocation unit 12. Thereafter, the estimation unit 11 measures the delay amount ⁇ for access to the system memory.
  • the delay amount ⁇ can be obtained from the following command line. $ taskset 0x1 ./lat_mem_rd -N 1 -P 1 4096k 512 Further, the estimation unit 11 measures the% CPU utilization u 1 to u N of each core and the overall% CPU utilization u all . These% CPU utilization rates can be obtained from the following command line. $ mpstat -P ALL
  • the estimation unit 11 obtains the probability pi according to the equation (2) based on the% usage rate of each core. Further, an increase ⁇ in the number of cycles necessary for transferring one packet by operating N cores is obtained by Expression (1). Then, based on Expression (3), the maximum throughput S2 is obtained.
  • u 1 to u N and u all may be 1.
  • the number of cores having the maximum throughput within the target range can be appropriately set, and the remaining cores can be allocated to other processes.
  • an interface mounted on a computer used as the packet transfer apparatus 50 is selected so that the maximum throughput S1 is larger than the target range. That is, normally, the maximum throughput ⁇ is limited by the maximum throughput S2, and is not limited by the maximum throughput S1. Therefore, the control device 1 can obtain only the maximum throughput S2 and set it as the maximum throughput ⁇ .
  • the control device can be realized by a program that causes a computer to operate as the control device.
  • These computer programs can be stored in a computer-readable storage medium or distributed via a network.

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  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)

Abstract

Le dispositif de contrôle comprend: un moyen de maintien pour maintenir une plage cible pour le débit de transfert de paquets; un moyen d'estimation pour estimer le débit maximal pour l'instant où N coeurs (N étant un entier égal ou supérieur à 2) sont attribués au processus de transfert de paquets sur la base du nombre de cycles de référence requis dans un processus de transfert d'un paquet de référence, lorsqu'un seul coeur est attribué au processus de transfert de paquets; et un moyen d'attribution pour déterminer le nombre N auquel le débit maximal se trouve dans la plage cible, et pour contrôler l'ordinateur de sorte que le nombre de coeurs déterminé soit attribué au processus de transfert de paquets.
PCT/JP2016/087229 2015-12-21 2016-12-14 Dispositif de contrôle d'un dispositif de transfert de paquets comportant une unité centrale de traitement (uct) multicoeur, et support de stockage lisible par ordinateur Ceased WO2017110619A1 (fr)

Applications Claiming Priority (2)

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JP2015248962A JP6600250B2 (ja) 2015-12-21 2015-12-21 マルチコアｃｐｕを有するパケット転送装置の制御装置及びプログラム
JP2015-248962 2015-12-21

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112181894A (zh) * 2019-07-04 2021-01-05 山东省计算中心（国家超级计算济南中心） 一种基于申威众核处理器的核组内分组自适应调整运行方法

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2019004593A (ja) 2017-06-14 2019-01-10 本田技研工業株式会社 車両の電源装置

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008129767A (ja) * 2006-11-20 2008-06-05 Mitsubishi Electric Corp ネットワーク装置
WO2011111230A1 (fr) * 2010-03-12 2011-09-15 富士通株式会社 Système de processeur multicœur, procédé de réglage de puissance, et programme de réglage de puissance
WO2012105677A1 (fr) * 2011-02-04 2012-08-09 日本電気株式会社 Dispositif de traitement de paquet, procédé de traitement de paquet et programme
JP2014110538A (ja) * 2012-12-03 2014-06-12 Nec Corp ネットワークスイッチ装置、タスク移動方法、およびタスク移動プログラム

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5988930B2 (ja) * 2013-07-23 2016-09-07 日本電信電話株式会社 サーバ仮想化環境における予備系装置の配備装置およびその配備方法
US20170302558A1 (en) * 2014-10-07 2017-10-19 Nec Corporation Measuring apparatus, measuring system, measuring method, and recording medium in which program is recorded

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008129767A (ja) * 2006-11-20 2008-06-05 Mitsubishi Electric Corp ネットワーク装置
WO2011111230A1 (fr) * 2010-03-12 2011-09-15 富士通株式会社 Système de processeur multicœur, procédé de réglage de puissance, et programme de réglage de puissance
WO2012105677A1 (fr) * 2011-02-04 2012-08-09 日本電気株式会社 Dispositif de traitement de paquet, procédé de traitement de paquet et programme
JP2014110538A (ja) * 2012-12-03 2014-06-12 Nec Corp ネットワークスイッチ装置、タスク移動方法、およびタスク移動プログラム

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112181894A (zh) * 2019-07-04 2021-01-05 山东省计算中心（国家超级计算济南中心） 一种基于申威众核处理器的核组内分组自适应调整运行方法
CN112181894B (zh) * 2019-07-04 2022-05-31 山东省计算中心（国家超级计算济南中心） 一种基于申威众核处理器的核组内分组自适应调整运行方法

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JP2017117009A (ja) 2017-06-29

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