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WO2017000360A1 - 一种扫描驱动电路 - Google Patents

一种扫描驱动电路 Download PDF

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Publication number
WO2017000360A1
WO2017000360A1 PCT/CN2015/086487 CN2015086487W WO2017000360A1 WO 2017000360 A1 WO2017000360 A1 WO 2017000360A1 CN 2015086487 W CN2015086487 W CN 2015086487W WO 2017000360 A1 WO2017000360 A1 WO 2017000360A1
Authority
WO
WIPO (PCT)
Prior art keywords
switch tube
output end
input
control
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2015/086487
Other languages
English (en)
French (fr)
Inventor
赵莽
田勇
陈归
陈彩琴
张鑫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Wuhan China Star Optoelectronics Technology Co Ltd
Original Assignee
Wuhan China Star Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Wuhan China Star Optoelectronics Technology Co Ltd filed Critical Wuhan China Star Optoelectronics Technology Co Ltd
Priority to US14/783,100 priority Critical patent/US9628050B2/en
Publication of WO2017000360A1 publication Critical patent/WO2017000360A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/01—Details
    • H03K3/012—Modifications of generator to improve response time or to decrease power consumption
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0814—Several active elements per pixel in active matrix panels used for selection purposes, e.g. logical AND for partial update
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0202—Addressing of scan or signal lines
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0289—Details of voltage level shifters arranged for use in a driving circuit

Definitions

  • the present invention relates to the field of display driving, and more particularly to a scan driving circuit.
  • GOA Gate Driver On Array
  • the existing scan driving circuit needs to be driven by using the clock signal CK and the cascaded signal Q_N-1 of the previous stage. Since the cascaded signal of the upper stage is susceptible to interference by the corresponding clock signal CK, the normal influence is caused. Display driver. At the same time, the fluctuation of the cascaded signal Q_N-1 of the upper stage also causes additional power consumption of the scan driving circuit.
  • An embodiment of the present invention provides a scan driving circuit for driving a cascaded scan line, wherein the scan drive circuit includes:
  • An input control module configured to input a first clock signal of the current stage, a cascaded signal of the previous stage, and a cascaded signal of the next stage, and according to the first clock signal of the current stage, the level of the upper stage a joint signal and a cascade signal of the next stage to generate a control signal;
  • a latching module configured to perform a latching operation on the control signal
  • a driving signal generating module configured to generate a driving signal according to the control signal and the second clock signal of the current stage
  • An output control module configured to output a scan signal of the current level according to the driving signal
  • Constant voltage low level source for providing low level voltage
  • the inverted signal of the control signal is input to the scan driving circuit of the next stage as a cascade signal of the current stage;
  • the output control module includes a nineteenth switch tube, a twentieth switch tube, a twenty-first switch tube, a twenty-second switch tube, a twenty-third switch tube, and a twenty-fourth switch tube;
  • a control end of the nineteenth switch tube is connected to an output end of the driving signal generating module, and an input end of the nineteenth switch tube is connected to the constant voltage high level source, the nineteenth switch tube
  • the output ends are respectively connected to the control end of the twenty-first switch tube and the control end of the twenty-second switch tube;
  • a control end of the twentieth switch tube is connected to an output end of the drive signal generating module, and an input end of the twentieth switch tube is connected to the constant voltage low level source, and the twentieth switch tube
  • the output ends are respectively connected to the control ends of the twenty-one switch tubes and the control ends of the twenty-second switch tubes;
  • the input end of the twenty-first switch tube is connected to the constant voltage high level source, and the output end of the twenty-first switch tube and the control end of the twenty-third switch tube and the first The control end of the twenty-four switch tube is connected;
  • the input end of the 22nd switch tube is connected to the constant voltage low level source, and the output end of the 22nd switch tube and the control end of the 23rd switch tube and the first The control end of the twenty-four switch tube is connected;
  • the input end of the 23rd switch tube is connected to the constant voltage high level source, and the output end of the 23rd switch tube is connected to the output end of the output control module;
  • the input end of the 24th switch tube is connected to the constant voltage low level source, and the output end of the 24th switch tube is connected to the output end of the output control module;
  • the nineteenth switch tube, the twenty-first switch tube, and the twenty-third switch tube are PMOS tubes, the twentieth switch tube, the second switch tube, and the Twenty-four switch tubes are NMOS tubes.
  • the input control module includes a first switch tube, a second switch tube, a third switch tube, a fourth switch tube, a fifth switch tube, and a sixth switch tube;
  • a control end of the first switch tube inputs a first clock signal of the current stage, an input end of the first switch tube is connected to the constant voltage high level source, and an output end of the first switch tube is The output of the input control module is connected;
  • a control end of the second switch tube inputs a cascade signal of the upper stage, an input end of the second switch tube is connected to the constant voltage high level source, and an output end of the second switch tube is The input end of the third switch tube is connected;
  • a control end of the third switch tube inputs a cascade signal of the next stage, and an output end of the third switch tube is connected to an output end of the input control module;
  • a control end of the fourth switch tube inputs a first clock signal of the current stage, an input end of the fourth switch tube is connected to an output end of the fifth switch tube, and an output end of the fourth switch tube Connected to an output of the input control module;
  • a control end of the fifth switch tube inputs a cascade signal of the upper stage, and an input end of the fifth switch tube is connected to the constant voltage low level source;
  • a control end of the sixth switch tube inputs a cascade signal of the next stage, an input end of the sixth switch tube is connected to the constant voltage low level source, and an output end of the sixth switch tube is The output ends of the fifth switch tubes are connected.
  • the first switching transistor, the second switching transistor, and the third switching transistor are PMOS transistors, the fourth switching transistor, the fifth switching transistor, and the
  • the sixth switch tube is an NMOS tube.
  • the input control module includes a first switch tube, a second switch tube, a third switch tube, a fourth switch tube, a fifth switch tube, and a sixth switch tube;
  • a control end of the first switch tube inputs a first clock signal of the current stage, an input end of the first switch tube is connected to the constant voltage high level source, and an output end of the first switch tube is The output of the input control module is connected;
  • a control end of the second switch tube inputs a cascade signal of the upper stage, an input end of the second switch tube is connected to the constant voltage high level source, and an output end of the second switch tube is The input end of the third switch tube is connected;
  • a control end of the third switch tube inputs a cascade signal of the next stage, and an output end of the third switch tube is connected to an output end of the input control module;
  • a control end of the fourth switch tube inputs a first clock signal of the current stage, an input end of the fourth switch tube is connected to the constant voltage low level source, and an output end of the fourth switch tube is The input end of the fifth switch tube is connected;
  • a control end of the fifth switch tube inputs a cascade signal of the upper stage, and an output end of the fifth switch tube is connected to an output end of the input control module;
  • a control end of the sixth switch tube inputs a cascade signal of the next stage, an input end of the sixth switch tube is connected to an input end of the fifth switch tube, and an output end of the sixth switch tube Connected to the output of the input control module.
  • the first switching transistor, the second switching transistor, and the third switching transistor are PMOS transistors, the fourth switching transistor, the fifth switching transistor, and the
  • the sixth switch tube is an NMOS tube.
  • the latch module includes a first inverter, a second inverter, a seventh switch, an eighth switch, a ninth switch, a tenth switch, and a An eleven switch tube, a twelfth switch tube, a thirteenth switch tube, and a fourteenth switch tube;
  • a control end of the seventh switch tube is connected to an output end of the input control module, an input end of the seventh switch tube is connected to the constant voltage high level source, and an output end of the seventh switch tube is The input end of the eighth switch tube is connected;
  • the control end of the eighth switch tube inputs a cascade signal of the upper stage, and the output end of the eighth switch tube is connected to the output end of the latch module through the second inverter;
  • the control end of the ninth switch tube inputs a cascade signal of the previous stage, and the output end of the ninth switch tube is connected to the output end of the latch module through the second inverter;
  • a control end of the tenth switch tube is connected to an output end of the input control module through the first inverter, and an input end of the tenth switch tube is connected to the constant voltage low level source, An output end of the tenth switch tube is connected to an input end of the ninth switch tube;
  • the control end of the eleventh switch tube is connected to the output end of the input control module through the first inverter, and the input end of the eleventh switch tube is connected to the constant voltage high level source.
  • An output end of the eleventh switch tube is connected to an input end of the twelfth switch tube;
  • a control end of the twelfth switch is connected to an output end of the latch module, and an output end of the twelfth switch is connected to an output end of the latch module through the second inverter;
  • a control end of the thirteenth switch tube is connected to an output end of the latch module, and an output end of the thirteenth switch tube is connected to an output end of the latch module through the second inverter;
  • a control end of the fourteenth switch tube is connected to an output end of the input control module, and an input end of the fourteenth switch tube is connected to the constant voltage low level source, and the fourteenth switch tube The output end is connected to the input end of the thirteenth switch tube.
  • the seventh switch tube, the eighth switch tube, the eleventh switch tube, and the twelfth switch tube are PMOS tubes, and the ninth switch tube
  • the tenth switch tube, the thirteenth switch tube, and the fourteenth switch tube are NMOS tubes.
  • the driving signal generating module includes a fifteenth switch tube, a sixteenth switch tube, a seventeenth switch tube, and an eighteenth switch tube;
  • a control end of the fifteenth switch tube is connected to an output end of the latch module, and an input end of the fifteenth switch tube is connected to the constant voltage high level source, and the fifteenth switch tube The output end is connected to an output end of the driving signal generating module;
  • the control end of the sixteenth switch tube inputs a second clock signal of the current stage, and the input end of the sixteenth switch tube is connected to the constant voltage high level source, and the output end of the sixteenth switch tube Connected to an output of the driving signal generating module;
  • a control end of the seventeenth switch tube is connected to an output end of the latch module, and an input end of the seventeenth switch tube is connected to an output end of the eighteenth switch tube, the seventeenth switch An output end of the tube is connected to an output end of the driving signal generating module;
  • the control end of the eighteenth switch tube inputs a second clock signal of the current stage, and the input end of the eighteenth switch tube is connected to the constant voltage low level source.
  • the fifteenth switch tube and the sixteenth switch tube are PMOS tubes, and the seventeenth switch tube and the eighteenth switch tube are NMOS tubes.
  • An embodiment of the present invention provides a scan driving circuit for driving a cascaded scan line, which includes:
  • An input control module configured to input a first clock signal of the current stage, a cascaded signal of the previous stage, and a cascaded signal of the next stage, and according to the first clock signal of the current stage, the level of the upper stage a joint signal and a cascade signal of the next stage to generate a control signal;
  • a latching module configured to perform a latching operation on the control signal
  • a driving signal generating module configured to generate a driving signal according to the control signal and the second clock signal of the current stage
  • An output control module configured to output a scan signal of the current level according to the driving signal
  • a constant voltage low level source that provides a low level voltage.
  • the input control module includes a first switch tube, a second switch tube, a third switch tube, a fourth switch tube, a fifth switch tube, and a sixth switch tube;
  • a control end of the first switch tube inputs a first clock signal of the current stage, an input end of the first switch tube is connected to the constant voltage high level source, and an output end of the first switch tube is The output of the input control module is connected;
  • a control end of the second switch tube inputs a cascade signal of the upper stage, an input end of the second switch tube is connected to the constant voltage high level source, and an output end of the second switch tube is The input end of the third switch tube is connected;
  • a control end of the third switch tube inputs a cascade signal of the next stage, and an output end of the third switch tube is connected to an output end of the input control module;
  • a control end of the fourth switch tube inputs a first clock signal of the current stage, an input end of the fourth switch tube is connected to an output end of the fifth switch tube, and an output end of the fourth switch tube Connected to an output of the input control module;
  • a control end of the fifth switch tube inputs a cascade signal of the upper stage, and an input end of the fifth switch tube is connected to the constant voltage low level source;
  • a control end of the sixth switch tube inputs a cascade signal of the next stage, an input end of the sixth switch tube is connected to the constant voltage low level source, and an output end of the sixth switch tube is The output ends of the fifth switch tubes are connected.
  • the input control module includes a first switch tube, a second switch tube, a third switch tube, a fourth switch tube, a fifth switch tube, and a sixth switch tube;
  • a control end of the first switch tube inputs a first clock signal of the current stage, an input end of the first switch tube is connected to the constant voltage high level source, and an output end of the first switch tube is The output of the input control module is connected;
  • a control end of the second switch tube inputs a cascade signal of the upper stage, an input end of the second switch tube is connected to the constant voltage high level source, and an output end of the second switch tube is The input end of the third switch tube is connected;
  • a control end of the third switch tube inputs a cascade signal of the next stage, and an output end of the third switch tube is connected to an output end of the input control module;
  • a control end of the fourth switch tube inputs a first clock signal of the current stage, an input end of the fourth switch tube is connected to the constant voltage low level source, and an output end of the fourth switch tube is The input end of the fifth switch tube is connected;
  • a control end of the fifth switch tube inputs a cascade signal of the upper stage, and an output end of the fifth switch tube is connected to an output end of the input control module;
  • a control end of the sixth switch tube inputs a cascade signal of the next stage, an input end of the sixth switch tube is connected to an input end of the fifth switch tube, and an output end of the sixth switch tube Connected to the output of the input control module.
  • the first switching transistor, the second switching transistor, and the third switching transistor are PMOS transistors, the fourth switching transistor, the fifth switching transistor, and the
  • the sixth switch tube is an NMOS tube.
  • the latch module includes a first inverter, a second inverter, a seventh switch, an eighth switch, a ninth switch, a tenth switch, and a An eleven switch tube, a twelfth switch tube, a thirteenth switch tube, and a fourteenth switch tube;
  • a control end of the seventh switch tube is connected to an output end of the input control module, an input end of the seventh switch tube is connected to the constant voltage high level source, and an output end of the seventh switch tube is The input end of the eighth switch tube is connected;
  • the control end of the eighth switch tube inputs a cascade signal of the upper stage, and the output end of the eighth switch tube is connected to the output end of the latch module through the second inverter;
  • the control end of the ninth switch tube inputs a cascade signal of the previous stage, and the output end of the ninth switch tube is connected to the output end of the latch module through the second inverter;
  • a control end of the tenth switch tube is connected to an output end of the input control module through the first inverter, and an input end of the tenth switch tube is connected to the constant voltage low level source, An output end of the tenth switch tube is connected to an input end of the ninth switch tube;
  • the control end of the eleventh switch tube is connected to the output end of the input control module through the first inverter, and the input end of the eleventh switch tube is connected to the constant voltage high level source.
  • An output end of the eleventh switch tube is connected to an input end of the twelfth switch tube;
  • a control end of the twelfth switch is connected to an output end of the latch module, and an output end of the twelfth switch is connected to an output end of the latch module through the second inverter;
  • a control end of the thirteenth switch tube is connected to an output end of the latch module, and an output end of the thirteenth switch tube is connected to an output end of the latch module through the second inverter;
  • a control end of the fourteenth switch tube is connected to an output end of the input control module, and an input end of the fourteenth switch tube is connected to the constant voltage low level source, and the fourteenth switch tube The output end is connected to the input end of the thirteenth switch tube.
  • the seventh switch tube, the eighth switch tube, the eleventh switch tube, and the twelfth switch tube are PMOS tubes, and the ninth switch tube
  • the tenth switch tube, the thirteenth switch tube, and the fourteenth switch tube are NMOS tubes.
  • the driving signal generating module includes a fifteenth switch tube, a sixteenth switch tube, a seventeenth switch tube, and an eighteenth switch tube;
  • a control end of the fifteenth switch tube is connected to an output end of the latch module, and an input end of the fifteenth switch tube is connected to the constant voltage high level source, and the fifteenth switch tube The output end is connected to an output end of the driving signal generating module;
  • the control end of the sixteenth switch tube inputs a second clock signal of the current stage, and the input end of the sixteenth switch tube is connected to the constant voltage high level source, and the output end of the sixteenth switch tube Connected to an output of the driving signal generating module;
  • a control end of the seventeenth switch tube is connected to an output end of the latch module, and an input end of the seventeenth switch tube is connected to an output end of the eighteenth switch tube, the seventeenth switch An output end of the tube is connected to an output end of the driving signal generating module;
  • the control end of the eighteenth switch tube inputs a second clock signal of the current stage, and the input end of the eighteenth switch tube is connected to the constant voltage low level source.
  • the fifteenth switch tube and the sixteenth switch tube are PMOS tubes, and the seventeenth switch tube and the eighteenth switch tube are NMOS tubes.
  • the inverted signal of the control signal is input as a cascade signal of the current stage to the scan driving circuit of the next stage.
  • the output control module includes a nineteenth switch tube, a twentieth switch tube, a twenty-first switch tube, a twenty-second switch tube, and a twenty-third switch tube, and Twenty-four switch tube;
  • a control end of the nineteenth switch tube is connected to an output end of the driving signal generating module, and an input end of the nineteenth switch tube is connected to the constant voltage high level source, the nineteenth switch tube
  • the output ends are respectively connected to the control end of the twenty-first switch tube and the control end of the twenty-second switch tube;
  • a control end of the twentieth switch tube is connected to an output end of the drive signal generating module, and an input end of the twentieth switch tube is connected to the constant voltage low level source, and the twentieth switch tube
  • the output ends are respectively connected to the control ends of the twenty-one switch tubes and the control ends of the twenty-second switch tubes;
  • the input end of the twenty-one switch tube is connected to the constant voltage high-level source, and the output end of the twenty-one switch tube and the control end of the twenty-third switch tube and the twentieth The control end of the four switch tubes is connected;
  • the input end of the 22nd switch tube is connected to the constant voltage low level source, and the output end of the 22nd switch tube and the control end of the 23rd switch tube and the first The control end of the twenty-four switch tube is connected;
  • the input end of the 23rd switch tube is connected to the constant voltage high level source, and the output end of the 23rd switch tube is connected to the output end of the output control module;
  • the input end of the 24th switch tube is connected to the constant voltage low level source, and the output end of the 24th switch tube is connected to the output end of the output control module;
  • the nineteenth switch tube, the twenty-first switch tube, and the twenty-third switch tube are PMOS tubes, the twentieth switch tube, the second switch tube, and the Twenty-four switch tubes are NMOS tubes.
  • the scan driving circuit of the present invention can drive the input control module by the cascaded signal of the previous stage and the cascaded signal of the next stage, which can effectively reduce the interference, and the entire scan driving circuit
  • the dynamic power consumption is small; the technical problem of the dynamic power consumption of the existing scan driving circuit is solved.
  • FIG. 1 is a schematic structural view of a first preferred embodiment of a scan driving circuit of the present invention
  • FIG. 2 is a schematic diagram of signal waveforms of a first preferred embodiment of a scan driving circuit of the present invention
  • FIG. 3 is a schematic structural view of a second preferred embodiment of the scan driving circuit of the present invention.
  • FIG. 1 is a schematic structural view of a first preferred embodiment of a scan driving circuit of the present invention.
  • the scan driving circuit of the preferred embodiment is used for driving the cascaded scan lines.
  • the scan drive circuit 10 of each stage includes an input control module 11, a latch module 12, a drive signal generating module 13, and an output control module 14. Constant voltage high level source VGH and constant voltage low level source VGL.
  • the input control module 11 is configured to input the first clock signal CK_1 of the current stage, the concatenated signal Q_N-1 of the previous stage, and the concatenated signal Q_N+1 of the next stage, and according to the first clock signal CK_1 of the current stage,
  • the cascaded signal Q_N-1 of the first stage and the cascaded signal Q_N+1 of the next stage generate a control signal.
  • the latch module 12 is used to perform a latch operation on the control signal.
  • the driving signal generating module 13 is configured to generate a driving signal according to the control signal and the second clock signal CK_2 of the current stage.
  • the output control module 14 is configured to output the scan signal G_N of the current stage according to the driving signal.
  • the constant voltage high level source VGH is used to supply a high level voltage.
  • the constant voltage low level source VGL is used to supply a low level voltage.
  • the input control module 11 of the preferred embodiment includes a first switch tube PT1, a second switch tube PT2, a third switch tube PT3, a fourth switch tube PT4, a fifth switch tube PT5, and a sixth switch tube PT6.
  • the control end of the first switch tube PT1 is input to the first clock signal CK_1 of the current stage, the input end of the first switch tube PT1 is connected to the constant voltage high level source VGH, and the output end of the first switch tube PT1 is connected to the input control module 11 The output is connected.
  • the control end of the second switch tube PT2 inputs the cascaded signal Q_N-1 of the previous stage, the input end of the second switch tube PT2 is connected to the constant voltage high level source VGH, and the output end of the second switch tube PT2 and the third switch The input of the tube PT3 is connected.
  • the control end of the third switch PT3 is input to the cascaded signal Q_N+1 of the next stage, and the output end of the third switch PT3 is connected to the output of the input control module 11.
  • the control end of the fourth switch tube PT4 is input to the first clock signal CK_1 of the current stage, the input end of the fourth switch tube PT4 is connected to the output end of the fifth switch tube PT5, and the output end of the fourth switch tube PT4 is connected to the input control module 11 The output is connected.
  • the control terminal of the fifth switching transistor PT5 inputs the cascaded signal Q_N-1 of the previous stage, and the input terminal of the fifth switching transistor PT5 is connected to the constant voltage low level source VGL.
  • the control end of the sixth switch tube PT6 inputs the cascaded signal Q_N+1 of the next stage, the input end of the sixth switch tube PT6 is connected with the constant voltage low level source VGL, and the output end of the sixth switch tube PT6 and the fifth switch The output of the tube PT5 is connected.
  • the latch module 12 of the preferred embodiment includes a first inverter 121, a second inverter 122, a seventh switch tube PT7, an eighth switch tube PT8, a ninth switch tube PT9, a tenth switch tube PT10, and a tenth A switch tube PT11, a twelfth switch tube PT12, a thirteenth switch tube PT13, and a fourteenth switch tube PT14.
  • the control end of the seventh switch tube PT7 is connected to the output end of the input control module 11, the input end of the seventh switch tube PT7 is connected to the constant voltage high level source VGH, and the output end of the seventh switch tube PT7 and the eighth switch tube PT8 Input connection;
  • the control end of the eighth switch tube PT8 inputs the cascaded signal Q_N-1 of the previous stage, and the output end of the eighth switch tube PT8 is connected to the output end of the latch module 12 through the second inverter 122;
  • the control terminal of the ninth switch PT9 inputs the cascaded signal Q_N-1 of the previous stage, and the output of the ninth switch PT9 is connected to the output of the latch module 12 through the second inverter 122;
  • the control end of the tenth switch tube PT10 is connected to the output end of the input control module 11 through the first inverter 121, the input end of the tenth switch tube PT10 is connected to the constant voltage low level source VGL, and the output of the tenth switch tube PT10 The end is connected to the input end of the ninth switch tube PT9;
  • the control end of the eleventh switch tube PT11 is connected to the output end of the input control module 11 through the first inverter 121, and the input end of the eleventh switch tube PT11 is connected to the constant voltage high level source VGH, and the eleventh switch tube The output end of the PT11 is connected to the input end of the twelfth switch tube PT12;
  • the control end of the twelfth switch tube PT12 is connected to the output end of the latch module 12, and the output end of the twelfth switch tube PT12 is connected to the output end of the latch module 12 through the second inverter 122;
  • the control end of the thirteenth switch tube PT13 is connected to the output end of the latch module 12, and the output end of the thirteenth switch tube PT13 is connected to the output end of the latch module 12 through the second inverter 122;
  • the control end of the fourteenth switch tube PT14 is connected to the output end of the input control module 11, the input end of the fourteenth switch tube PT14 is connected to the constant voltage low level source VGL, and the output end of the fourteenth switch tube PT14 is the tenth The input end of the three-switch PT13 is connected.
  • the driving signal generating module 13 of the preferred embodiment includes a fifteenth switch tube PT15, a sixteenth switch tube PT16, a seventeenth switch tube PT17, and an eighteenth switch tube PT18.
  • the control end of the fifteenth switch tube PT15 is connected to the output end of the latch module 12, the input end of the fifteenth switch tube PT15 is connected to the constant voltage high level source VGH, and the output end of the fifteenth switch tube PT15 and the drive signal The output of the generating module 13 is connected;
  • the control end of the sixteenth switch tube PT16 is input to the second clock signal CK_2 of the current stage, the input end of the sixteenth switch tube PT16 is connected with the constant voltage high level source VGH, and the output end of the sixteenth switch tube PT16 and the drive signal The output of the generating module 13 is connected;
  • the control end of the seventeenth switch tube PT17 is connected to the output end of the latch module 12, the input end of the seventeenth switch tube PT17 is connected to the output end of the eighteenth switch tube PT18, and the output end of the seventeenth switch tube PT17 is The output of the driving signal generating module 13 is connected;
  • the control end of the eighteenth switch tube PT18 is input to the second clock signal CK_2 of the current stage, and the input end of the eighteenth switch tube PT18 is connected to the constant voltage low level source VGL.
  • the output control module 14 of the preferred embodiment includes a nineteenth switch tube PT19, a twentieth switch tube PT20, a twenty-first switch tube PT21, a twenty-second switch tube PT22, a twenty-third switch tube PT23, and a second Fourteen switch tube PT24.
  • the control end of the nineteenth switch tube PT19 is connected to the output end of the drive signal generating module 13, the input end of the nineteenth switch tube PT19 is connected to the constant voltage high level source VGH, and the output end of the nineteenth switch tube PT19 is respectively
  • the control end of the twenty-first switch tube PT21 is connected to the control end of the twenty-second switch tube PT22;
  • the control end of the twentieth switch tube PT20 is connected to the output end of the drive signal generating module 13, the input end of the twentieth switch tube PT20 is connected to the constant voltage low level source VGL, and the output end of the twentieth switch tube PT20 is respectively
  • the control end of the twenty-one switch tube PT21 is connected to the control end of the twenty-second switch tube PT22;
  • the input end of the twenty-first switch tube PT21 is connected with the constant voltage high level source VGH, and the output end of the twenty-first switch tube PT21 is respectively connected with the control end of the twenty-third switch tube PT23 and the twenty-fourth switch tube PT24 Control terminal connection;
  • the input end of the 22nd switch tube PT22 is connected with the constant voltage low level source VGL, and the output end of the 22nd switch tube PT22 is respectively connected with the control end of the 23rd switch tube PT23 and the 24th switch tube PT24 Control terminal connection;
  • the input end of the twenty-third switch tube PT23 is connected to the constant voltage high level source VGH, and the output end of the twenty-third switch tube PT23 is connected to the output end of the output control module 14;
  • the input end of the twenty-fourth switch tube PT24 is connected to the constant voltage low level source VGL, and the output end of the twenty-fourth switch tube PT24 is connected to the output end of the output control module 14.
  • the first switch tube PT1, the second switch tube PT2, and the third switch tube PT3 are PMOS tubes
  • the fourth switch tube PT4, the fifth switch tube PT5, and the sixth switch tube PT6 are NMOS tubes.
  • the seventh switch tube PT7, the eighth switch tube PT8, the eleventh switch tube PT11, and the twelfth switch tube PT12 are PMOS tubes
  • the four switch tube PT14 is an NMOS tube.
  • the fifteenth switch tube PT15 and the sixteenth switch tube PT16 are PMOS tubes
  • the seventeenth switch tube PT17 and the eighteenth switch tube PT18 are NMOS tubes.
  • the nineteenth switch tube PT19, the twenty-first switch tube PT21 and the twenty-third switch tube PT23 are PMOS tubes
  • the twentieth switch tube PT20, the twenty-second switch tube PT22 and the twenty-fourth switch tube PT24 are NMOS tube.
  • FIG. 2 is a schematic diagram of signal waveforms of the first preferred embodiment of the scan driving circuit of the present invention.
  • the fifth switching transistor PT5 When the cascaded signal Q_N-1 of the upper stage is at a high level, the fifth switching transistor PT5 is turned on, so that when the fourth switching transistor PT4 is turned on by the first clock signal CK_1 of the current level of the high level
  • the output of the input control module 11 outputs a low level control signal.
  • the control signal of the low level is converted to the control signal CK. of the high level through the first inverter 121, and is input to the control end of the tenth switch tube PT10, and the control end of the ninth switch tube PT9 is input to the high level.
  • the cascade signal Q_N-1 of the previous stage so that the ninth switch tube PT9 and the tenth switch tube PT10 are simultaneously turned on, and the eighth switch tube PT8 is turned off, and the low potential signal of the constant voltage low level source VGL passes the tenth
  • the switching transistor PT10, the ninth switching transistor PT9, and the second inverter 122 become a high-level cascade signal Q_N of the current stage, and are output from the output terminal of the latch module 12.
  • the high-level cascaded signal Q_N of this stage is simultaneously input to the scan drive circuit of the next stage.
  • the first clock signal CK_1 is converted into a low level signal, and the output end of the input control module 11 outputs a high level control signal through the first switching transistor PT1.
  • the high-level control signal XCK is input to the control terminal of the fourteenth switch tube PT14, and the high-level cascaded signal Q_N of the current stage is input to the control end of the thirteenth switch tube PT13, so that the thirteenth switch tube PT13 and The fourteenth switch tube PT14 is turned on at the same time, and the twelfth switch tube PT12 is turned off, and the low level signal of the constant voltage low level source VGL passes through the fourteenth switch tube PT14, the thirteenth switch tube PT13, and the second reverse
  • the cascaded signal Q_N of the current stage in which the phaser 122 becomes a high level is outputted from the output terminal of the latch module 12, that is, the cascaded signal Q_N of the current stage of the high potential is latched.
  • the output of the input control module 11 outputs a low level control signal again.
  • the cascaded signal Q_N-1 of the previous stage has turned to a low level, at which time the seventh switch tube PT7 and the eighth switch tube PT8 are turned on, and the high-level potential of the constant-voltage high-level source VGH passes through
  • the cascaded signal Q_N of the current stage in which the seven-switching transistor PT7, the eighth switching transistor PT8, and the second inverter 122 become a low level is output from the output terminal of the latch module 12.
  • the cascading signal Q_N of this level of the low level is simultaneously input to the scan driving circuit of the next stage.
  • the first clock signal CK_1 is converted into a low level signal, and the output end of the input control module 11 outputs a high level control signal through the first switching transistor PT1.
  • the high-level control signal is input to the control terminal of the eleventh switch PT11 through the control signal CK that is converted to the low level by the first inverter 121, and the cascaded signal Q_N of the current level of the low level is input to The control end of the twelfth switch tube PT12, such that the eleventh switch tube PT11 and the twelfth switch tube PT12 are simultaneously turned on, and the thirteenth switch tube PT13 is turned off, the high voltage signal of the constant voltage high level source VGH
  • the cascaded signal Q_N of the current stage that has become a low level through the eleventh switch PT11, the twelfth switch PT12, and the second inverter 122 is output from the output terminal of the latch module 12, that is, to a low level
  • the cascaded signal Q_N of this stage is latched.
  • the driving signal generating module 13 functions as a NAND gate, that is, the cascading signal Q_N of the current stage outputted by the latching module 12 is NANDed with the second clock signal CK_2 of the current stage. Specifically, when the cascaded signal Q_N of the current stage and the second clock signal CK_2 of the current stage are simultaneously at a high level, the fifteenth switch tube PT15 and the sixteenth switch tube PT16 are disconnected, and the seventeenth switch tube PT17 and the The eighteen switch tube PT18 is turned on, at which time the output end of the drive signal generating module 13 outputs a low level voltage of the constant voltage low level source VGL.
  • the twentieth switch tube PT20 When the driving signal outputted by the driving signal generating module 13 is at a high level, the twentieth switch tube PT20 is turned on, and the nineteenth switch tube PT19 is turned off; the low voltage of the constant voltage low level source VGL is input to the twentieth The control end of a switch tube PT21 and the control end of the 22nd switch tube PT22, the 21st switch tube PT21 is turned on, the 22nd switch tube PT22 is turned off, and the constant voltage high level source VGH is high level The voltage is input to the control end of the twenty-third switch tube PT23 and the control end of the twenty-fourth switch tube PT24, the twenty-third switch tube PT23 is turned off, the twenty-fourth switch tube PT24 is turned on, and the output control module 13 outputs The scanning signal G_N of the current level of the low level.
  • the twentieth switch tube PT20 When the driving signal outputted by the driving signal generating module 13 is low level, the twentieth switch tube PT20 is turned off, and the nineteenth switch tube PT19 is turned on; the high level voltage of the constant voltage high level source VGH is input to the twentieth The control end of a switching tube PT21 and the control end of the twenty-second switching tube PT22, the twenty-first switching tube PT21 is turned off, the twenty-second switching tube PT22 is turned on, the low voltage of the constant voltage low level source VGL The voltage is input to the control end of the twenty-third switch tube PT23 and the control end of the twenty-fourth switch tube PT24, the twenty-third switch tube PT23 is turned on, the twenty-fourth switch tube PT24 is turned off, and the output control module 13 outputs The scanning signal G_N of the current level of the high level.
  • the cascading signal Q_N-1 of the first stage has noise fluctuation, and when the cascading signal Q_N+1 of the next stage is in a normal state, the final output is not
  • the scanning signal G_N is specifically shown in the area A of FIG. Therefore, the scan driving circuit of the preferred embodiment can drive the input control module by the cascaded signal of the previous stage and the cascaded signal of the next stage, and the interference can be effectively reduced.
  • FIG. 3 is a schematic structural diagram of a second preferred embodiment of the scan driving circuit of the present invention.
  • the input control module 21 of the scan driving circuit 20 of the preferred embodiment includes a first switch tube PT1, a second switch tube PT2, a third switch tube PT3, and a fourth switch tube PT4.
  • the control end of the first switch tube PT1 is input to the first clock signal CK_1 of the current stage, the input end of the first switch tube PT1 is connected to the constant voltage high level source VGH, and the output end of the first switch tube PT1 is connected to the input control module 21 Output connection;
  • the control end of the second switch tube PT2 inputs the cascaded signal Q_N-1 of the previous stage, the input end of the second switch tube PT2 is connected to the constant voltage high level source VGH, and the output end of the second switch tube PT2 and the third switch The input end of the tube PT3 is connected;
  • the control end of the third switch tube PT3 is input to the cascaded signal Q_N+1 of the next stage, and the output end of the third switch tube PT3 is connected to the output end of the input control module 21;
  • the control end of the fourth switch tube PT4 is input to the first clock signal CK_1 of the current stage, the input end of the fourth switch tube PT4 is connected to the constant voltage low level source VGL, and the output end of the fourth switch tube PT4 and the fifth switch tube PT5 Input connection;
  • the control end of the fifth switch tube PT5 inputs the cascaded signal Q_N-1 of the upper stage, and the output end of the fifth switch tube PT5 is connected with the output end of the input control module 21;
  • the control end of the sixth switch tube PT6 inputs the cascaded signal Q_N+1 of the next stage, the input end of the sixth switch tube PT6 is connected to the input end of the fifth switch tube PT5, and the output end of the sixth switch tube PT6 and the input control The output of module 21 is connected.
  • the specific working principle of the scan driving circuit 20 of the preferred embodiment is the same as or similar to the description of the first preferred embodiment described above. For details, refer to the related description in the first preferred embodiment.
  • the scan driving circuit of the preferred embodiment further enhances the configuration flexibility of the scan driving circuit based on the first preferred embodiment.
  • the scan driving circuit of the invention drives the input control module through the cascaded signal of the upper stage and the cascaded signal of the next stage, which can effectively reduce the interference, and the dynamic power consumption of the entire scan driving circuit is small; There are technical problems with large dynamic power consumption of the scan drive circuit.

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Abstract

一种扫描驱动电路（10，20），用于对级联的扫描线进行驱动操作，其包括输入控制模块（11，21）、锁存模块（12）、驱动信号产生模块（13）、输出控制模块（14）、恒压高电平源（VGH）以及恒压低电平源（VGL）。该扫描驱动电路（10，20）通过上一级的级联信号（Q -N-1）以及下一级的级联信号（Q -N+1）进行输入控制模块（11，21）的驱动，可以有效的降低干扰，并且整个扫描驱动电路（10，20）的动态功耗较小。

Description

一种扫描驱动电路 技术领域
本发明涉及显示驱动领域，特别是涉及一种扫描驱动电路。
背景技术
Gate Driver On Array，简称GOA，即在现有薄膜晶体管液晶显示器的阵列基板上制作扫描驱动电路，实现对扫描线逐行扫描的驱动方式。
但是现有的扫描驱动电路均需要使用时钟信号CK和上一级的级联信号Q_N-1进行驱动，由于上一级的级联信号在容易受到相应的时钟信号CK的干扰，造成影响正常的显示驱动。同时上一级的级联信号Q_N-1的波动也会造成扫描驱动电路额外的功耗。
故，有必要提供一种扫描驱动电路，以解决现有技术所存在的问题。
 技术问题
本发明的目的在于提供一种结构简单且功耗较小的扫描驱动电路，以解决现有的扫描驱动电路的动态功耗较大的技术问题。
 技术解决方案
为解决上述问题，本发明提供的技术方案如下：
本发明实施例提供一种扫描驱动电路，用于对级联的扫描线进行驱动操作，其中所述扫描驱动电路包括：
输入控制模块，用于输入本级的第一时钟信号、上一级的级联信号以及下一级的级联信号，并根据所述本级的第一时钟信号、所述上一级的级联信号以及所述下一级的级联信号产生控制信号；
锁存模块，用于对所述控制信号进行锁存操作；
驱动信号产生模块，用于根据所述控制信号以及本级的第二时钟信号产生驱动信号；
输出控制模块，用于根据所述驱动信号输出本级的扫描信号；
恒压高电平源，用于提供高电平电压；以及
恒压低电平源，用于提供低电平电压；
其中将所述控制信号的反向信号作为本级的级联信号输入到下一级的扫描驱动电路中；
所述输出控制模块包括第十九开关管、第二十开关管、第二十一开关管、第二十二开关管、第二十三开关管以及第二十四开关管；
所述第十九开关管的控制端与所述驱动信号产生模块的输出端连接，所述第十九开关管的输入端与所述恒压高电平源连接，所述第十九开关管的输出端分别与所述第二十一开关管的控制端和所述第二十二开关管的控制端连接；
所述第二十开关管的控制端与所述驱动信号产生模块的输出端连接，所述第二十开关管的输入端与所述恒压低电平源连接，所述第二十开关管的输出端分别与所述二十一开关管的控制端和所述第二十二开关管的控制端连接；
所述第二十一开关管的输入端与所述恒压高电平源连接，所述第二十一开关管的输出端分别与所述第二十三开关管的控制端和所述第二十四开关管的控制端连接；
所述第二十二开关管的输入端与所述恒压低电平源连接，所述第二十二开关管的输出端分别与所述第二十三开关管的控制端和所述第二十四开关管的控制端连接；
所述第二十三开关管的输入端与所述恒压高电平源连接，所述第二十三开关管的输出端与所述输出控制模块的输出端连接；
所述第二十四开关管的输入端与所述恒压低电平源连接，所述第二十四开关管的输出端与所述输出控制模块的输出端连接；
其中所述第十九开关管、所述第二十一开关管以及所述第二十三开关管为PMOS管，所述第二十开关管、所述第二十二开关管以及所述第二十四开关管为NMOS管。
在本发明所述的扫描驱动电路中，所述输入控制模块包括第一开关管、第二开关管、第三开关管、第四开关管、第五开关管以及第六开关管；
所述第一开关管的控制端输入所述本级的第一时钟信号，所述第一开关管的输入端与所述恒压高电平源连接，所述第一开关管的输出端与所述输入控制模块的输出端连接；
所述第二开关管的控制端输入所述上一级的级联信号，所述第二开关管的输入端与所述恒压高电平源连接，所述第二开关管的输出端与所述第三开关管的输入端连接；
所述第三开关管的控制端输入所述下一级的级联信号，所述第三开关管的输出端与所述输入控制模块的输出端连接；
所述第四开关管的控制端输入所述本级的第一时钟信号，所述第四开关管的输入端与所述第五开关管的输出端连接，所述第四开关管的输出端与所述输入控制模块的输出端连接；
所述第五开关管的控制端输入所述上一级的级联信号，所述第五开关管的输入端与所述恒压低电平源连接；
所述第六开关管的控制端输入所述下一级的级联信号，所述第六开关管的输入端与所述恒压低电平源连接，所述第六开关管的输出端与所述第五开关管的输出端连接。
在本发明所述的扫描驱动电路中，所述第一开关管、所述第二开关管以及所述第三开关管为PMOS管，所述第四开关管、所述第五开关管以及所述第六开关管为NMOS管。
在本发明所述的扫描驱动电路中，所述输入控制模块包括第一开关管、第二开关管、第三开关管、第四开关管、第五开关管以及第六开关管；
所述第一开关管的控制端输入所述本级的第一时钟信号，所述第一开关管的输入端与所述恒压高电平源连接，所述第一开关管的输出端与所述输入控制模块的输出端连接；
所述第二开关管的控制端输入所述上一级的级联信号，所述第二开关管的输入端与所述恒压高电平源连接，所述第二开关管的输出端与所述第三开关管的输入端连接；
所述第三开关管的控制端输入所述下一级的级联信号，所述第三开关管的输出端与所述输入控制模块的输出端连接；
所述第四开关管的控制端输入所述本级的第一时钟信号，所述第四开关管的输入端与所述恒压低电平源连接，所述第四开关管的输出端与所述第五开关管的输入端连接；
所述第五开关管的控制端输入所述上一级的级联信号，所述第五开关管的输出端与所述输入控制模块的输出端连接；
所述第六开关管的控制端输入所述下一级的级联信号，所述第六开关管的输入端与所述第五开关管的输入端连接，所述第六开关管的输出端与所述输入控制模块的输出端连接。
在本发明所述的扫描驱动电路中，所述第一开关管、所述第二开关管以及所述第三开关管为PMOS管，所述第四开关管、所述第五开关管以及所述第六开关管为NMOS管。
在本发明所述的扫描驱动电路中，所述锁存模块包括第一反相器、第二反相器、第七开关管、第八开关管、第九开关管、第十开关管、第十一开关管、第十二开关管、第十三开关管以及第十四开关管；
所述第七开关管的控制端与所述输入控制模块的输出端连接，所述第七开关管的输入端与所述恒压高电平源连接，所述第七开关管的输出端与所述第八开关管的输入端连接；
所述第八开关管的控制端输入上一级的级联信号，所述第八开关管的输出端通过所述第二反相器与所述锁存模块的输出端连接；
所述第九开关管的控制端输入上一级的级联信号，所述第九开关管的输出端通过所述第二反相器与所述锁存模块的输出端连接；
所述第十开关管的控制端通过所述第一反相器与所述输入控制模块的输出端连接，所述第十开关管的输入端与所述恒压低电平源连接，所述第十开关管的输出端与所述第九开关管的输入端连接；
所述第十一开关管的控制端通过所述第一反相器与所述输入控制模块的输出端连接，所述第十一开关管的输入端与所述恒压高电平源连接，所述第十一开关管的输出端与所述第十二开关管的输入端连接；
所述第十二开关管的控制端与所述锁存模块的输出端连接，所述第十二开关管的输出端通过所述第二反相器与所述锁存模块的输出端连接；
所述第十三开关管的控制端与所述锁存模块的输出端连接，所述第十三开关管的输出端通过所述第二反相器与所述锁存模块的输出端连接；
所述第十四开关管的控制端与所述输入控制模块的输出端连接，所述第十四开关管的输入端与所述恒压低电平源连接，所述第十四开关管的输出端与所述第十三开关管的输入端连接。
在本发明所述的扫描驱动电路中，所述第七开关管、所述第八开关管、所述第十一开关管以及所述第十二开关管为PMOS管，所述第九开关管、所述第十开关管、所述第十三开关管以及所述第十四开关管为NMOS管。
在本发明所述的扫描驱动电路中，所述驱动信号产生模块包括第十五开关管、第十六开关管、第十七开关管以及第十八开关管；
所述第十五开关管的控制端与所述锁存模块的输出端连接，所述第十五开关管的输入端与所述恒压高电平源连接，所述第十五开关管的输出端与所述驱动信号产生模块的输出端连接；
所述第十六开关管的控制端输入本级的第二时钟信号，所述第十六开关管的输入端与所述恒压高电平源连接，所述第十六开关管的输出端与所述驱动信号产生模块的输出端连接；
所述第十七开关管的控制端与所述锁存模块的输出端连接，所述第十七开关管的输入端与所述第十八开关管的输出端连接，所述第十七开关管的输出端与所述驱动信号产生模块的输出端连接；
所述第十八开关管的控制端输入本级的第二时钟信号，所述第十八开关管的输入端与所述恒压低电平源连接。
在本发明所述的扫描驱动电路中，，所述第十五开关管和所述第十六开关管为PMOS管，所述第十七开关管和所述第十八开关管为NMOS管。
本发明实施例提供一种扫描驱动电路，用于对级联的扫描线进行驱动操作，其包括：
输入控制模块，用于输入本级的第一时钟信号、上一级的级联信号以及下一级的级联信号，并根据所述本级的第一时钟信号、所述上一级的级联信号以及所述下一级的级联信号产生控制信号；
锁存模块，用于对所述控制信号进行锁存操作；
驱动信号产生模块，用于根据所述控制信号以及本级的第二时钟信号产生驱动信号；
输出控制模块，用于根据所述驱动信号输出本级的扫描信号；
恒压高电平源，用于提供高电平电压；以及
恒压低电平源，用于提供低电平电压。
在本发明所述的扫描驱动电路中，所述输入控制模块包括第一开关管、第二开关管、第三开关管、第四开关管、第五开关管以及第六开关管；
所述第一开关管的控制端输入所述本级的第一时钟信号，所述第一开关管的输入端与所述恒压高电平源连接，所述第一开关管的输出端与所述输入控制模块的输出端连接；
所述第二开关管的控制端输入所述上一级的级联信号，所述第二开关管的输入端与所述恒压高电平源连接，所述第二开关管的输出端与所述第三开关管的输入端连接；
所述第三开关管的控制端输入所述下一级的级联信号，所述第三开关管的输出端与所述输入控制模块的输出端连接；
所述第四开关管的控制端输入所述本级的第一时钟信号，所述第四开关管的输入端与所述第五开关管的输出端连接，所述第四开关管的输出端与所述输入控制模块的输出端连接；
所述第五开关管的控制端输入所述上一级的级联信号，所述第五开关管的输入端与所述恒压低电平源连接；
所述第六开关管的控制端输入所述下一级的级联信号，所述第六开关管的输入端与所述恒压低电平源连接，所述第六开关管的输出端与所述第五开关管的输出端连接。
在本发明所述的扫描驱动电路中，所述输入控制模块包括第一开关管、第二开关管、第三开关管、第四开关管、第五开关管以及第六开关管；
所述第一开关管的控制端输入所述本级的第一时钟信号，所述第一开关管的输入端与所述恒压高电平源连接，所述第一开关管的输出端与所述输入控制模块的输出端连接；
所述第二开关管的控制端输入所述上一级的级联信号，所述第二开关管的输入端与所述恒压高电平源连接，所述第二开关管的输出端与所述第三开关管的输入端连接；
所述第三开关管的控制端输入所述下一级的级联信号，所述第三开关管的输出端与所述输入控制模块的输出端连接；
所述第四开关管的控制端输入所述本级的第一时钟信号，所述第四开关管的输入端与所述恒压低电平源连接，所述第四开关管的输出端与所述第五开关管的输入端连接；
所述第五开关管的控制端输入所述上一级的级联信号，所述第五开关管的输出端与所述输入控制模块的输出端连接；
所述第六开关管的控制端输入所述下一级的级联信号，所述第六开关管的输入端与所述第五开关管的输入端连接，所述第六开关管的输出端与所述输入控制模块的输出端连接。
在本发明所述的扫描驱动电路中，所述第一开关管、所述第二开关管以及所述第三开关管为PMOS管，所述第四开关管、所述第五开关管以及所述第六开关管为NMOS管。
在本发明所述的扫描驱动电路中，所述锁存模块包括第一反相器、第二反相器、第七开关管、第八开关管、第九开关管、第十开关管、第十一开关管、第十二开关管、第十三开关管以及第十四开关管；
所述第七开关管的控制端与所述输入控制模块的输出端连接，所述第七开关管的输入端与所述恒压高电平源连接，所述第七开关管的输出端与所述第八开关管的输入端连接；
所述第八开关管的控制端输入上一级的级联信号，所述第八开关管的输出端通过所述第二反相器与所述锁存模块的输出端连接；
所述第九开关管的控制端输入上一级的级联信号，所述第九开关管的输出端通过所述第二反相器与所述锁存模块的输出端连接；
所述第十开关管的控制端通过所述第一反相器与所述输入控制模块的输出端连接，所述第十开关管的输入端与所述恒压低电平源连接，所述第十开关管的输出端与所述第九开关管的输入端连接；
所述第十一开关管的控制端通过所述第一反相器与所述输入控制模块的输出端连接，所述第十一开关管的输入端与所述恒压高电平源连接，所述第十一开关管的输出端与所述第十二开关管的输入端连接；
所述第十二开关管的控制端与所述锁存模块的输出端连接，所述第十二开关管的输出端通过所述第二反相器与所述锁存模块的输出端连接；
所述第十三开关管的控制端与所述锁存模块的输出端连接，所述第十三开关管的输出端通过所述第二反相器与所述锁存模块的输出端连接；
所述第十四开关管的控制端与所述输入控制模块的输出端连接，所述第十四开关管的输入端与所述恒压低电平源连接，所述第十四开关管的输出端与所述第十三开关管的输入端连接。
在本发明所述的扫描驱动电路中，所述第七开关管、所述第八开关管、所述第十一开关管以及所述第十二开关管为PMOS管，所述第九开关管、所述第十开关管、所述第十三开关管以及所述第十四开关管为NMOS管。
在本发明所述的扫描驱动电路中，所述驱动信号产生模块包括第十五开关管、第十六开关管、第十七开关管以及第十八开关管；
所述第十五开关管的控制端与所述锁存模块的输出端连接，所述第十五开关管的输入端与所述恒压高电平源连接，所述第十五开关管的输出端与所述驱动信号产生模块的输出端连接；
所述第十六开关管的控制端输入本级的第二时钟信号，所述第十六开关管的输入端与所述恒压高电平源连接，所述第十六开关管的输出端与所述驱动信号产生模块的输出端连接；
所述第十七开关管的控制端与所述锁存模块的输出端连接，所述第十七开关管的输入端与所述第十八开关管的输出端连接，所述第十七开关管的输出端与所述驱动信号产生模块的输出端连接；
所述第十八开关管的控制端输入本级的第二时钟信号，所述第十八开关管的输入端与所述恒压低电平源连接。
在本发明所述的扫描驱动电路中，所述第十五开关管和所述第十六开关管为PMOS管，所述第十七开关管和所述第十八开关管为NMOS管。
在本发明所述的扫描驱动电路中，将所述控制信号的反向信号作为本级的级联信号输入到下一级的扫描驱动电路中。
在本发明所述的扫描驱动电路中，所述输出控制模块包括第十九开关管、第二十开关管、第二十一开关管、第二十二开关管、第二十三开关管以及第二十四开关管；
所述第十九开关管的控制端与所述驱动信号产生模块的输出端连接，所述第十九开关管的输入端与所述恒压高电平源连接，所述第十九开关管的输出端分别与所述第二十一开关管的控制端和所述第二十二开关管的控制端连接；
所述第二十开关管的控制端与所述驱动信号产生模块的输出端连接，所述第二十开关管的输入端与所述恒压低电平源连接，所述第二十开关管的输出端分别与所述二十一开关管的控制端和所述第二十二开关管的控制端连接；
所述二十一开关管的输入端与所述恒压高电平源连接，所述二十一开关管的输出端分别与所述第二十三开关管的控制端和所述第二十四开关管的控制端连接；
所述第二十二开关管的输入端与所述恒压低电平源连接，所述第二十二开关管的输出端分别与所述第二十三开关管的控制端和所述第二十四开关管的控制端连接；
所述第二十三开关管的输入端与所述恒压高电平源连接，所述第二十三开关管的输出端与所述输出控制模块的输出端连接；
所述第二十四开关管的输入端与所述恒压低电平源连接，所述第二十四开关管的输出端与所述输出控制模块的输出端连接；
其中所述第十九开关管、所述第二十一开关管以及所述第二十三开关管为PMOS管，所述第二十开关管、所述第二十二开关管以及所述第二十四开关管为NMOS管。
 有益效果
相较于现有的扫描驱动电路，本发明的扫描驱动电路通过上一级的级联信号以及下一级的级联信号进行输入控制模块的驱动，可以有效的降低干扰，并且整个扫描驱动电路的动态功耗较小；解决了现有的扫描驱动电路的动态功耗较大的技术问题。
 附图说明
图1为本发明的扫描驱动电路的第一优选实施例的结构示意图；
图2为本发明的扫描驱动电路的第一优选实施例的信号波形示意图；
图3为本发明的扫描驱动电路的第二优选实施例的结构示意图。
 本发明的最佳实施方式
以下各实施例的说明是参考附加的图式，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。
在图中，结构相似的单元是以相同标号表示。
请参照图1，图1为本发明的扫描驱动电路的第一优选施实施例的结构示意图。本优选实施例的扫描驱动电路用于对级联的扫描线进行驱动操作，每一级的扫描驱动电路10包括输入控制模块11、锁存模块12、驱动信号产生模块13、输出控制模块14、恒压高电平源VGH以及恒压低电平源VGL。
输入控制模块11用于输入本级的第一时钟信号CK_1、上一级的级联信号Q_N-1以及下一级的级联信号Q_N+1，并根据本级的第一时钟信号CK_1、上一级的级联信号Q_N-1以及下一级的级联信号Q_N+1产生控制信号。锁存模块12用于对控制信号进行锁存操作。驱动信号产生模块13用于根据控制信号以及本级的第二时钟信号CK_2产生驱动信号。输出控制模块14用于根据驱动信号输出本级的扫描信号G_N。恒压高电平源VGH用于提供高电平电压。恒压低电平源VGL用于提供低电平电压。
本优选实施例的输入控制模块11包括第一开关管PT1、第二开关管PT2、第三开关管PT3、第四开关管PT4、第五开关管PT5以及第六开关管PT6。
第一开关管PT1的控制端输入本级的第一时钟信号CK_1，第一开关管PT1的输入端与恒压高电平源VGH连接，第一开关管PT1的输出端与输入控制模块11的输出端连接。
第二开关管PT2的控制端输入上一级的级联信号Q_N-1，第二开关管PT2的输入端与恒压高电平源VGH连接，第二开关管PT2的输出端与第三开关管PT3的输入端连接。
第三开关管PT3的控制端输入下一级的级联信号Q_N+1，第三开关管PT3的输出端与输入控制模块11的输出端连接。
第四开关管PT4的控制端输入本级的第一时钟信号CK_1，第四开关管PT4的输入端与第五开关管PT5的输出端连接，第四开关管PT4的输出端与输入控制模块11的输出端连接。
第五开关管PT5的控制端输入上一级的级联信号Q_N-1，第五开关管PT5的输入端与恒压低电平源VGL连接。
第六开关管PT6的控制端输入下一级的级联信号Q_N+1，第六开关管PT6的输入端与恒压低电平源VGL连接，第六开关管PT6的输出端与第五开关管PT5的输出端连接。
本优选实施例的锁存模块12包括第一反相器121、第二反相器122、第七开关管PT7、第八开关管PT8、第九开关管PT9、第十开关管PT10、第十一开关管PT11、第十二开关管PT12、第十三开关管PT13以及第十四开关管PT14。
第七开关管PT7的控制端与输入控制模块11的输出端连接，第七开关管PT7的输入端与恒压高电平源VGH连接，第七开关管PT7的输出端与第八开关管PT8的输入端连接；
第八开关管PT8的控制端输入上一级的级联信号Q_N-1，第八开关管PT8的输出端通过第二反相器122与锁存模块12的输出端连接；
第九开关管PT9的控制端输入上一级的级联信号Q_N-1，第九开关管PT9的输出端通过第二反相器122与所述锁存模块12的输出端连接；
第十开关管PT10的控制端通过第一反相器121与输入控制模块11的输出端连接，第十开关管PT10的输入端与恒压低电平源VGL连接，第十开关管PT10的输出端与第九开关管PT9的输入端连接；
第十一开关管PT11的控制端通过第一反相器121与输入控制模块11的输出端连接，第十一开关管PT11的输入端与恒压高电平源VGH连接，第十一开关管PT11的输出端与第十二开关管PT12的输入端连接；
第十二开关管PT12的控制端与锁存模块12的输出端连接，第十二开关管PT12的输出端通过第二反相器122与锁存模块12的输出端连接；
第十三开关管PT13的控制端与锁存模块12的输出端连接，第十三开关管PT13的输出端通过第二反相器122与锁存模块12的输出端连接；
第十四开关管PT14的控制端与输入控制模块11的输出端连接，第十四开关管PT14的输入端与恒压低电平源VGL连接，第十四开关管PT14的输出端与第十三开关管PT13的输入端连接。
本优选实施例的驱动信号产生模块13包括第十五开关管PT15、第十六开关管PT16、第十七开关管PT17以及第十八开关管PT18。
第十五开关管PT15的控制端与锁存模块12的输出端连接，第十五开关管PT15的输入端与恒压高电平源VGH连接，第十五开关管PT15的输出端与驱动信号产生模块13的输出端连接；
第十六开关管PT16的控制端输入本级的第二时钟信号CK_2，第十六开关管PT16的输入端与恒压高电平源VGH连接，第十六开关管PT16的输出端与驱动信号产生模块13的输出端连接；
第十七开关管PT17的控制端与锁存模块12的输出端连接，第十七开关管PT17的输入端与第十八开关管PT18的输出端连接，第十七开关管PT17的输出端与驱动信号产生模块13的输出端连接；
第十八开关管PT18的控制端输入本级的第二时钟信号CK_2，第十八开关管PT18的输入端与恒压低电平源VGL连接。
本优选实施例的输出控制模块14包括第十九开关管PT19、第二十开关管PT20、第二十一开关管PT21、第二十二开关管PT22、第二十三开关管PT23以及第二十四开关管PT24。
第十九开关管PT19的控制端与驱动信号产生模块13的输出端连接，第十九开关管PT19的输入端与恒压高电平源VGH连接，第十九开关管PT19的输出端分别与第二十一开关管PT21的控制端和第二十二开关管PT22的控制端连接；
第二十开关管PT20的控制端与驱动信号产生模块13的输出端连接，第二十开关管PT20的输入端与恒压低电平源VGL连接，第二十开关管PT20的输出端分别与二十一开关管PT21的控制端和第二十二开关管PT22的控制端连接；
第二十一开关管PT21的输入端与恒压高电平源VGH连接，第二十一开关管PT21的输出端分别与第二十三开关管PT23的控制端和第二十四开关管PT24的控制端连接；
第二十二开关管PT22的输入端与恒压低电平源VGL连接，第二十二开关管PT22的输出端分别与第二十三开关管PT23的控制端和第二十四开关管PT24的控制端连接；
第二十三开关管PT23的输入端与恒压高电平源VGH连接，第二十三开关管PT23的输出端与输出控制模块14的输出端连接；
第二十四开关管PT24的输入端与恒压低电平源VGL连接，第二十四开关管PT24的输出端与输出控制模块14的输出端连接。
在本优选实施例中第一开关管PT1、第二开关管PT2、第三开关管PT3为PMOS管，第四开关管PT4、第五开关管PT5以及第六开关管PT6为NMOS管。第七开关管PT7、第八开关管PT8、第十一开关管PT11以及第十二开关管PT12为PMOS管，第九开关管PT9、第十开关管PT10、第十三开关管PT13以及第十四开关管PT14为NMOS管。第十五开关管PT15和第十六开关管PT16为PMOS管，第十七开关管PT17和第十八开关管PT18为NMOS管。第十九开关管PT19、第二十一开关管PT21以及第二十三开关管PT23为PMOS管，第二十开关管PT20、第二十二开关管PT22以及第二十四开关管PT24为NMOS管。
本优选实施例的扫描驱动电路使用时，请参照图1至图2，图2为本发明的扫描驱动电路的第一优选实施例的信号波形示意图。
当上一级的级联信号Q_N-1为高电平时，第五开关管PT5导通，这样当第四开关管PT4在高电平的本级的第一时钟信号CK_1的作用下导通时，输入控制模块11的输出端输出低电平的控制信号。
低电平的控制信号通过第一反相器121，转变为高电平的控制信号CK.，输入到第十开关管PT10的控制端，同时第九开关管PT9的控制端输入高电平的上一级的级联信号Q_N-1,这样第九开关管PT9和第十开关管PT10同时导通，且第八开关管PT8断开，恒压低电平源VGL的低电位信号通过第十开关管PT10、第九开关管PT9以及第二反相器122变成高电位的本级的级联信号Q_N，从锁存模块12的输出端输出。该高电位的本级的级联信号Q_N同时输入到下一级的扫描驱动电路中。
随后第一时钟信号CK_1转变为低电平信号，输入控制模块11的输出端通过第一开关管PT1输出高电平的控制信号。
高电平的控制信号XCK输入到第十四开关管PT14的控制端，同时高电位的本级的级联信号Q_N输入到第十三开关管PT13的控制端，这样第十三开关管PT13和第十四开关管PT14同时导通，且第十二开关管PT12断开，恒压低电平源VGL的低电平信号通过第十四开关管PT14、第十三开关管PT13以及第二反相器122变成高电平的本级的级联信号Q_N，从锁存模块12的输出端输出，即对高电位的本级的级联信号Q_N进行了锁存操作。
当第一时钟信号CK_1再次转变为高电平信号时，输入控制模块11的输出端再次输出低电平的控制信号。这时的上一级的级联信号Q_N-1已转为低电平，这时第七开关管PT7和第八开关管PT8导通，恒压高电平源VGH的高电平电位通过第七开关管PT7、第八开关管PT8以及第二反相器122变成低电平的本级的级联信号Q_N，从锁存模块12的输出端输出。该低电平的本级的级联信号Q_N同时输入到下一级的扫描驱动电路中。
随后第一时钟信号CK_1转变为低电平信号，输入控制模块11的输出端通过第一开关管PT1输出高电平的控制信号。
这时高电平的控制信号通过第一反相器121转变为低电平的控制信号CK输入到第十一开关管PT11的控制端，同时低电平的本级的级联信号Q_N输入到第十二开关管PT12的控制端，这样第十一开关管PT11和第十二开关管PT12同时导通，且第十三开关管PT13断开，恒压高电平源VGH的高电平信号通过第十一开关管PT11、第十二开关管PT12以及第二反相器122变成低电平的本级的级联信号Q_N，从锁存模块12的输出端输出，即对低电平的本级的级联信号Q_N进行了锁存操作。
驱动信号产生模块13起到一个与非门的作用，即将锁存模块12输出的本级的级联信号Q_N与本级的第二时钟信号CK_2进行与非运算。具体为，当本级的级联信号Q_N和本级的第二时钟信号CK_2同时为高电平时，第十五开关管PT15和第十六开关管PT16断开，第十七开关管PT17和第十八开关管PT18导通，这时驱动信号产生模块13的输出端输出恒压低电平源VGL的低电平电压。
当本级的第二时钟信号CK_2转为低电平时，第十八开关管PT18断开，第十六开关管PT16导通，驱动信号产生模块13的输出端输出恒压高电平源VGH的高电平电压；当本级的级联信号Q_N转为低电平时，第十五开关管PT15导通，第十七开关管PT17断开，驱动信号产生模块13的输出端输出恒压高电平源VGH的高电平电压。
当驱动信号产生模块13输出的驱动信号为高电平时，第二十开关管PT20导通，第十九开关管PT19断开；恒压低电平源VGL的低电平电压输入到第二十一开关管PT21的控制端以及第二十二开关管PT22的控制端，第二十一开关管PT21导通，第二十二开关管PT22断开，恒压高电平源VGH的高电平电压输入到第二十三开关管PT23的控制端和第二十四开关管PT24的控制端，第二十三开关管PT23断开，第二十四开关管PT24导通，输出控制模块13输出低电平的本级的扫描信号G_N。
当驱动信号产生模块13输出的驱动信号为低电平时，第二十开关管PT20断开，第十九开关管PT19导通；恒压高电平源VGH的高电平电压输入至第二十一开关管PT21的控制端以及第二十二开关管PT22的控制端，第二十一开关管PT21断开，第二十二开关管PT22导通，恒压低电平源VGL的低电平电压输入至第二十三开关管PT23的控制端和第二十四开关管PT24的控制端，第二十三开关管PT23导通，第二十四开关管PT24断开，输出控制模块13输出高电平的本级的扫描信号G_N。
这样即完成了本优选实施例的扫描驱动电路的扫描线的驱动过程。
本优选实施例的扫描驱动电路在工作过程中，如上一级的级联信号Q_N-1出现噪声波动，而下一级的级联信号Q_N+1处于正常状态时，并不会对最终输出的扫描信号G_N，具体如图2的A区域所示。因此本优选实施例的扫描驱动电路通过上一级的级联信号以及下一级的级联信号进行输入控制模块的驱动，可以有效的降低干扰。
请参照图3，图3为本发明的扫描驱动电路的第二优选实施例的结构示意图。在第一优选实施例的基础上，本优选实施例的扫描驱动电路20的输入控制模块21包括第一开关管PT1、第二开关管PT2、第三开关管PT3、第四开关管PT4、第五开关管PT5以及第六开关管PT6。
第一开关管PT1的控制端输入本级的第一时钟信号CK_1，第一开关管PT1的输入端与恒压高电平源VGH连接，第一开关管PT1的输出端与输入控制模块21的输出端连接；
第二开关管PT2的控制端输入上一级的级联信号Q_N-1，第二开关管PT2的输入端与恒压高电平源VGH连接，第二开关管PT2的输出端与第三开关管PT3的输入端连接；
第三开关管PT3的控制端输入下一级的级联信号Q_N+1，第三开关管PT3的输出端与输入控制模块21的输出端连接；
第四开关管PT4的控制端输入本级的第一时钟信号CK_1，第四开关管PT4的输入端与恒压低电平源VGL连接，第四开关管PT4的输出端与第五开关管PT5的输入端连接；
第五开关管PT5的控制端输入上一级的级联信号Q_N-1，第五开关管PT5的输出端与输入控制模块21的输出端连接；
第六开关管PT6的控制端输入下一级的级联信号Q_N+1，第六开关管PT6的输入端与第五开关管PT5的输入端连接，第六开关管PT6的输出端与输入控制模块21的输出端连接。
本优选实施例的扫描驱动电路20的具体工作原理与上述的第一优选实施例的描述相同或相似，具体请参见上述第一优选实施例中的相关描述。
因此本优选实施例的扫描驱动电路在第一优选实施例的基础上进一步加强了该扫描驱动电路的配置灵活性。
本发明的扫描驱动电路通过上一级的级联信号以及下一级的级联信号进行输入控制模块的驱动，可以有效的降低干扰，并且整个扫描驱动电路的动态功耗较小；解决了现有的扫描驱动电路的动态功耗较大的技术问题。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (20)

  1. 一种扫描驱动电路，用于对级联的扫描线进行驱动操作，其中所述扫描驱动电路包括：
    输入控制模块，用于输入本级的第一时钟信号、上一级的级联信号以及下一级的级联信号，并根据所述本级的第一时钟信号、所述上一级的级联信号以及所述下一级的级联信号产生控制信号；
    锁存模块，用于对所述控制信号进行锁存操作；
    驱动信号产生模块，用于根据所述控制信号以及本级的第二时钟信号产生驱动信号；
    输出控制模块，用于根据所述驱动信号输出本级的扫描信号；
    恒压高电平源，用于提供高电平电压；以及
    恒压低电平源，用于提供低电平电压；
    其中将所述控制信号的反向信号作为本级的级联信号输入到下一级的扫描驱动电路中；
    所述输出控制模块包括第十九开关管、第二十开关管、第二十一开关管、第二十二开关管、第二十三开关管以及第二十四开关管；
    所述第十九开关管的控制端与所述驱动信号产生模块的输出端连接，所述第十九开关管的输入端与所述恒压高电平源连接，所述第十九开关管的输出端分别与所述第二十一开关管的控制端和所述第二十二开关管的控制端连接；
    所述第二十开关管的控制端与所述驱动信号产生模块的输出端连接，所述第二十开关管的输入端与所述恒压低电平源连接，所述第二十开关管的输出端分别与所述二十一开关管的控制端和所述第二十二开关管的控制端连接；
    所述第二十一开关管的输入端与所述恒压高电平源连接，所述第二十一开关管的输出端分别与所述第二十三开关管的控制端和所述第二十四开关管的控制端连接；
    所述第二十二开关管的输入端与所述恒压低电平源连接，所述第二十二开关管的输出端分别与所述第二十三开关管的控制端和所述第二十四开关管的控制端连接；
    所述第二十三开关管的输入端与所述恒压高电平源连接，所述第二十三开关管的输出端与所述输出控制模块的输出端连接；
    所述第二十四开关管的输入端与所述恒压低电平源连接，所述第二十四开关管的输出端与所述输出控制模块的输出端连接；
    其中所述第十九开关管、所述第二十一开关管以及所述第二十三开关管为PMOS管，所述第二十开关管、所述第二十二开关管以及所述第二十四开关管为NMOS管。
  2. 根据权利要求1所述的扫描驱动电路，其中所述输入控制模块包括第一开关管、第二开关管、第三开关管、第四开关管、第五开关管以及第六开关管；
    所述第一开关管的控制端输入所述本级的第一时钟信号，所述第一开关管的输入端与所述恒压高电平源连接，所述第一开关管的输出端与所述输入控制模块的输出端连接；
    所述第二开关管的控制端输入所述上一级的级联信号，所述第二开关管的输入端与所述恒压高电平源连接，所述第二开关管的输出端与所述第三开关管的输入端连接；
    所述第三开关管的控制端输入所述下一级的级联信号，所述第三开关管的输出端与所述输入控制模块的输出端连接；
    所述第四开关管的控制端输入所述本级的第一时钟信号，所述第四开关管的输入端与所述第五开关管的输出端连接，所述第四开关管的输出端与所述输入控制模块的输出端连接；
    所述第五开关管的控制端输入所述上一级的级联信号，所述第五开关管的输入端与所述恒压低电平源连接；
    所述第六开关管的控制端输入所述下一级的级联信号，所述第六开关管的输入端与所述恒压低电平源连接，所述第六开关管的输出端与所述第五开关管的输出端连接。
  3. 根据权利要求2所述的扫描驱动电路，其中所述第一开关管、所述第二开关管以及所述第三开关管为PMOS管，所述第四开关管、所述第五开关管以及所述第六开关管为NMOS管。
  4. 根据权利要求1所述的扫描驱动电路，其中所述输入控制模块包括第一开关管、第二开关管、第三开关管、第四开关管、第五开关管以及第六开关管；
    所述第一开关管的控制端输入所述本级的第一时钟信号，所述第一开关管的输入端与所述恒压高电平源连接，所述第一开关管的输出端与所述输入控制模块的输出端连接；
    所述第二开关管的控制端输入所述上一级的级联信号，所述第二开关管的输入端与所述恒压高电平源连接，所述第二开关管的输出端与所述第三开关管的输入端连接；
    所述第三开关管的控制端输入所述下一级的级联信号，所述第三开关管的输出端与所述输入控制模块的输出端连接；
    所述第四开关管的控制端输入所述本级的第一时钟信号，所述第四开关管的输入端与所述恒压低电平源连接，所述第四开关管的输出端与所述第五开关管的输入端连接；
    所述第五开关管的控制端输入所述上一级的级联信号，所述第五开关管的输出端与所述输入控制模块的输出端连接；
    所述第六开关管的控制端输入所述下一级的级联信号，所述第六开关管的输入端与所述第五开关管的输入端连接，所述第六开关管的输出端与所述输入控制模块的输出端连接。
  5. 根据权利要求4所述的扫描驱动电路，其中所述第一开关管、所述第二开关管以及所述第三开关管为PMOS管，所述第四开关管、所述第五开关管以及所述第六开关管为NMOS管。
  6. 根据权利要求1所述的扫描驱动电路，其中所述锁存模块包括第一反相器、第二反相器、第七开关管、第八开关管、第九开关管、第十开关管、第十一开关管、第十二开关管、第十三开关管以及第十四开关管；
    所述第七开关管的控制端与所述输入控制模块的输出端连接，所述第七开关管的输入端与所述恒压高电平源连接，所述第七开关管的输出端与所述第八开关管的输入端连接；
    所述第八开关管的控制端输入上一级的级联信号，所述第八开关管的输出端通过所述第二反相器与所述锁存模块的输出端连接；
    所述第九开关管的控制端输入上一级的级联信号，所述第九开关管的输出端通过所述第二反相器与所述锁存模块的输出端连接；
    所述第十开关管的控制端通过所述第一反相器与所述输入控制模块的输出端连接，所述第十开关管的输入端与所述恒压低电平源连接，所述第十开关管的输出端与所述第九开关管的输入端连接；
    所述第十一开关管的控制端通过所述第一反相器与所述输入控制模块的输出端连接，所述第十一开关管的输入端与所述恒压高电平源连接，所述第十一开关管的输出端与所述第十二开关管的输入端连接；
    所述第十二开关管的控制端与所述锁存模块的输出端连接，所述第十二开关管的输出端通过所述第二反相器与所述锁存模块的输出端连接；
    所述第十三开关管的控制端与所述锁存模块的输出端连接，所述第十三开关管的输出端通过所述第二反相器与所述锁存模块的输出端连接；
    所述第十四开关管的控制端与所述输入控制模块的输出端连接，所述第十四开关管的输入端与所述恒压低电平源连接，所述第十四开关管的输出端与所述第十三开关管的输入端连接。
  7. 根据权利要求6所述的扫描驱动电路，其中所述第七开关管、所述第八开关管、所述第十一开关管以及所述第十二开关管为PMOS管，所述第九开关管、所述第十开关管、所述第十三开关管以及所述第十四开关管为NMOS管。
  8. 根据权利要求1所述的扫描驱动电路，其中所述驱动信号产生模块包括第十五开关管、第十六开关管、第十七开关管以及第十八开关管；
    所述第十五开关管的控制端与所述锁存模块的输出端连接，所述第十五开关管的输入端与所述恒压高电平源连接，所述第十五开关管的输出端与所述驱动信号产生模块的输出端连接；
    所述第十六开关管的控制端输入本级的第二时钟信号，所述第十六开关管的输入端与所述恒压高电平源连接，所述第十六开关管的输出端与所述驱动信号产生模块的输出端连接；
    所述第十七开关管的控制端与所述锁存模块的输出端连接，所述第十七开关管的输入端与所述第十八开关管的输出端连接，所述第十七开关管的输出端与所述驱动信号产生模块的输出端连接；
    所述第十八开关管的控制端输入本级的第二时钟信号，所述第十八开关管的输入端与所述恒压低电平源连接。
  9. 根据权利要求8所述的扫描驱动电路，其特征在于，所述第十五开关管和所述第十六开关管为PMOS管，所述第十七开关管和所述第十八开关管为NMOS管。
  10. 一种扫描驱动电路，用于对级联的扫描线进行驱动操作，其中所述扫描驱动电路包括：
    输入控制模块，用于输入本级的第一时钟信号、上一级的级联信号以及下一级的级联信号，并根据所述本级的第一时钟信号、所述上一级的级联信号以及所述下一级的级联信号产生控制信号；
    锁存模块，用于对所述控制信号进行锁存操作；
    驱动信号产生模块，用于根据所述控制信号以及本级的第二时钟信号产生驱动信号；
    输出控制模块，用于根据所述驱动信号输出本级的扫描信号；
    恒压高电平源，用于提供高电平电压；以及
    恒压低电平源，用于提供低电平电压。
  11. 根据权利要求10所述的扫描驱动电路，其中所述输入控制模块包括第一开关管、第二开关管、第三开关管、第四开关管、第五开关管以及第六开关管；
    所述第一开关管的控制端输入所述本级的第一时钟信号，所述第一开关管的输入端与所述恒压高电平源连接，所述第一开关管的输出端与所述输入控制模块的输出端连接；
    所述第二开关管的控制端输入所述上一级的级联信号，所述第二开关管的输入端与所述恒压高电平源连接，所述第二开关管的输出端与所述第三开关管的输入端连接；
    所述第三开关管的控制端输入所述下一级的级联信号，所述第三开关管的输出端与所述输入控制模块的输出端连接；
    所述第四开关管的控制端输入所述本级的第一时钟信号，所述第四开关管的输入端与所述第五开关管的输出端连接，所述第四开关管的输出端与所述输入控制模块的输出端连接；
    所述第五开关管的控制端输入所述上一级的级联信号，所述第五开关管的输入端与所述恒压低电平源连接；
    所述第六开关管的控制端输入所述下一级的级联信号，所述第六开关管的输入端与所述恒压低电平源连接，所述第六开关管的输出端与所述第五开关管的输出端连接。
  12. 根据权利要求11所述的扫描驱动电路，其中所述第一开关管、所述第二开关管以及所述第三开关管为PMOS管，所述第四开关管、所述第五开关管以及所述第六开关管为NMOS管。
  13. 根据权利要求10所述的扫描驱动电路，其中所述输入控制模块包括第一开关管、第二开关管、第三开关管、第四开关管、第五开关管以及第六开关管；
    所述第一开关管的控制端输入所述本级的第一时钟信号，所述第一开关管的输入端与所述恒压高电平源连接，所述第一开关管的输出端与所述输入控制模块的输出端连接；
    所述第二开关管的控制端输入所述上一级的级联信号，所述第二开关管的输入端与所述恒压高电平源连接，所述第二开关管的输出端与所述第三开关管的输入端连接；
    所述第三开关管的控制端输入所述下一级的级联信号，所述第三开关管的输出端与所述输入控制模块的输出端连接；
    所述第四开关管的控制端输入所述本级的第一时钟信号，所述第四开关管的输入端与所述恒压低电平源连接，所述第四开关管的输出端与所述第五开关管的输入端连接；
    所述第五开关管的控制端输入所述上一级的级联信号，所述第五开关管的输出端与所述输入控制模块的输出端连接；
    所述第六开关管的控制端输入所述下一级的级联信号，所述第六开关管的输入端与所述第五开关管的输入端连接，所述第六开关管的输出端与所述输入控制模块的输出端连接。
  14. 根据权利要求13所述的扫描驱动电路，其中所述第一开关管、所述第二开关管以及所述第三开关管为PMOS管，所述第四开关管、所述第五开关管以及所述第六开关管为NMOS管。
  15. 根据权利要求10所述的扫描驱动电路，其中所述锁存模块包括第一反相器、第二反相器、第七开关管、第八开关管、第九开关管、第十开关管、第十一开关管、第十二开关管、第十三开关管以及第十四开关管；
    所述第七开关管的控制端与所述输入控制模块的输出端连接，所述第七开关管的输入端与所述恒压高电平源连接，所述第七开关管的输出端与所述第八开关管的输入端连接；
    所述第八开关管的控制端输入上一级的级联信号，所述第八开关管的输出端通过所述第二反相器与所述锁存模块的输出端连接；
    所述第九开关管的控制端输入上一级的级联信号，所述第九开关管的输出端通过所述第二反相器与所述锁存模块的输出端连接；
    所述第十开关管的控制端通过所述第一反相器与所述输入控制模块的输出端连接，所述第十开关管的输入端与所述恒压低电平源连接，所述第十开关管的输出端与所述第九开关管的输入端连接；
    所述第十一开关管的控制端通过所述第一反相器与所述输入控制模块的输出端连接，所述第十一开关管的输入端与所述恒压高电平源连接，所述第十一开关管的输出端与所述第十二开关管的输入端连接；
    所述第十二开关管的控制端与所述锁存模块的输出端连接，所述第十二开关管的输出端通过所述第二反相器与所述锁存模块的输出端连接；
    所述第十三开关管的控制端与所述锁存模块的输出端连接，所述第十三开关管的输出端通过所述第二反相器与所述锁存模块的输出端连接；
    所述第十四开关管的控制端与所述输入控制模块的输出端连接，所述第十四开关管的输入端与所述恒压低电平源连接，所述第十四开关管的输出端与所述第十三开关管的输入端连接。
  16. 根据权利要求15所述的扫描驱动电路，其中所述第七开关管、所述第八开关管、所述第十一开关管以及所述第十二开关管为PMOS管，所述第九开关管、所述第十开关管、所述第十三开关管以及所述第十四开关管为NMOS管。
  17. 根据权利要求10所述的扫描驱动电路，其中所述驱动信号产生模块包括第十五开关管、第十六开关管、第十七开关管以及第十八开关管；
    所述第十五开关管的控制端与所述锁存模块的输出端连接，所述第十五开关管的输入端与所述恒压高电平源连接，所述第十五开关管的输出端与所述驱动信号产生模块的输出端连接；
    所述第十六开关管的控制端输入本级的第二时钟信号，所述第十六开关管的输入端与所述恒压高电平源连接，所述第十六开关管的输出端与所述驱动信号产生模块的输出端连接；
    所述第十七开关管的控制端与所述锁存模块的输出端连接，所述第十七开关管的输入端与所述第十八开关管的输出端连接，所述第十七开关管的输出端与所述驱动信号产生模块的输出端连接；
    所述第十八开关管的控制端输入本级的第二时钟信号，所述第十八开关管的输入端与所述恒压低电平源连接。
  18. 根据权利要求17所述的扫描驱动电路，其中所述第十五开关管和所述第十六开关管为PMOS管，所述第十七开关管和所述第十八开关管为NMOS管。
  19. 根据权利要求10所述的扫描驱动电路，其中将所述控制信号的反向信号作为本级的级联信号输入到下一级的扫描驱动电路中。
  20. 根据权利要求10所述的扫描驱动电路，其中所述输出控制模块包括第十九开关管、第二十开关管、第二十一开关管、第二十二开关管、第二十三开关管以及第二十四开关管；
    所述第十九开关管的控制端与所述驱动信号产生模块的输出端连接，所述第十九开关管的输入端与所述恒压高电平源连接，所述第十九开关管的输出端分别与所述第二十一开关管的控制端和所述第二十二开关管的控制端连接；
    所述第二十开关管的控制端与所述驱动信号产生模块的输出端连接，所述第二十开关管的输入端与所述恒压低电平源连接，所述第二十开关管的输出端分别与所述二十一开关管的控制端和所述第二十二开关管的控制端连接；
    所述第二十一开关管的输入端与所述恒压高电平源连接，所述第二十一开关管的输出端分别与所述第二十三开关管的控制端和所述第二十四开关管的控制端连接；
    所述第二十二开关管的输入端与所述恒压低电平源连接，所述第二十二开关管的输出端分别与所述第二十三开关管的控制端和所述第二十四开关管的控制端连接；
    所述第二十三开关管的输入端与所述恒压高电平源连接，所述第二十三开关管的输出端与所述输出控制模块的输出端连接；
    所述第二十四开关管的输入端与所述恒压低电平源连接，所述第二十四开关管的输出端与所述输出控制模块的输出端连接；
    其中所述第十九开关管、所述第二十一开关管以及所述第二十三开关管为PMOS管，所述第二十开关管、所述第二十二开关管以及所述第二十四开关管为NMOS管。
PCT/CN2015/086487 2015-07-02 2015-08-10 一种扫描驱动电路 Ceased WO2017000360A1 (zh)

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