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WO2017124598A1 - 一种栅极驱动电路及显示面板 - Google Patents

一种栅极驱动电路及显示面板 Download PDF

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Publication number
WO2017124598A1
WO2017124598A1 PCT/CN2016/074228 CN2016074228W WO2017124598A1 WO 2017124598 A1 WO2017124598 A1 WO 2017124598A1 CN 2016074228 W CN2016074228 W CN 2016074228W WO 2017124598 A1 WO2017124598 A1 WO 2017124598A1
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WO
WIPO (PCT)
Prior art keywords
switch tube
node
transistor
circuit
voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2016/074228
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English (en)
French (fr)
Inventor
赵莽
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Wuhan China Star Optoelectronics Technology Co Ltd
Original Assignee
Wuhan China Star Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Wuhan China Star Optoelectronics Technology Co Ltd filed Critical Wuhan China Star Optoelectronics Technology Co Ltd
Priority to US15/022,199 priority Critical patent/US9898990B2/en
Publication of WO2017124598A1 publication Critical patent/WO2017124598A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13454—Drivers integrated on the active matrix substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H03K17/6871—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0219—Reducing feedthrough effects in active matrix panels, i.e. voltage changes on the scan electrode influencing the pixel voltage due to capacitive coupling

Definitions

  • the present invention relates to the field of display driving, and in particular to a gate driving circuit and a display panel.
  • GOA Gate Driver On Array, array substrate row drive
  • Such a gate switching circuit integrated on an array substrate using GOA technology is also referred to as a gate driving circuit.
  • the conventional gate driving circuit when the output circuit outputting the gate scanning driving signal is controlled, the node connected to the output circuit needs to maintain the voltage intensity for a certain time, thereby temporarily outputting the gate scanning driving signal in the clock signal pulse, if During this certain period of time, the node connected to the output circuit cannot maintain the voltage strength due to the occurrence of leakage current, which may cause the circuit to fail and the gate scan driving signal cannot be output normally.
  • the present invention provides a technical solution for providing a gate driving circuit, including:
  • An input circuit, an output circuit, a stabilization circuit, a pull circuit, and a pull control circuit the input circuit includes a first switch tube and a second switch tube, and the stabilization circuit includes a third switch tube;
  • the first path end of the first switch tube is connected to the control end of the first switch tube and the control end of the second switch tube, and receives the upper scan drive signal, the second path end of the first switch tube is connected to the pull circuit, and the first switch tube Turning on under the action of the upper-level scan driving signal, thereby transmitting the upper-level scan driving signal to the pulling circuit, and setting the pulling circuit to the first state;
  • the first path end of the second switch tube is connected to the first reference potential
  • the second path end of the second switch tube is connected to the first node
  • the first node is connected to the output circuit
  • the second switch tube is turned on by the upper scan drive signal And causing the first reference potential to set the voltage of the first node to the first voltage, and being held by the output circuit, so that the output circuit outputs the scan driving signal of the current level according to the first clock signal;
  • the second path end of the first switch tube is simultaneously connected to the control end of the third switch tube to receive the upper scan drive signal, the first path end of the third switch tube is connected to the first reference potential, and the second path end of the third switch tube is Connecting the second node, the third switch tube is turned on by the upper scan driving signal, so that the first reference potential sets the voltage of the second node to the first voltage, and is held by the third switch tube;
  • Pulling the circuit is connected to the second path end of the second switch tube at the first node, the pull circuit is connected to the second path end of the third switch tube at the second node, pulling the circuit connection to pull the control circuit, and pulling the control circuit to respond to the second clock signal
  • the pull circuit is set to the second state, and the voltages of the first node and the second node are pulled and maintained at the second voltage by the second reference potential.
  • a gate driving circuit including:
  • Input circuit output circuit, stabilization circuit, pull circuit, pull control circuit;
  • the output circuit is connected to the input circuit and the pull circuit at the first node, and the input circuit sets the pull circuit to the first state in response to the upper scan drive signal, and sets the voltage of the first node to the first voltage by using the first reference potential, and is output by the output The circuit is maintained, so that the output circuit outputs the scan driving signal of the current stage according to the first clock signal;
  • the stabilization circuit is connected to the pull circuit at the second node, and the input circuit sets the voltage of the second node to the first voltage by using the first reference potential in response to the upper-level scan driving signal, and is maintained by the stabilization circuit, thereby reducing the first node and the second node. Leakage current between nodes;
  • the pull control circuit sets the pull circuit to the second state in response to the second clock signal, and thereby pulls and maintains the voltages of the first node and the second node to a second voltage by using the second reference potential.
  • the input circuit comprises a first switch tube and a second switch tube
  • the first path end of the first switch tube is connected to the control end of the first switch tube and the control end of the second switch tube, and receives the upper scan drive signal, the second path end of the first switch tube is connected to the pull circuit, and the first switch tube Turning on under the action of the upper-level scan driving signal, thereby transmitting the upper-level scan driving signal to the pulling circuit, and setting the pulling circuit to the first state;
  • the first path end of the second switch tube is connected to the first reference potential
  • the second path end of the second switch tube is connected to the first node
  • the second switch tube is turned on under the action of the upper scan drive signal, so that the first reference potential will be
  • the voltage of the first node is set to a first voltage
  • the second path end of the first switch tube is further connected to the stabilization circuit
  • the first switch tube further transmits the upper scan drive signal to the stabilization circuit
  • the control stabilization circuit is turned on, thereby enabling the A reference potential sets the voltage of the second node to the first voltage and is held by the stabilization circuit.
  • the first switch tube is a first transistor, and the control end of the first switch tube corresponds to the gate of the first transistor, and the first path end and the second path end of the first switch tube respectively correspond to the source and the drain of the first transistor pole;
  • the second switching transistor is a second transistor, and the control end of the second switching transistor corresponds to the gate of the second transistor, and the first path end and the second path end of the second switching tube respectively correspond to the source and the drain of the second transistor.
  • the input circuit further comprises a third switch tube
  • the control end of the third switch is connected to the first reference potential or the second reference potential
  • the first end of the third switch is connected to the second end of the second switch
  • the second end of the third switch is connected to the first The node
  • the third switch tube is turned on by the first reference potential or the second reference potential to regulate the voltage of the first node.
  • the third switch tube is a third transistor, and the control end of the third switch tube corresponds to the gate of the third transistor, and the first path end and the second path end of the third switch tube respectively correspond to the source and drain of the third transistor pole.
  • the output circuit comprises a switch tube and a bootstrap capacitor
  • the control end of the switch tube is connected to the first node, and the first path end of the switch tube inputs a first clock signal
  • the bootstrap capacitor is connected between the control end of the switch tube and the second path end of the switch tube, and the voltage of the first node is When the first voltage is set, the bootstrap capacitor holds the first voltage to turn on the switch, and then outputs the current scan drive signal at the second path end of the switch according to the first clock signal.
  • the switch tube is a transistor, and the control end of the switch tube corresponds to the gate of the transistor, and the first path end and the second path end of the switch tube respectively correspond to the source and the drain of the transistor.
  • the stabilization circuit comprises a switch tube
  • the control end of the switch tube is connected to the input circuit to receive the upper scan drive signal, the first path end of the switch tube is connected to the first reference potential, the second path end of the switch tube is connected to the second node, and the switch tube is driven by the upper stage drive signal Turning on, the first reference potential sets the voltage of the second node to the first voltage and is held by the switch tube.
  • the switch tube is a transistor, and the control end of the switch tube corresponds to the gate of the transistor, and the first path end and the second path end of the switch tube respectively correspond to the source and the drain of the transistor.
  • the stabilization circuit further comprises another switch tube
  • the first path end of the other switch tube is connected to the control end of the second node and the other switch tube, and the second path end of the other switch tube is connected to the input circuit to receive the upper scan drive signal, and the other switch tube is at the second node
  • the voltage is set to be the first voltage
  • the other switch tube and the switch tube jointly hold the first voltage
  • the other switch tube is another transistor
  • the control end of the other switch tube corresponds to the gate of the other transistor
  • the first path end and the second path end of the other switch tube respectively correspond to the source and drain of the other transistor pole.
  • the pulling circuit includes a first switching tube, a second switching tube, a third switching tube, a fourth switching tube and a bootstrap capacitor;
  • the first path end of the first switch tube is connected to the second node, the first path end of the first switch tube is connected to the first node, and the control end of the first switch tube is connected to the third node;
  • the control end of the second switch tube is connected to the input circuit to receive the upper scan drive signal, the first path end of the second switch tube is connected to the third node, and the second path end of the second switch tube is connected to the second reference potential;
  • the control end of the third switch is connected to the third node, the first end of the third switch is connected to the second node, and the second end of the third switch is connected to the second reference potential;
  • the control end of the fourth switch tube is connected to the third node, the first path end of the fourth switch tube is connected to the output end of the output circuit, and the second path end of the fourth switch tube is connected to the second reference potential;
  • the bootstrap capacitor is connected between the third node and the second reference potential
  • the second switch tube is turned on by the upper scan driving signal, so that the second reference potential sets the voltage of the third node to the second voltage, and the first switch tube, the third switch tube and the fourth switch tube are in the third The node is turned off, so that the first voltage of the first node is maintained in the output circuit, and the first voltage of the second node is maintained in the stabilization circuit;
  • the pull control circuit sets the voltage of the third node to the first voltage in response to the second clock signal, so that the first switch tube, the third switch tube and the fourth switch tube are turned on, so that the second reference potential will be the first node and the first node
  • the voltage of the two nodes is set to the second voltage.
  • the first switch tube is a first transistor, and the control end of the first switch tube corresponds to the gate of the first transistor, and the first path end and the second path end of the first switch tube respectively correspond to the source and the drain of the first transistor pole;
  • the second switching transistor is a second transistor, the control end of the second switching transistor corresponds to the gate of the second transistor, and the first path end and the second path end of the second switching tube respectively correspond to the source and the drain of the second transistor;
  • the third switching transistor is a third transistor, and the control end of the third switching transistor corresponds to the gate of the third transistor, and the first path end and the second path end of the third switching tube respectively correspond to the source and the drain of the third transistor;
  • the fourth switch tube is a fourth transistor, and the control end of the fourth switch tube corresponds to the gate of the fourth transistor, and the first path end and the second path end of the fourth switch tube respectively correspond to the source and the drain of the fourth transistor.
  • the pull control circuit includes a fifth switch tube and a sixth switch tube;
  • the first path end of the fifth switch tube is connected to the third node, the second path end of the fifth switch tube is connected to the first reference potential, the first path end of the sixth switch tube is connected to the stabilization circuit, and the second path of the sixth switch tube is connected
  • the terminal is connected to the second reference potential, and the control end of the fifth switch tube and the control end of the sixth switch tube receive the second clock signal;
  • the sixth switch tube is turned on under the action of the second clock signal, so that the second reference potential is passed through the sixth switch tube, and the control stabilization circuit releases the hold of the first voltage;
  • the fifth switch tube is turned on by the second clock signal, so that the first reference potential sets the voltage of the third node to the first voltage via the fifth switch tube, so that the first switch tube, the third switch tube, and the fourth The switch tube is turned on, and the voltages of the first node and the second node are set to the second voltage by using the second reference potential.
  • the fifth switch tube is a fifth transistor, and the control end of the fifth switch tube corresponds to the gate of the fifth transistor, and the first path end and the second path end of the fifth switch tube respectively correspond to the source and the drain of the fifth transistor pole;
  • the sixth switch tube is a sixth transistor, and the control end of the sixth switch tube corresponds to the gate of the sixth transistor, and the first path end and the second path end of the sixth switch tube respectively correspond to the source and the drain of the sixth transistor.
  • the first reference potential is one of a high reference potential and a low reference potential
  • the second reference potential is the other of the high reference potential and the low reference potential
  • the first voltage is one of a high potential and a low potential
  • the second voltage is the other of the high potential and the low potential
  • a display panel including a substrate and a gate driving circuit on the substrate.
  • the invention has the beneficial effects that the present invention sets the pull circuit to the first state by responding to the upper level scan driving signal in the input circuit, and sets the voltage of the first node to the first reference potential by using the first reference potential. While a voltage is maintained by the output circuit, the voltage of the second node is set to the first voltage by the first reference potential in response to the upper-level scan driving signal by the input circuit, and is held by the stabilization circuit, thereby causing the output circuit to be A clock signal outputs the scan drive signal of the current stage. In this way, the voltage of the first node is the first voltage, and the voltage of the second node is the first voltage, thereby reducing the leakage current between the first node and the second node. The voltage of a node can be maintained by the output circuit for a certain period of time, waiting for the arrival of the clock signal, thereby outputting the scanning drive signal of the current stage, thereby reducing the risk of circuit failure.
  • FIG. 1 is a schematic diagram showing the principle of implementing a gate driving circuit of the present invention
  • Embodiment 2 is a specific circuit diagram of Embodiment 1 of a gate driving circuit of the present invention.
  • FIG. 3 is a schematic view of a driving frame of a first embodiment of a gate driving circuit of the present invention.
  • Embodiment 2 is a specific circuit diagram of Embodiment 2 of a gate driving circuit of the present invention.
  • Fig. 6 is a timing chart showing the second embodiment of the gate driving circuit of the present invention.
  • the first embodiment of the gate driving circuit of the present invention includes an input circuit 101 , an output circuit 102 , a stabilization circuit 103 , a pull circuit 104 , and a pull control circuit 105 .
  • the output circuit 102 connects the input circuit 101 and the pull circuit 104 at the first node Q(N), and the input circuit 101 sets the pull circuit 104 to the first state in response to the upper scan drive signal Gate(N-2), and utilizes the first reference potential.
  • V1 sets the voltage of the first node Q(N) to the first voltage, and is held by the output circuit 102, so that the output circuit 102 outputs the current-level scan driving signal Gate(N) according to the first clock signal CK(M);
  • the stabilization circuit 103 is connected to the pull circuit 104 at the second node H(N), and the input circuit 101 sets the voltage of the second node H(N) to the first value by the first reference potential V1 in response to the upper scan drive signal Gate(N-2). The voltage is held by the stabilization circuit 103 to reduce leakage current between the first node Q(N) and the second node H(N);
  • the pull control circuit 105 sets the pull circuit 104 to the second state in response to the second clock signal CK(M+1), thereby using the second reference potential V2 to convert the voltage of the first node Q(N) and the second node H(N) Pull and hold to a second voltage.
  • the circuit of the first embodiment uses the upper-level scan driving signal Gate(N-2) as the start signal, and outputs the current-level scan driving signal Gate(N) under the action of the first clock signal CK(M).
  • the scan drive signal Gate(N) of the current stage needs to be restored to the normal state even if the switch tube of the scan line thereof is kept off, therefore,
  • the pull control circuit 105 sets the pull circuit 104 to the second state in response to the second clock signal CK(M+1), thereby using the second reference potential V2 to the first node Q(N) and the second node H(N). The voltage is pulled and maintained at the second voltage, so that the voltage of the scanning drive signal Gate(N) of the current stage is maintained at the second voltage, and the second voltage keeps the switching tube of the scanning line turned off.
  • the upper-level scan driving signal Gate(N-2) of the first embodiment is the scan driving signal of the first two stages of the scan driving signal Gate(N) of the current stage.
  • the upper-level scan driving signal can be selected as the scanning drive of the current stage.
  • the number of stages is not limited by the number of scan drive signals in the first few stages of the signal, or the number of scan drive signals after several stages of the scan drive signal.
  • the first clock signal CK(M) and the second clock signal CK(M+1) may select a high frequency or low frequency clock signal.
  • a node connected to an output circuit (similar to the first node of the first embodiment) is set to a voltage of a certain intensity to wait for the arrival of a clock signal to output a scan drive signal of the present stage, and is not capable of outputting with the connection.
  • the node of the circuit maintains the node of the same voltage or the storage voltage. At this time, if the leakage characteristic of the switch of the node connected to the output circuit is not very good, the voltage of the node of the output circuit cannot maintain a certain strength, and when the clock signal comes, the connection is made.
  • the node of the output circuit makes the output circuit inoperable, and the gate scan drive signal cannot be output normally, resulting in circuit failure.
  • the first node Q(N) is connected to the input circuit 101, the output circuit 102, and the pull circuit 104, and is a point for controlling the output of the scanning signal Gate(N) of the current stage, and the second node H(N) is connected to Between the stabilizing circuit 103 and the pulling circuit 104 is a point for preventing leakage current from appearing.
  • the input circuit 101 first needs to set the pulling circuit 104 to the first state in response to the upper scanning driving signal, which is the first node Q(N) and the second node.
  • the voltage setting of H(N) and the holding of the voltage after setting are prepared, and when the input circuit 101 inputs the upper-level scan driving signal so that the voltage of the first node Q(N) is set to the first voltage by the first reference potential V1, the input circuit 101 also sets the voltage of the second node H(N) to the first voltage by the first reference potential V1 through the stabilization circuit 103, the first node Q(N) and the voltage of the second node H(N) are the same, two nodes There is almost no leakage current between them, and the voltage of the first node Q(N) is maintained in the output circuit 102, and in this way, the risk of circuit failure is greatly reduced.
  • the first reference potential V1 is one of a high reference potential VGH and a low reference potential VGL
  • the second reference potential V2 is the other of the high reference potential VGH and the low reference potential VGL, that is, If the first reference potential V1 is the high reference potential VGH, then the second reference potential V2 is the low reference potential VGL, and if the first reference potential V1 is the low reference potential VGL, then the first reference potential V1 is the high reference potential VGH, A reference potential V1 and a second reference potential V2 are used to set the first voltage to one of a high potential and a low potential, and the second voltage is the other of the high potential and the low potential.
  • the switching transistor of the gate driving circuit usually adopts a thin film transistor.
  • the thin film transistor has two types of devices, one is a P-type device (PMOS) mainly based on hole conduction, and the other is an N type mainly based on electronic conduction.
  • PMOS P-type device
  • NMOS N-type mainly based on electronic conduction.
  • an NMOS gate driving circuit designed and integrated by an NMOS single-type device is taken as an example for detailed description, wherein a control end of each switching transistor corresponds to an NMOS transistor.
  • the gate, the first path end and the second path end of the switch tube respectively correspond to the source and the drain of the NMOS transistor.
  • the locations of the source and drain of the NMOS transistor can also be interchanged as needed.
  • the input circuit 101 includes a transistor T1, a transistor T2, and a transistor T3;
  • the source of the transistor T1 is connected to the gate of the transistor T1 and the gate of the transistor T2, and receives the upper scanning drive signal Gate (N-2), the drain of the transistor T1 is connected to the pull circuit 104, the stabilization circuit 103; the source of the transistor T2 Connected to the first reference potential VGH, the drain of the transistor T2 is connected to the source of the transistor T3, the drain of the transistor T3 is connected to the first node Q(N), and the gate of the transistor T3 is connected to the first reference potential V1, the first reference potential V1 Is a high reference potential VGH;
  • the input circuit 101 realizes the input of the scan driving stage transmission signal, realizes the setting of the voltage of the first node Q(N) and the second node H(N), and realizes the setting of the first state of the pulling circuit 104, wherein the transistor T3 mainly To stabilize the voltage.
  • the output circuit 102 includes a transistor T4 and a bootstrap capacitor C1;
  • the gate of the transistor T4 is connected to the first node Q(N), the source of the transistor T4 is input with the first clock signal CK(M), and the bootstrap capacitor C1 is connected between the gate of the transistor T4 and the drain of the transistor T4.
  • the bootstrap capacitor C1 holds the first voltage to turn on the transistor T4, and further outputs the drain of the transistor T4 according to the first clock signal CK(M). This level scans the drive signal Gate(N).
  • the stabilization circuit 103 includes a transistor T5 and a transistor T6;
  • the gate of the transistor T5 is connected to the drain of the transistor T1 to receive the upper-stage scan driving signal Gate(N-2), the source of the transistor T5 is connected to the first reference potential VGH, and the drain of the transistor T5 is connected to the second node H(N).
  • the source of the transistor T6 is connected to the second node H(N) and the gate of the transistor T6, and the drain of the transistor T6 is connected to the drain of the transistor T1.
  • the transistor T6 in the stabilization circuit 103 can be removed.
  • Pulling circuit 104 includes a transistor T7, a transistor T8, a transistor T9 and a transistor T10 and a bootstrap capacitor C2;
  • the source of the transistor T7 is connected to the second node H(N), the drain of the transistor T7 is connected to the first node Q(N), the gate of the transistor T7 is connected to the third node P(N), and the gate of the transistor T8 is connected to the transistor T1.
  • the drain is received to receive the upper scan drive signal Gate(N-2), the source of the transistor T8 is connected to the third node P(N), the drain of the transistor T8 is connected to the second reference potential V2, and the second reference potential V2 is low.
  • the gate of the transistor T9 is connected to the third node P(N), the source of the transistor T9 is connected to the second node H(N), the drain of the transistor T9 is connected to the second reference potential VGL; the gate of the transistor T10 is connected The third node P(N), the source of the transistor T10 is connected to the drain of the transistor T4, the drain of the transistor T10 is connected to the second reference potential VGL; the bootstrap capacitor C2 is connected to the third node P(N) and the second reference potential Between VGL.
  • the pull control circuit 105 includes a transistor T11, a transistor T12;
  • the source of the transistor T11 is connected to the third node P(N), the drain of the transistor T11 is connected to the first reference potential VGH, the source of the transistor T12 is connected to the drain of the transistor T5, and the drain of the transistor T12 is connected to the second reference potential VGL.
  • the gate of the transistor T11 and the gate of the transistor T12 receive the second clock signal CK(M+1).
  • the first reference potential VGH may be selected from a constant voltage positive potential
  • the second reference potential VGL may be selected as a constant voltage negative potential
  • First clock signal CK (M), second clock signal CK (M+1) is two sets of clock signals selected from four clock signals of the same group.
  • CK(1), CK(2), CK(3), and CK(4) are the same group of clock signals CK ( M) includes four sets of alternate cycle clock signals, all of which are low frequency clock signals, as shown in FIG. 3, which is a schematic diagram of the drive frame of the first embodiment, if the first stage scan drive signal Gate(1) uses the clock
  • the signals CK(M) and CK(M+1) correspond to CK(1) and CK(2), then the clock signals CK(M) and CK(M+1) used by the second-stage scan driving signal Gate(2).
  • the clock signals CK(M) and CK(M+1) used by the third-stage scan driving signal Gate(3) correspond to CK(3), CK(4)
  • the clock signals CK(M) and CK(M+1) used by the fourth-stage scan driving signal Gate(4) correspond to CK(4) and CK(1), and are alternately cycled by analogy.
  • the scan drive signal Gate(N) of the current stage functions with the scan drive signal Gate(N-2) of the first two stages as the input enable signal, but in the first stage scan drive signal Gate ( 1)
  • the connection relationship of the first-stage scan driving signal Gate(1) in the first embodiment is The gate and the source of the transistor T1 are connected to the input enable signal STV1.
  • the gate and the source of the transistor T1 are connected to the input enable signal STV2, and the enable signal STV1 is input.
  • STV2 gives a high-potential pulse to start the circuit.
  • FIG. 4 is a timing diagram of the first embodiment of the gate driving circuit of the present invention. Referring to FIG. 2, the specific working process of the first embodiment is as follows:
  • the transistor T1 and the transistor T2 are turned on, and since the gate of the transistor T3 is connected to the high potential of the first reference potential VGH, the first reference potential is in a normal state.
  • the high potential of VGH sets the voltage of the first node Q(N) to the first voltage through the transistor T2 and the transistor T3, and the first voltage is a high potential;
  • the high potential of the upper scanning drive signal Gate (N-2) causes the gate of the transistor T5 to be high through the transistor T1, the transistor T5 is turned on, and the high potential of the first reference potential VGH passes the second node H(N) through the transistor T5.
  • the voltage is set to the first voltage, that is, the high potential, the transistor T6 is turned on, and the high potential of the upper scanning drive signal Gate(N-2) continues to accelerate the rise of the potential of the second node H(N) through the transistor T6, and the second node H(N)
  • the high potential is stored and held in the transistor T5 and the transistor T6;
  • the high potential of the upper scan driving signal Gate (N-2) causes the gate of the transistor T8 to be high through the transistor T1, the transistor T8 is turned on, and the third node P(N) is pulled down to the second voltage by the second reference potential VGL.
  • the second voltage is low, the transistor T7, the transistor T9, and the transistor T10 are turned off.
  • the second clock signal CK(M+1) is also low, the transistor T11 and the transistor T12 are turned off, and the pull circuit 104 is maintained in the first state;
  • the transistor T1 and the transistor T2 are turned off, the pull-up circuit 104 has been set to the first state, the transistor T7 and the transistor T9 are turned off, and the first node Q(N) The voltage is maintained at a high potential.
  • the high potential of the first node Q(N) needs to be held for two clock pulses, the first clock.
  • the circuit of the first embodiment increases the potential storage of the second node H(N) on the basis of the conventional circuit, so that the sources of the transistor T2 and the transistor T7 connected to the first node Q(N) are both high potential, There is a leakage path to reduce the risk of circuit failure;
  • the transistor T4 is turned on, and when the high potential of the first clock signal CK(M) comes, the first node Q(N) is bootstrapped by the bootstrap capacitor C1. A potential rise of the potential occurs, and the high potential of the scanning drive signal Gate(N) of the present stage is output through the transistor T4.
  • the transistor T11 and the transistor T12 are turned on, and the drain of the transistor T1 is second referenced by the transistor T12.
  • the potential VGL is pulled down to the low potential of the second voltage, the transistor T5 and the transistor T8 are turned off, and the high potential of the first reference potential VGH is set to the high potential of the first voltage through the transistor T11, and is pulled at this time.
  • the circuit is in a second state;
  • the high potential of the third node P(N) turns on the transistor T9 and the transistor T7, and the first node Q(N) is pulled down to the low potential by the second reference potential VGL through the transistor T7 and the transistor T9, and the second node H(N) The transistor T9 is pulled down to the low potential by the second reference potential VGL.
  • the low potential of the second node H(N) is not enough to turn off the transistor T6, the low potential of the source of the transistor T6 also accelerates the second node H (N). The pull-down of the potential;
  • the high potential of the third node P(N) simultaneously turns on the transistor T10, and the current-stage scan driving signal Gate(N) is also pulled down to the low potential by the second reference potential VGL, thereby completing the operation of one cycle of the entire circuit.
  • Embodiment 2 of the gate driving circuit of the present invention is specifically described by taking a PMOS gate driving circuit designed and integrated by a PMOS single-type device as an example, wherein the control end of each switching transistor corresponds to the gate of the PMOS transistor, and the switching transistor A channel end and a second path end respectively correspond to a source and a drain of the PMOS transistor.
  • the difference between the second embodiment and the second embodiment is that all the NMOS transistors in the circuit are replaced by PMOS transistors, the first reference potential is a low reference potential VGL, and the second reference potential is a high reference potential.
  • VGH the circuit structure is similar to that of the first embodiment, and will not be described again here.
  • FIG. 6 is a timing diagram of the second embodiment of the gate driving circuit of the present invention. Specifically, in conjunction with FIG. 5, the working process of the PMOS gate driving circuit of the second embodiment is as follows:
  • the transistor PT1 and the transistor PT2 are turned on, and since the gate of the transistor PT3 is connected to the low potential of the first reference potential VGL, the first reference potential is in a normal state.
  • the low potential of the VGL sets the voltage of the first node Q(N) to the first voltage through the transistor PT2 and the transistor PT3, and the first voltage is a low potential;
  • the low potential of the upper scanning drive signal Gate(N-2) causes the gate of the transistor PT5 to be low through the transistor PT1, the transistor PT5 is turned on, and the low potential of the first reference potential VGL passes the second node H(N) through the transistor PT5.
  • the voltage is set to the first voltage, that is, the low potential, the transistor PT6 is turned on, and the low potential of the upper scanning drive signal Gate(N-2) continues to accelerate the decrease of the potential of the second node H(N) through the transistor PT6, and the second node H(N)
  • the low potential is stored and held in the transistor PT5 and the transistor PT6;
  • the low potential of the upper scan driving signal Gate(N-2) causes the gate of the transistor PT8 to be low through the transistor PT1, the transistor PT8 is turned on, and the third node P(N) is pulled up to the second voltage by the second reference potential VGH.
  • the second voltage is a high potential, and the transistor PT7, the transistor PT9, and the transistor PT10 are turned off.
  • the second clock signal CK(M+1) is also at a high potential, and the transistor PT11 and the transistor PT12 are turned off;
  • the transistor PT1 and the transistor PT2 are turned off, and the aforementioned transistor PT11 and the transistor PT12 are turned off, and the voltage of the first node Q(N) is maintained in the bootstrap capacitor C1.
  • the circuit of the second circuit increases the potential storage of the second node H(N) on the basis of the conventional circuit, so that the sources of the transistor PT2 and the transistor PT7 connected to the first node Q(N) are both low, and there is almost no leakage path. , reducing the risk of circuit failure;
  • the transistor PT4 is turned on, and when the high potential of the first clock signal CK(M) comes, the first node Q(N) is bootstrapped by the bootstrap capacitor C1. A potential drop continues to occur, and the low potential of the scanning drive signal Gate(N) of the present stage is output through the transistor PT4.
  • the transistor PT11 and the transistor PT12 are turned on, and the drain of the transistor PT1 is second referenced by the transistor PT12.
  • the potential VGH is pulled up to a high potential of the second voltage, the transistor PT5, the transistor PT8 is turned off, and the low potential of the first reference potential VGL sets the third node P(N) to a low potential of the first voltage through the transistor PT11;
  • the low potential of the third node P(N) turns on the transistor PT9 and the transistor PT7, and the first node Q(N) is pulled up to the high potential of the second voltage by the second reference potential VGH through the transistor PT7 and the transistor PT9, and the second The node H(N) is pulled to the high potential by the second reference potential VGH through the transistor PT9, and the high potential of the source of the transistor PT6 is also accelerated when the high potential of the second node H(N) is insufficient to turn off the transistor PT6.
  • the low potential of the third node P(N) simultaneously turns on the transistor PT10, and the scan drive signal Gate(N) of the current stage is also pulled to the high potential by the second reference potential VGH, thereby completing the operation of one cycle of the entire circuit.
  • a third embodiment of the present invention provides a display panel including a substrate and a gate driving circuit formed on the substrate.
  • the gate driving circuit is a gate driving circuit provided in any of the above embodiments.
  • the first embodiment of the present invention and the second embodiment of the present invention respectively take an NMOS gate driving circuit and a PMOS gate driving circuit as an example, but are not limited thereto. In other embodiments, based on different implementation principles, the gate driving is performed.
  • the specific circuit structure of the circuit can be different, and the components included in the circuit can also be different, such as transistor optional CMOS semiconductor components, etc., to meet actual needs.
  • the present invention describes in detail the gate driving circuit and the display panel by the above three embodiments, by setting the pulling circuit to the first state in response to the upper level scanning driving signal in the input circuit, and using the first reference potential to the first node
  • the voltage is set to the first voltage, and while being held by the output circuit, the voltage of the second node is set to the first voltage by the first reference potential in response to the upper-level scan driving signal by the input circuit, and is held by the stabilization circuit, thereby
  • the output circuit outputs the scan drive signal of the current stage according to the first clock signal.
  • the present invention sets the voltage of the second node to the first voltage while setting the voltage of the first node to the first voltage, thereby reducing the leakage current between the first node and the second node. Therefore, the voltage of the first node can be maintained by the output circuit for a certain time, waiting for the arrival of the clock signal, thereby outputting the scan driving signal of the current stage, thereby reducing the risk of circuit failure.

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Abstract

一种栅极驱动电路及显示面板。其中，输出电路(102)在第一节点(Q(N))连接输入电路(101)和拉动电路(104)，输入电路(101)响应上级扫描驱动信号(Gate(N-2))将拉动电路(104)设置为第一状态，并利用第一参考电位(V1)将第一节点(Q(N))的电压设置为第一电压并保持，进而使得输出电路(102)根据第一时钟信号(CK(M))输出本级扫描驱动信号(Gate(N))；稳定电路(103)在第二节点(H(N))连接拉动电路(104)，输入电路(101)响应上级扫描驱动信号(Gate(N-2))利用第一参考电位(V1)将第二节点(H(N))的电压设置为第一电压并保持；拉动控制电路(105)响应第二时钟信号(CK(M+1))将拉动电路(104)设置为第二状态，进而利用第二参考电位(V2)将第一节点(Q(N))和第二节点(H(N))的电压拉动并保持成第二电压。通过上述方式，能够减小第一节点(Q(N))和第二节点(H(N))之间的漏电流，降低电路失效的风险。

Description

一种栅极驱动电路及显示面板
【技术领域】
本发明涉及显示驱动领域，特别是涉及一种栅极驱动电路及显示面板。
【背景技术】
随着低温多晶硅（Low Temperature Poly-silicon，LTPS）技术的快速发展，相应的面板周边集成电路也成为大家关注的焦点，其中一项非常重要的技术就是GOA（Gate Driver On Array，阵列基板行驱动）技术量产化的实现，利用GOA技术将栅极开关电路集成在液晶显示面板的阵列基板上，从而可以省掉栅极驱动集成电路部分，以从材料成本和制作工艺两方面降低产品成本。
这种利用GOA技术集成在阵列基板上的栅极开关电路也称栅极驱动电路。传统的栅极驱动电路中，在控制其中的输出电路输出栅极扫描驱动信号时，需要连接输出电路的节点保持一定时间的电压强度，从而在时钟信号脉冲来临时输出栅极扫描驱动信号，如果在这一定时间内，连接输出电路的节点因为漏电流的出现而无法保持电压强度，会导致电路失效，无法正常输出栅极扫描驱动信号。
【发明内容】
本发明的目的在于提供一种栅极驱动电路及显示面板，旨在解决因连接输出电路的节点无法保持一定时间的电压强度而导致电路失效的问题。
为实现上述目的，本发明提供的一种技术方案是：提供一种栅极驱动电路，包括：
输入电路、输出电路、稳定电路、拉动电路、拉动控制电路，输入电路包括第一开关管和第二开关管，稳定电路包括第三开关管；
第一开关管的第一通路端连接第一开关管的控制端及第二开关管的控制端，并接收上级扫描驱动信号，第一开关管的第二通路端连接拉动电路，第一开关管在上级扫描驱动信号的作用下导通，进而将上级扫描驱动信号传递至拉动电路，并将拉动电路设置为第一状态；
第二开关管的第一通路端连接第一参考电位，第二开关管的第二通路端连接第一节点，第一节点连接输出电路，第二开关管在上级扫描驱动信号的作用下导通，使第一参考电位将第一节点的电压设置为第一电压，并由输出电路进行保持，进而使得输出电路根据第一时钟信号输出本级扫描驱动信号；
第一开关管的第二通路端同时连接第三开关管的控制端，以接收上级扫描驱动信号，第三开关管的第一通路端连接第一参考电位，第三开关管的第二通路端连接第二节点，第三开关管在上级扫描驱动信号的作用下导通，使第一参考电位将第二节点的电压设置为第一电压，并由第三开关管进行保持；
拉动电路在第一节点连接第二开关管的第二通路端，拉动电路在第二节点连接第三开关管的第二通路端，拉动电路连接拉动控制电路，拉动控制电路响应第二时钟信号将拉动电路设置为第二状态，进而利用第二参考电位将第一节点和第二节点的电压拉动并保持成第二电压。
为实现上述目的，本发明提供的另一技术方案是：提供一种栅极驱动电路，包括：
输入电路、输出电路、稳定电路、拉动电路、拉动控制电路；
输出电路在第一节点连接输入电路和拉动电路，输入电路响应上级扫描驱动信号将拉动电路设置为第一状态，并利用第一参考电位将第一节点的电压设置为第一电压，且由输出电路进行保持，进而使得输出电路根据第一时钟信号输出本级扫描驱动信号；
稳定电路在第二节点连接拉动电路，输入电路响应上级扫描驱动信号利用第一参考电位将第二节点的电压设置为第一电压，并由稳定电路进行保持，进而减小第一节点与第二节点之间的漏电流；
拉动控制电路响应第二时钟信号将拉动电路设置为第二状态，进而利用第二参考电位将第一节点和第二节点的电压拉动并保持成第二电压。
其中，输入电路包括第一开关管和第二开关管；
第一开关管的第一通路端连接第一开关管的控制端及第二开关管的控制端，并接收上级扫描驱动信号，第一开关管的第二通路端连接拉动电路，第一开关管在上级扫描驱动信号的作用下导通，进而将上级扫描驱动信号传递至拉动电路，并将拉动电路设置为第一状态；
第二开关管的第一通路端连接第一参考电位，第二开关管的第二通路端连接第一节点，第二开关管在上级扫描驱动信号的作用下导通，使第一参考电位将第一节点的电压设置为第一电压，第一开关管的第二通路端进一步连接稳定电路，第一开关管进一步使将上级扫描驱动信号传递至稳定电路，控制稳定电路导通，进而使第一参考电位将第二节点的电压设置为第一电压，并由稳定电路进行保持。
其中，第一开关管是第一晶体管，第一开关管的控制端对应第一晶体管的栅极，第一开关管的第一通路端及第二通路端分别对应第一晶体管的源极及漏极；
第二开关管是第二晶体管，第二开关管的控制端对应第二晶体管的栅极，第二开关管的第一通路端及第二通路端分别对应第二晶体管的源极及漏极。
其中，输入电路进一步包括第三开关管；
第三开关管的控制端连接第一参考电位或第二参考电位，第三开关管的第一通路端连接第二开关管的第二通路端，第三开关管的第二通路端连接第一节点，第三开关管在第一参考电位或第二参考电位的作用下导通，以对第一节点的电压进行稳压。
其中，第三开关管是第三晶体管，第三开关管的控制端对应第三晶体管的栅极，第三开关管的第一通路端及第二通路端分别对应第三晶体管的源极及漏极。
其中，输出电路包括开关管及自举电容；
开关管的控制端连接第一节点，开关管的第一通路端输入第一时钟信号，自举电容连接于开关管的控制端与开关管的第二通路端之间，第一节点的电压被设置第一电压时，自举电容对第一电压进行保持，以使得开关管导通，进而根据第一时钟信号在开关管的第二通路端输出本级扫描驱动信号。
其中，开关管是晶体管，开关管的控制端对应晶体管的栅极，开关管的第一通路端及第二通路端分别对应晶体管的源极及漏极。
其中，稳定电路包括开关管；
开关管的控制端连接输入电路，以接收上级扫描驱动信号，开关管的第一通路端连接第一参考电位，开关管的第二通路端连接第二节点，开关管在上级扫描驱动信号的作用下导通，使第一参考电位将第二节点的电压设置为第一电压，并由开关管保持。
其中，开关管是晶体管，开关管的控制端对应晶体管的栅极，开关管的第一通路端及第二通路端分别对应晶体管的源极及漏极。
其中，稳定电路还包括另一开关管；
另一开关管的第一通路端连接第二节点和另一开关管的控制端，另一开关管的第二通路端连接输入电路，以接收上级扫描驱动信号，另一开关管在第二节点的电压设置为第一电压时导通，另一开关管与开关管共同对第一电压进行保持。
其中，另一开关管是另一晶体管，另一开关管的控制端对应另一晶体管的栅极，另一开关管的第一通路端及第二通路端分别对应另一晶体管的源极及漏极。
其中，拉动电路包括第一开关管、第二开关管、第三开关管、第四开关管和自举电容；
第一开关管的第一通路端连接第二节点，第一开关管的第一通路端连接第一节点，第一开关管的控制端连接第三节点；
第二开关管的控制端连接输入电路，以接收上级扫描驱动信号，第二开关管的第一通路端连接第三节点，第二开关管的第二通路端连接第二参考电位；
第三开关管的控制端连接第三节点，第三开关管的第一通路端连接第二节点，第三开关管的第二通路端连接第二参考电位；
第四开关管的控制端连接第三节点，第四开关管的第一通路端连接输出电路的输出端，第四开关管的第二通路端连接第二参考电位；
自举电容连接于第三节点与第二参考电位之间；
其中，第二开关管在上级扫描驱动信号作用下导通，使第二参考电位将第三节点的电压设置为第二电压，第一开关管、第三开关管及第四开关管在第三节点的作用下关闭，从而使得第一节点的第一电压在输出电路中保持，第二节点的第一电压在稳定电路中保持；
拉动控制电路响应第二时钟信号将第三节点的电压设置为第一电压，使得第一开关管、第三开关管及第四开关管导通，进而使第二参考电位将第一节点和第二节点的电压设置为第二电压。
其中，第一开关管是第一晶体管，第一开关管的控制端对应第一晶体管的栅极，第一开关管的第一通路端及第二通路端分别对应第一晶体管的源极及漏极；
第二开关管是第二晶体管，第二开关管的控制端对应第二晶体管的栅极，第二开关管的第一通路端及第二通路端分别对应第二晶体管的源极及漏极；
第三开关管是第三晶体管，第三开关管的控制端对应第三晶体管的栅极，第三开关管的第一通路端及第二通路端分别对应第三晶体管的源极及漏极；
第四开关管是第四晶体管，第四开关管的控制端对应第四晶体管的栅极，第四开关管的第一通路端及第二通路端分别对应第四晶体管的源极及漏极。
其中，拉动控制电路包括第五开关管、第六开关管；
第五开关管的第一通路端连接第三节点，第五开关管的第二通路端连接第一参考电位，第六开关管的第一通路端连接稳定电路，第六开关管的第二通路端连接第二参考电位，第五开关管的控制端及第六开关管的控制端接收第二时钟信号；
第六开关管在第二时钟信号的作用下导通，使第二参考电位经第六开关管，控制稳定电路解除对第一电压的保持；
第五开关管在第二时钟信号的作用下导通，使第一参考电位经第五开关管将第三节点的电压设置为第一电压，使得第一开关管、第三开关管、第四开关管导通，进而利用第二参考电位将第一节点、第二节点的电压设置为第二电压。
其中，第五开关管是第五晶体管，第五开关管的控制端对应第五晶体管的栅极，第五开关管的第一通路端及第二通路端分别对应第五晶体管的源极及漏极；
第六开关管是第六晶体管，第六开关管的控制端对应第六晶体管的栅极，第六开关管的第一通路端及第二通路端分别对应第六晶体管的源极及漏极。
其中，第一参考电位为高参考电位和低参考电位中的一个，第二参考电位为高参考电位和低参考电位中的另一个。
其中，第一电压为高电位和低电位中的一个，第二电压为高电位和低电位中的另一个。
为实现上述目的，本发明提供的又一技术方案是：提供一种显示面板，包括基板及基板上的栅极驱动电路。
本发明的有益效果是：区别于现有技术的情况，本发明通过在输入电路响应上级扫描驱动信号将拉动电路设置为第一状态，并利用第一参考电位将第一节点的电压设置为第一电压，且由输出电路进行保持的同时，通过输入电路响应上级扫描驱动信号利用第一参考电位将第二节点的电压设置为第一电压，并由稳定电路进行保持，进而使得输出电路根据第一时钟信号输出本级扫描驱动信号。通过这种方式，本发明在第一节点的电压为第一电压的同时，也使第二节点的电压为第一电压，从而减小第一节点和第二节点之间的漏电流，使得第一节点的电压可以由输出电路保持一定时间的强度，等待时钟信号的到来，从而输出本级扫描驱动信号，降低电路失效的风险。
【附图说明】
图1是本发明栅极驱动电路实施一的原理示意图；
图2是本发明栅极驱动电路实施例一的具体电路图；
图3是本发明栅极驱动电路实施例一的驱动框架示意图；
图4是本发明栅极驱动电路实施例一的时序图；
图5是本发明栅极驱动电路实施例二的具体电路图；
图6是本发明栅极驱动电路实施例二的时序图。
【具体实施方式】
为使本领域的技术人员更好地理解本发明的技术方案，下面结合附图和具体实施方式对本发明所提供的一种栅极驱动电路及显示面板做进一步详细描述。
如图1所示，本发明栅极驱动电路实施例一包括：输入电路101、输出电路102、稳定电路103、拉动电路104、拉动控制电路105。
输出电路102在第一节点Q（N）连接输入电路101和拉动电路104，输入电路101响应上级扫描驱动信号Gate（N-2）将拉动电路104设置为第一状态，并利用第一参考电位V1将第一节点Q（N）的电压设置为第一电压，且由输出电路102进行保持，进而使得输出电路102根据第一时钟信号CK（M）输出本级扫描驱动信号Gate（N）；
稳定电路103在第二节点H（N）连接拉动电路104，输入电路101响应上级扫描驱动信号Gate（N-2）利用第一参考电位V1将第二节点H（N）的电压设置为第一电压，并由稳定电路103进行保持，进而减小第一节点Q（N）与第二节点H（N）之间的漏电流；
拉动控制电路105响应第二时钟信号CK（M+1）将拉动电路104设置为第二状态，进而利用第二参考电位V2将第一节点Q（N）与第二节点H（N）的电压拉动并保持成第二电压。
具体地，本实施例一的电路利用上级扫描驱动信号Gate（N-2）作为启动信号，在第一时钟信号CK（M）的作用下，输出本级扫描驱动信号Gate（N），在本级扫描驱动信号Gate（N）的作用下，其所在行的开关管写入像素后，需要将本级扫描驱动信号Gate（N）恢复到常态即使其所在扫描行的开关管保持截止，因此需要使拉动控制电路105响应第二时钟信号CK（M+1）将拉动电路104设置为第二状态，进而利用第二参考电位V2将第一节点Q（N）与第二节点H（N）的电压拉动并保持成第二电压，使本级扫描驱动信号Gate（N）的电压保持为第二电压，第二电压使扫描行的开关管保持截止。
其中，本实施例一的上级扫描驱动信号Gate（N-2）是本级扫描驱动信号Gate（N）前两级的扫描驱动信号，在其他实施中，上级扫描驱动信号可选本级扫描驱动信号前几级的扫描驱动信号，或本级扫描驱动信号后几级的扫描驱动信号，级数并不做限定。第一时钟信号CK（M）、第二时钟信号CK（M+1）可选高频或低频时钟信号。
在传统电路中，连接输出电路的节点（类比本实施例一的第一节点）被设置为一定强度的电压，以等待时钟信号的来临从而输出本级扫描驱动信号时，并没有能与连接输出电路的节点保持同等电压的节点或是存储电压，此时，如果连接输出电路的节点的开关管的漏电特性不是很好，输出电路的节点的电压无法保持一定强度，当时钟信号来临时，连接输出电路的节点使输出电路无法发挥作用，栅极扫描驱动信号无法正常输出，导致电路失效。
而本实施例一中，第一节点Q（N）连接输入电路101、输出电路102、拉动电路104，是控制本级扫描信号Gate（N）输出的点，第二节点H（N）连接于稳定电路103与拉动电路104之间，是防止漏电流出现的点，输入电路101首先需要响应上级扫描驱动信号将拉动电路104设置为第一状态，为第一节点Q（N）、第二节点H（N）的电压设置以及设置后电压的保持做准备，在输入电路101输入上级扫描驱动信号使第一节点Q（N）的电压被第一参考电位V1设置为第一电压时，输入电路101也通过稳定电路103将第二节点H（N）的电压被第一参考电位V1设置为第一电压，第一节点Q（N）与第二节点H（N）的电压相同，两个节点之间几乎不存在漏电流，第一节点Q（N）的电压在输出电路102中得以保持，通过这种方式，使电路失效的风险大大降低。
其中，在优选实施例中，第一参考电位V1为高参考电位VGH和低参考电位VGL中的一个，第二参考电位V2为高参考电位VGH和低参考电位VGL中的另一个，也就是说，如果第一参考电位V1是高参考电位VGH，那么第二参考电位V2就是低参考电位VGL，如果第一参考电位V1是低参考电位VGL，那么第一参考电位V1就是高参考电位VGH，第一参考电位V1和第二参考电位V2用于设置第一电压为高电位和低电位中的一个，第二电压为高电位和低电位中的另一个。
栅极驱动电路的开关管通常采用膜薄晶体管，薄膜晶体管有两种类型的器件，一种是以空穴导电为主的P型器件（PMOS），一种是以电子导电为主的N型器件（NMOS）。
在本实施例一的一应用场景中，如图2所示，以NMOS单型器件设计集成的NMOS栅极驱动电路为例来进行具体阐述，其中，各个开关管的控制端对应于NMOS晶体管的栅极，开关管的第一通路端及第二通路端分别对应于NMOS晶体管的源极及漏极。在其他实施例中，NMOS晶体管的源极及漏极的位置也可以根据需要进行互换。
具体地，输入电路101包括晶体管T1、晶体管T2、晶体管T3；
晶体管T1的源极连接晶体管T1的栅极及晶体管T2的栅极，并接收上级扫描驱动信号Gate（N-2），晶体管T1的漏极连接拉动电路104、稳定电路103；晶体管T2的源极连接第一参考电位VGH，晶体管T2的漏极连接晶体管T3的源极，晶体管T3的漏极连接第一节点Q（N），晶体管T3的栅极连接第一参考电位V1，第一参考电位V1是高参考电位VGH；
输入电路101实现扫描驱动级传信号的输入，实现对第一节点Q（N）、第二节点H（N）电压的设置，实现对拉动电路104第一状态的设置，其中，晶体管T3主要起到稳定电压的作用。
输出电路102包括晶体管T4及自举电容C1；
晶体管T4的栅极连接第一节点Q（N），晶体管T4的源极输入第一时钟信号CK（M），自举电容C1连接于晶体管T4的栅极与晶体管T4的漏极之间，第一节点Q（N）的电压被设置第一电压时，自举电容C1对第一电压进行保持，以使得晶体管T4导通，进而根据第一时钟信号CK（M）在晶体管T4的漏极输出本级扫描驱动信号Gate（N）。
稳定电路103包括晶体管T5和晶体管T6；
晶体管T5的栅极连接晶体管T1的漏极，以接收上级扫描驱动信号Gate（N-2），晶体管T5的源极连接第一参考电位VGH，晶体管T5的漏极连接第二节点H（N），晶体管T6的源极连接第二节点H（N）和晶体管T6的栅极，晶体管T6的漏极连接晶体管T1的漏极。
其中，在其他实施例中，稳定电路103中晶体管T6可以移除。
拉动电路104包括晶体管T7、晶体管T8、晶体管T9和晶体管T10和自举电容C2；
晶体管T7的源极连接第二节点H（N），晶体管T7的漏极连接第一节点Q（N），晶体管T7的栅极连接第三节点P（N）；晶体管T8的栅极连接晶体管T1的漏极，以接收上级扫描驱动信号Gate（N-2），晶体管T8的源极连接第三节点P（N），晶体管T8的漏极连接第二参考电位V2，第二参考电位V2是低参考电位VGL；晶体管T9的栅极连接第三节点P（N），晶体管T9的源极连接第二节点H（N），晶体管T9的漏极连接第二参考电位VGL；晶体管T10的栅极连接第三节点P（N），晶体管T10的源极连接晶体管T4的漏极，晶体管T10的漏极连接第二参考电位VGL；自举电容C2连接于第三节点P（N）与第二参考电位VGL之间。
拉动控制电路105包括晶体管T11、晶体管T12；
晶体管T11的源极连接第三节点P（N），晶体管T11的漏极连接第一参考电位VGH，晶体管T12的源极连接晶体管T5的漏极，晶体管T12的漏极连接第二参考电位VGL，晶体管T11的栅极及晶体管T12的栅极接收第二时钟信号CK（M+1）。
在上述电路中，第一参考电位VGH可选恒压正电位，第二参考电位VGL可选恒压负电位。
第一时钟信号CK（M）、第二时钟信号CK （M+1）是从同一组的四个时钟信号中选取的两组时钟信号，比如，CK（1）、CK（2）、CK（3）、CK（4）为同一组时钟信号CK（M）所包含的四组交替循环的时钟信号，均为低频时钟信号，如图3所示，是本实施例一的驱动框架示意图，如果第一级扫描驱动信号Gate（1）用到的时钟信号CK（M）、CK(M+1)对应于CK（1）、CK（2），那么第二级扫描驱动信号Gate（2）用到的时钟信号CK（M）、CK(M+1)对应于CK（2）、CK（3），第三级扫描驱动信号Gate（3）用到的时钟信号CK（M）、CK(M+1)对应于CK（3）、CK（4），第四级扫描驱动信号Gate（4）用到的时钟信号CK（M）、CK(M+1)对应于CK（4）、CK（1），以次类推交替循环。
同时从图3可以看出，本级扫描驱动信号Gate（N）是以其前两级的扫描驱动信号Gate（N-2）为输入启动信号进行作用，但是在第一级扫描驱动信号Gate（1）、第二级扫描驱动信号Gate（2）的连接关系中，无法使用其前两级的扫描驱动信号，因此，在本实施例一的第一级扫描驱动信号Gate（1）的连接关系中，晶体管T1的栅极及源极连接输入启动信号STV1，在第二级扫描驱动信号Gate（2）的连接关系中，晶体管T1的栅极及源极连接输入启动信号STV2，输入启动信号STV1、STV2给出高电位脉冲，使电路启动。
图4所示是本发明栅极驱动电路实施例一的时序图，结合图2，本实施例一的具体工作过程为：
当上级扫描驱动信号Gate（N-2）的高电位来临时，晶体管T1、晶体管T2导通，由于晶体管T3的栅极连接第一参考电位VGH的高电位，处于导通常态，第一参考电位VGH的高电位通过晶体管T2、晶体管T3将第一节点Q（N）的电压设置为第一电压，第一电压为高电位；
上级扫描驱动信号Gate（N-2）的高电位通过晶体管T1使晶体管T5的栅极为高电位，晶体管T5导通，第一参考电位VGH的高电位通过晶体管T5将第二节点H（N）的电压设置为第一电压即高电位，晶体管T6导通，上级扫描驱动信号Gate（N-2）的高电位通过晶体管T6继续加速第二节点H（N）电位的上升，第二节点H（N）的高电位在晶体管T5、晶体管T6中进行存储保持；
上级扫描驱动信号Gate（N-2）的高电位通过晶体管T1使晶体管T8的栅极为高电位，晶体管T8导通，第三节点P（N）被第二参考电位VGL拉低至第二电压，第二电压是低电位，晶体管T7、晶体管T9、晶体管T10截止，此时第二时钟信号CK（M+1）也为低电位，晶体管T11、晶体管T12截止，拉动电路104保持为第一状态；
上级扫描驱动信号Gate（N-2）的高电位作用完毕后，晶体管T1、晶体管T2截止，前述拉动电路104已经被设置为第一状态，晶体管T7、晶体管T9截止，第一节点Q（N）的电压得以保持为高电位，从图6可以看出，在等待第一时钟信号CK（M）来临时，第一节点Q（N）的高电位需要保持两个时钟脉冲的时间，第一时钟信号本实施例一的电路，在传统电路的基础上增加第二节点H（N）的电位存储，使得连接第一节点Q（N）的晶体管T2、晶体管T7的源极均为高电位，不存在漏电路径，降低电路失效的风险；
在第一节点Q（N）的高电位保持期间，晶体管T4导通，当第一时钟信号CK（M）的高电位来临时，第一节点Q（N）由于自举电容C1的自举作用会出现电位的继续上升，通过晶体管T4输出本级扫描驱动信号Gate（N）的高电位。
第一时钟信号CK（M）的高电位作用完毕后，第二时钟信号CK（M+1）的高电位来临，晶体管T11、晶体管T12导通，晶体管T1的漏极通过晶体管T12被第二参考电位VGL拉低至第二电压的低电位，晶体管T5、晶体管T8截止，第一参考电位VGH的高电位通过晶体管T11将第三节点P（N）设置为第一电压的高电位，此时拉动电路为第二状态；
第三节点P（N）的高电位使晶体管T9、晶体管T7导通，第一节点Q（N）通过晶体管T7、晶体管T9被第二参考电位VGL下拉至低电位，第二节点H（N）通过晶体管T9被第二参考电位VGL下拉至低电位，在第二节点H（N）的低电位还不足以使晶体管T6截止时，晶体管T6源极的低电位也会加速第二节点H（N）电位的下拉；
第三节点P（N）的高电位同时使晶体管T10导通，本级扫描驱动信号Gate（N）也被第二参考电位VGL下拉至低电位，至此，完成整个电路一个时序周期的工作。
本发明栅极驱动电路实施例二，以PMOS单型器件设计集成的PMOS栅极驱动电路为例来进行具体阐述，其中，各个开关管的控制端对应于PMOS晶体管的栅极，开关管的第一通路端及第二通路端分别对应于PMOS晶体管的源极及漏极。
如图5所示，该实施例二与实施例一图2的区别在于，将电路中的NMOS晶体管全部换成PMOS晶体管，第一参考电位是低参考电位VGL，第二参考电位是高参考电位VGH，电路结构与实施例一相类似，此处不再赘述。
图6是本发明栅极驱动电路实施例二的时序图，具体地，结合图5，本实施例二PMOS栅极驱动电路的工作过程为：
当上级扫描驱动信号Gate（N-2）的低电位来临时，晶体管PT1、晶体管PT2导通，由于晶体管PT3的栅极连接第一参考电位VGL的低电位，处于导通常态，第一参考电位VGL的低电位通过晶体管PT2、晶体管PT3将第一节点Q（N）的电压设置为第一电压，第一电压为低电位；
上级扫描驱动信号Gate（N-2）的低电位通过晶体管PT1使晶体管PT5的栅极为低电位，晶体管PT5导通，第一参考电位VGL的低电位通过晶体管PT5将第二节点H（N）的电压设置为第一电压即低电位，晶体管PT6导通，上级扫描驱动信号Gate（N-2）的低电位通过晶体管PT6继续加速第二节点H（N）电位的下降，第二节点H（N）的低电位在晶体管PT5、晶体管PT6中进行存储保持；
上级扫描驱动信号Gate（N-2）的低电位通过晶体管PT1使晶体管PT8的栅极为低电位，晶体管PT8导通，第三节点P（N）被第二参考电位VGH拉高至第二电压，第二电压是高电位，晶体管PT7、晶体管PT9、晶体管PT10截止，此时第二时钟信号CK（M+1）也为高电位，晶体管PT11、晶体管PT12截止；
上级扫描驱动信号Gate（N-2）的低电位作用完毕后，晶体管PT1、晶体管PT2截止，前述提到晶体管PT11、晶体管PT12截止，第一节点Q（N）的电压在自举电容C1中保持为低电位，从图6可以看出，在等待第一时钟信号CK（M）来临时，第一节点Q（N）的低电位需要保持两个时钟脉冲的时间，第一时钟信号本实施例二的电路，在传统电路的基础上增加第二节点H（N）的电位存储，使得连接第一节点Q（N）的晶体管PT2、晶体管PT7的源极均为低电位，几乎不存在漏电路径，降低电路失效的风险；
在第一节点Q（N）的低电位保持期间，晶体管PT4导通，当第一时钟信号CK（M）的高电位来临时，第一节点Q（N）由于自举电容C1的自举作用会出现电位的继续下降，通过晶体管PT4输出本级扫描驱动信号Gate（N）的低电位。
第一时钟信号CK（M）的低电位作用完毕后，第二时钟信号CK（M+1）的低电位来临，晶体管PT11、晶体管PT12导通，晶体管PT1的漏极通过晶体管PT12被第二参考电位VGH拉高至第二电压的高电位，晶体管PT5、晶体管PT8截止，第一参考电位VGL的低电位通过晶体管PT11将第三节点P（N）设置为第一电压的低电位；
第三节点P（N）的低电位使晶体管PT9、晶体管PT7导通，第一节点Q（N）通过晶体管PT7、晶体管PT9被第二参考电位VGH拉高至第二电压的高电位，第二节点H（N）通过晶体管PT9被第二参考电位VGH拉至高电位，在第二节点H（N）的高电位还不足以使晶体管PT6截止时，晶体管PT6源极的高电位也会加速第二节点H（N）电位的上升；
第三节点P（N）的低电位同时使晶体管PT10导通，本级扫描驱动信号Gate（N）也被第二参考电位VGH拉至高电位，至此，完成整个电路一个时序周期的工作。
本发明实施例三提供一种显示面板，包括基板及在基板上形成栅极驱动电路，该栅极驱动电路为上述任一实施例提供的栅极驱动电路。
本发明实施例一及本发明实施例二分别以NMOS栅极驱动电路及PMOS栅极驱动电路为例，但并不以此为限，在其他实施例中，基于不同的实现原理，栅极驱动电路的具体电路结构可以不同，电路中包含的元器件也可不同，如晶体管可选CMOS半导体元件等，以满足实际需求为准。
本发明通过上述三个实施例详细描述了一种栅极驱动电路及显示面板，通过在输入电路响应上级扫描驱动信号将拉动电路设置为第一状态，并利用第一参考电位将第一节点的电压设置为第一电压，且由输出电路进行保持的同时，通过输入电路响应上级扫描驱动信号利用第一参考电位将第二节点的电压设置为第一电压，并由稳定电路进行保持，进而使得输出电路根据第一时钟信号输出本级扫描驱动信号。通过这种方式，本发明在将第一节点的电压设置为第一电压的同时，也将第二节点的电压设置为第一电压，从而减小第一节点和第二节点之间的漏电流，使得第一节点的电压可以由输出电路保持一定时间的强度，等待时钟信号的到来，从而输出本级扫描驱动信号，减小电路失效的风险。
以上所述仅为本发明的实施方式，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (19)

  1. 一种栅极驱动电路，其中，包括：
    输入电路、输出电路、稳定电路、拉动电路、拉动控制电路，所述输入电路包括第一开关管和第二开关管，所述稳定电路包括第三开关管；
    所述第一开关管的第一通路端连接所述第一开关管的控制端及所述第二开关管的控制端，并接收上级扫描驱动信号，所述第一开关管的第二通路端连接所述拉动电路，所述第一开关管在所述上级扫描驱动信号的作用下导通，进而将所述上级扫描驱动信号传递至所述拉动电路，并将所述拉动电路设置为第一状态；
    所述第二开关管的第一通路端连接第一参考电位，所述第二开关管的第二通路端连接第一节点，所述第一节点连接所述输出电路，所述第二开关管在所述上级扫描驱动信号的作用下导通，使所述第一参考电位将所述第一节点的电压设置为第一电压，并由所述输出电路进行保持，进而使得所述输出电路根据第一时钟信号输出本级扫描驱动信号；
    所述第一开关管的第二通路端同时连接所述第三开关管的控制端，以接收所述上级扫描驱动信号，所述第三开关管的第一通路端连接所述第一参考电位，所述第三开关管的第二通路端连接第二节点，所述第三开关管在所述上级扫描驱动信号的作用下导通，使所述第一参考电位将所述第二节点的电压设置为所述第一电压，并由所述第三开关管进行保持；
    所述拉动电路在所述第一节点连接所述第二开关管的第二通路端，所述拉动电路在所述第二节点连接所述第三开关管的第二通路端，所述拉动电路连接所述拉动控制电路，所述拉动控制电路响应第二时钟信号将所述拉动电路设置为第二状态，进而利用第二参考电位将所述第一节点和所述第二节点的电压拉动并保持成第二电压。
  2. 一种栅极驱动电路，其中，包括：
    输入电路、输出电路、稳定电路、拉动电路、拉动控制电路；
    所述输出电路在第一节点连接所述输入电路和所述拉动电路，所述输入电路响应上级扫描驱动信号将所述拉动电路设置为第一状态，并利用第一参考电位将所述第一节点的电压设置为第一电压，且由所述输出电路进行保持，进而使得所述输出电路根据第一时钟信号输出本级扫描驱动信号；
    所述稳定电路在第二节点连接所述拉动电路，所述输入电路响应所述上级扫描驱动信号利用所述第一参考电位将所述第二节点的电压设置为所述第一电压，并由所述稳定电路进行保持，进而减小所述第一节点与所述第二节点之间的漏电流；
    所述拉动控制电路响应第二时钟信号将所述拉动电路设置为第二状态，进而利用第二参考电位将所述第一节点和所述第二节点的电压拉动并保持成第二电压。
  3. 根据权利要求2所述的栅极驱动电路，其中，
    所述输入电路包括第一开关管和第二开关管；
    所述第一开关管的第一通路端连接所述第一开关管的控制端及所述第二开关管的控制端，并接收所述上级扫描驱动信号，所述第一开关管的第二通路端连接所述拉动电路，所述第一开关管在所述上级扫描驱动信号的作用下导通，进而将所述上级扫描驱动信号传递至所述拉动电路，并将所述拉动电路设置为所述第一状态；
    所述第二开关管的第一通路端连接所述第一参考电位，所述第二开关管的第二通路端连接所述第一节点，所述第二开关管在所述上级扫描驱动信号的作用下导通，使所述第一参考电位将所述第一节点的电压设置为所述第一电压，所述第一开关管的第二通路端进一步连接所述稳定电路，所述第一开关管进一步使将所述上级扫描驱动信号传递至所述稳定电路，控制所述稳定电路导通，进而使所述第一参考电位将所述第二节点的电压设置为所述第一电压，并由所述稳定电路进行保持。
  4. 根据权利要求3所述的栅极驱动电路，其中，
    所述第一开关管是第一晶体管，所述第一开关管的控制端对应所述第一晶体管的栅极，所述第一开关管的第一通路端及第二通路端分别对应所述第一晶体管的源极及漏极；
    所述第二开关管是第二晶体管，所述第二开关管的控制端对应所述第二晶体管的栅极，所述第二开关管的第一通路端及第二通路端分别对应所述第二晶体管的源极及漏极。
  5. 根据权利要求3所述的栅极驱动电路，其中，
    所述输入电路进一步包括第三开关管；
    所述第三开关管的控制端连接所述第一参考电位或所述第二参考电位，所述第三开关管的第一通路端连接所述第二开关管的第二通路端，所述第三开关管的第二通路端连接所述第一节点，所述第三开关管在所述第一参考电位或所述第二参考电位的作用下导通，以对所述第一节点的电压进行稳压。
  6. 根据权利要求5所述的栅极驱动电路，其中，
    所述第三开关管是第三晶体管，所述第三开关管的控制端对应所述第三晶体管的栅极，所述第三开关管的第一通路端及第二通路端分别对应所述第三晶体管的源极及漏极。
  7. 根据权利要求2所述的栅极驱动电路，其中，
    所述输出电路包括开关管及自举电容；
    所述开关管的控制端连接所述第一节点，所述开关管的第一通路端输入所述第一时钟信号，所述自举电容连接于所述开关管的控制端与所述开关管的第二通路端之间，所述第一节点的电压被设置所述第一电压时，所述自举电容对所述第一电压进行保持，以使得所述开关管导通，进而根据所述第一时钟信号在所述开关管的第二通路端输出所述本级扫描驱动信号。
  8. 根据权利要求7所述的栅极驱动电路，其中，
    所述开关管是晶体管，所述开关管的控制端对应所述晶体管的栅极，所述开关管的第一通路端及第二通路端分别对应所述晶体管的源极及漏极。
  9. 根据权利要求2所述的栅极驱动电路，其中，
    所述稳定电路包括开关管；
    所述开关管的控制端连接所述输入电路，以接收所述上级扫描驱动信号，所述开关管的第一通路端连接所述第一参考电位，所述开关管的第二通路端连接所述第二节点，所述开关管在所述上级扫描驱动信号的作用下导通，使所述第一参考电位将所述第二节点的电压设置为所述第一电压，并由所述开关管保持。
  10. 根据权利要求9所述的栅极驱动电路，其中，
    所述开关管是晶体管，所述开关管的控制端对应所述晶体管的栅极，所述开关管的第一通路端及第二通路端分别对应所述晶体管的源极及漏极。
  11. 根据权利要求9所述的栅极驱动电路，其中，
    所述稳定电路还包括另一开关管；
    所述另一开关管的第一通路端连接所述第二节点和所述另一开关管的控制端，所述另一开关管的第二通路端连接所述输入电路，以接收所述上级扫描驱动信号，所述另一开关管在所述第二节点的电压设置为所述第一电压时导通，所述另一开关管与所述开关管共同对所述第一电压进行保持。
  12. 根据权利要求11所述的栅极驱动电路，其中，
    所述另一开关管是另一晶体管，所述另一开关管的控制端对应所述另一晶体管的栅极，所述另一开关管的第一通路端及第二通路端分别对应所述另一晶体管的源极及漏极。
  13. 根据权利要求2所述的栅极驱动电路，其中，
    所述拉动电路包括第一开关管、第二开关管、第三开关管、第四开关管和自举电容；
    所述第一开关管的第一通路端连接所述第二节点，所述第一开关管的第二通路端连接所述第一节点，所述第一开关管的控制端连接第三节点；
    所述第二开关管的控制端连接所述输入电路，以接收所述上级扫描驱动信号，所述第二开关管的第一通路端连接所述第三节点，所述第二开关管的第二通路端连接所述第二参考电位；
    所述第三开关管的控制端连接所述第三节点，所述第三开关管的第一通路端连接所述第二节点，所述第三开关管的第二通路端连接所述第二参考电位；
    所述第四开关管的控制端连接所述第三节点，所述第四开关管的第一通路端连接所述输出电路的输出端，所述第四开关管的第二通路端连接所述第二参考电位；
    所述自举电容连接于所述第三节点与所述第二参考电位之间；
    其中，所述第二开关管在所述上级扫描驱动信号作用下导通，使所述第二参考电位将所述第三节点的电压设置为所述第二电压，所述第一开关管、所述第三开关管及所述第四开关管在所述第三节点的作用下关闭，从而使得所述第一节点的第一电压在所述输出电路中保持，所述第二节点的第一电压在所述稳定电路中保持；
    所述拉动控制电路响应所述第二时钟信号将所述第三节点的电压设置为所述第一电压，使得所述第一开关管、所述第三开关管及所述第四开关管导通，进而使所述第二参考电位将所述第一节点和所述第二节点的电压设置为所述第二电压。
  14. 根据权利要求13所述的栅极驱动电路，其中，
    所述第一开关管是第一晶体管，所述第一开关管的控制端对应所述第一晶体管的栅极，所述第一开关管的第一通路端及第二通路端分别对应所述第一晶体管的源极及漏极；
    所述第二开关管是第二晶体管，所述第二开关管的控制端对应所述第二晶体管的栅极，所述第二开关管的第一通路端及第二通路端分别对应所述第二晶体管的源极及漏极；
    所述第三开关管是第三晶体管，所述第三开关管的控制端对应所述第三晶体管的栅极，所述第三开关管的第一通路端及第二通路端分别对应所述第三晶体管的源极及漏极；
    所述第四开关管是第四晶体管，所述第四开关管的控制端对应所述第四晶体管的栅极，所述第四开关管的第一通路端及第二通路端分别对应所述第四晶体管的源极及漏极。
  15. 根据权利要求13所述的栅极驱动电路，其中，
    所述拉动控制电路包括第五开关管、第六开关管；
    所述第五开关管的第一通路端连接所述第三节点，所述第五开关管的第二通路端连接所述第一参考电位，所述第六开关管的第一通路端连接所述稳定电路，所述第六开关管的第二通路端连接所述第二参考电位，所述第五开关管的控制端及所述第六开关管的控制端接收所述第二时钟信号；
    所述第六开关管在所述第二时钟信号的作用下导通，使所述第二参考电位经所述第六开关管，控制所述稳定电路解除对所述第一电压的保持；
    所述第五开关管在所述第二时钟信号的作用下导通，使所述第一参考电位经所述第五开关管将所述第三节点的电压设置为所述第一电压，使得所述第一开关管、所述第三开关管、所述第四开关管导通，进而利用所述第二参考电位将所述第一节点、所述第二节点的电压设置为所述第二电压。
  16. 根据权利要求15所述的栅极驱动电路，其中，
    所述第五开关管是第五晶体管，所述第五开关管的控制端对应所述第五晶体管的栅极，所述第五开关管的第一通路端及第二通路端分别对应所述第五晶体管的源极及漏极；
    所述第六开关管是第六晶体管，所述第六开关管的控制端对应所述第六晶体管的栅极，所述第六开关管的第一通路端及第二通路端分别对应所述第六晶体管的源极及漏极。
  17. 根据权利要求2所述的栅极驱动电路，其中，
    所述第一参考电位为高参考电位和低参考电位中的一个，所述第二参考电位为高参考电位和低参考电位中的另一个。
  18. 根据权利要求2所述的栅极驱动电路，其中，
    所述第一电压为高电位和低电位中的一个，所述第二电压为高电位和低电位中的另一个。
  19. 一种显示面板，其中，包括基板及基板上如权利要求1所述的栅极驱动电路。
PCT/CN2016/074228 2016-01-21 2016-02-22 一种栅极驱动电路及显示面板 Ceased WO2017124598A1 (zh)

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