WO2016194795A1 - Thin film transistor comprising oxide semiconductor layer - Google Patents

Abstract

The present invention relates to a thin film transistor which comprises, on a substrate, at least a gate electrode, a gate insulating film, an oxide semiconductor layer, a source/drain electrode, and two or more protective films, and which is configured such that: the metal elements constituting the oxide semiconductor layer are In, Ga, Zn and Sn; the source/drain electrode is composed of a Ti-based film, an Mo-based film, a Ti-based/Cu-based multilayer film or an Mo-based/Cu-based multilayer film; and the source/drain electrode is directly bonded to the oxide semiconductor layer. This thin film transistor has excellent switching characteristics, S value, stress resistance and photostress resistance (in other words, the amount of threshold value change of the transistor due to photostress is small), while maintaining high electric field mobility even if a Ti-based film, an Mo-based film, a Ti-based/Cu-based multilayer film or an Mo-based/Cu-based multilayer film is used for the source/drain electrode.

Description

Thin film transistor including an oxide semiconductor layer

The present invention relates to a thin film transistor including an oxide semiconductor layer. More specifically, the present invention relates to a thin film transistor including an oxide semiconductor layer used in a display device such as a liquid crystal display or an organic EL display.

An amorphous oxide semiconductor has a higher carrier mobility than general-purpose amorphous silicon. Amorphous oxide semiconductors are expected to be applied to display devices that require large size, high resolution, and high speed driving.

The carrier mobility is also called field effect mobility. Hereinafter, it may be simply referred to as “mobility”.

As the oxide semiconductor, an amorphous oxide semiconductor material IGZO (hereinafter, simply referred to as “IGZO”) composed of In, Ga, Zn, and O described in Patent Document 1 is well known. The field effect mobility of the thin film transistor including this oxide semiconductor is 10 cm ² / Vs or less. However, in order to cope with an increase in the screen size and driving speed of a display device, a material having higher field effect mobility is required.

Patent Document 2 discloses a method of suppressing an increase in TFT characteristic variation and a reduction in TFT on-current by using dry etching for processing a source / drain electrode. Patent Document 3 discloses that good electrical characteristics can be obtained by removing the damaged region on the channel surface.

In addition to high mobility, compatibility with the thin film transistor manufacturing process is also required. There are various structures of a thin film transistor using an oxide semiconductor. As an example, a stacked cross-sectional structure of the thin film transistor is illustrated in FIGS. 1A and 1B. FIG. 1A shows an etch stopper (ESL) type thin film transistor having an etch stopper layer 9, and FIG. 1B shows a back channel etch (BCE) type thin film transistor stack without the etch stopper layer 9. It is a cross-sectional structure.

Among the two patterns of thin film transistors, the BCE type is low in production cost from the viewpoint of mass production, has a small parasitic capacitance, and is easy to shorten. However, when the source / drain electrodes are processed by wet etching, the surface of the oxide semiconductor thin film (back channel) is exposed to the etching solution by the etching solution, which causes the surface to become rough, and further damage such as oxygen vacancies. As a result, transistor characteristics and stress resistance may be reduced.

Therefore, an oxide semiconductor thin film used for a BCE thin film transistor is required to have high resistance to the etching solution. On the other hand, an oxide semiconductor thin film is also required to be patterned without any residue by being etched at an appropriate rate with respect to an organic acid such as oxalic acid as an etchant when the oxide semiconductor thin film itself is processed by wet etching. Is done.

US Patent Application Publication No. 2012/153277 US Patent Application Publication No. 2011/049508 US Patent Application Publication No. 2008/315193

In the above-described IGZO, when using Mo wiring, Mo alloy wiring, or multilayer wiring of Al wiring or Al alloy wiring and Mo wiring or Mo alloy wiring for the source / drain electrodes, phosphoric acid, nitric acid, acetic acid are used for electrode processing. A general-purpose inorganic acid-based etching solution including the above is used. However, since IGZO is easily etched by the inorganic acid-based etching solution, a BCE thin film transistor using the above-described wiring cannot be formed.

Furthermore, in IGZO, Mo wiring of Mo wiring or Mo alloy wiring on the source / drain electrodes, Mo / Cu laminated wiring of the Mo wiring and Cu wiring or Cu alloy wiring, Ti wiring of Ti wiring or Ti alloy wiring When a wiring or a Ti / Cu laminated wiring of the Ti wiring and Cu wiring or Cu alloy wiring is used, an inorganic etching solution containing hydrogen fluoride in fluoride is used for electrode processing. . However, since IGZO is easily etched by the inorganic etching solution, it is impossible to form a BCE thin film transistor using the above-described wiring.

The present invention has been made in view of the above circumstances, and the source / drain electrodes include at least one of a Mo-based film of a pure Mo film and a Mo alloy film, or the Mo-based film, a pure Cu film, and a Cu alloy film. A laminated film with at least one of the Cu-based films (hereinafter sometimes referred to as “Mo-based / Cu-based laminated film”), a Ti-based film of at least one of a pure Ti film and a Ti alloy film, or When a laminated film of the Ti-based film and at least one of a Cu-based film of pure Cu film and Cu alloy film (hereinafter sometimes referred to as “Ti-based / Cu-based laminated film”) is used. An object of the present invention is to provide a thin film transistor having excellent characteristics.

The present invention relates to the following [1] to [6].
[1] A thin film transistor having at least a gate electrode, a gate insulating film, an oxide semiconductor layer, a source / drain electrode, and a protective film having two or more layers on a substrate,
The metal elements constituting the oxide semiconductor layer are In, Ga, Zn, and Sn,
The source / drain electrode is a Ti-based film of at least one of a pure Ti film and a Ti alloy film, or a Ti-based film of the Ti-based film and at least one of a Cu-based film of a pure Cu film and a Cu alloy film. A thin film transistor which is a Cu-based laminated film and in which the source / drain electrodes are directly bonded to the oxide semiconductor layer.
[2] A thin film transistor having at least a gate electrode, a gate insulating film, an oxide semiconductor layer, a source / drain electrode, and a protective film having two or more layers on a substrate,
The metal elements constituting the oxide semiconductor layer are In, Ga, Zn, and Sn,
The source / drain electrode is a Mo-based film of at least one of a pure Mo film and a Mo alloy film, or a Mo-based film of the Mo-based film and at least one of a pure Cu film and a Cu alloy film. A thin film transistor which is a Cu-based laminated film and in which the source / drain electrodes are directly bonded to the oxide semiconductor layer.
[3] The thin film transistor according to [1] or [2], wherein a ratio of Sn to a total of all metal elements in the oxide semiconductor layer is 9 atomic% or more and 50 atomic% or less.
[4] The ratio of each metal element to the total of all metal elements in the oxide semiconductor layer is
In: 15-25 atomic%,
Ga: 5 to 20 atomic%,
Zn: 35 to 60 atomic%, and Sn: 9 to 30 atomic%
The thin film transistor according to [3] above, wherein
[5] The two or more protective films include at least a first protective film that is directly joined to the oxide semiconductor layer and a second protective film different from the first protective film, and the first protective film is hydrogen. The thin film transistor according to any one of [1] to [4], wherein the thin film transistor is a SiO _x film having a concentration of 4.5 atomic% or less.
[6] The thin film transistor according to any one of [1] to [5], wherein the thin film transistor is a back channel etch type in which an etch stopper layer is not provided immediately above the oxide semiconductor layer.

According to the present invention, at least one of a Mo-based film of a pure Mo film and a Mo alloy film, or at least one of a Cu-based film of the Mo-based film, a pure Cu film, and a Cu alloy film is used as a source / drain electrode. Mo-based / Cu-based laminated film, at least one Ti-based film of pure Ti film and Ti alloy film, or Cu-based film of at least one of Ti-based film, pure Cu film and Cu alloy film Even when using a Ti-based / Cu-based multilayer film, switching characteristics, S value, stress resistance, and light stress resistance (the amount of change in the threshold value of the transistor due to light stress is small while maintaining high electric field mobility) ), More preferably a BCE thin film transistor.
In addition, since the thin film transistor according to the present invention can form the source / drain electrodes by wet etching, a display device with high characteristics can be obtained easily and at low cost.

FIG. 1A is a schematic cross-sectional view for explaining an ESL thin film transistor. FIG. 1B is a schematic cross-sectional view for explaining a BCE thin film transistor. FIG. 2 is a schematic cross-sectional view for explaining the BCE-type thin film transistor used in Examples 1 and 2. FIG. 3 shows an inorganic material containing fluoride in hydrogen peroxide in each of a pure Ti film, a pure Mo film, a pure Cu film, a conventional oxide semiconductor layer (IGZO), and an oxide semiconductor layer (GIZTO) in the present invention. It is the graph which showed the etching rate by a system etching liquid. FIG. 4A is a top optical micrograph of the oxide semiconductor layer between the source and drain electrodes after 20% overetching in the thin film transistor using the IGZO oxide semiconductor layer according to Comparative Example 1-2. FIG. 4B is a top optical micrograph of the thin film transistor using the IGZO oxide semiconductor layer according to Comparative Example 1-2 after 50% overetching of the oxide semiconductor layer between the source and drain electrodes. FIG. 4C is an upper surface optical micrograph after 100% overetching of the oxide semiconductor layer between the source and drain electrodes in the thin film transistor using the IGZO oxide semiconductor layer according to Comparative Example 1-2. FIG. 4D is a top optical micrograph of the oxide semiconductor layer between the source and drain electrodes after 20% overetching in the thin film transistor using the GIZTO oxide semiconductor layer according to Example 1-2. FIG. 4E is a top optical micrograph of the oxide semiconductor layer between the source and drain electrodes after 50% overetching in the thin film transistor using the GIZTO oxide semiconductor layer according to Example 1-2. FIG. 4F is a top optical micrograph of the oxide semiconductor layer between the source and drain electrodes after 100% overetching in the thin film transistor using the GIZTO oxide semiconductor layer according to Example 1-2. FIG. 5 shows 20%, 50%, and 100% overetching in the TFT using the GIZTO oxide semiconductor layer according to Example 1-2 and the TFT using the IGZO oxide semiconductor layer according to Comparative Example 1-2. 3 is a graph showing the I _d -V _g characteristics of. FIG. 6 shows 20%, 50%, and 100% overetching in the TFT using the GIZTO oxide semiconductor layer according to Example 2-2 and the TFT using the IGZO oxide semiconductor layer according to Comparative Example 2-2. 3 is a graph showing the I _d -V _g characteristics of. FIG. 7 is a graph of I _d -V _g characteristics showing a typical example of the result of optical stress resistance using the TFT using the GIZTO oxide semiconductor layer according to Example 2-1. FIG. 8 illustrates a hydrogen peroxide solution in each of the GIZTO oxide semiconductor layer, the GIZTO (1) oxide semiconductor layer, the GIZTO (2) oxide semiconductor layer, the GIZTO (3) oxide semiconductor layer, and the IGZO oxide semiconductor layer. It is the graph which showed the etching rate by the inorganic type etching liquid containing fluoride. FIG. 9A is a graph showing I _d -V _g characteristics after 20%, 50%, and 100% overetching in the TFT using the GIZTO (1) oxide semiconductor layer of Example 4-1. FIG. 9B is a graph showing I _d -V _g characteristics after 20%, 50%, and 100% overetching in the TFT using the GIZTO (2) oxide semiconductor layer of Example 4-2. FIG. 10A is a graph showing I _d -V _g characteristics after 50% overetching in a TFT using the GIZTO (1) oxide semiconductor layer of Example 4-1. FIG. 10B is a graph showing I _d -V _g characteristics after 50% over-etching in the TFT using the GIZTO (2) oxide semiconductor layer of Example 4-2.

The thin film transistor of the present invention is a thin film transistor having at least a gate electrode, a gate insulating film, an oxide semiconductor layer, a source / drain electrode, and two or more protective films on a substrate, and a metal constituting the oxide semiconductor layer The elements are In, Ga, Zn, and Sn.
The source / drain electrode is directly bonded to the oxide semiconductor layer and is at least one of a pure Mo film and a Mo alloy film, or a Mo based film and the pure Cu film and a Cu alloy film. Mo-based / Cu-based laminated film with one Cu-based film, or Ti-based film of at least one of pure Ti film and Ti alloy film, or Ti-based / Cu-based laminated film of Ti-based film and Cu-based film It is.

The oxide semiconductor layer in the present invention is an oxide (GIZTO) containing In, Ga, Zn, and Sn, which are metal elements, as essential components. By containing Sn as an essential component, even when exposed to an etching solution such as an inorganic etching solution containing fluoride in hydrogen peroxide, the etching of the oxide semiconductor layer is suppressed, and the surface of the oxide semiconductor layer is damaged. Can be suppressed. Therefore, a TFT with a uniform oxide semiconductor layer thickness can be obtained. On the other hand, if there is too much Sn, there is a concern that the etching of the oxide semiconductor layer itself becomes difficult. Therefore, the ratio of Sn is preferably 9 to 50 atomic%, more preferably 9 to 30 atomic%, and further preferably 9 to 25 atomic% with respect to the total of all metal elements of In, Ga, Zn, and Sn (In + Ga + Zn + Sn). .

In addition, the ratio of each metal element to the total (In + Ga + Zn + Sn) of all metal elements in the oxide semiconductor layer is
In: 15-25 atomic%,
Ga: 5 to 20 atomic%,
Zn: 35-60 atomic% and Sn: 9-30 atomic%
An oxide semiconductor layer that satisfies the above conditions is preferable in terms of suppression of etching or TFT characteristics, and it is more preferable that Sn is 9 to 25 atomic%. Further, Zn is more preferably 40 to 60 atomic%. Note that the ratio of the metal element in the oxide semiconductor layer can be measured by ICP emission analysis.

Inorganic etching solution using Mo-based film or Mo-based film / Cu-based laminated film of Mo-based film and Cu-based film as source / drain electrodes, and patterning of source / drain electrodes containing hydrogen fluoride in fluoride Even when using an etching solution such as the above, the surface state of the oxide semiconductor layer is good, it has excellent static characteristics and particularly switching characteristics, and it has excellent resistance to light stress with suppressed deterioration of the S value. BCE type TFT can be obtained.

In addition, a Ti-based film or a Ti-based / Cu-based laminated film of a Ti-based film and a Cu-based film is used as a source / drain electrode, and the source / drain electrode is patterned by an inorganic system containing fluoride in hydrogen peroxide water. Even when using an etchant such as an etchant, the surface state of the oxide semiconductor layer is good, the static characteristics and particularly the switching characteristics are excellent, and the S-value deterioration is suppressed, and the resistance to light stress is reduced. BCE type TFT excellent in the above can be obtained.

Al wiring and Cu wiring are mainly used for the source / drain electrodes, and Mo-based materials have been conventionally used for barrier metal and cap metal for these wiring films. On the other hand, Ti-based materials are often performed by dry etching.
However, according to the study by the present inventors, it has been found that wet etching can be performed even when a Ti-based material is used as long as it is limited to a hydrogen peroxide-based etching solution containing fluoride.

Further, in the case of a conventional Cu-based / Ti-based laminated film, Cu was performed by wet etching and Ti was performed by dry etching, but similarly, by combining Ti with Cu wiring using a hydrogen peroxide-based etching solution, Batch etching of the Cu-based / Ti-based laminated film becomes possible.

In the source / drain electrodes according to the present invention, if Mo generates a residue, the characteristics of a BCE TFT using an oxide semiconductor may be easily deteriorated, whereas Ti does not deteriorate the characteristics even if a residue is generated. Therefore, it is more preferable to use a Ti-based film or a Ti-based / Cu-based laminated film as the source / drain electrodes from the viewpoint of improving characteristics.
Also, when a Mo alloy film containing Ti is used, characteristics are improved as compared with pure Mo. Therefore, a Mo alloy film containing Ti or a Mo-based / Cu-based laminated film using the Mo alloy is used. It is also preferable.

The protective film having two or more layers can be used without particular limitation as long as it is a protective film generally used conventionally. It is preferable that the two or more protective films include at least a first protective film that is directly bonded to the oxide semiconductor layer and a second protective film that is different from the first protective film. The second protective film may be a single layer or two or more layers as long as it is a protective film other than the first protective film.
The first protective film is preferably a SiO _x film having a hydrogen concentration of 4.5 atomic% or less because the resistance to light stress can be further improved.

By configuring the protective film as described above, the static characteristics of the TFT are deteriorated even if the source / drain electrodes are a Mo-based film, a Mo-based / Cu-based laminated film, a Ti-based film, or a Ti-based / Cu-based laminated film. Without being damaged, damage caused by an etching solution such as an inorganic etching solution containing fluoride in hydrogen peroxide can be suppressed. That is, a TFT having a uniform oxide semiconductor layer thickness and excellent static characteristics and stress resistance can be obtained.
The second protective film can be used without any particular limitation as long as it is a protective film generally used conventionally. Of these, a SiN _x film and a SiO _x film are preferable.

As the substrate, the gate electrode, and the gate insulating film constituting the thin film transistor according to the present invention, those conventionally used in general can be used.
Among them, the substrate is preferably a glass substrate or quartz from the viewpoint of transparency. The gate electrode is preferably a pure Mo thin film, Mo / Al / Mo, Cu / Mo, Cu / Ti, or the like in terms of heat resistance and resistivity. The gate insulating film is preferably formed by a plasma CVD method using a mixed gas of SiH ₄ and N ₂ O as a carrier gas from the viewpoint of hydrogen diffusion into the oxide semiconductor film.

Since the thin film transistor according to the present invention can be a BCE type that does not have an etch stopper layer directly on the oxide semiconductor layer as described above, the number of mask forming steps in the TFT manufacturing process is small, and the cost is sufficiently reduced. can do. In addition, unlike the ESL type TFT, the BCE type TFT does not have an overlap portion between the etch stopper layer and the source / drain electrodes, so that the TFT can be made smaller than the ESL type TFT.

EXAMPLES Hereinafter, the present invention will be described more specifically with reference to examples and comparative examples, but the present invention is not limited to these examples.
[Example 1]
A thin film transistor having the structure shown in FIG.
First, on a glass substrate 1 (Corning Eagle XG, diameter 100 nm × thickness 0.7 mm), a pure Mo thin film 100 nm as the gate electrode 2 and a SiO _x film (film thickness 250 nm) as the gate insulating film 3 are sequentially formed. Filmed. The gate electrode 2 was formed using a pure Mo sputtering target by DC sputtering under the conditions of film formation temperature: room temperature, film formation power: 300 W, carrier gas: Ar, gas pressure: 2 mTorr. The gate insulating film 3 was formed using a plasma CVD method under the conditions of a carrier gas: a mixed gas of SiH ₄ and N ₂ O, a film formation power: 300 W, and a film formation temperature: 350 ° C.

Next, as the oxide semiconductor layer 4 (film thickness: 40 nm), Ga—In—Zn—Sn—O having an atomic ratio of Ga: In: Zn: Sn = 16.8: 16.6: 47.2: 19.4 A film was formed on the gate insulating film 3. For the film formation, a sputtering target having the same metal element ratio was used, and the film was formed by DC sputtering.
The apparatus used for sputtering is “CS-200” manufactured by ULVAC, Inc., and the sputtering conditions are as follows.

(Sputtering conditions)
Substrate temperature: room temperature Deposition power: DC 200W
Gas pressure: 1mTorr
Oxygen partial pressure: 100 × O ₂ / (Ar + O ₂ ) = 10%

After forming the oxide semiconductor layer 4 (GIZTO) as described above, patterning was performed by photolithography and wet etching. In the wet etching, “ITO-07N” manufactured by Kanto Chemical Co., Ltd. was used, and the liquid temperature was set to room temperature. In this example, it was confirmed that etching was possible without any residue on all the oxide thin films tested.

As described above, after the oxide semiconductor layer 4 was patterned, a pre-annealing process was performed in order to improve the film quality of the oxide semiconductor layer 4. The pre-annealing process was performed at 350 ° C. for 60 minutes in an air atmosphere.

Next, source / drain electrodes 5 were formed. Specifically, a pure Mo film that is a pure Mo single layer is formed (Example 1-1), or a pure Mo film and a pure Cu film are laminated to form a pure Mo film (thickness 20 nm) / pure Cu film. A three-layered film (pure Mo / pure Cu / pure Mo laminated film) of (film thickness 200 nm) / pure Mo film (film thickness 20 nm) was formed (Example 1-2). After the source / drain electrode 5 was formed, patterning was performed by photolithography and wet etching. For the patterning, an inorganic etching solution containing a fluoride in hydrogen peroxide solution was used. By patterning the source / drain electrodes 5, the TFT channel length was set to 10 μm and the channel width was set to 200 μm. In order to prevent a short circuit of the source / drain electrode 5, overetching of 20%, 50% or 100% was performed on the electrode film thickness. Note that 50% overetching was used as a standard condition.

Thereafter, an SiO _x film was first formed as the first protective film 6A as the protective film. The SiO _x film was formed by a plasma CVD method using “PD-220NL” manufactured by Samco. For the formation of the SiO _x film, a mixed gas of SiH ₄ and N ₂ O was used. The film formation power was 100 W and the film formation temperature was 230 ° C. The gas ratio of SiH ₄ and N ₂ O was SiH ₄ : N ₂ O = 4: 100, and in this case, the hydrogen concentration of the SiO _x film was 4.3 atomic%. The film thickness of the SiO _x film was 200 nm.

Thereafter, a SiN _x film was formed as the second protective film 6B. Formation of the the SiN _x film is also used steel SAMCO "PD-220 NL], the formation of .SiN _x film was carried out by plasma CVD, using a mixed gas of SiH ₄ and NH _3, and _{N 2.} The formation The film power was 100 W and the film formation temperature was 200 ° C. The gas ratio of SiH ₄ , N ₂ O, and N ₂ was SiH ₄ : N ₂ O: N ₂ = 12.5: 6.0: 297.5. It was.

Next, contact holes 7 for probing for transistor characteristic evaluation were formed in the first protective film 6A and the second protective film 6B by photolithography and dry etching.
Finally, a post-annealing process was performed. The post-annealing treatment was performed at 250 ° C. for 30 minutes in a nitrogen atmosphere. A TFT was manufactured by the above procedure.

[Comparative Example 1]
Except that the composition of the metal element of the oxide semiconductor layer 4 is an In—Ga—Zn—O (IGZO) film of In: Ga: Zn = 1: 1: 1 (atomic ratio), A thin film transistor was manufactured. As in Example 1, a pure Mo film having a pure Mo single layer as a source / drain electrode was formed in Comparative Example 1-1, and a pure Mo film and a pure Cu film were laminated to form a pure Mo film (film thickness 20 nm) / A three-layer laminated film (pure Mo / pure Cu / pure Mo laminated film) of a pure Cu film (film thickness 200 nm) / pure Mo film (film thickness 20 nm) is referred to as Comparative Example 1-2.

[Evaluation of resistance to inorganic etching solution containing fluoride in hydrogen peroxide solution 1]
The effect of the presence or absence of Sn in the oxide semiconductor layer on the resistance to an inorganic etching solution containing fluoride in the hydrogen peroxide solution used when forming the source / drain electrodes was examined. The etching rate was measured by reducing the thickness of the oxide semiconductor layer.
In addition to the oxide semiconductor layers in Example 1 and Comparative Example 1, etching rates were similarly measured for each of the pure Mo film, the pure Ti film, and the pure Cu film.

The graph of FIG. 3 shows the measurement results of the etching rate in an inorganic etching solution containing fluoride in hydrogen peroxide solution. In FIG. 3, “Ti” is a pure Ti film, “Mo” is a pure Mo film, “Cu” is a pure Cu film, “IGZO” is an oxide semiconductor layer in Comparative Example 1, and “GIZTO”. Each of the oxide semiconductor layers in Example 1 is meant.
As a result, the etching rate of the IGZO oxide semiconductor layer was 1.71 nm / second, whereas that of the GIZTO oxide semiconductor layer containing Sn was 0.44 nm / second, which is about 3.9 times as resistant. I understood.

[Evaluation of resistance to inorganic etching solution containing fluoride in hydrogen peroxide solution 2]
The top surface optical micrograph of the oxide semiconductor layer between the source and drain electrodes when overetching 20%, 50% and 100% was performed on the TFTs obtained in Example 1-2 and Comparative Example 1-2. Are shown in FIGS. 4A to 4F. 4A to 4C are TFTs using the IGZO oxide semiconductor layer according to Comparative Example 1-2, and FIGS. 4D to 4F are TFTs using the GIZTO oxide semiconductor layer according to Example 1-2. 4D are the results of 20% overetching, FIGS. 4B and 4E are the results of 50% overetching, and FIGS. 4C and 4F are the results of 100% overetching.

As is apparent from FIGS. 4A to 4F, in the TFT using the IGZO oxide semiconductor layer according to Comparative Example 1-2, the oxide semiconductor layer disappears after 50% overetching, whereas the example In the TFT using the GIZTO oxide semiconductor layer according to 1-2, it was confirmed that the oxide semiconductor layer did not disappear even with 100% overetching.
The same evaluation was performed on the TFTs of Example 1-1 and Comparative Example 1-1. The above evaluation results are summarized in “Evaluation of optical microscope after S / D electrode etching” in Table 1.

[Evaluation of field effect mobility and S value in static characteristics 1]
Using the TFTs of Example 1-2 and Comparative Example 1-2, the field effect mobility and stress resistance (S value) in static characteristics were evaluated.
I _d -V _g characteristics were measured using the TFTs of Example 1-2 and Comparative Example 1-2. The I _d -V _g characteristics were measured using a prober and a semiconductor parameter analyzer (Keithley 4200SCS) with the gate voltage and source / drain electrode voltages set as follows.
・ Gate voltage: -30-30V (step 0.25V)
・ Source voltage: 0V
・ Drain voltage: 10V
・ Measurement temperature: Room temperature

The measured I _d -V _g characteristics are shown together in FIG. In FIG. 5, “OE.20%”, “OE.50%”, and “OE.100%” mean overetching of 20%, 50%, and 100%, respectively. The vertical axis of each graph is I _d (A), and the horizontal axis is V _g (V). Note that the TFT using the IGZO oxide semiconductor layer according to Comparative Example 1-2 disappeared when immersed in an etching solution at an overetching time of 50% and 100%, and thus no I _d -V _g characteristic was observed (drain) Current did not flow). On the other hand, in the TFT using the GIZTO oxide semiconductor layer according to Example 1-2, good I _d -V _g characteristics were obtained.

The same evaluation was performed on the TFTs of Example 1-1 and Comparative Example 1-1. The above evaluation results are summarized in “mobility”, “S value”, and “S value determination” in Table 1.
The mobility is 7.0 cm ² / Vs or higher.
The criteria for “S value judgment” are shown below.
○: S value is 0.45 V / dec or less Δ: S value is 0.45 V / dec or more and 1.0 V / dec or less ×: S value exceeds 1.0 V / dec

As shown in Table 1, the TFT using the IGZO oxide semiconductor layer showed a decrease in mobility even in the overetching of 20% in the patterning of the source / drain electrodes.

[Stress tolerance evaluation 1]
Using the TFTs of Example 1-1, Example 1-2, Comparative Example 1-1, and Comparative Example 1-2, stress resistance (resistance against light + negative bias stress) was evaluated.
Stress tolerance was evaluated by conducting a stress application test in which light was irradiated while applying a negative bias to the gate electrode. The stress application conditions are as follows.
・ Gate voltage: -20V
・ Source-drain voltage: 10V
-Substrate temperature: 60 ° C
・ Stress application time: 2 hours ・ Light stress conditions:
Light intensity: 25000NIT
Light source: White LED

The threshold voltage shift before and after application of light + negative bias stress (difference in gate voltage at which the drain current becomes 10 ⁻⁹ A) was measured. This difference is called ΔV _th . The evaluation results are summarized in “ΔV _th ” and “ΔV _th judgment” in Table 1. The criteria for determining ΔV _th are as follows.
○: ΔV _th is 3.5 V or less ×: ΔV _th exceeds 3.5 V

From the above evaluation results, TFTs using a GIZTO oxide semiconductor layer have the same S value as TFTs using a conventional IGZO oxide semiconductor layer, and very good results are obtained in both mobility and stress resistance. Therefore, it was evaluated as “good” as a comprehensive judgment.

[Example 2]
As in Example 1, a thin film transistor having the structure shown in FIG.

Specifically, the glass substrate 1, the gate electrode 2, the gate insulating film 3, and the oxide semiconductor layer 4 were formed in the same manner as in Example 1. Next, a pure Ti film that is a pure Ti single layer is formed as the source / drain electrode 5 (Example 2-1), or a pure Ti film and a pure Cu film are laminated to form a pure Ti film (film thickness 20 nm). ) / Pure Cu film (thickness 200 nm) / pure Ti film (thickness 20 nm) was formed (pure Ti / pure Cu / pure Ti laminate film) (Example 2-2). Patterning by photolithography and wet etching after the formation of the source / drain electrodes 5 was performed in the same manner as in Example 1.

Thereafter, the formation of the laminated protective film and the contact hole and the post-annealing treatment were performed in the same manner as in Example 1.

[Comparative Example 2]
Except that the composition of the metal element of the oxide semiconductor layer 4 is an In—Ga—Zn—O (IGZO) film of In: Ga: Zn = 1: 1: 1 (atomic ratio), A thin film transistor was manufactured. As in Example 2, the source / drain electrode is a pure Ti film that is a pure Ti single layer, Comparative Example 2-1, and a pure Ti film (thickness) obtained by laminating a pure Ti film and a pure Cu film. 20 nm) / pure Cu film (thickness 200 nm) / pure Ti film (thickness 20 nm) was a three-layer laminated film (pure Ti / pure Cu / pure Ti laminated film).

[Evaluation of field effect mobility and S value in static characteristics 2]
Using the TFTs of Example 2-2 and Comparative Example 2-2, the field effect mobility and stress resistance (S value) in the static characteristics were evaluated.
Using the TFTs of Example 2-2 and Comparative Example 2-2, I _d -V _g characteristics were measured under the same conditions as in Example 1 and the like.

The measured I _d -V _g characteristics are summarized in FIG. In FIG. 6, “OE.20%”, “OE.50%”, and “OE.100%” mean 20%, 50%, and 100% overetching, respectively. The vertical axis of each graph is I _d (A), and the horizontal axis is V _g (V). Note that the TFT using the IGZO oxide semiconductor layer according to Comparative Example 2-2 disappeared when immersed in an etching solution with an overetching time of 50% and 100%, and thus no I _d -V _g characteristic was observed (drain) Current did not flow). On the other hand, in the TFT using the GIZTO oxide semiconductor layer according to Example 2-2, good I _d -V _g characteristics were obtained.

The same evaluation was performed on the TFTs of Example 2-1 and Comparative Example 2-1. The above evaluation results are summarized in “Mobility”, “S value”, and “S value determination” in Table 2.
Evaluation criteria for “mobility” and “S value determination” are the same as those in the first embodiment.

As shown in Table 2, the TFT using the IGZO oxide semiconductor layer showed a decrease in mobility even in the overetching of 20% in the patterning of the source / drain electrodes.

[Stress tolerance evaluation 2]
Stress resistance (resistance to light + negative bias stress) was evaluated using the TFTs of Example 2-1, Example 2-2, Comparative Example 2-1, and Comparative Example 2-2, and are summarized in Table 2.
The stress tolerance evaluation method and evaluation criteria are the same as those in Example 1.

FIG. 7 shows the I _d -V _g characteristics of the TFT of Example 2-1 during 100% over-etching. The stress application time was 0 seconds, 3600 seconds, or 7200 seconds. At this time, ΔV _th in the stress resistance was 2.2 V regardless of the stress application time, and a good result was obtained.
From the above evaluation results, the TFT using the GIZTO oxide semiconductor layer obtained very good characteristics over all of the mobility, S value, and stress resistance.

From the results of Table 1 and Table 2, in the case of a TFT using an IGZO oxide semiconductor layer that does not contain Sn in the oxide semiconductor layer, an inorganic material containing fluoride in the hydrogen peroxide solution during patterning of the source / drain electrodes It was found that the TFT cannot be manufactured in a sufficient over-etching time because the oxide semiconductor layer easily disappears by immersion in a system etching solution.

On the other hand, in the case of a TFT using the Ga—In—Zn—Sn—O (GIZTO) oxide semiconductor layer according to the present invention, the TFT can be manufactured with sufficient over-etching time, and the static characteristics and stress can be obtained. The resistance results were also found to be good.
Furthermore, since the S value in the static characteristics is good and the ΔV _th in the stress resistance is small, the GIZTO oxide semiconductor layer is inhibited from being etched by immersion in an inorganic etching solution containing fluoride in hydrogen peroxide. In addition, damage to the oxide semiconductor layer surface could be suppressed.

[Example 3]
As in Example 1, a thin film transistor having the structure shown in FIG.

Specifically, the glass substrate 1, the gate electrode 2, the gate insulating film 3, and the oxide semiconductor layer 4 were formed in the same manner as in Example 1. Next, a pure Ti film that is a pure Ti single layer is formed as the source / drain electrode 5 (Example 3-1), or a pure Ti film and a pure Cu film are laminated to form a pure Ti film (film thickness 20 nm). ) / Pure Cu film (film thickness 200 nm) / pure Ti film (film thickness 20 nm) was formed (pure Ti / pure Cu / pure Ti laminate film) (Example 3-2). After the source / drain electrode 5 was formed, patterning was performed by photolithography and wet etching. For the patterning, an inorganic etching solution containing a fluoride in hydrogen peroxide solution was used. By patterning the source / drain electrodes 5, the TFT channel length was set to 10 μm and the channel width was set to 200 μm. In order to prevent a short circuit between the source / drain electrodes 5, overetching of 50% of the electrode film thickness was performed.

Thereafter, the formation of the laminated protective film and the contact hole and the post-annealing treatment were performed in the same manner as in Example 1.

Further, a thin film transistor was fabricated in the same manner as in Example 3-1, except that the SiO _x film with the flow rate of SiH ₄ increased and the gas ratio with N ₂ O changed was used as the first protective film 6A. The hydrogen concentration of the SiO _x film was 6.5 atomic% (Reference Example 1-1) and 7.2 atomic% (Reference Example 2-1). The film thickness of the SiO _x film was 200 nm.
A thin film transistor was fabricated in the same manner as in Example 3-2 except that the SiO _x film with the SiH ₄ flow rate increased and the gas ratio with N ₂ O changed was used as the first protective film 6A. The hydrogen concentration of the SiO _x film was 6.5 atomic% (Reference Example 1-2) and 7.2 atomic% (Reference Example 2-2). The film thickness of the SiO _x film was 200 nm.

[Evaluation of field effect mobility and S value in static characteristics 3]
The field effect mobility and stress resistance (S value) in static characteristics were evaluated using the TFTs of Example 3 and Reference Example.
Using the TFTs of Example 3-1, Example 3-2, Reference Example 1-1, Reference Example 2-1, Reference Example 1-2, and Reference Example 2-2, I under the same conditions as in Example 1 etc. _{The d} −V _g characteristic was measured.

The field effect mobility and S value were calculated from the measured I _d -V _g characteristic results. The above evaluation results are summarized in “mobility”, “S value”, and “S value determination” in Table 3.
Evaluation criteria for “mobility” and “S value determination” are the same as those in the first embodiment.

[Stress tolerance evaluation 3]
Stress resistance (resistance to light + negative bias stress) using the TFTs of Example 3-1, Example 3-2, Reference Example 1-1, Reference Example 2-1, Reference Example 1-2, and Reference Example 2-2 ) And are summarized in Table 3.
The stress tolerance evaluation method and evaluation criteria are the same as those in Example 1.

[Example 4]
A thin film transistor having the structure shown in FIG. 2 was produced by the following procedure.

Specifically, the glass substrate 1, the gate electrode 2, the gate insulating film 3, and the oxide semiconductor layer 4 were formed in the same manner as in Example 1. Next, as the oxide semiconductor layer 4 (film thickness: 40 nm), Ga—In—Zn—Sn—O having an atomic ratio of Ga: In: Zn: Sn = 16.0: 17.4: 42.3: 24.4 (1) A film was formed on the gate insulating film 3 (Example 4-1). For the film formation, a sputtering target having the same metal element ratio was used, and the film was formed by DC sputtering.
The apparatus used for sputtering is “CS-200” manufactured by ULVAC, Inc., and the sputtering conditions are the same as those in Example 1. In addition, a Ga—In—Zn—Sn—O (2) film in which the atomic ratio of the oxide semiconductor layer is Ga: In: Zn: Sn = 16.2: 17.4: 38.1: 28.3 (implementation) Example 4-2) or a Ga—In—Zn—Sn—O (3) film having an atomic ratio of Ga: In: Zn: Sn = 16.5: 16.6: 61.6: 5.3 ( Reference Example 4-3) was formed in the same manner.

After each oxide semiconductor layer 4 (GIZTO) was formed as described above, patterning was performed by photolithography and wet etching. In the wet etching, “ITO-07N” manufactured by Kanto Chemical Co., Ltd. was used, and the liquid temperature was set to room temperature or 40 ° C. In this example, it was confirmed that etching was possible without any residue on all the oxide thin films tested.

As described above, after the oxide semiconductor layer 4 was patterned, a pre-annealing process was performed in order to improve the film quality of the oxide semiconductor layer 4. The pre-annealing process was performed at 350 ° C. for 60 minutes in an air atmosphere.

Next, source / drain electrodes 5 were formed. Specifically, a pure Ti film that is a pure Ti single layer was formed. After the source / drain electrode 5 was formed, patterning was performed by photolithography and wet etching. For the patterning, an inorganic etching solution containing a fluoride in hydrogen peroxide solution was used. By patterning the source / drain electrodes 5, the TFT channel length was set to 10 μm and the channel width was set to 200 μm. In order to prevent short-circuiting of the source / drain electrodes 5, 50% overetching, which is a standard condition, was performed on the electrode film thickness.

Thereafter, the formation of the laminated protective film and the contact hole and the post-annealing treatment were performed in the same manner as in Example 1.

[Example 5]
A pure Ti film and a pure Cu film are laminated as the source / drain electrodes 5, and a three-layer laminated film (pure Ti film (film thickness 20 nm) / pure Cu film (film thickness 200 nm) / pure Ti film (film thickness 20 nm)). A TFT was manufactured in the same manner as in Example 4 except that (Ti / pure Cu / pure Ti laminated film).
Note that the atomic ratio Ga: In: Zn: Sn of the oxide semiconductor layer 4 (film thickness 40 nm) in the TFT is Ga-In in which Example 5-1 is 16.0: 17.4: 42.3: 24.4. -Zn-Sn-O (1) film, Example 5-2 is 16.2: 17.4: 38.1: 28.3 Ga-In-Zn-Sn-O (2) film, Reference Example 5 −3 is a Ga—In—Zn—Sn—O (3) film of 16.5: 16.6: 61.6: 5.3.

[Evaluation of resistance to inorganic etching solution containing fluoride in hydrogen peroxide solution 3]
The effect of the addition amount of Sn in the oxide semiconductor layer on the resistance to an inorganic etching solution containing fluoride in the hydrogen peroxide solution used when forming the source / drain electrodes was examined. The etching rate was measured by reducing the thickness of the oxide semiconductor layer.
The graph of FIG. 8 shows the measurement results of the etching rate in an inorganic etching solution containing fluoride in hydrogen peroxide solution. In FIG. 8, “GIZTO” is an oxide semiconductor thin film having an atomic ratio of Ga: In: Zn: Sn = 16.8: 16.6: 47.2: 19.4. Examples 2-1 and 2 -2 is an oxide semiconductor layer. “GIZTO (1)” is an oxide semiconductor thin film having an atomic ratio of Ga: In: Zn: Sn = 16.0: 17.4: 42.3: 24.4. Examples 4-1 and 5- 1 is an oxide semiconductor layer in FIG. “GIZTO (2)” is an oxide semiconductor thin film having an atomic ratio of Ga: In: Zn: Sn = 16.2: 17.4: 38.1: 28.3. Examples 4-2 and 5- 2 is an oxide semiconductor layer. “GIZTO (3)” is an oxide semiconductor thin film having an atomic ratio of Ga: In: Zn: Sn = 16.5: 16.6: 61.6: 5.3. Reference examples 4-3 and 5- 3 is an oxide semiconductor layer. “IGZO” is an oxide semiconductor thin film having an atomic ratio of Ga: In: Zn = 1: 1: 1 and containing no Sn, and is an oxide semiconductor layer in Comparative Examples 2-1 and 2-2.
As a result, the etching rate of the IGZO oxide semiconductor layer decreased as the amount of Sn added increased. In particular, when the Sn content was 5.3 atomic% and 19.4 atomic%, the etching rate was considerably reduced. Therefore, it was found that if the Sn content is about 9 atomic% or more, very good etching resistance can be obtained.

[Evaluation of field effect mobility and S value in static characteristics 4]
Using the TFTs of Examples 2-1, 2-2, 4-1, 4-2, 5-1, and 5-2, field effect mobility and stress resistance (S value) in static characteristics were evaluated. . The oxide semiconductor layers are GIZTO in Examples 2-1 and 2-2, GIZTO (1) in Examples 4-1 and 5-1 and GIZTO (2) in Examples 4-2 and 5-2. The source / drain electrodes are pure Ti film in Examples 2-1, 4-1 and 4-2, and pure Ti film / pure Cu film / pure Ti film in Examples 2-2, 5-1 and 5-2. It is a three-layer laminated film.
Note that the IGZO oxide semiconductor layer not containing Sn (corresponding to Comparative Examples 2-1 and 2-2) and the GIZTO (3) oxide semiconductor layer (Reference Examples 4-3 and 5-3) were 50% in the etching solution. Since it disappeared when immersed in the over-etching time, the I _d -V _g characteristic was not observed (drain current did not flow), and the mobility and stress resistance could not be evaluated.

Using the TFTs of Examples 2-1, 2-2, 4-1, 4-2, 5-1, and 5-2, I _d -V _g characteristics were measured under the same conditions as in Example 1 and the like.

Of the measured I _d -V _g characteristics, the result of Example 4-1 is shown in FIG. 9A, and the result of Example 4-2 is shown in FIG. 9B. 9A and 9B, “No1” means 30% overetching, “No2” means 50% overetching, and “No3” means 100% overetching. The vertical axis of the graph is I _d (A), and the horizontal axis is V _g (V). Similar to the GIZTO oxide semiconductor layer, a TFT using the GIZTO (1) oxide semiconductor layer and the GIZTO (2) oxide semiconductor layer also showed good I _d -V _g characteristics.

The above evaluation results are summarized in “mobility”, “S value”, and “S value determination” in Table 4.
Evaluation criteria for “mobility” and “S value determination” are the same as those in the first embodiment.

[Stress tolerance evaluation 4]
Using the TFTs of Examples 2-1, 2-2, 4-1, 4-2, 5-1 and 5-2, stress resistance (resistance to light + negative bias stress) was evaluated and summarized in Table 4. It was.
The stress tolerance evaluation method and evaluation criteria are the same as those in Example 1. In Reference Examples 4-3 and 5-3, the stress resistance could not be evaluated because the film disappeared by immersion in the etching solution.

The I _d -V _g characteristics after 50% overetching of GIZTO (1) of Example 4-1 and GIZTO (2) of Example 4-2 are shown in FIGS. 10A and 10B, respectively. The stress application time was 0 seconds, 3600 seconds, or 7200 seconds. At this time, ΔV _th in the stress resistance was good with 2.5 V and 2.25 V, respectively, regardless of the stress application time.
From the above evaluation results, TFTs using an oxide semiconductor layer containing a certain amount or more of Sn obtained very good characteristics over all of mobility, S value, and stress resistance. did.
In this evaluation, a relatively large amount of fluoride was used in an inorganic etching solution containing hydrogen fluoride in a hydrogen peroxide solution. However, when manufacturing a TFT with a smaller amount of fluoride, There is also.

From the above evaluation results, in the case of the TFT using the Ga—In—Zn—Sn—O (GIZTO) oxide semiconductor layer according to the present invention, the resistance to the etching solution is improved by including Sn in the oxide semiconductor layer. Furthermore, it was found that by including Sn at 9 atomic% or more with respect to the total amount of metal elements in the oxide semiconductor layer, good results can be obtained over all of the switching characteristics, S value, and stress resistance. Furthermore, it has been found that the stress resistance result can be made very good by setting the hydrogen concentration contained in the SiO _x film as the first protective film 6A to 4.5 atomic% or less.

Although the invention has been described in detail with reference to specific embodiments, it will be apparent to those skilled in the art that various changes and modifications can be made without departing from the spirit and scope of the invention.
In addition, this application is a Japanese patent application (Japanese Patent Application No. 2015-109825) filed on May 29, 2015 and a Japanese patent application (Japanese Patent Application No. 2015-206513) filed on October 20, 2015. Which is incorporated by reference in its entirety.

DESCRIPTION OF SYMBOLS 1 Glass substrate 2 Gate electrode 3 Gate insulating film 4 Oxide semiconductor layer 5 Source / drain electrode 6 Protective film 6A First protective film 6B Second protective film 7 Contact hole 8 Transparent conductive film 9 Etch stopper layer

Claims (14)

A thin film transistor having at least a gate electrode, a gate insulating film, an oxide semiconductor layer, a source / drain electrode, and a protective film of two or more layers on a substrate,
The metal elements constituting the oxide semiconductor layer are In, Ga, Zn, and Sn,
The source / drain electrode is a Ti-based film of at least one of a pure Ti film and a Ti alloy film, or a Ti-based film of the Ti-based film and at least one of a Cu-based film of a pure Cu film and a Cu alloy film. A thin film transistor which is a Cu-based laminated film and in which the source / drain electrodes are directly bonded to the oxide semiconductor layer. A thin film transistor having at least a gate electrode, a gate insulating film, an oxide semiconductor layer, a source / drain electrode, and a protective film of two or more layers on a substrate,
The metal elements constituting the oxide semiconductor layer are In, Ga, Zn, and Sn,
The source / drain electrode is a Mo-based film of at least one of a pure Mo film and a Mo alloy film, or a Mo-based film of the Mo-based film and at least one of a pure Cu film and a Cu alloy film. A thin film transistor which is a Cu-based laminated film and in which the source / drain electrodes are directly bonded to the oxide semiconductor layer. The thin film transistor according to claim 1, wherein a ratio of Sn to a total of all metal elements in the oxide semiconductor layer is 9 atomic% or more and 50 atomic% or less. The thin film transistor according to claim 2, wherein a ratio of Sn to a total of all metal elements in the oxide semiconductor layer is 9 atomic% or more and 50 atomic% or less. The ratio of each metal element to the total of all metal elements in the oxide semiconductor layer is
In: 15-25 atomic%,
Ga: 5 to 20 atomic%,
Zn: 35 to 60 atomic%, and Sn: 9 to 30 atomic%
The thin film transistor according to claim 3. The ratio of each metal element to the total of all metal elements in the oxide semiconductor layer is
In: 15-25 atomic%,
Ga: 5 to 20 atomic%,
Zn: 35 to 60 atomic%, and Sn: 9 to 30 atomic%
The thin film transistor according to claim 4. The two or more protective films comprise at least a first protective film that is directly bonded to the oxide semiconductor layer and a second protective film different from the first protective film, and the first protective film has a hydrogen concentration of 4. 2. The thin film transistor according to claim 1, wherein the thin film transistor is a SiO _x film of 5 atomic% or less. The two or more protective films comprise at least a first protective film that is directly bonded to the oxide semiconductor layer and a second protective film different from the first protective film, and the first protective film has a hydrogen concentration of 4. The thin film transistor according to claim 2, which is a SiO _x film of 5 atomic% or less. 2. The thin film transistor according to claim 1, wherein the thin film transistor is a back channel etch type in which an etch stopper layer is not provided immediately above the oxide semiconductor layer. 3. The thin film transistor according to claim 2, wherein the thin film transistor is a back channel etch type in which an etch stopper layer is not provided immediately above the oxide semiconductor layer. 6. The thin film transistor according to claim 5, wherein the thin film transistor is of a back channel etch type in which no etch stopper layer is provided immediately above the oxide semiconductor layer. The thin film transistor according to claim 6, wherein the thin film transistor is of a back channel etch type in which an etch stopper layer is not provided immediately above the oxide semiconductor layer. The thin film transistor according to claim 7, wherein the thin film transistor is of a back channel etch type in which an etch stopper layer is not provided immediately above the oxide semiconductor layer. The thin film transistor according to claim 8, wherein the thin film transistor is of a back channel etch type in which an etch stopper layer is not provided immediately above the oxide semiconductor layer.

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